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EE-281
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Hardware Design Checklist Blackfin® Processors
Contributed Robert Kilgore October 2005
Introduction
This engineer-to-engineer note describes most common mistakes avoid when designing with Blackfin® processors. addition this document, designer should read most current data sheet, Hardware Reference Manual, and, errata list (available from Analog Devices site) specific Blackfin processor being used.
Five-Volt Tolerance
General Hardware Problems
following sections address design issues associated with memory interfaces specific peripherals.
Polarity
Applying five volts pins that rated this potential damage pins cause malfunction. Blackfin processor outputs that connect inputs five-volt devices left floating pulled five volts. Most Blackfin processor pins cannot tolerate five volts. There exceptions, such Two-Wire Interface (TWI) pins. Level shifters required other processor pins keep voltage below absolute maximum ratings defined specific Blackfin processor data sheet. Current limiting resistors provide sufficient protection against high voltage.
Unused Pins
Double-check polarity Non-Maskable Interrupt (NMI) processor being used. several Blackfin processors (the ADSPBF531/BF532/BF533/BF535 ADSPBF561), active high. other Blackfin processors, active order better connect standard Supervisory parts. Also, please remember that used, should tied inactive state. float, active state.
Check list description section data sheet what with unused pins. general, need terminate unused pins been eliminated, pins that require termination found data sheet.
Signal Integrity
Rapid rise-time fall-time signals primary cause signal integrity problems. These edge rates Blackfin processor differ from pin. Likewise, some pins have greater sensitivity noise reflections than other pins. simple signal integrity methods prevent transmission-line reflections that cause extraneous clock sync signals. Short
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trace length series termination critical following signals:
CLKIN pins should have impedance-matching
MHz, 0.1, 0.01, 0.001 even preferred 500-MHz range VDD_INT.
Driving/RESET
series resistance driver SPORT interface signals (TCLK, RCLK, RFS, TFS) should termination pins, such PPI_CLK Sync signals, also benefit from these standard signal integrity techniques SDRAM clocks, control, address, data also benefit from series termination reduce unwanted EMI. cases where signals have multiple sources, will difficult keep traces short, simulation appropriate. IBIS models that assist with signal simulation available from Analog Devices site.
Test Points Signal Access
pins Blackfin processor have hysteresis, thus, they require monotonic rise fall. Therefore, even /RESET should connected directly time delay because such circuit would noise sensitive. Instead, /RESET should provided through reset supervisory chip.
JTAG
application note dedicated entirely considerations JTAG connections. Refer Analog Devices JTAG Emulation Technical Reference (EE-68)[1] details.
Pins Used Outputs
debug process aided adding test points signals such CLKOUT SCLK, bank selects, PPICLK, RESET. selection pins such Boot Mode (BMODE) connected directly power ground, they will inaccessible under BGA-package chip. debugging, helpful pull-up pull-down resistors instead tying power ground directly.
pins used outputs should have pull-up pull-down resistors determine state after reset.
Using EZ-KIT Lite® Schematics
Bypass Capacitors
Appropriate bypass capacitors internal power supply become critical higher operating speeds. Unwanted parasitic inductance capacitors traces reduces effectiveness high frequency. things needed when processors operate above MHz. First, capacitors should physically small their leads should short reduce inductance. Surface mounted capacitors size 0402 will yield better results than larger sizes. Second, lower values capacitance will raise resonant frequency circuit. Although several capacitors work well below
EZ-KIT Lite® evaluation system schematics good starting reference. Because EZKIT Lite board evaluation development, extra circuitry provided some cases. Read EZ-KIT Lite board schematic carefully because sometimes component populated sometimes been added make easier access, etc.
Request
Request (/BR) requires pull-up resistor designs. Erroneous requests occur this signal pulled when unused when driven external device.
Hardware Design Checklist Blackfin® Processors (EE-281)
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Asynchronous Memory
8-Bit Memories
Mapping" section Hardware Reference Manual processor being used.
Remember proper addresses connect 8-bit-wide memories ASYNC memory banks. Because there true byte addressing external memory, 8-bit memory addressed same 16-bit memory. (not /ABE0 /ABE1) address. Blackfin devices with 32-bit EBIU programmed connect with 16-bit memory, using /ABE3 external device. Refer processor's Hardware Reference Manual more information.
ARDY
Interface
Booting
used, ARDY terminated. addition, ARDY also programmed ignored software. ARDY used, consult Hardware Reference Manual. Some Blackfin devices require ARDY input synchronous SCLK (CLKOUT)
Master Boot mode requires pull-up resistor used chip-select memory device. ADSP-BF531/BF532/BF533 ADSP-BF561 processors, this PF2. ADSP-BF534/BF536/BF537 devices, PF10 used. Check booting section Blackfin processor's data sheet find connection booting. Most current processors require pull-up resistor MISO. SPI_SCK best used with pull-up resistor define state before port enabled. Also, refer "SPI Master Booting" section application note ADSP-BF533 Blackfin Booting Process (EE-240)[2].
MOSI MISO
Synchronous Memory
SDRAM Bank Addressing
ADDR18 connect BA0. ADDR19 connect BA1.
SDRAM Address SA10
interface requires that MOSI pins tied together MISO pins tied together. prevent contention possible damage pins, double-check that these pins have been interchanged. Connect MISO MISO MOSI MOSI. peripheral names DOUT connect them according their master slave function. Proper schematic signal names will reduce confusion.
SA10 directly connect SDRAM device. SA10 replaces Blackfin processor's ADDRx, based whether 32bit (for 32-bit-wide external memory interface derivatives) device connected SDRAM interface. example, ADSP-BF561 Blackfin processor, SA10 replaces ADDR11 when 16-bit SDRAM device used, SA10 replaces ADDR12 when 32-bit device used. ADSP-BF533 Blackfin processor, SA10 replaces ADDR11. Note that replaced ADDRx used. Refer "SDRAM Address
Two-Wire Interface
Two-Wire Interface I2C-compatible peripheral. Because never driven high, both signals need pull-up resistors just like standard requires them.
SPORT Interface
SPORTs Multi-Channel Mode that master clocks frame syncs should connect RFS. this mode, frames active
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Hardware Design Checklist Blackfin® Processors (EE-281)
transmit channel data role Transmit Data Valid (TDV) pin. ADSP-BF533 Blackfin Processors (EE-228)[3] further details component selection. power dissipation considerations, data sheet gives "typical" power. This power changes with processor activity, temperature, applied voltage, manufacturing changes from chip chip. application note Estimating Power ADSP-BF533 Blackfin Processors (EE-229)[4] will help estimate demand voltage maximum current.
Clock Input Signal
CLKIN
clock input Blackfin processor should start toggling after power-up continuous while power applied.
XTAL
Real-Time Clock (RTC)
Power
When using oscillator output instead crystal, XTAL output should have capacitor ground. shown this EZ-KIT Lite board schematic. Note that populated board, should populated design.
Does your design require battery continuous time information? not, connect power VDD_IO.
Crystal
Power Regulator
aware that internal voltage regulator switching regulator circuit (not linear regulation circuit). Ensure that diode shown data sheet present keep VROUT signal trace short! Refer application note Switching Regulator Design Considerations
Ensure that additional shunt resistor present crystal circuit. used, pull RTXI low.
References
Analog Devices JTAG Emulation Technical Reference (EE-68). October 2004. Analog Devices, Inc. ADSP-BF533 Blackfin Booting Process (EE-240). January 2005. Analog Devices, Inc. Switching Regulator Design Considerations ADSP-BF533 Blackfin Processors (EE-228). February 2005. Analog Devices, Inc. Estimating Power ADSP-BF533 Blackfin Processors (EE-229). February 2004. Analog Devices, Inc.
Document History
Revision October 2005 Robert Kilgore Description Initial Release
Hardware Design Checklist Blackfin® Processors (EE-281)
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