Single-chip Demodulator Digital Satellite Broadcasting MB86660A D

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Single-chip Demodulator Digital Satellite Broadcasting MB86660A D

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DS04-24500-2E
Single-chip Demodulator Digital Satellite Broadcasting MB86660A
DESCRIPTION
MB86660A single-chip demodulator digital satellite broadcasting, compatible DVB-S DSS*. consists converters I-input Q-input, QPSK demodulator forward-error correction (FEC) unit which Viterbi decoder Reed-Solomon decoder.
FEATURES
DVB-S DSS* compatible single-chip demodulator Operation rate Mbps converters I-input Q-input Analog Msymbol/s input QPSK demodulator Gray-coded QPSK demodulation with absolute mapping On-chip multi-rate operation) Automatic carrier capture range Half Nyquist filters roll-off factor 0.35 Automatic gain control output
(Continued)
PACKAGE
48-pin plastic
(FPT-48P-M15)
MB86660A
(Continued) Viterbi decoder Constraint length Viterbi rate 1/2, 2/3, 3/4, 5/6, Reed-Solomon decoder 204, 188, Deinterleaver: depth Energy-dispersal removal: PRBS polynomial monitoring output interface interface Power supply voltage: +3.3 Package: QFP-48 Process: 0.35 CMOS
detailed information usage, please contact your nearest Fujitsu.
MB86660A
ASSIGNMENT
VIEW
FSYNC
RESET
TCLK
VRHI AVSS AVDD VRLI VRLQ AVDD AVSS VRHQ
AVSS
AVDD
CLKI
CLKO
(FPT-48P-M15)
EXTCLK
BCLK
ADR2
ADR1
ADR0
TESTI
MB86660A
DESCRIPTION
Symbol name QPSK analog I-input QPSK analog Q-input high reference reference high reference reference output Function QPSK analog in-phase input: Analog input. maximum input rate Msymbol/s. QPSK analog quadrature-phase input: Analog input. maximum input rate Msymbol/s. high reference input IIN: High reference voltage input. typical voltage reference input IIN: reference voltage input. typical voltage high reference input QIN: High reference voltage input. typical voltage reference input QIN: reference voltage input. typical voltage output: (Pulse Width Modulation) `H/L' level output. This output external analog filter that controls amplifier tuner. Crystal oscillator input: Connect 27.0 crystal oscillator between these pins. used frequency internal multi-rate VCO. This crystal oscillator required when EXTCLK inputs 27.0 clock. When crystal oscillator used, CLKI CLKO must `OPEN' respectively. When crystal oscillator used, EXTCLK must `L'. External clock input: This inputs 27.0 clock frequency internal multi-rate VCO. crystal oscillator required when this used. When this EXTCLK used, must `L'. Transport data output: These pins transport stream packet data. User select output mode, either from 8-bit parallel data serial data output. When parallel output, user select position, TS0. When serial output, user select output position, TS7. selections done setting register. Transport clock output: This transport stream packet clock TS0. User select output mode that parallel serial clock, select clock polarity. selections done setting register. Transport enable output: This outputs during valid data packet, outputs during others such parity byte.
VRHI VRLI VRHQ VRLQ
CLKI CLKO
Crystal oscillator input
EXTCLK
External clock input
Transport packet data output
TCLK
Transport packet clock output
Transport packet enable
(Continued)
MB86660A
(Continued)
Symbol name Error indicator Function Error indicator output: This outputs period packet that ReedSolomon decoder could correct, outputs period packet that could correct. Frame synchronous output: This outputs when frame synchronized. Serial clock input Serial data Address input bus: These lower 3-bit address. upper 4-bit fixed with "0001". Reset input: MB86660A reset when this inputs `L'. must reset when power turned Refer Power-on Reset detail. clock output: This output twice clock symbol rate, same clock symbol rate, packet start signal. selections done setting register. This outputs initial stage. Test pin: This input test must connected `L'. Analog VDD: Analog internal A/Ds VCO. Analog VSS: Analog internal A/Ds VCO. Digital Digital
FSYNC
Frame synchronous output clock data address Reset input
ADR2 ADR1 ADR0 RESET
BCLK
clock output
TESTI AVDD AVSS
Test Analog Analog Digital Digital
MB86660A
BLOCK DIAGRAM
QPSK Block RESET VRHI VRLI VRLQ VRHQ
Block
Complex multiplier
Half Nyquist filter Half Nyquist filter
Energy-dispersal removal Reed-Solomon decoder TCLK FSYNC
Sync-byte decoder Deinterleaver
Viterbi decoder
Carrier recovery
recovery BCLK
CLKI CLKO EXTCLK
MB86660A
ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VDD, AVDD Rating Min. -0.5 -0.5 -0.5 Max. +4.0 +125 Unit
WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage High level input voltage level input voltage Operating temperature Symbol VDD, AVDD Value Min. 0.65 -0.3 Typ. Max. 0.25 Unit
WARNING: Recommended operating conditions normal operating ranges semiconductor device. device's electrical characteristics warranted when operated within these ranges. Always semiconductor devices within recommended operating conditions. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representative beforehand.
MB86660A
ELECTRICAL CHARACTERISTICS
Characteristics (VDD +3.3 +70°C unless otherwise specified) Value Conditions Unit Min. Max. Typ. 0.65 -0.3 0.25
Parameter Logic input Input high voltage Input voltage input (SDA SCL) Input high voltage Input voltage Input reference high voltage (for VRHI VRHQ) Input reference voltage (for VRLI VRLQ) Differential reference voltage Reference input resistance Analog input voltage (for QIN) Analog input capacitance (for QIN) Logic output Output high voltage Output voltage output (SDA) Output voltage
Symbol
-0.5
input (VRHI, VRHQ, VRLI, VRLQ, QIN)
IIN, Mbaud/s
Power supply current (VDD AVDD) Average power supply current T.B.D.
Typical values assume that +3.3 +25°C.
MB86660A
REGISTER TABLE
Register <I2C address: Register address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 (10) 00001011 (11) 00001100 (12)
ADR2
ADR1 (MSB)
MOD7
ADR0 function
MOD5
Access
Register name MODE-1 MODE-2 Viterbi Expansion Frame Sync.
MOD4 BCLK1 AGC4 VCO4 VIR4
MOD3 BCLK0 AGC3 VCO3 VIR3
MOD2 ER_EN AGC2 VCO2 VIR2
MOD1 RS_EN AGC1 VCO1 VIR1
MOD0 DI_EN AGC0 VCO0 VIR0
Reserved
Reserved Reserved Reserved Reserved VCO7 LVCO AGCP VCO6 AGCM VCO5
SYT3
SYT2 CA_2 CL_2
SYT1 CA_1 CL_1
SYT0 CA_0 CL_0 STA4
SYA3
SYA2 CA_2 CL_2 STA2
SYA1 CA_1 CL_1 QP_RST STA1
SYA0 CA_0 CL_0 LSI_RST STA0
Carrier Recovery CA_SW loop filter Coeff. Clock Recovery loop filter Coeff.
RESET Status Reserved
STA3
AFC7
AFC6
AFC5
AFC4
AFC3
AFC2
AFC1
AFC0
00010000 (16) 00010001 (17) 00010010 (18) 00010011 (19)
Reserved Start Carrier Coeff. Unused Coefficiency
CAS_2
CAS_1
CAS_0
CAS_2
CAS_1
CAS_0
AGC_2
AGC_1
AGC_0
AGC_2
AGC_1
AGC_0
Note: Don't care. (1): Initial value
MB86660A
FUNCTIONAL DESCRIPTION
MODE-1 User select output polarity TCLK, output mode setting register. Register value: address 0001ADR [2:0], Register address 00000000 name MOD0 MOD1 Function TCLK polarity Error indicator value (initial) (initial) MOD2 MOD3 MOD4 MOD5 Output mode Output order FSYNC output mode Frame sync-mode Reserved Data reverse switch (initial) (initial) (initial) (initial) bit6 MOD7 (initial) (initial) Operation latched falling edge TCLK. latched rising edge TCLK. error indicator flag transport stream packet when Reed-Solomon decoder cannot correct error. error indicator flag transport stream packet changed. Parallel output. Serial output. Another bits output `L'. when parallel. outputs when serial. when parallel. outputs when serial. FSYNC outputs frame synchronous signal. FSYNC outputs Viterbi synchronous signal. `B8(h)' frame sync-byte value changed `47(h)' inversely. `B8(h)' frame sync-byte value changed. Don't change. Normal operation. Received data reversed LSI.
[MOD0 function] MOD0 MOD0
TCLK
TCLK
(Continued)
MB86660A
(Continued)
[MOD1 function] structure transport packet
byte Packet header byte)
Transport packet
Sync.byte
Transport error indicator
Data
MOD1 This when Reed-Solomon decoder cannot correct error. MOD1 This changed.
[MOD5 function] MOD5
packet packet Packet Frame sync. sync. byte byte byte Frame Packet sync. sync. byte byte byte
packet Frame Packet sync. sync. byte byte byte
packet Frame Packet sync. sync. byte byte byte
byte
byte
byte
Reverse
Frame Packet sync. sync. byte byte byte Frame Packet sync. sync. byte byte byte
Reverse
Frame Packet sync. sync. byte byte byte
Reverse
Reverse
byte
byte
byte
Frame Packet sync. sync. byte byte byte
MOD5
packet packet Packet Frame sync. sync. byte byte byte Frame Packet sync. sync. byte byte byte
packet Frame Packet sync. sync. byte byte byte
packet Frame Packet sync. sync. byte byte byte
byte
byte
byte
Non-reverse
Frame Packet sync. sync. byte byte byte Frame Packet sync. sync. byte byte byte
Non-reverse
Frame Packet sync. sync. byte byte byte
Non-reverse
Frame Packet sync. sync. byte byte byte
byte
byte
byte
MB86660A
MODE-2 Deinterleaver, Reed-Solomon Energy dispersal removal functions passed through setting register. Register value: address 0001ADR [2:0], Register address 00000001 (10) name DI_EN RS_EN ER_EN Function Deinterleaver enable Reed-Solomon enable Energy dispersal removal enable value (initial) (initial) (initial) Operation Deinterleaver performed. Normal operation. Deinterleaver performed. Read-Solomon decoder performed. Normal operation. Reed-Solomon decoder performed. Energy dispersal removal performed. Normal operation. Energy dispersal removal performed.
BCLK output changed setting register. Register value: address 0001ADR [2:0], Register address 00000001 (10) name BCLK [1:0] Function BCLK output select value (initial) level output. Packet start signal output. Clock symbol rate output. same clock symbol rate output. Operation
prohibited change Register value: address 0001ADR [2:0], Register address 00000001 name Function Reserved value (initial) (initial) (initial) Don't change. Don't change. Don't change.
(10)
Operation
MB86660A
Status User monitor internal status. Register value: address 0001ADR [2:0], Register address 00001001 name STA0 STA1 [4:2] Function Frame synchronization Viterbi decode synchronization Viterbi rate detection value converter analog input data automatically sampled internal clock. Nyquist filter Digital half Nyquist filtering done each input signal. roll-off factor 0.35. (10), Read only
Operation shows Frame isn't synchronization. shows Frame synchronization. shows Viterbi decoder isn't synchronization. shows Viterbi decoder synchronization. shows Viterbi decoder isn't synchronization. shows Viterbi rate 1/2. shows Viterbi rate 2/3. shows Viterbi rate 3/4. shows Viterbi rate 5/6. shows Viterbi rate 7/8.
MB86660A
amplitude input data compared with reference value [4:0] register. compared result output (Pulse Width Modulation) form `H/L' level. adjusts amplifier gain tuner external analog filter. pulse width output changed 1/(2Fs) (µs) step (n=0 255, symbol rate (Msymbol/ s)). frequency Fs/128 (MHz). pulse width 'H/L' level output changed minimum 4/Fs (µs) step (Fs: symbol rate (Msymbol/s)). frequency maximum Fs/4 (MHz). response rapider than PWM, useful quick response request. reference value [4:0] output polarity programmable. Register value: address 0001ADR [2:0], Register address 00000010 (10) name [4:0] Function Reference value value 00000 10000 (initial) 11111 AGCM AGCP output mode output polarity (initial) (initial) Maximum reference value. output. `H/L' level output. When [4:0] Amplitude input data: When AGCM (PWM output), repeatedly outputs pulse that period longer than period. When AGCM (`H/L' level output), outputs `H'. When [4:0] Amplitude input data: When AGCM (PWM output), repeatedly outputs pulse that period longer than period. When AGCM (`H/L' level output), outputs `L'. When [4:0] Amplitude input data: When AGCM (PWM output), repeatedly outputs pulse that period longer than period. When AGCM (`H/L' level output), outputs `L'. When [4:0] Amplitude input data: When AGCM (PWM output), repeatedly outputs pulse that period longer than period. When AGCM (`H/L' level output), outputs `H'. Reserved (initial) this bit. amplifier gain tuner adjusted equal reference value. Minimum reference value. Operation
(Continued)
MB86660A
Some external AGC-loop configuration user systems need adjust filter value using following register. Register value: address 0001ADR [2:0], Register address 00010011 (10) name AGC_ [2:0] Function -Coefficiency loopfilter value (default) AGC_ [2:0] -Coefficiency loopfilter (default) Block Diagram AGC:
AGC_ [2:0]
Operation
128)
Detector
AGC_ [2:0]
(Continued)
MB86660A
output wave form: pulse width changed 1/(2Fs) (µs) step 255, symbol rate (Msymbol/s). frequency Fs/128 (MHz).
AGCP 1/(2Fs) (µs) [4:0] When difference amplitude [4:0] max. 1/(2Fs) (µs) 1/(2Fs) (µs) AGCP 1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
[4:0]
1/(2Fs) (µs) 1/(2Fs) (µs)
1/(2Fs) (µs) 1/(2Fs) (µs)
When amplitude [4:0].
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
[4:0] 1/(2Fs) (µs) 1/(2Fs) (µs) 1/(2Fs) (µs) 1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs) 1/(2Fs) (µs)
[4:0] When difference [4:0] amplitude max. symbol rate (Msymbol/s)
level
level
(Continued)
MB86660A
(Continued)
`H/L' level output wave form: pulse width changed minimum 4/Fs (µs) step (Fs: symbol rate) frequency Fs/8 (MHz)
AGCP 4/Fs (µs) [4:0] Amp. AGCP 4/Fs (µs)
level
level
4/Fs (µs) [4:0] Amp. level symbol rate (Msymbol/s)
4/Fs (µs)
level
MB86660A
Carrier recovery difference carrier recovery tuner automatically recovered LSI. loop filter coefficient carrier recovery operates with CAS_ [2:0] CAS_ [2:0] first then automatically switches [2:0] [2:0] after lock-up. However, when CA_SW "0", filter coefficient always operates with [2:0] [2:0]. loop filter variable. Register value: address 0001ADR [2:0] <Register address 00010001(2) 17(10)> name Function value Operation CAS_ [2:0] -factor loop filter first (initial) CAS_ [2:0] -factor loop filter first (initial) (=2) (=4) (=8) (=16) (=32) (=64) (=256) (=512) (=1024) (=2048) (=4096) (=8192) CA_SW Carrier Recovery Block Diagram: Loop filter [2:0] -factor loop filter after lock-up <Register address 00000110(2) 6(10)> name Function value Operation [2:0] -factor loop filter after lock-up (initial) (initial) 1(initial) CAS_ [2:0] [2:0] Phase Detector Sin/Cos table (=2) (=4) (=8) (=16) (=32) (=64) (=256) (=512) (=1024) (=2048) (=4096) (=8192) Auto Auto
CAS_ [2:0] [2:0]
MB86660A
User monitor difference local oscillator frequency tuner. different frequency tuner calculated following reading register [7:0]. (KHz) (128 [7:0]) 82.474 (n/42.192) Receiving rate (Mbps)) Ex.1: When [7:0] 01111100 Receiving rate (Mbps), (DEC) 312.8 (KHz) shows local oscillator frequency tuner 312.8KHz higher. Ex.2: When [7:0] 10000101 Receiving rate (Mbps), (DEC) -586.4(KHz) shows local oscillator frequency tuner 586.4KHz lower. Register value: address 0001ADR [2:0], Register address 00001010 (2), Read only name [7:0] Function difference carrier frequency value 00000000 00000001 01111111 10000000 10000001 11111110 11111111 shows local oscillator frequency tuner very low. shows local oscillator frequency tuner almost fit. Operation shows local oscillator frequency tuner very high.
MB86660A
Clock recovery clock synchronized base band data automatically recovered LSI. internal must required frequency advance. Refer `10. VCO' setting internal frequency. Loop filter variable. Register value: address 0001ADR [2:0], Register address 00000111(2) 7(10) name [2:0] Function -factor clock recovery loop filter value (initial) 110, [2:0] -factor clock recovery loop filter (initial) 110, Clock Recovery Block Diagram: (=512) (=1024) (=2048) (=4096) (=8192) (=16384) Prohibited (=131072) (=262144) (=524288) (=1048576) (=2097152) (=4194304) Prohibited Operation
[2:0] Phase Detector
[2:0]
MB86660A
internal frequency must times received data symbol rate. Because frequency step every step, nearest frequency. E.X.: When received data symbol rate 21.096 Msym/s, 42.2 21.096 Msym/s 42.192 Register value: adress 0001ADR [2:0], Register address 00000011(2) 3(10) 00000100(2) 4(10) name [7:0] Function Freq. (0.1 step) value 00000000 00000001 00000110 00010110 01000100 01110100 10010110 10100010 11001000 11011000 11100000 11111110 11111111 Operation LVCO register Internal 40.0 MHz. Internal 40.1 MHz. Internal 40.6 MHz. Internal 42.2 MHz. (Initial value) Internal 46.8 MHz. Internal 51.6 MHz. Internal 55.0 MHz. Internal 56.2 MHz. Internal 60.0 MHz. Internal 61.6 MHz. Internal 62.4 MHz. Internal 65.4 MHz. Internal 65.5 MHz. 36.0 36.8 39.8 39.9 LVCO register
MB86660A
RESET whole block QPSK-Block only reset when LSI_RST QP_RST `1'. Register value: address 0001ADR [2:0], Register address 00001000 8(10) name LSI_RST Function whole Software reset QPSK Block Software reset value Operation whole reset when LSI_RST `1'.
QP_RST
QPSK-Block only reset when QP_RST `1'.
Viterbi decoder Constraint length Optionally some Viterbi rates selected from 1/2, 2/3, 3/4, 7/8. receiving Viterbi rate automatically detected from some selected Viterbi rates. getting longer detect proportion number selected rates. recommended select rate, rate known beforehand. detected Viterbi rate written [4:2] register which shown Status'. Register value: address 0001ADR [2:0], Register address 00000100 4(10) name VIR0 VIR1 VIR2 VIR3 VIR4 Function setting setting setting setting setting value (initial) (initial) (initial) (initial) (initial) Operation Viterbi rate detection performed 1/2. Viterbi rate detection performed 1/2. Viterbi rate detection performed 2/3. Viterbi rate detection performed 2/3. Viterbi rate detection performed 3/4. Viterbi rate detection performed 3/4. Viterbi rate detection performed 5/6. Viterbi rate detection performed 5/6. Viterbi rate detection performed 7/8. Viterbi rate detection performed 7/8.
MB86660A
monitor approximate value input monitored. monitored value depends evaluation circumstance, mounting conditions, user application system. Therefore, value must carefully checked before user's finished product. typical characteristic curve shown below. Register value: address 0001ADR [2:0], Register address 00001011 11(10), Read only name [7:0] Function monitor value 00000000 11111111 shows error receiving data small. Operation shows error receiving data large.
Monitor Characteristics
[7:0] Read Value
(dB) Note: [7:0] Read Value transferred decimal value.
MB86660A
Frame synchronization frame synchronization signal (B8h) head packets detected. number states acquisition tracking programmable. judged lock synchronization signal would continuously detected number acquisition states, then FSYNC changing (when MOD4 (Register address: 00000000) `0'). After lock, judged lock synchronization signal would continuously detected number tracking states, then FSYNC changing `L'. Register value: address 0001ADR [2:0], Register address 00000101 5(10) name [3:0] Function Number acquisition states value 0000,0001, 0010 (initial) 1111 [3:0] Number tracking states 0000 0010 1111 (initial) Timing judged lock synchronization signal would continuously detected fifteen times. judged lock synchronization signal would continuously detected fifteen times. judged lock synchronization signal would continuously detected times. Operation judged lock synchronization signal would continuously detected times.
packet packet Sync. Sync. -byte -byte byte byte byte byte Frame sync. (B8h) (47h)
packet Sync. Sync. -byte -byte byte byte byte (47h) byte Sync. -byte byte (47h) Sync. -byte byte byte
packet byte Sync. -byte byte (47h) Sync. -byte byte byte
Frame sync. (B8h)
Frame sync. (B8h)
FSYNC
Frame sync. (B8h)
frame-sync continuously detected number acquisition states.
frame-sync continuously detected number tracking states.
Deinterleaver deinterleaving depth byte-stream. When DI_EN (Register address =00000001) `0', Deinterleaver performed. When DI_EN `1', Deinterleaver performed.
MB86660A
Reed-Solomon decoder 204, 188, Code Generator Polynomial: Field Generator Polynomial: total errors less than bytes bytes unit, errors corrected. total errors more than bytes, errors corrected. outputs packet that errors were corrected. outputs packet that errors were corrected. distinguish parity bytes Reed-Solomon, outputs period valid data, then outputs period parity bytes. When RS_EN (Register address: 00000001) `0', Reed-Solomon decoder performed errors corrected. operates normally, outputs `L'. When RS_EN `1', Reed-Solomon decoder performed. Timing
Corrected Packet
Uncorrected packet Data byte
Corrected Packet Data byte Parity Sync. -byte byte byte
Sync. -byte byte
Data byte
Parity Sync. -byte byte byte
Parity Sync. -byte byte byte
TCLK (when RSEN `1') (when RSEN `0')
level
Energy dispersal removal When ER_EN (Register address: 00000001) `0', Energy dispersal removal performed. When ER_EN `1', Energy dispersal removal performed. Pseudo Random Binary Sequence (PRBS) Polynomial: polynomial initialized into sequence `100101010000000' every eight packets.
MB86660A
Write format
address (LSI) address-1 Register Data-1 address-2 (LSI) (LSI) Register Data-2 -ACK (LSI) (LSI) (LSI)
Write register address-1
Write register address-2
Read format
address (LSI) address-1 Register (LSI) address (LSI) (LSI) Data-1
register address-1 before reading
Read register address-1
address
(LSI)
Register
(LSI)
address
(LSI)
(LSI) Data-2
address-2
register address-2 before reading
Read register address-2
Note: Start condition address (7bit): 0001 (ADR2) (ADR1) (ADR0) [2:0]: user setting (1bit): write, read Data-n (8bit): Data register address-n ACK: Acknowledge Stop condition Output signal master (LSI): Output signal MB86660A
MB86660A
OUTPUT SIGNAL TIMING
Corrected Packet
Uncorrected packet Data byte
Corrected Packet Data byte Parity Sync. -byte byte byte
TCLK BCLK (when BCLK [1:0] `01')
Sync. -byte byte
Data byte
Parity Sync. -byte byte byte
Parity Sync. -byte byte byte
FSYNC
level
Note: TCLK polarity changed setting register.
MB86660A
POWER-ON RESET
MB86660A must reset RESET when power turned Apply reset signal power-on, then cancel reset after AVDD have reached input reset pulse with width after they reached Note that 27.0 clock crystal oscillator external clock EXTCLK must stable before reset canceled. (See diagram below.)
VDD, AVDD VDD, AVDD
more
(inactive) RESET (active) Stable clock clock Select either RESET (inactive) (active) more Stable clock clock (inactive)
MB86660A
APPLICATION EXAMPLE
When crystal oscillator used.
Tuner
TCLK CLKO
Demultiplexer MPEG2 decoder
MB86660A
deg. shifter L.O. CLKI
X'tal
When external clock used.
Tuner
Demultiplexer MPEG2 decoder
MB86660A
deg. shifter L.O. EXTCLK
TCLK
clock
MB86660A
PERIPHERAL CIRCUIT EXAMPLE
line
FSYNC RESET TCLK VIEW AVSS AVDD CLKI CLKO EXTCLK TESTO ADR2 TESTI ADR1 ADR0
VRHI AVSS AVDD VRLI
VRLQ AVDD AVSS VRHQ
Analog
X'tal
Digital
Notes: analog digital power supplies should separated each pattern should sufficient wide. Connect bypass capacitors with good high frequency characteristics AVDD AVSS. Connect analog digital power supply pattern point such above illustration. Connect bypass capacitors with good high frequency characteristics between analog `AVSS' VRHI, VRLI, VRHQ VRLQ which reference voltage A/Ds. most important stabilize reference voltage A/D. Furthermore, recommended connect large value about AVSS. board with 4-layer more.
MB86660A
PACKAGE DIMENSION
48-pin plastic (FPT-48P-M15)
15.30±0.40 (.602±.016) +0.30 12.00 -0.10 +.012 .472 -.004
2.70(.106)MAX 0.05(.002)MIN (STAND OFF)
Details part 0.15(.006) 8.80 (.346)
13.60±0.40 (.535±.016)
0.20(.008) 0.15(.006)MAX 0.50(.020)MAX
INDEX
Details part LEAD
0.80(.0315)TYP
0.30±0.06 (.012±.002)
0.16(.006)
0.15 -0.01 +.002 .006 -.0004 0.85±0.30 (.033±.012)
+0.05
0~10°
0.10(.004)
1994 FUJITSU LIMITED F48025S-1C-1
Dimensions (inches)
MB86660A
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inherently certain rate failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Control Japan, prior authorization Japanese government should required export those products from Japan.
http://www.fujitsu.co.jp/
North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9802 FUJITSU LIMITED Printed Japan

Single-chip Demodulator Digital Satellite Broadcasting MB86660A D

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