Devices September 2005, ver. Introduction MAX® devices

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Devices September 2005, ver. Introduction MAX® devices

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In-System Programmability
Devices
September 2005, ver.
Introduction
MAX® devices programmable logic devices (PLDs), based Altera® Multiple Array MatriX (MAX) architecture that supports IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. devices also in-system programmable, which adds programming flexibility provides benefits many phases product development, manufacturing, field use. This application note provides background information in-system programmability (ISP) IEEE Std. 1149.1 JTAG interface discusses advantages using ISP-capable devices. In-system design, prototyping, manufacturing, reduces cost, shortens development time, provides wider range programming options than standard device programming methods. With ISP, can:
Features Benefits
Program reprogram devices after they soldered onto printed circuit board (PCB), minimizing possibility lead damage electrostatic discharge (ESD) exposure. Manufacture systems before finalize device configuration. Perform boundary-scan test (BST) procedures program devices using in-circuit testers. Upgrade systems field after they have been shipped.
Altera Corporation
A-AN-095-1.5
In-System Programmability Devices
Table describes features benefits using ISP-capable devices. Table ISP-Capable Device Features Benefits Product Development Phase
Device prototyping
Features
Benefits
Devices programmed with VCC-level Eliminates need 12.0-V programming voltage. programming voltage possibility accidental damage lower voltage parts. Also reduces system power requirements. Devices programmed while soldered PCB. Prototype systems assembled before device configuration finalized. Minimizes device handling, thereby protecting devices from lead damage. Cuts prototype development time saves development costs. Simplifies manufacturing, saves time, protects devices from lead damage.
System manufacturing PLDs treated same other board-level devices because they programmed after assembled. implemented using IEEE Std. 1149.1 (JTAG) interface; therefore, circuit testing device programming combined into single manufacturing step using standard in-circuit tester. Programming data downloaded from in-circuit testers, PCs, workstations during final test. Devices programmed with test configurations. In-field programming
Enhances design debugging boardlevel testing capabilities.
Devices reprogrammed field. Adds versatility reduces service costs, thereby making products more attractive consumer.
VCC-Level Programming
ISP-capable devices support through VCC-level programming voltage. devices generate 12.0-V programming voltage internally program, verify, erase device's EEPROM cells, eliminating need external 12.0-V programming voltage typically required programming. ISP-capable devices guaranteed erase programming cycles with 100% programming functional yields.
Altera Corporation
In-System Programmability Devices
Programming Systems
Altera devices, implemented using IEEE Std.1149.1 JTAG interface, which streamlines testing device programming operations into single manufacturing step. ISP-capable devices supported following systems:
MAX+PLUS development system In-circuit testers Embedded processors
MAX+PLUS Development System
UNIX workstation, MAX+PLUS Programmer, BitBlasterserial ByteBlasterMVparallel port download cable download Programmer Object Files (.pof), Files (.jam), JamByte-Code Files (.jbc)from MAX+PLUS software ISPcapable devices mounted PCB. This method more costeffective than other programming methods because design, simulation, prototyping performed using same UNIX workstation-based system. production, implement using Altera's free stand-alone programming software BitBlasterMV cable download POFs. PC-based stand-alone programming software, asap2.exe, available from Altera's site ftp.altera.com \pub\misc directory.
Figure shows 10-pin female plug dimensions BitBlaster ByteBlasterMV download cable.
Altera Corporation
In-System Programmability Devices
Figure 10-Pin Female Plug Dimensions
Dimensions shown inches. spacing between centers inch.
0.425 Typ.
Color Strip
0.250 Typ.
0.100 0.700 Typ.
0.025
Table identifies 10-pin female plug's names corresponding download mode. Table Female Plug's Names Download Modes JTAG Mode Signal Name
Mode Signal Name
DCLK CONFIG_DONE nCONFIG nSTATUS DATA0
Description
Clock signal Signal ground Data from device Power supply JTAG state machine control connect connect connect Data device Signal ground
Description
Clock signal Signal ground Configuration control Power supply Configuration control connect Configuration status connect Data device Signal ground
circuit board must supply ground ByteBlasterMV cable.
Altera Corporation
In-System Programmability Devices
ISP-capable devices programmed device's JTAG pins: TCK, TMS, TDI, TDO. Figure shows BitBlaster ByteBlasterMV download cable interfaces with ISP-capable device. pins tri-stated during in-system programming. Figure ISP-Capable Device Programming with BitBlaster ByteBlasterMV Download Cable
Target Altera Device
10-Pin Male Header (Top View)
Search "Programming Single Device with BitBlaster ByteBlasterMV" MAX+PLUS Help, BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet this handbook more information.
In-Circuit Test Programming
program ISP-capable devices during final testing stage using in-circuit testers IEEE Std. 1149.1 (JTAG) interface. program device using in-circuit testers, create File with MAX+PLUS software download this file from in-circuit test station more ISP-capable devices.
Embedded Processor Programming
program ISP-capable devices in-system using embedded processor. example, programming information stored EPROM shifted into ISP-capable device using 4-bit interface from processor device's JTAG pins. This method lets program devices during burn-in upgrade devices field.
Altera Corporation
In-System Programmability Devices
program devices with embedded processor creating File from MAX+PLUS software downloading with Player.
IEEE Std. 1149.1 Interface
Refer 122: Using STAPL Embedded Processor more information embedded processor programming. device JTAG pins functions described Table
Table JTAG Pins
Description
Test data input
Function
Serial input data instructions, which shifted rising edge TCK. This signal needs externally pulled high during normal operation. Serial data output instructions data. Data shifted falling edge TCK. This signal tri-stated data being shifted device.
Test data output
Test mode select Input controls IEEE Std. 1149.1 JTAG state machine evaluated rising edge TCK. This signal needs externally pulled high during normal operation. Test clock Provides clock signal JTAG circuits. maximum operating frequency MHz. This signal needs externally pulled during normal operation.
During erasure, programming, verification, device pins tri-stated eliminate interference from other devices PCB. Devices programmed applying appropriate signals inputs shifting data into devices pins, respectively. After programming, IEEE Std. 1149.1 JTAG Test Access Port (TAP) controller state machine must advanced RESET state, which maintained external pull-up resistors TCK, TMS, pins. During normal operation, pull-up resistors prevent device from entering other modes. Figure shows timing waveforms IEEE Std. 1149.1 JTAG controller state machine.
Altera Corporation
In-System Programmability Devices
Figure JTAG Waveforms Devices
tJCP tJCH tJCL tJPSU tJPH
tJPZX tJPCO tJPXZ
tJSSU tJSH
Signal Captured Signal Driven
tJSZX
tJSCO
tJSXZ
Table shows JTAG timing parameters values ISP-capable devices. Table JTAG Timing Parameters Values Devices Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
IEEE Std.1149.1 (JTAG) Boundary-Scan Testing Altera Devices information IEEE Std.1149.1 JTAG controller state machine.
Altera Corporation
In-System Programmability Devices
Programming ISP-Capable Devices
IEEE Std.1149.1 JTAG-compatible header program single device chain devices, depending layout your PCB.
Single-Device Programming
PCBs that contain single ISP-capable device, JTAG-compatible header-such 10-pin BitBlaster ByteBlasterMV header-can used program device. Figure
Altera Corporation
In-System Programmability Devices
Figure Single-Device Programming
Target Device
IEEE Std. 1149.1 JTAG Interface
JTAG-Chain Device Programming
When programming chain devices, JTAG-compatible plug, such BitBlaster ByteBlasterMV 10-pin male plug, connected several devices. number devices JTAG chain limited only drive capability BitBlaster ByteBlasterMV download cable. However, when three more devices connected JTAG chain, Altera recommends buffering TDO,TCK, TDI, pins. JTAG-chain device programming ideal when circuit board contains multiple devices, when circuit board tested using JTAG BST. Figure
Altera Corporation
In-System Programmability Devices
Figure JTAG-Chain Device Programming with BitBlaster ByteBlasterMV Cable
ByteBlaster 10-Pin Male Header
Other IEEE Std. 1149.1 JTAGCompliant Device
Target Altera Device
Other IEEE Std. 1149.1 JTAGCompliant Device
program single ISP-capable device JTAG chain, programming software puts other devices JTAG chain BYPASS mode. When BYPASS mode, devices pass programming data from through single bypass register. Bypassed devices affected internally, thereby enabling programming software erase, program, verify target device.
Conclusion
toAN IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices more information BYPASS mode. ISP-capable devices offer benefits product design, prototyping, manufacturing. simplifies manufacturing flow allowing devices mounted with standard pick-and-place equipment before they programmed. ISP-capable devices programmed downloading information in-circuit testers, embedded processors, BitBlaster ByteBlasterMV download cables. addition, programming these devices after they placed board eliminates lead damage high pin-count packages, e.g., quad flat pack (QFP) packages, device handling. These devices also reprogrammed field (i.e., product upgrades performed field software modem).
Altera Corporation
In-System Programmability Devices
Innovation Drive Jose, 95134 (408) 544-7000 www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: literature@altera.com
Printed Recycled Paper.
Copyright 2005 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
Altera Corporation

Devices September 2005, ver. Introduction MAX® devices

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