programmable logic devices (PLDs) increase density pins, demand small
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Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
programmable logic devices (PLDs) increase density pins, demand small packages diverse packaging options continues grow. Ball-grid array (BGA) packages ideal solution because connections interior device, improving ratio between count board area. Typical packages contain twice many connections quad flat pack (QFP) packages same area. Further, solder balls considerably stronger than leads, resulting robust packages that tolerate rough handling. Altera developed high-density solutions users high-density PLDs. These formats require less than half board space standard packages. This application note provides guidelines designing your printed circuit board (PCB) Altera's high-density packages discusses:
Overview Packages Layout Terminology Layout High-Density Packages
Overview Packages
packages, connections located interior device. Leads normally placed along periphery package replaced with solder balls arranged matrix across bottom substrate. final device soldered directly using assembly processes that virtually identical standard surface mount technology preferred system designers. Additionally, packages provide following advantages:
Fewer damaged leads-BGA leads consist solid solder balls, which less likely suffer damage during handling. More leads unit area-Lead counts increased moving solder balls closer edges package decreasing pitch flip-chip BGAs micro-BGAs.
Altera Corporation AN-114-3.0
Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
Less expensive surface mount equipment-BGA packages tolerate slightly imperfect placement during mounting, requiring less expensive surface mount equipment. placement imperfect because packages self-align during solder reflow. Smaller footprints-BGA packages usually smaller than packages, making packages more attractive applications that require high performance smaller footprint. Integrated circuit speed advantages-BGA packages operate well into microwave frequency spectrum achieve high electrical performance using ground planes, ground rings, power rings package construction. Improved heat dissipation-Because located center package most pins located center package, pins located under die. result, heat generated device transferred through pins (i.e., pins heat sink).
Layout Terminology
This section defines common terms used layout that need know design with Altera's high-density BGAs.
Escape Routing
Escape routing method used route each signal from package another element PCB.
Multi-Layer PCBs
increased count associated with packages made multi-layer PCBs industry-standard method performing escape routing. Signals routed other elements through various numbers layers.
Vias
Vias, plated through holes, used multi-layer PCBs transfer signals from layer another. Vias actual holes drilled through multi-layer provide electrical connections between various layers. vias provide layer-to-layer connections only. Device leads other reinforcing materials inserted into vias.
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Layout Terminology
Table describes terms used define dimensions.
Table Dimension Terms Term
Aspect ratio Drilled hole diameter Finished diameter
Definition
ratio via's length depth pre-plated diameter final diameter actual hole drilled board final diameter hole after been plated
Table shows three types typically used PCBs.
Table Types Type
Through
Description
interconnection between bottom layer PCB. Vias also provide interconnections inner layers. interconnection from bottom layer inner layer. interconnection between numbers inner layers.
Blind Embedded
Figure shows three types. Figure Types Vias
Through Blind Embedded
Connection Layer Layers
Altera Corporation
Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
Blind vias through vias used more frequently than embedded vias. Blind vias more expensive than through vias, overall costs reduced when signal traces routed under blind via, requiring fewer layers. Through vias, other hand, permit signals routed through lower layers, which increase required number layers overall costs.
Capture
Vias connected electrically layers through capture pads that surround each via.
Surface Land
Surface land pads areas which solder balls adhere. size these pads affects space available vias escape routing. general, surface land pads available following basic designs:
solder mask defined (NSMD), also known copper defined Solder mask defined (SMD)
main differences between surface land types size trace space, type vias use, shapes solder balls after solder reflow.
Solder Mask Defined
NSMD pad, solder mask opening larger than copper pad. Thus, surface land pad's copper surface completely exposed, providing greater area which solder ball adhere (see Figure Altera recommends that NSMD most applications because provides more flexibility, fewer stress points, more line-routing space between pads.
Solder Mask Defined
pad, solder mask overlaps surface land pad's copper surface (see Figure page This overlapping provides greater adhesion strength between copper PCB's epoxy/glass laminate, which important under extreme bending during accelerated thermal cycling tests. However, solder mask overlap reduces amount copper surface available solder ball.
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Layout Terminology
Figure Side View NSMD Land Pads
NSMD Solder Mask Solder Mask Opening Copper Solder Solder Mask Mask Opening Copper
Figure shows side view NSMD solder joint. Figure Side View NSMD Solder Joints
NSMD Solder Joint Solder Joint
Package Solder Ball Solder Mask Copper
Stringer
Stringers rectangular square interconnect segments that electrically connect capture pads surface land pads. Figure shows connection between vias, capture pads, surface land pads, stringers. Figure Via, Land Pad, Stringer Capture
Stringer Capture
Surface Land
Altera Corporation
Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
Layout High-Density Packages
When designing high-density packages, consider following factors:
Surface land dimension capture layout dimension Signal-line space trace width Number layers Controlling dimension calculated millimeters high-density figures
Surface Land Dimension
Altera done extensive modeling simulation experimental studies determine optimum land design provide longest solder joint fatigue life. results these studies show that design that provides balanced stress solder joint provides best solder joint reliability. Since pads solder mask defined, pads used PCB, surface land pads should same size provide balanced stress solder joints. non-solder mask defined pads used PCB, land pads should approximately smaller than size achieve balanced stress solder joints. Table page lists recommended sizes NSMD land patterns. should NSMD pads high-density board layouts because smaller sizes allow more space between vias trace routing. example, Figure page shows space available vias escape routing when NSMD surface land pads 1.00-mm flip-chip BGA. Figure Dimensions
Substrate
Solder Ball
Altera Corporation
Layout High-Density Packages
Table shows recommended sizes NSMD land patterns.
Table Recommended Sizes NSMD Pads Pitch
1.27 (Plastic Ball Grid Array (PBGA)) 1.27 (Super Ball Grid Array (SBGA)) 1.27 (Tape Ball Grid Array (TBGA)) 1.27 (flip-chip) 1.00 (wirebond) 1.00 (flip-chip) 1.00 (flip-chip) APEX 20KE 0.80 UBGA Substrate) 0.80 UBGA (EPC16U88) Note Table
Opening Solder Ball (mm) Diameter (mm)
0.60 0.60 0.60 0.65 0.45 0.55 0.60 0.75 0.75 0.75 0.75 0.63 0.63 0.65 0.55 0.45
Recommended Size (mm)
0.60 0.60 0.60 0.65 0.45 0.55 0.60
Recommended NSMD Size (mm)
0.51 0.51 0.51 0.55 0.38 0.47 0.51 0.34 0.34
FineLine BGA® packages that flip-chip technology marked "Thermally Enhanced FineLine BGA" wirebond packages marked "Non-Thermally Enhanced FineLine BGA" Altera Device Package Information Data Sheet.
Altera Corporation
Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
Figure Routing Space Available 1.00-mm Flip-Chip NSMD Land Pads
1.00 (39.37 mil)
0.53 (21.20 mil)
0.94 (37.60 mil)
1.00 (39.37 mil)
urface Land Pads
Capture Layout Dimension
size layout capture pads affect amount space available escape routing. general, capture pads following ways:
In-line with surface land pads
Diagonal surface land pads.
Figure shows both layouts 1.00-mm flip-chip NSMD land pads.
Altera Corporation
Layout High-Density Packages
Figure Placement Capture 1.00-mm Flip-Chip NSMD Land Pads
Line
Surface land capture Vias Stringer 1.00 (39.37 mil) 1.00 (39.37 mil)
Diagonally
Stringer length Stringer width Minimum clearance between capture surface land capture diameter Trace width Space width Area escape routing (This area different layer than surface land pads.)
0.53 (21.20 mil) 1.00 (39.37 mil) 0.47 (18.80 mil)
0.47 (18.80 mil)
decision place capture pads diagonally in-line with surface lands pads based following factors:
Diameter capture Stringer length Clearance between capture surface land
decide your PCB, information shown Figure Table your design guidelines conform either equation Table contact Altera® Applications further assistance.
Table Formula Layouts 1.00-mm Flip-Chip NSMD Land Pads Layout
In-line Diagonally 0.53 0.94
Formula
Table shows that place larger capture diagonally than in-line with surface land pads.
Altera Corporation
Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
capture size also affects many traces routed PCB. Figure shows sample layouts typical premium capture pads. typical layout shows capture size 0.66 size 0.254 inner space trace 0.102 With this layout, only trace routed between vias. more traces required, must reduce capture size space trace size. premium layout shows capture size 0.508 size 0.203 inner space trace 0.076 This layout provides enough space route traces between vias. Figure Typical Premium Capture Sizes 1.00-mm Flip-Chip
Typical
39.37
Premium
39.37 Capture Space Trace
10.00 26.00
8.00 20.00
15.00
Table shows typical premium layout specifications used most vendors.
Table Vendor Specifications Specification
Trace space width Drilled hole diameter Finished diameter capture Aspect ratio
Typical (mm)
0.127/0.127 0.305 0.254 0.66
Premium (mm)
0.076/0.076 0.254 0.203 0.508 10:1
Altera Corporation
Layout High-Density Packages
detailed information drill sizes, sizes, space trace sizes, capture sizes, contact your vendor directly.
Signal Line Space Trace Width
ability perform escape routing defined width trace minimum space required between traces. minimum area signal routing smallest area that signal must routed through (i.e., distance between vias, Figure This area calculated following formula: (BGA pitch) number traces that routed through this area based permitted line trace space widths. Table determine total number traces that routed through
Table Number Traces Number Traces
Formula
(space width)] trace width (space width)] (trace width)] (space width)] (trace width)]
Figure shows that reducing trace space size, route more traces through Increasing number traces reduces required number layers decreases overall cost. Figure Escape Routing Double Single Traces 1.00-mm Flip-Chip
Double Trace Routing
(4.2 mil) 0.40 (15.75 mil) 0.53 (21.20 mil) 0.47 (18.80 mil) 0.47 (18.80 mil)
Single Trace Routing
0.18 (7.07 mil) 0.47 (18.80 mil) 0.53 (21.20 mil) Capture Space Trace
Altera Corporation
Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
Number Layers
general, number layers required route signals inversely proportional number traces between vias (i.e., more traces used, fewer layers required). estimate number layers your requires first determining:
Trace space size Number traces routed between capture pads Type vias used
Using fewer pins than maximum reduce required number layers. type selected also reduce number layers required. type affect required number layers, consider sample layouts shown Figure Figure Sample Layout 1.00-mm Flip-Chip
Blind
signal from Ball routed under second layer. Ball Ball Ball Ball Ball
18.80-mil Surface Land 26-mil Capture 10-mil
5-mil Trace
Through
signal from Ball routed through third layer. Ball Ball Ball Ball Ball
Signal travels through first layer Signal travels through second layer Signal travels through third layer
blind layout Figure requires only layers. signals from first balls routed directly through first layer. signals from third fourth balls routed through
Altera Corporation
Conclusion
second layer, signal from fifth ball routed under vias third fourth balls second layer. Together, only layers required. contrast, through layout Figure requires three layers, because signals cannot routed under through vias. signals from third fourth balls still routed through second layer, signal from fifth ball must routed through third layer. Using blind vias rather than through vias this example saves layer.
Conclusion
Altera taken leadership position packaging with introduction high-density packages. These packages reduced area while maintaining very high count. using information this application note, easily design PCBs high-density packages, take advantage package's reduced size. Yuan Anil Pannikkat, Larry Anderson, Tarun Verma, Bruce Euzent, Building Reliability Into Full-Array BGA's, 26th IEMT Symposium, PackCon 2000.
References:
Revision History
Version
Information contained 114: Designing with High-Density Packages Altera Devices version supersedes information published previous versions. Version 114: Designing with High-Density Packages Altera Devices contains following changes:
Changed title Designing with High-Density Packages Altera Devices from Desigining with FineLine Packages Updated document reflect change opening diameter 1.00-mm flip-chip 0.55 Added Table include design guidelines pitches Updated layout High-Density Packages section Updated document show dimensions millimeter (mm) units
Version
Version 114: Designing with FineLine Packages contains following changes: updated Figure
Altera Corporation
Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
Version
Version 114: Designing with FineLine Packages contains following changes: updated Table
Version 1.03
Version 1.03 114: Designing with FineLine Packages contains following changes:
Dimensions Figure Tables were updated Minor textual style changes were made throughout document
Version 1.02
Version 1.02 114: Designing with FineLine Packages contains following changes:
dimension solder ball Figure updated surface land size Figure updated
Version 1.01
Version 1.01 114: Designing with FineLine Packages contains following changes:
Information Table updated Minor textual style changes were made throughout document
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Revision History
Altera Corporation
Designing With Fineline Packages APEX, FLEX, ACEX, 7000 3000 Devices
Innovation Drive Jose, 95134 (408) 544-7000 www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com
Copyright 2005 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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