EBJ52UD6CASA, EBJ52UD6BASA (64M words bits, Ranks) Density: 512MB

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EBJ52UD6CASA, EBJ52UD6BASA (64M words bits, Ranks) Density: 512MB

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512MB DDR3 SDRAM SO-DIMM
EBJ52UD6CASA, EBJ52UD6BASA (64M words bits, Ranks)
Density: 512MB Organization words bits, ranks Mounting pieces 512M bits DDR3 SDRAM sealed FBGA Package: 204-pin socket type small outline dual line memory module (SO-DIMM) height: 30.0mm Lead pitch: 0.6mm Lead-free (RoHS compliant) Power supply: 1.5V 0.075V Data rate: 1333Mbps/1066Mbps/800Mbps (max.) Eight internal banks concurrent operation (components) Interface: SSTL_15 Burst lengths (BL): with Burst Chop (BC) /CAS Latency (CL): /CAS write latency (CWL): Precharge: auto precharge option each burst access Refresh: auto-refresh, self-refresh Refresh cycles Average refresh period 7.8s +85°C 3.9s +85°C +95°C Operating case temperature range +95°C
Features
Double-data-rate architecture; data transfers clock cycle high-speed data transfer realized bits prefetch pipelined architecture Bi-directional differential data strobe (DQS /DQS) transmitted/received with data capturing data receiver edge-aligned with data READs; centeraligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data data mask referenced both edges Data mask (DM) write data Posted /CAS programmable additive latency better command data efficiency On-Die-Termination (ODT) better signal quality Synchronous Dynamic Asynchronous Multi Purpose Register (MPR) temperature read calibration drive Programmable Partial Array Self-Refresh (PASR) /RESET Power-up sequence reset function range: Normal/extended Auto/manual self-refresh Programmable Output driver impedance control
Document E1130E10 (Ver. 1.0) Date Published October 2007 Japan Printed Japan URL: http://www.elpida.com ©Elpida Memory, Inc. 2007
EBJ52UD6CASA, EBJ52UD6BASA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed (CL-tRCD-tRP) DDR3-1333G (8-8-8) DDR3-1333H (9-9-9) 1066 DDR3-1066E (6-6-6) Contact
Part number
Package
Mounted devices EDJ5316BASE-DG-E EDJ5316BASE-DG-E EDJ5316BASE-DJ-E EDJ5316BASE-DG-E EDJ5316BASE-DJ-E EDJ5316BASE-AC-E EDJ5316BASE-DG-E EDJ5316BASE-DJ-E EDJ5316BASE-AC-E EDJ5316BASE-8A-E EDJ5316BASE-AE-E EDJ5316BASE-DG-E EDJ5316BASE-DJ-E EDJ5316BASE-AC-E EDJ5316BASE-8A-E EDJ5316BASE-DG-E EDJ5316BASE-DJ-E EDJ5316BASE-AC-E EDJ5316BASE-8A-E EDJ5316BASE-AE-E EDJ5316BASE-8C-E
EBJ52UD6CASA-DG-E 1333 EBJ52UD6CASA-DJ-E EBJ52UD6BASA-AC-E
204-pin SO-DIMM Gold (lead-free)
EBJ52UD6BASA-AE-E
DDR3-1066F (7-7-7)
EBJ52UD6BASA-8A-E
DDR3-800D (5-5-5)
EBJ52UD6BASA-8C-E
DDR3-800E (6-6-6)
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Configurations
Front side
Back side
Front side name VREFDQ /DQS1 DQS1 DQ10 DQ11 DQ16 DQ17 /DQS2 DQS2 DQ18 DQ19 DQ24 DQ25 DQ26 name /CK0 (AP) /CAS /CS1 DQ32 DQ33 /DQS4 DQS4 DQ34 DQ35 DQ40 DQ41 DQ42 DQ43 DQ48 DQ49 /DQS6
Back side name /DQS0 DQS0 DQ12 DQ13 /RESET DQ14 DQ15 DQ20 DQ21 DQ22 DQ23 DQ28 DQ29 /DQS3 DQS3 DQ30 name /CK1 /RAS /CS0 ODT0 ODT1 VREFCA DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 /DQS5 DQS5 DQ46 DQ47 DQ52 DQ53
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Front side name DQ27 CKE0 (/BC) name DQS6 DQ50 DQ51 DQ56 DQ57 DQ58 DQ59 VDDSPD Back side name DQ31 CKE1 name DQ54 DQ55 DQ60 DQ61 /DQS7 DQS7 DQ62 DQ63 /EVENT
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Description
name (AP) (/BC) BA0, BA1, DQ63 /RAS /CAS /CS0, /CS1 CKE0, CKE1 CK0, /CK0, /CK1 DQS0 DQS7, /DQS0 /DQS7 SA0, VDDSPD VREFCA VREFDQ /RESET ODT0, ODT1 /EVENT Function Address input address Column address Auto precharge Burst chop Bank select address Data input/output address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Reference voltage Reference voltage Ground termination supply SDRAM DRAM known state control Temperature event connection
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Serial Matrix
Byte Function described Number serial bytes written/SPD device size/CRC coverage revision byte/DRAM device type byte/module type SDRAM density banks SDRAM addressing Reserved Module organization Module memory width Fine timebase (FTB) dividend/divisor Medium timebase (MTB) dividend Medium timebase (MTB) divisor SDRAM minimum cycle time (tCK (min.)) -DG, -AC, -8A, Reserved SDRAM /CAS latencies supported, SDRAM /CAS latencies supported, SDRAM minimum /CAS latencies time (tAA (min.)) SDRAM write recovery time (tWR) SDRAM minimum /RAS /CAS delay (tRCD) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 0-116/256/176 Revision DDR3 SDRAM SO-DIMM 512M bits, banks rows, columns bits bits non-ECC 1.5ns 1.875ns 2.5ns 12ns 13.5ns 11.25ns 13.125ns 12.5ns 15ns 15ns 12ns 13.5ns 11.25ns 13.125ns 12.5ns 15ns
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Byte Function described
Bit7 Bit6
Bit5
Bit4 Bit3 Bit2 Bit1 Bit0 value
Comments 7.5ns 10ns 12ns 13.5ns 11.25ns 13.125ns 12.5ns 15ns
SDRAM minimum active active delay (tRRD) -DG, -AC, -AE, -8A, SDRAM minimum precharge time (tRP)
SDRAM upper nibbles tRAS
SDRAM minimum active precharge time (tRAS), -DG, -AC, -AE, -8A, SDRAM minimum active active /autorefresh time (tRC),
36ns 37.5ns 48ns 49.5ns 48.75ns 50.625ns 50ns 52.5ns 90ns 90ns 7.5ns 7.5ns
SDRAM minimum refresh recovery time delay (tRFC), SDRAM minimum refresh recovery time delay (tRFC), SDRAM minimum internal write read command delay (tWTR) SDRAM minimum internal read precharge command delay (tRTP) Upper nibble tFAW Minimum four activate window delay time (tFAW) -DG, -AC, -AE, -8A,
45ns 50ns RZQ/6, refresh, ODTS height 30mm
SDRAM output drivers supported SDRAM refresh options
Reserved Module nominal height Module maximum thickness Reference card used
Card
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Bit4 Bit3 Bit2 Bit1 Bit0 value Year code (BCD) Week code (BCD)
Byte Function described
Bit7 Bit6
Bit5
Comments standard Elpida Memory Elpida Memory
Address mapping from edge connecter DRAM Module specific section Module manufacturer's JEDEC code, Module manufacturer's JEDEC code, Module manufacturing location Module manufacturing date Module manufacturing date Module module serial number Cyclical redundancy code (CRC) Cyclical redundancy code (CRC)
Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -DG, -AC, -AE, -8A, Module part number Module part number Module part number Module part number
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Bit4 Bit3 Bit2 Bit1 Bit0 value
Byte Function described Module part number -DG, -AC, -8A, Module part number -AC, Module part number Module part number Module part number Module revision code Module revision code SDRAM manufacturer's JEDEC code, SDRAM manufacturer's JEDEC code, Manufacturer's specific data Open customer
Bit7 Bit6
Bit5
Comments (Space) Initial (Space)
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Block Diagram
/CK1 /CK0 /CS1 ODT1 CKE1 Command Address, /CS0 ODT0 CKE0 /DQS0 DQS0 /DQS1 DQS1 DQ15
/DQSL DQSL DQL0 DQL7 /DQSU DQSU
Command
/DQSL DQSL DQL0 DQL7 /DQSU DQSU
Address
Command
DQU0 DQU7
DQU0 DQU7
Address
Serial /DQS2 DQS2 DQ16 DQ23 /DQS3 DQS3 DQ24 DQ31
/DQSL
/DQSL DQSL DQL0 DQL7
DQSL
DQL0 DQL7 /DQSU
/EVENT
Command
/DQSU DQSU
Command
/EVENT
DQSU
Address
Address
DQU0 DQU7
/RESET VDDSPD VREFCA VREFDQ
/RESET:SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs SPD)
DQU0 DQU7
/DQS4 DQS4 DQ32 DQ39 /DQS5 DQS5 DQ40 DQ47
/DQSL DQSL
/DQSL DQSL DQL0 DQL7
DQL0 DQL7 /DQSU DQSU
Command
/DQSU DQSU
Command
Address
DQU0 DQU7
DQU0 DQU7
Address
Notes wiring changed. DQS, /DQS, ODT, CKE, relationships must meintained shown. Refer appropriate clock wiring topology under DIMM wiring details section this document. 512M bits DDR3 SDRAM Address, A11, Command: /RAS, /CAS, bytes EEPROM Rs1: Rs2:
/DQS6 DQS6 DQ48 DQ55 /DQS7 DQS7 DQ56 DQ63
/DQSL
/DQSL DQSL DQL0 DQL7
DQSL
DQL0 DQL7 /DQSU DQSU
Command
Command
Address
DQU0 DQU7
DQU0 DQU7
Address
DQSU
Preliminary Data Sheet E1130E10 (Ver. 1.0)
/DQSU
EBJ52UD6CASA, EBJ52UD6BASA
Electrical voltages referenced (GND). Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Reference voltage Reference voltage Storage temperature Power dissipation Short circuit output current Symbol VOUT VREFCA VREFDQ Tstg IOUT Value -0.4 +1.975 -0.4 +1.975 -0.4 +1.975 -0.4 -0.4 VDDQ +100 Unit Notes
Notes: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Storage temperature case surface temperature center/top side DRAM. VDDQ must within 300mV each other times; VREF must greater than VDDQ, When VDDQ less than 500mV; VREF equal less than 300mV. DDR3 SDRAM component specification. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Operating Temperature Condition
Parameter Operating case temperature Symbol Rating Unit Notes
Notes: Operating temperature case surface temperature center/top side DRAM. Normal Temperature Range specifies temperatures where DRAM specifications will supported. During operation, DRAM case temperature must maintained between +85°C under operating conditions. Some applications require operation DRAM Extended Temperature Range between +85°C +95°C case temperature. Full specifications guaranteed this range, following additional conditions apply: Refresh commands must doubled frequency, therefore reducing refresh interval tREFI 3.9s. (This double refresh requirement apply some devices.) Self-refresh operation required Extended Temperature Range, then mandatory either Manual Self-Refresh mode with Extended Temperature Range capability (MR2 [A6, enable optional Auto Self-Refresh mode (MR2 [A6, 0]).
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Recommended Operating Conditions +85°C) (DDR3 SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ VDDSPD Input reference voltage Input reference voltage Termination voltage VREFCA (DC) VREFDQ (DC) min. 1.425 0.49 VDDQ 0.49 VDDQ VDDQ/2 typ. max. 1.575 Unit Notes
0.50 VDDQ 0.51 VDDQ 0.50 VDDQ 0.51 VDDQ VDDQ/2
Notes: Under conditions VDDQ must less than equal VDD. VDDQ tracks with VDD. parameters measured with VDDQ tied together. peak noise VREF allow VREF deviate from VREF(DC) more than (for reference: approx mV). reference: approx. VDD/2
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Characteristics +85°C, 1.5V 0.075V,
Parameter Operating current (ACT-PRE) (Another rank IDD2PF) Symbol IDD0 Data rate (Mbps) 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 1333 1066 max. 1020 1140 1040 1480 1240 1020 1740 1460 1200 1440 1200 1700 1420 1140 1400 1340 1260 1660 1560 1440 1860 1700 1660 2120 1920 1840 Unit Notes
Operating current (ACT-PRE)
(Another rank IDD3N) Operating current (ACT-READ-PRE) (Another rank IDD2PF) Operating current (ACT-READ-PRE) (Another rank IDD3N)
IDD0
IDD1
IDD1
IDD2PF Precharge power-down standby current IDD2PS
Fast Exit
Slow Exit
Precharge quiet standby current
IDD2Q
Precharge standby current Active power-down current (Always fast exit) Active standby current Operating current (Burst read operating) (Another rank IDD2PF) Operating current (Burst read operating) (Another rank IDD3N) Operating current (Burst write operating) (Another rank IDD2PF) Operating current (Burst write operating) (Another rank IDD3N) Burst refresh current (Another rank IDD2PF) Burst refresh current (Another rank IDD3N) bank interleave read current (Another rank IDD2PF) bank interleave read current (Another rank IDD3N)
IDD2N
IDD3P
IDD3N
IDD4R
IDD4R
IDD4W
IDD4W
IDD5B
IDD5B
IDD7R
IDD7R
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Self-Refresh Current +85°C, 1.5V 0.075V)
Parameter Self-refresh current normal temperature range Self-refresh current extended temperature range Auto self-refresh current Symbol IDD6 IDD6ET IDD6TC Grade max. Unit Notes
Timing Test Conditions purposes testing, following parameters utilized.
DDR3-1333 Parameter (IDD) min.(IDD) tRCD min. (IDD) min. (IDD) tRAS min.(IDD) min. (IDD) tFAW tRRD tRFC (IDD) 8-8-8 9-9-9 13.5 49.5 13.5 DDR3-1066 6-6-6 1.875 11.25 48.75 37.5 11.25 7-7-7 1.875 13.13 50.63 37.5 13.13 8-8-8 1.875 52.50 37.5 DDR3-800 5-5-5 12.5 37.5 12.5 6-6-6 52.5 37.5 Unit
Characteristics +85°C, VDD, VDDQ 1.5V 0.075V) (DDR3 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol Value Unit Notes VOUT
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Functions
(input pin) differential clock inputs. address control input signals sampled crossing positive edge negative edge /CK. Output (read) data referenced crossings (both directions crossing). (input pin) commands masked when registered high. provides external rank selection systems with multiple ranks. considered part command code. /RAS, /CAS, (input pins) /RAS, /CAS (along with /CS) define command being entered. (input pins) Provided address active commands column address read/write commands select location memory array respective bank. (A10(AP) A12(/BC) have additional functions, below) address inputs also provide op-code during mode register commands. [Address Pins Table]
Address A11) address (RA) AX11 Column address (CA) Notes
A10(AP) (input pin) sampled during read/write commands determine whether auto-precharge should performed accessed bank after read/write operation. (high: auto-precharge; low: auto-precharge) sampled during precharge command determine whether precharge applies bank (A10 low) banks (A10 high). only bank precharged, bank selected bank addresses (BA). (/BC) (input pin) sampled during read write commands determine burst chop (on-the-fly) will performed. (A12 high: burst chop, low: burst chopped.) (input pins) BA0, define which bank active, read, write precharge command being applied. also determine mode register accessed during cycle. [Bank Select Signal Table]
Bank Bank Bank Bank Bank Bank Bank Bank
Remark: VIH. VIL.
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
(input pin) high activates, deactivates, internal clock signals device input buffers output drivers. Taking provides precharge power-down self-refresh operation (all banks idle), active power-down (row active bank). asynchronous self-refresh exit. After VREF become stable during power-on initialization sequence, must maintained proper operation receiver. proper self-refresh entry exit, VREF must maintained this input. must maintained high throughout read write accesses. Input buffers, excluding /CK, disabled during power-down. Input buffers, excluding CKE, disabled during self-refresh. (input output pins) Bi-directional data bus. /DQS (input output pin) Output with read data, input with write data. Edge-aligned with read data, centered write data. data strobe paired with differential signals /DQS provide differential pair signaling system during READs WRITEs. (input pins) (registered high) enables termination resistance internal DDR3 SDRAM. When enabled, only applied each DQS, /DQS, will ignored mode register (MR1) programmed disable ODT. (input pins) reference signal data input mask function. sampled cross point /DQS. (power supply pins) 1.5V applied. (VDD internal circuit.) VDDSPD (power supply pin) 1.5V applied (For serial EEPROM). (power supply pin) Ground connected. (power supply pin) termination supply SDRAM. VREFDQ (power supply) Reference voltage VREFCA (power supply) Reference voltage /RESET (input pin) /RESET negative active signal (active low) referred GND. /EVENT (output pin) /EVENT reserved flag critical module temperature. resistor connected from /EVENT line VDDSPD system planar pull-up.
Detailed Operation Part, Electrical Characteristics Timing Waveforms
Refer EDJ5304BASE, EDJ5308BASE, EDJ5316BASE datasheet (E0966E).
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
Physical Outline
Unit:
Front side
2.00 21.15 9.00 (DATUM -A-) 3.80
Full
2.15
21.00
67.60
39.00 2.45 1.00 0.10
4.00
Component area (Front)
6.00
Back side 63.60 2.45
2.15
4.00
20.00
Component area (Back)
(DATUM -A-) Detail 0.60
2.55
Detail FULL 1.65
0.35
3.00
4.00 0.10
1.00 0.10
0.45 0.03
Detail
Detail Contact 3.00
0.35
1.35
ECA-TS2-0215-01
Preliminary Data Sheet E1130E10 (Ver. 1.0)
30.00
EBJ52UD6CASA, EBJ52UD6BASA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E1130E10 (Ver. 1.0)
EBJ52UD6CASA, EBJ52UD6BASA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] aware that this product typical electronic equipment general-purpose applications. Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] Usage environments with special characteristics listed below considered design. Accordingly, company assumes responsibility loss customer third party when used environments with special characteristics listed below. Example: Usage liquids, including water, oils, chemicals organic solvents. Usage exposure direct sunlight outdoors, dusty places. Usage involving exposure significant amounts corrosive gas, including air, Usage environments with static electricity, strong electromagnetic waves radiation. Usage places where forms. Usage environments with mechanical vibration, impact, stress. Usage near heating elements, igniters, flammable items. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0706
Preliminary Data Sheet E1130E10 (Ver. 1.0)

EBJ52UD6CASA, EBJ52UD6BASA (64M words bits, Ranks) Density: 512MB

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