EBE51UD8AHWA (64M words bits, Rank) Density: 512MB Organization w

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EBE51UD8AHWA (64M words bits, Rank) Density: 512MB Organization w

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512MB Unbuffered DDR2 SDRAM DIMM
EBE51UD8AHWA (64M words bits, Rank)
Density: 512MB Organization words bits, rank Mounting pieces 512M bits DDR2 SDRAM sealed FBGA Package: 240-pin socket type dual line memory module (DIMM) height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) Power supply: 1.8V 0.1V Data rate: 800Mbps (max.) Four internal banks concurrent operation (components) Interface: SSTL_18 Burst lengths (BL): /CAS Latency (CL): Precharge: auto precharge option each burst access Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms Average refresh period 7.8µs +85°C 3.9µs +85°C +95°C Operating case temperature range +95°C
Features
Double-data-rate architecture; data transfers clock cycle high-speed data transfer realized bits prefetch pipelined architecture Bi-directional differential data strobe (DQS /DQS) transmitted/received with data capturing data receiver edge-aligned with data READs; centeraligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data data mask referenced both edges Data mask (DM) write data Posted /CAS programmable additive latency better command data efficiency Off-Chip-Driver Impedance Adjustment On-DieTermination better signal quality /DQS disabled single-ended Data Strobe operation
Document E1030E10 (Ver. 1.0) Date Published April 2007 Japan Printed Japan URL: http://www.elpida.com Elpida Memory, Inc. 2007
EBE51UD8AHWA
Ordering Information
Part number EBE51UD8AHWA-8E-E EBE51UD8AHWA-8G-E Data rate Mbps (max.) Component JEDEC speed (CL-tRCD-tRP) DDR2-800 (5-5-5) DDR2-800 (6-6-6) Package 240-pin DIMM (lead-free) Contact Gold Mounted devices EDE5108AHBG-8E-E EDE5108AHBG-8E-E EDE5108AHBG-8G-E
Configurations
Front side
Back side
name VREF /DQS0 DQS0 /DQS1 DQS1 DQ10 DQ11 DQ16 DQ17 /DQS2 DQS2
name /CAS DQ32 DQ33 /DQS4 DQS4 DQ34 DQ35
name DQ12 DQ13 /CK1 DQ14 DQ15 DQ20 DQ21
name /CK0 /RAS /CS0 ODT0 DQ36 DQ37 DQ38 DQ39 DQ44
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
name DQ18 DQ19 DQ24 DQ25 /DQS3 DQS3 DQ26 DQ27 CKE0 name DQ40 DQ41 /DQS5 DQS5 DQ42 DQ43 DQ48 DQ49 /DQS6 DQS6 DQ50 DQ51 DQ56 DQ57 /DQS7 DQS7 DQ58 DQ59 name DQ22 DQ23 DQ28 DQ29 DQ30 DQ31 name DQ45 DQ46 DQ47 DQ52 DQ53 /CK2 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63 VDDSPD
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Description
name (AP) BA0, DQ63 /RAS /CAS /CS0 CKE0 /CK0 /CK2 DQS0 DQS7, /DQS0 /DQS7 VDDSPD VREF ODT0 Function Address input address Column address Auto precharge Bank select address Data input/output address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Input reference voltage Ground control connection
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Serial Matrix
Byte Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM ranks Module data width Module data width continuation Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments bytes bytes DDR2 SDRAM SSTL 1.8V 2.5ns*
Voltage interface level this assembly SDRAM cycle time,
2.5ns* 0.4ns* None. 7.8µs None.
SDRAM access from clock (tAC) DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width Reserved SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency
DIMM Mechanical Characteristics DIMM type information SDRAM module attributes SDRAM device attributes: General
4.00mm max. Unbuffered Normal Weak Driver Support 3.75ns* 3.0ns* 0.5ns*
Minimum clock cycle time Maximum data access time (tAC) from clock
0.45ns* 5.0ns*
Minimum clock cycle time Maximum data access time (tAC) from clock
3.75ns* 0.6ns*
0.5ns*
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Byte
Function described Minimum precharge time (tRP)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments (ASCII-8bit code) Continuation code Elpida Memory Rev. Undefined 57.5ns* 60ns*
12.5ns 15ns 7.5ns 12.5ns 15ns 45ns 512M bytes 0.17ns* 0.25ns* 0.05ns* 0.12ns* 15ns*
Minimum active active delay (tRRD) Minimum /RAS /CAS delay (tRCD) Revision Checksum bytes Minimum active precharge time (tRAS) Module rank density Address command setup time before clock (tIS) Address command hold time after clock (tIH) Data input setup time before clock (tDS) Data input hold time after clock (tDH) Write recovery time (tWR) Internal write read command delay (tWTR) Internal read precharge command delay (tRTP) Memory analysis probe characteristics Extension Byte Active command period (tRC) Auto refresh active/ Auto refresh command cycle (tRFC) SDRAM cycle max. (tCK max.) Dout skew Data hold skew (tQHS) relock time
7.5ns* 7.5ns*
105ns* 8ns*
0.20ns* 0.30ns*
Undefined
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number Module part number Module part number
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Byte Function described Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacture specific data Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments (Space) Initial (Space) Year code (BCD) Week code (BCD)
Note: These specifications defined based component specification, module.
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Block Diagram
/CS0
/DQS4
DQS4
/DQS0
DQS0
/DQS
/DQS
DQ32 DQ39
/DQS1
/DQS5
DQS1
DQS5
/DQS
/DQS
DQ15
DQ40 DQ47
/DQS2
/DQS6
DQS2
/DQS
DQS6
/DQS
DQ16 DQ23
DQ48 DQ55
/DQS3
/DQS7
DQS3
/DQS
DQS7
/DQS
DQ24 DQ31
DQ56 DQ63
BA1: SDRAMs
A13: SDRAMs
Serial
/RAS
/RAS: SDRAMs
/CAS: SDRAMs
/CAS
/WE: SDRAMs
CKE0
ODT0
CKE: SDRAMs
ODT:SDRAMs
Notes wiring maybe changed within byte. DQS, /DQS, ODT, CKE, relationships must meintained shown. Refer appropriate clock wiring topology under DIMM wiring details section this document.
VDDSPD VREF
SDRAMs
SDRAMs
512M bits DDR2 SDRAM bits EEPROM
SDRAMs
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Logical Clock Structure
3DRAM loads (CK1 /CK1, /CK2)
DRAM
DRAM
DIMM connector
DRAM
2DRAM loads (CK0 /CK0)
DRAM
DIMM connector
DRAM
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Electrical voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol Tstg Value -0.5 +2.3 -0.5 +2.3 +100 Unit Notes
Notes: DDR2 SDRAM component specification. Supporting +85°C being able extend +95°C with doubling auto-refresh commands frequency 32ms period (tREFI 3.9µs) higher temperature self-refresh entry control EMRS required. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Operating Conditions +85°C) (DDR2 SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ VDDSPD Input reference voltage Termination voltage input logic high input input logic high input VREF (DC) (DC) (AC) (AC) min. 0.49 VDDQ VREF 0.04 VREF 0.125 -0.3 VREF 0.200 typ. max. Unit Notes
0.50 VDDQ 0.51 VDDQ VREF VREF 0.04 VDDQ VREF 0.125 VREF 0.200
Notes: value VREF selected user provide optimum noise margin system. Typically value VREF expected about VDDQ transmitting device VREF expected track variations VDDQ. Peak peak noise VREF exceed VREF (DC). transmitting device must track VREF receiving device. VDDQ must equal VDD.
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Overshoot/Undershoot Specification (DDR2 SDRAM Component Specification)
Parameter Maximum peak amplitude allowed overshoot Maximum peak amplitude allowed undershoot Maximum overshoot area above DDR2-800 Maximum undershoot area below DDR2-800 Maximum peak amplitude allowed overshoot Maximum peak amplitude allowed undershoot Maximum overshoot area above DDR2-800 Maximum undershoot area below DDR2-800 Maximum peak amplitude allowed overshoot Maximum peak amplitude allowed undershoot Maximum overshoot area above VDDQ DDR2-800 Maximum undershoot area below VSSQ DDR2-800 DQS, /DQS, RDQS, /RDQS, Pins Command, Address, CKE, Specification 0.66 0.66 0.23 0.23 0.23 0.23 Unit V-ns V-ns V-ns V-ns V-ns V-ns
Maximum amplitude Overshoot area
Volts
VDD, VDDQ VSS, VSSQ
Undershoot area
Time (ns)
Overshoot/Undershoot Definition
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Characteristics +85°C, 1.8V 0.1V,
Parameter Symbol Grade max. Unit Test condition bank; (IDD), (IDD), tRAS tRAS min.(IDD); between valid commands; Address inputs SWITCHING; Data inputs SWITCHING bank; IOUT 0mA; CL(IDD), (IDD), (IDD), tRAS tRAS min.(IDD); tRCD tRCD (IDD); between valid commands; Address inputs SWITCHING; Data pattern same IDD4W banks idle; (IDD); Other control address inputs STABLE; Data inputs FLOATING banks idle; (IDD); Other control address inputs STABLE; Data inputs FLOATING banks idle; (IDD); Other control address inputs SWITCHING; Data inputs SWITCHING banks open; (IDD); Other control address inputs STABLE; Data inputs FLOATING Fast Exit MRS(12) Slow Exit MRS(12)
Operating current (ACT-PRE)
IDD0
Operating current (ACT-READ-PRE)
IDD1
Precharge power-down standby current
IDD2P
Precharge quiet standby IDD2Q current
Idle standby current
IDD2N
IDD3P-F Active power-down standby current IDD3P-S
Active standby current
IDD3N
banks open; (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING banks open, continuous burst reads, IOUT 0mA; CL(IDD), (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Address inputs SWITCHING; Data pattern same IDD4W banks open, continuous burst writes; CL(IDD), (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Address inputs SWITCHING; Data inputs SWITCHING
Operating current (Burst read operating)
IDD4R
1080
Operating current (Burst write operating)
IDD4W
1120
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Parameter
Symbol
Grade
max.
Unit
Test condition (IDD); Refresh command every tRFC (IDD) interval; between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING Self Refresh Mode; 0.2V; Other control address inputs FLOATING; Data inputs FLOATING bank interleaving reads, IOUT 0mA; CL(IDD), tRCD (IDD) (IDD); (IDD), (IDD), tRRD tRRD(IDD), tRCD (IDD); between valid commands; Address inputs STABLE during DESELECTs; Data pattern same IDD4W;
Auto-refresh current
IDD5
1560
Self-refresh current
IDD6
Operating current (Bank interleaving)
IDD7
1360
Notes:
specifications tested after device properly initialized. Input slew rate specified Input Test Condition. parameters specified with disabled. Data consists DQS, /DQS, RDQS /RDQS. values must with combinations EMRS bits Definitions defined (AC) (max.) defined (AC) (min.) STABLE defined inputs stable level FLOATING defined inputs VREF VDDQ/2 SWITCHING defined inputs changing between every other clock cycle (once clocks) address control signals, inputs changing between every other data transfer (once clock) signals including masks strobes. Refer Timing Test Conditions.
Timing Test Conditions purposes testing, following parameters utilized.
DDR2-800 Parameter (IDD) tRCD (IDD) (IDD) tRRD (IDD) (IDD) tRAS (min.)(IDD) tRAS (max.)(IDD) (IDD) tRFC (IDD) 5-5-5 12.5 57.5 70000 12.5 DDR2-800 6-6-6 70000 Unit
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol Value 0.603 0.603 VDDQ +13.4 -13.4 Unit Notes VDDQ VOUT
Minimum required output pull-up under test load Maximum required output pull-down under test load Output timing measurement reference level VOTR Output minimum sink current Output minimum source current
Notes:
VDDQ device under test referenced. VDDQ 1.7V; VOUT 1.42V. VDDQ 1.7V; VOUT 0.28V. value VREF applied receiving device expected VTT. After calibration 25°C, VDDQ 1.8V.
Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter differential input voltage differential cross point voltage differential cross point voltage Symbol (AC) (AC) (AC) min. VDDQ 0.175 VDDQ 0.125 max. VDDQ VDDQ 0.175 VDDQ 0.125 Unit Notes
Notes: (AC) specifies input differential voltage |VTR -VCP| required switching, where true input signal (such DQS, RDQS) complementary input signal (such /CK, /DQS, /RDQS). minimum value equal (AC) (AC). typical value (AC) expected about VDDQ transmitting device (AC) expected track variations VDDQ. (AC) indicates voltage which differential input signals must cross. typical value (AC) expected about VDDQ transmitting device (AC) expected track variations VDDQ. (AC) indicates voltage which differential output signals must cross.
VDDQ
VSSQ
Crossing point
Differential Signal Levels*1,
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Electrical Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter effective impedance value EMRS (A6, effective impedance value EMRS (A6, effective impedance value EMRS (A6, Deviation with respect VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) min. typ. max. Unit Note
Note: Test condition measurements. Measurement Definition (eff) Apply (AC) (AC) test separately, then measure current I(VIH (AC)) I(VIL (AC)) respectively. (AC), VDDQ values defined SSTL_18.
(eff
VIL( (VIH (VIL(
Measurement Definition Measure voltage (VM) test (midpoint) with load.
VDDQ
Default Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Output impedance Pull-up pull-down mismatch Output slew rate min. 12.6 typ. max. 23.4 Unit V/ns Notes
Notes: Impedance measurement condition output source current: VDDQ 1.7V; VOUT 1420mV; (VOUT-VDDQ)/IOH must less than 23.4 values VOUT between VDDQ VDDQ-280mV. Impedance measurement condition output sink current: VDDQ 1.7V; VOUT 280mV; VOUT/IOL must less than 23.4 values VOUT between 280mV. Mismatch absolute value between pull pull down, both measured same temperature voltage. Slew rate measured from VIL(AC) VIH(AC). absolute value slew rate measured from equal greater than slew rate measured from This guaranteed design characterization. DRAM specifications timing, voltage, slew rate longer applicable changed from default settings.
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Capacitance 25°C, 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter input capacitance Symbol Pins /RAS, /CAS, /WE, /CS, CKE, ODT, Address DQS, /DQS, RDQS, /RDQS, min. max. Unit Notes
Input capacitance
1.75
Input/output capacitance
CI/O
Notes: Matching within 0.25pF. Matching within 0.50pF.
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Characteristics +85°C, VDD, VDDQ 1.8V 0.1V, VSS, VSSQ (DDR2 SDRAM Component Specification) units tCK(avg) nCK, introduced DDR2-800 DDR2-667 tCK(avg): actual tCK(avg) input clock under operation. nCK: clock cycle input clock, counting actual clock edges.
-8E, Frequency (Mbps) Parameter /CAS latency Active read write command delay Precharge command period Active active/auto-refresh command time output access time from output access time from high-level width low-level width half period Clock cycle time input hold time input setup time Control Address input pulse width each input input pulse width each input Data-out high-impedance time from CK,/CK DQS, /DQS low-impedance time from CK,/CK low-impedance time from CK,/CK DQS-DQ skew associated signals hold skew factor DQ/DQS output hold time from latching rising transitions associated clock edges input high pulse width input pulse width falling edge setup time falling edge hold time from Mode register command cycle time Write postamble Write preamble Address control input hold time Address control input setup time Read preamble Read postamble Active precharge command Active auto precharge delay Symbol tRCD tDQSCK (avg) tCL(avg) (avg) (base) (base) tIPW tDIPW (DQS) (DQ) tDQSQ tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE (base) (base) tRPRE tRPST tRAS tRAP min. (-8E) (-8G) 12.5 (-8E) (-8G) 12.5 (-8E) (-8G) 57.5(-8E) (-8G) -400 -350 0.48 0.48 Min. (tCL(abs), tCH(abs)) 2500 0.35 min. min. tQHS -0.25 0.35 0.35 0.35 tRCD min. max. (-8E) (-8G) +400 +350 0.52 0.52 8000 max. max. max. +0.25 70000 Unit (avg) (avg) (avg) (avg) (avg) (avg) (avg) (avg) (avg) (avg) (avg) (avg) (avg) Notes
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
-8E, Frequency (Mbps) Parameter Active bank active bank command period /CAS /CAS command delay Write recovery time Auto precharge write recovery precharge time Internal write read command delay Internal read precharge command delay Exit self-refresh non-read command Exit self-refresh read command Exit precharge power-down non-read command Exit active power-down read command Exit active power-down read command (slow exit/low power mode) minimum pulse width (high pulse width) Output impedance test driver delay command update delay Auto-refresh active/auto-refresh command time Average periodic refresh interval (0°C +85°C) (+85°C +95°C) Minimum time clocks remains after asynchronously drops Symbol tRRD tCCD tDAL tWTR tRTP tXSNR tXSRD tXARD tXARDS tCKE tOIT
tMOD
min. (tRP/tCK(avg)) tRFC tCK(avg) max. Unit Notes
tRFC tREFI tREFI tDELAY
Notes:
each terms above, already integer, round next higher integer. Additive Latency. defines which active power down exit timing applied. figures Input Waveform Timing referenced from input signal crossing VIH(AC) level rising signal VIL(AC) falling signal applied device under test. figures Input Waveform Timing referenced from input signal crossing VIH(DC) level rising signal VIL(DC) falling signal applied device under test.
/DQS
VDDQ (AC)(min.) (DC)(min.) VREF (DC)(max.) (AC)(max.)
VDDQ (AC)(min.) (DC)(min.) VREF (DC)(max.) (AC)(max.)
Input Waveform Timing (tDS, tDH)
Input Waveform Timing (tIS, tIH)
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
minimum absolute half period actual input clock. input parameter input specification parameter. used conjunction with tQHS derive DRAM output timing tQH. value used calculation determined following equation; tCH(abs), tCL(abs) where, tCH(abs) minimum actual instantaneous clock high time; tCL(abs) minimum actual instantaneous clock time; tQHS accounts for: pulse duration distortion on-chip clock circuits, which represents well actual input transferred output; worst case push-out transition followed worst case pull-in next transition, both which independent each other, data skew, output pattern effects, p-channel n-channel variation output drivers. tQHS, where: minimum absolute half period actual input clock; tQHS specification value under column. {The less half-pulse width distortion present, larger value larger valid data will be.} Examples: system provides 1315ps into DDR2-667 SDRAM, DRAM provides 975ps (min.) system provides 1420ps into DDR2-667 SDRAM, DRAM provides 1080ps (min.) stands round refers parameter stored MRS. When device operated with input clock jitter, this parameter needs derated actual tERR(6-10per) input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tERR(6-10per) min. -272ps tERR(6-10per) max. +293ps, then tDQSCK min.(derated) tDQSCK min. tERR(6-10per) max. -400ps 293ps -693ps tDQSCK max.(derated) tDQSCK max. tERR(6-10per) min. 400ps 272ps +672ps. Similarly, tLZ(DQ) DDR2-667 derates tLZ(DQ) min.(derated) -900ps 293ps -1193ps tLZ(DQ) max.(derated)= 450ps 272ps +722ps. When device operated with input clock jitter, this parameter needs derated actual tJIT(per) input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tJIT(per) min. -72ps tJIT(per) max. +93ps, then tRPRE min.(derated) tRPRE min. tJIT(per) min. tCK(avg) 72ps +2178ps tRPRE max.(derated) tRPRE max. tJIT(per) max. tCK(avg) 93ps +2843ps. When device operated with input clock jitter, this parameter needs derated actual tJIT(duty) input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tJIT(duty) min. -72ps tJIT(duty) max. +93ps, then tRPST min.(derated) tRPST min. tJIT(duty) min. tCK(avg) 72ps +928ps tRPST max.(derated) tRPST max. tJIT(duty) max. tCK(avg) 93ps +1592ps. Refer Clock Jitter table.
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter turn-on delay turn-on turn-on (power down mode) turn-off delay turn-off turn-off (power down mode) power down entry latency power down exit latency Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD min. tAC(min) tAC(min) 2000 tAC(min) tAC(min) 2000 max. tAC(max) 2tCK tAC(max) 1000 tAC(max) 2.5tCK tAC(max) 1000 Unit Notes
Notes: turn time when device leaves high impedance resistance begins turn turn time when resistance fully Both measured from tAOND. turn time when device starts turn resistance. turn time when high impedance. Both measured from tAOFD. When device operated with input clock jitter, this parameter needs derated actual tERR(6-10per) input clock. (output deratings relative SDRAM input clock.) When device operated with input clock jitter, this parameter needs derated {-tJIT(duty) max. tERR(6-10per) max. -tJIT(duty) min. tERR(6-10per) min. actual input clock.(output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tERR(6-10per) min. -272ps, tERR(6-10per) max. +293ps, tJIT(duty) min. -106ps tJIT(duty) max. +94ps, then tAOF min.(derated) tAOF min. -tJIT(duty) max. tERR(6-10per) max. -450ps -94ps 293ps} -837ps tAOF max.(derated) tAOF max. -tJIT(duty) min. tERR(6-10per) min. 1050ps 106ps 272ps} +1428ps. tAOFD DDR2-667/800, clock assumes tCH(avg), average input clock high pulse width relative tCK(avg). tAOF min. tAOF max. should each derated same amount actual amount tCH(avg) offset present DRAM input with respect 0.5. example, input clock worst case tCH(avg) 0.48, tAOF min. should derated subtracting 0.02 tCK(avg) from whereas input clock worst case tCH(avg) 0.52, tAOF max. should derated adding 0.02 tCK(avg) Therefore, have; tAOF min.(derated) min. [0.5 Min.(0.5, tCH(avg) min.)] tCK(avg) tAOF max.(derated) max. [Max.(0.5, tCH(avg) max.) 0.5] tCK(avg) tAOF min.(derated) Min.(tAC min., min. [0.5 tCH(avg) min.] tCK(avg)) tAOF max.(derated) Max.(tAC max., max. [tCH(avg) max. 0.5] tCK(avg)) where tCH(avg) min. tCH(avg) max. minimum maximum tCH(avg) actually measured DRAM input balls.
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Input Test Conditions (DDR2 SDRAM Component Specification)
Parameter Input reference voltage Input signal maximum peak peak swing Input signal minimum slew rate Symbol VREF VSWING(max.) SLEW Value VDDQ Unit V/ns Notes
Notes: Input waveform timing referenced input signal crossing through VIH/IL (AC) level applied device under test. input signal minimum slew rate maintained over range from VREF VIH(AC) (min.) rising edges range from VREF VIL(AC) (max.) falling edges shown below figure. timings referenced with input waveforms switching from VIL(AC) VIH(AC) positive transitions VIH(AC) VIL(AC) negative transitions.
VDDQ (AC)(min.) (DC)(min.) VSWING(max.) VREF (DC)(max.) (AC)(max.) Falling slew VREF Rising slew (AC) min. VREF
(AC)(max.)
Input Test Signal Wave forms
Measurement point
Output Load
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Clock Jitter [DDR2-800]
-8E, Frequency (Mbps) Parameter Average clock period Clock period jitter Clock period jitter during locking period Cycle cycle period jitter Cycle cycle clock period jitter during locking period Cumulative error across cycles Cumulative error across cycles Cumulative error across cycles Cumulative error across cycles Cumulative error across n=6,7,8,9,10 cycles Cumulative error across n=11, 12,.49,50 cycles Average high pulse width Average pulse width Duty cycle jitter Symbol (avg) tJIT (per) tJIT (per, lck) tJIT (cc) tJIT (cc, lck) tERR (2per) tERR (3per) tERR (4per) tERR (5per) tERR (6-10per) tERR (11-50per) (avg) (avg) tJIT (duty) min. 2500 -100 -150 -175 -200 -200 -300 -450 0.48 0.48 -100 max. 8000 0.52 0.52 Unit (avg) (avg) Notes
Notes: (avg) calculated average clock period across consecutive 200cycle window.
(avg tCKj
(avg) defined average high pulse width, calculated across consecutive high pulses.
(avg tCHj (avg
(avg) defined average pulse width, calculated across consecutive pulses.
tCL(avg tCLj (avg
tJIT (duty) defined cumulative jitter jitter. jitter largest deviation single from (avg). jitter largest deviation single from (avg). tJIT (duty) subject production test. tJIT (duty) Min./Max. {tJIT (CH), tJIT (CL)}, where: tJIT (CH) {tCHj- (avg) where 200} tJIT (CL) {tCLj (avg) where 200} tJIT (per) defined largest deviation single from (avg). tJIT (per) Min./Max. tCKj (avg) where 200} tJIT (per) defines single period jitter when already locked. tJIT (per, lck) uses same definition single period jitter, during locking period only. tJIT (per) tJIT (per, lck) subject production test.
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
tJIT (cc) defined absolute difference clock period between consecutive clock cycles: tJIT (cc) Max. |tCKj+1 tCKj| tJIT (cc) defines cycle cycle jitter when already locked. tJIT (cc, lck) uses same definition cycle cycle jitter, during locking period only. tJIT (cc) tJIT (cc, lck) subject production test. tERR (nper) defined cumulative error across multiple consecutive cycles from (avg). tERR (nper) subject production test.
tERR(nper tCKj tCK(avg
tERR (nper) These parameters specified their average values, however understood that following relationship between average timing absolute instantaneous timing hold times. (minimum maximum spec values used calculations table below.)
Parameter Absolute clock period Absolute clock high pulse width Absolute clock pulse width Symbol (abs) (abs) (abs) min. (avg) min. tJIT (per) min. (avg) min. (avg) min. tJIT (duty) min. (avg) min. (avg) min. tJIT (duty) min. max. Unit (avg) max. tJIT (per) max. (avg) max. (avg) max. tJIT (duty) max. (avg) max. (avg) max. tJIT (duty) max.
Example: DDR2-667, tCH(abs) min. 0.48 3000 125ps 1315ps
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Functions
(input pin) master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (input pin) When low, commands data input. When high, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins) These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins) address (AX0 AX13) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin) defines precharge mode when precharge command, read command write command issued. high when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. high when read write command, auto-precharge function enabled. While low, auto-precharge function disabled. (input pins) BA0, bank select signals (BA). memory array divided into bank bank bank bank (See Bank Select Signal Table) [Bank Select Signal Table]
Bank Bank Bank Bank
Remark: VIH. VIL. (input pin) controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes high. level must kept cycle least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH. (input output pins) Data input output from these pins. /DQS (input output pin) /DQS provide read data strobes output) write data strobes input).
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
(input pins) reference signal data input mask function. sampled cross point /DQS. (power supply pins) 1.8V applied. (VDD internal circuit.) VDDSPD (power supply pin) 1.8V applied (For serial EEPROM). (power supply pin) Ground connected.
Detailed Operation Part Timing Waveforms
Refer EDE5108AHBG, EDE5116AHBG datasheet (E0933E).
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
Physical Outline
Unit:
3.18 3.00 (DATUM -A-)
63.00 133.35 55.00
1.27 0.10
10.00
17.80
4.00
Component area (Front)
(Back)
4.00
FULL
Detail
2.50 0.20
Detail 1.00 4.00
0.20 0.15
(DATUM -A-)
2.50 FULL
5.00
3.80
0.80 0.05
1.50 0.10
ECA-TS2-0126-02
Preliminary Data Sheet E01030E10 (Ver. 1.0)
30.00
EBE51UD8AHWA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E01030E10 (Ver. 1.0)
EBE51UD8AHWA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0107
Preliminary Data Sheet E01030E10 (Ver. 1.0)

EBE51UD8AHWA (64M words bits, Rank) Density: 512MB Organization w

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