ADCs integrated into package power channel MSPS Nyquist) ENOB bits SFD
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Quad, 14-Bit, MSPS Serial LVDS Converter AD9259
ADCs integrated into package power channel MSPS Nyquist) ENOB bits SFDR Nyquist) Excellent linearity ±0.5 (typical) ±1.5 (typical) Serial LVDS (ANSI-644, default) power, reduced signal option (similar IEEE 1596.3) Data frame clock outputs full-power analog bandwidth input voltage range supply operation Serial port control Full-chip individual-channel power-down modes Flexible orientation Built-in custom digital test pattern generation Programmable clock data alignment Programmable output resolution Standby mode
AVDD PDWN DRVDD DRGND
AD9259
VREF SENSE REFT REFB SELECT PIPELINE
SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS
PIPELINE PIPELINE PIPELINE
FCO+ 0.5V SERIAL PORT INTERFACE DATA RATE MULTIPLIER FCO- DCO+ DCO-
05965-001
RBIAS AGND SDIO/ODM SCLK/DTP CLK+ CLK-
Figure
APPLICATIONS
Medical imaging nondestructive ultrasound Portable ultrasound digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment
automatically multiplies sample rate clock appropriate LVDS serial data rate. data clock output (DCO) capturing data output frame clock output (FCO) signaling output byte provided. Individual-channel power-down supported typically consumes less than when channels disabled. contains several features designed maximize flexibility minimize system cost, such programmable clock data alignment programmable digital test pattern generation. available digital test patterns include built-in deterministic pseudorandom patterns, along with custom userdefined test patterns entered serial port interface (SPI). AD9259 available RoHS compliant, 48-lead LFCSP. specified over industrial temperature range -40°C +85°C.
GENERAL DESCRIPTION
AD9259 quad, 14-bit, MSPS analog-to-digital converter (ADC) with on-chip sample-and-hold circuit designed cost, power, small size, ease use. product operates conversion rate MSPS optimized outstanding dynamic performance power applications where small package size critical. requires single power supply LVPECL-/ CMOS-/LVDS-compatible sample rate clock full performance operation. external reference driver components required many applications.
PRODUCT HIGHLIGHTS
Small Footprint. Four ADCs contained small, spacesaving package. power mW/channel MSPS. Ease Use. data clock output (DCO) operates frequencies supports double data rate (DDR) operation. User Flexibility. control offers wide range flexible features meet specific system requirements. Pin-Compatible Family. This includes AD9287 (8-bit), AD9219 (10-bit), AD9228 (12-bit).
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
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AD9259 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Product Highlights Revision History Specifications. Specifications. Digital Specifications Switching Specifications Timing Diagrams. Absolute Maximum Ratings. Thermal Impedance Caution. Configuration Function Descriptions. Equivalent Circuits Typical Performance Characteristics Theory Operation Analog Input Considerations Clock Input Considerations. Serial Port Interface (SPI). Hardware Interface. Memory Reading Memory Table. Reserved Locations Default Values Logic Levels. Evaluation Board Power Supplies. Input Signals. Output Signals Default Operation Jumper Selection Settings. Alternative Analog Input Drive Configuration. Outline Dimensions Ordering Guide
REVISION HISTORY
7/07-Rev. Rev. Change General Description Changes Figure Figure Changes Hardware Interface Section. Changes Table 5/07-Rev. Rev. Changes Effective Number Bits (ENOB).4 Changes Logic Output (SDIO/ODM).5 Added Endnote Table Change Pipeline Latency Changes Figure Figure Changes Figure 10.12 Changes Figure Figure Figure Figure Changes Figure Figure Captions.15 Changes Figure 41.19 Changes Clock Duty Cycle Considerations Section.20 Changes Power Dissipation Power-Down Mode Section Changes Figure Figure Captions.23 Change Table 8.23 Changes Table Endnote Changes Digital Outputs Timing Section.25 Added Table 10.25 Changes RBIAS Section.26 Deleted Figure Figure Changes Figure 56.27 Changes Hardware Interface Section Added Figure 57.29 Changes Table 15.29 Changes Reading Memory Table Section.30 Change Output Signals Section.34 Changes Figure 60.34 Changes Default Operation Jumper Selection Settings Section Changes Alternative Analog Input Drive Configuration Section.36 Changes Figure 63.38 Changes Table 17.46 Changes Ordering Guide.50 6/06-Revision Initial Version
Rev. Page
AD9259 SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter RESOLUTION ACCURACY Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage Mode) REFERENCE Output Voltage Error (VREF Load Regulation (VREF Input Resistance ANALOG INPUTS Differential Input Voltage (VREF Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation CROSSTALK CROSSTALK (Overrange Condition)
Temperature
Unit Bits
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Guaranteed ±0.5 ±0.3 ±0.5 ±1.5 AVDD/2 32.5 -100 -100
±0.7 ±1.0 ±3.5
ppm/°C ppm/°C ppm/°C
192.5 34.7
AN-835 Application Note, Understanding High Speed Testing Evaluation, definitions details these tests were completed. controlled SPI. Overrange condition specific with full-scale input range.
Rev. Page
AD9259
SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter SIGNAL-TO-NOISE RATIO (SNR) 19.7 SIGNAL-TO-NOISE DISTORTION RATIO (SINAD) 19.7 EFFECTIVE NUMBER BITS (ENOB) 19.7 SPURIOUS-FREE DYNAMIC RANGE (SFDR) 19.7 WORST HARMONIC (Second Third) 19.7 WORST OTHER (Excluding Second Third) 19.7 TWO-TONE INTERMODULATION DISTORTION (IMD)- AIN1 AIN2 -7.0 dBFS fIN1 MHz, fIN2 fIN1 MHz, fIN2
Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
73.5 73.0 72.8 72.7 72.2 72.0 11.92 11.85 11.8
Unit Bits Bits Bits
71.0
70.2
11.5
25°C 25°C
80.0 80.0
AN-835 Application Note, Understanding High Speed Testing Evaluation, definitions details these tests were completed.
Rev. Page
AD9259
DIGITAL SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) Logic Voltage (IOH Logic Voltage (IOL DIGITAL OUTPUTS (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (Low Power, Reduced Signal Option) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default)
Temperature
CMOS/LVDS/LVPECL
Unit
Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full
1.79 0.05 LVDS DRVDD
Full Full
1.125 Offset binary
1.375
LVDS Full Full 1.10 Offset binary 1.30
AN-835 Application Note, Understanding High Speed Testing Evaluation, definitions details these tests were completed. This specified LVDS LVPECL only. This specified SDIO pins sharing same connection.
Rev. Page
AD9259
SWITCHING SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter CLOCK Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width (tEL) OUTPUT PARAMETERS3 Propagation Delay (tPD) Rise Time (tR) (20% 80%) Fall Time (tF) (20% 80%) Propagation Delay (tFCO) Propagation Delay (tCPD) Data Delay (tDATA)4 Delay (tFRAME)4 Data Data Skew (tDATA-MAX tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time
Temp Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Full
Unit MSPS MSPS cycles cycles
tFCO (tSAMPLE/28) (tSAMPLE/28) (tSAMPLE/28)
(tSAMPLE/28) (tSAMPLE/28)
(tSAMPLE/28) (tSAMPLE/28) ±150
25°C 25°C 25°C
AN-835 Application Note, Understanding High Speed Testing Evaluation, definitions details these tests were completed. Measured standard FR-4 material. adjusted SPI. tSAMPLE/28 based number bits multiplied delays based half duty cycles.
Rev. Page
AD9259 TIMING DIAGRAMS
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tDATA
05965-039
Figure 14-Bit Data Serial Stream, First (Default)
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tDATA
Figure 12-Bit Data Serial Stream, First
Rev. Page
05965-040
AD9259
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tDATA
05965-041
Figure 14-Bit Data Serial Stream, First
Rev. Page
AD9259 ABSOLUTE MAXIMUM RATINGS
Table
Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs DCO+, DCO-, FCO+, FCO-) CLK+, CLK- SDIO/ODM PDWN, SCLK/DTP, REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, sec) Storage Temperature Range (Ambient) With Respect AGND DRGND DRGND DRVDD DRGND Rating -0.3 +2.0 -0.3 +2.0 -0.3 +0.3 -2.0 +2.0 -0.3 +2.0
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL IMPEDANCE
AGND AGND AGND AGND AGND AGND -0.3 +3.9 -0.3 +2.0 -0.3 +2.0 -0.3 +3.9 -0.3 +2.0 -0.3 +2.0 -40°C +85°C 150°C 300°C -65°C +150°C
Table
Flow Velocity (m/sec)
12.6
Unit °C/W °C/W °C/W
4-layer with solid ground plane (simulated). Exposed soldered PCB.
CAUTION
Rev. Page
AD9259 CONFIGURATION FUNCTION DESCRIPTIONS
AVDD AVDD AVDD AVDD
INDICATOR
SENSE
RBIAS
AVDD
AVDD
AVDD
REFB
VREF
REFT
AVDD AVDD AVDD PDWN SDIO/ODM SCLK/DTP AVDD DRGND DRVDD
EXPOSED PADDLE, (BOTTOM PACKAGE)
AD9259
CLK- CLK+ AVDD
VIEW
AVDD DRGND DRVDD
FCO+
DCO+
Figure 48-Lead LFCSP Configuration, View
Table Function Descriptions
Mnemonic AGND AVDD DRGND DRVDD CLK- CLK+ FCO- FCO+ DCO- DCO+ SCLK/DTP SDIO/ODM PDWN Description Analog Ground (Exposed Paddle) Analog Supply Digital Output Driver Ground Digital Output Driver Supply Analog Input Complement Analog Input True Input Clock Complement Input Clock True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Frame Clock Output Complement Frame Clock Output True Data Clock Output Complement Data Clock Output True Serial Clock/Digital Test Pattern Serial Data IO/Output Driver Mode Chip Select Power-Down Analog Input True Analog Input Complement
Rev. Page
05965-003
FCO-
DCO-
AD9259
Mnemonic RBIAS SENSE VREF REFB REFT Description Analog Input Complement Analog Input True External resistor sets internal core bias current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) Analog Input True Analog Input Complement
Rev. Page
AD9259 EQUIVALENT CIRCUITS
DRVDD
05965-030
DRGND
Figure Equivalent Analog Input Circuit
Figure Equivalent Digital Output Circuit
CLK+
1.25V CLK-
SCLK/DTP PDWN
05965-032
05965-005
Figure Equivalent Clock Input Circuit
Figure Equivalent SCLK/DTP PDWN Input Circuit
RBIAS
SDIO/ODM
Figure Equivalent SDIO/ODM Input Circuit
05965-035
Figure Equivalent RBIAS Circuit
Rev. Page
05965-031
05965-033
AD9259
AVDD
VREF
05965-034
Figure Equivalent Input Circuit
Figure Equivalent VREF Circuit
SENSE
Figure Equivalent SENSE Circuit
05965-036
Rev. Page
05965-037
AD9259 TYPICAL PERFORMANCE CHARACTERISTICS
-0.5dBFS 73.8dB ENOB 11.97 BITS SFDR 83.4dBc
-0.5dBFS 67.31dB ENOB 10.89 BITS SFDR 77.38dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
-100
05965-052
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with MHz, fSAMPLE MSPS
Figure Single-Tone with MHz, fSAMPLE MSPS
-0.5dBFS 72.94dB ENOB 11.82 BITS SFDR 78.60dBc
-0.5dBFS 66.87dB ENOB 10.82 BITS SFDR 74.97dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
-100
05965-085
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with MHz, fSAMPLE MSPS
Figure Single-Tone with MHz, fSAMPLE MSPS
-0.5dBFS 71.96dB ENOB 11.66 BITS SFDR 76.68dBc
-0.5dBFS 65.62dB ENOB 10.61 BITS SFDR 68.11dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
-100
05965-053
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with MHz, fSAMPLE MSPS
Rev. Page
Figure Single-Tone with MHz, fSAMPLE MSPS
05965-050
-120
-120
05965-051
-120
-120
05965-054
-120
-120
AD9259
p-p, SFDR
35MHz fSAMPLE 50MSPS
p-p, SFDR
SNR/SFDR (dB)
SNR/SFDR (dB)
80dB REFERENCE p-p,
p-p,
05965-059
ENCODE (MSPS)
ANALOG INPUT LEVEL (dBFS)
Figure SNR/SFDR Encode, 10.3 MHz, fSAMPLE MSPS
Figure SNR/SFDR Analog Input Level, MHz, fSAMPLE MSPS
AIN1 AIN2 -7dBFS SFDR 87.76dBc IMD2 90.18dBc IMD3 87.27dBc
p-p, SFDR
AMPLITUDE (dBFS)
SNR/SFDR (dB)
p-p,
-100
ENCODE (MSPS)
05965-060
FREQUENCY (MHz)
Figure SNR/SFDR Encode, MHz, fSAMPLE MSPS
Figure Two-Tone with fIN1 fIN2 MHz, fSAMPLE MSPS
10.3MHz fSAMPLE 50MSPS
p-p, SFDR
AIN1 AIN2 -7dBFS SFDR 80.37dBc IMD2 79.75dBc IMD3 84.50dBc
AMPLITUDE (dBFS)
SNR/SFDR (dB)
05965-066
p-p,
80dB REFERENCE
-100
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure SNR/SFDR Analog Input Level, 10.3 MHz, fSAMPLE MSPS
Figure Two-Tone with fIN1 fIN2 MHz, fSAMPLE MSPS
Rev. Page
05965-055
-120
05965-056
-120
05965-065
AD9259
p-p, SFDR (dBc)
SNR/SFDR (dB)
p-p, (dB)
(LSB)
-0.1 -0.2 -0.3
-0.4
05965-071
1000
2000
4000
6000
ANALOG INPUT FREQUENCY (MHz)
8000 10000 12000 14000 16000 CODE
Figure SNR/SFDR Analog Input Frequency, fSAMPLE MSPS
Figure DNL, MHz, fSAMPLE MSPS
-45.0
p-p, SFDR
-45.5
SINAD/SFDR (dB)
-46.0
CMRR (dB)
-46.5
p-p, SINAD
-47.0
-47.5
05965-072
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure SINAD/SFDR Temperature, 10.3 MHz, fSAMPLE MSPS
Figure CMRR Frequency, fSAMPLE MSPS
1.006
NUMBER HITS (Millions)
(LSB)
-0.5 -1.0 -1.5 -2.0
05965-086
05965-073
2000
4000
6000
8000 10000 12000 14000 16000 CODE
CODE
Figure INL, MHz, fSAMPLE MSPS
Figure Input-Referred Noise Histogram, fSAMPLE MSPS
Rev. Page
05965-075
-48.0
05965-074
-0.5
AD9259
63.89dB NOTCH 18.0MHz NOTCH WIDTH 3.0MHz
FUNDAMENTAL LEVEL (dB)
05965-077
AMPLITUDE (dBFS)
-3dB CUTOFF 315MHz
-100
05965-076
-120
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Noise Power Ratio (NPR), fSAMPLE MSPS
Figure Full-Power Bandwidth Frequency, fSAMPLE MSPS
Rev. Page
AD9259 THEORY OPERATION
AD9259 architecture consists pipelined divided into three sections: 4-bit first stage followed eight 1.5-bit stages final 3-bit flash. Each stage provides sufficient overlap correct flash errors preceding stage. quantized outputs from each stage combined into final 14-bit result digital correction logic. pipelined architecture permits first stage operate with input sample while remaining stages operate with preceding samples. Sampling occurs rising edge clock. Each stage pipeline, excluding last, consists resolution flash connected switched-capacitor interstage residue amplifier (for example, multiplying digital-to-analog converter (MDAC)). residue amplifier magnifies difference between reconstructed output flash input next stage pipeline. redundancy used each stage facilitate digital correction flash errors. last stage simply consists flash ADC. output staging block aligns data, corrects errors, passes data output buffers. data then serialized aligned frame data clocks. inductors ferrite beads required when driving converter front high frequencies. Either shunt capacitor single-ended capacitors placed inputs provide matching passive network. This ultimately creates low-pass filter input limit unwanted broadband noise. AN-742 Application Note, AN-827 Application Note, Analog Dialogue article "Transformer-Coupled Front-End Wideband Converters" (Volume April 2005) more information. general, precise values depend application. analog inputs AD9259 internally dc-biased. Therefore, ac-coupled applications, user must provide this bias externally. Setting device that AVDD/2 recommended optimum performance, device function over wider range with reasonable performance, shown Figure Figure
2.3MHz fSAMPLE 50MSPS
SFDR (dBc)
SNR/SFDR (dB)
(dB)
ANALOG INPUT CONSIDERATIONS
analog input AD9259 differential switchedcapacitor circuit designed processing differential input signals. This circuit support wide common-mode range while maintaining excellent performance. using input common-mode voltage midsupply, users minimize signal-dependent errors achieve optimum performance.
ANALOG INPUT COMMON-MODE VOLTAGE
CPAR CSAMPLE CPAR
05965-006
Figure SNR/SFDR Common-Mode Voltage, MHz, fSAMPLE MSPS
CSAMPLE
30MHz fSAMPLE 50MSPS
SFDR (dBc)
SNR/SFDR (dB)
(dB)
Figure Switched-Capacitor Input Circuit
clock signal alternately switches input circuit between sample mode hold mode (see Figure 35). When input circuit switched sample mode, signal source must capable charging sample capacitors settling within one-half clock cycle. small resistor series with each input help reduce peak transient current injected from output stage driving source. addition, low-Q inductors ferrite beads placed each input reduce high differential capacitance analog inputs therefore achieve maximum bandwidth ADC. Such lowRev. Page
ANALOG INPUT COMMON-MODE VOLTAGE
Figure SNR/SFDR Common-Mode Voltage, MHz, fSAMPLE MSPS
05965-079
05965-078
AD9259
best dynamic performance, source impedances driving should matched such that commonmode settling errors symmetrical. These errors reduced common-mode rejection ADC. internal reference buffer creates positive negative reference voltages, REFT REFB, respectively, that define span core. output common-mode reference buffer midsupply, REFT REFB voltages span defined REFT (AVDD VREF) REFB (AVDD VREF) Span (REFT REFB) VREF seen from these equations that REFT REFB voltages symmetrical about midsupply voltage and, definition, input span twice value VREF voltage. Maximum performance achieved setting largest span differential configuration. case AD9259, largest input span available p-p.
ADT1-1WT RATIO 49.9 AVDD 0.1F
DIFF
05965-008
DIFF
AD9259
AGND
OPTIONAL.
Figure Differential Transformer-Coupled Configuration Baseband Applications
16nH ADT1-1WT 0.1F RATIO 16nH 16nH AVDD 0.1F
05965-047
2.2pF
AD9259
Differential Input Configurations
There several ways drive AD9259 either actively passively; however, optimum performance achieved driving analog input differentially. example, using AD8332 differential driver drive AD9259 provides excellent performance flexible interface (see Figure baseband applications. This configuration commonly used medical ultrasound systems. applications where parameter, differential transformer coupling recommended input configuration (see Figure Figure 39), because noise performance most amplifiers adequate achieve true performance AD9259. Regardless configuration, value shunt capacitor, dependent input frequency need reduced removed.
Figure Differential Transformer-Coupled Configuration Applications
Single-Ended Input Configuration
single-ended input provide adequate performance costsensitive applications. this configuration, SFDR distortion performance degrade large input common-mode swing. application requires single-ended input configuration, ensure that source impedances each input well matched order achieve best possible performance. full-scale input applied ADC's while terminated. Figure details typical singleended input configuration.
AVDD 49.9 0.1µF AVDD 0.1µF
DIFF
AD9259
DIFF
OPTIONAL.
Figure Single-Ended Input Configuration
0.1F
0.1F 120nH 22pF
680nH
AVDD
AD8332
68pF
AVDD
AD9259
0.1F
680nH
18nF
0.1F
Figure Differential Input Configuration Using AD8332 with Two-Pole, Low-Pass Filter
Rev. Page
05965-007
05965-009
AD9259
CLOCK INPUT CONSIDERATIONS
optimum performance, AD9259 sample clock inputs (CLK+ CLK-) should clocked with differential signal. This signal typically ac-coupled CLK+ CLK- pins transformer capacitors. These pins biased internally require additional biasing. Figure shows preferred method clocking AD9259. jitter clock source converted from single-ended signal differential signal using transformer. back-toback Schottky diodes across secondary transformer limit clock excursions into AD9259 approximately differential. This helps prevent large voltage swings clock from feeding through other portions AD9259, preserves fast rise fall times signal, which critical jitter performance.
Mini-Circuits® ADT1-1WT, 1:1Z 0.1µF XFMR 0.1µF 0.1µF SCHOTTKY DIODES: HSM2812
CLK+ input circuit supply AVDD (1.8 this input designed withstand input voltages therefore offers several selections drive logic voltage.
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
OPTIONAL 0.1µF
0.1µF
CLK+
CMOS DRIVER
CLK+
0.1µF
AD9259
CLK-
05965-027
0.1µF
RESISTOR OPTIONAL.
Figure Single-Ended CMOS Sample Clock
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
CMOS DRIVER 0.1µF
OPTIONAL 0.1µF
0.1µF CLK+
CLK+
0.1µF CLK+
CLK+
CLK-
05965-024
RESISTOR OPTIONAL.
Figure Single-Ended CMOS Sample Clock
Figure Transformer-Coupled Differential Clock
Clock Duty Cycle Considerations
Typical high speed ADCs both clock edges generate variety internal timing signals. result, these ADCs sensitive clock duty cycle. Commonly, tolerance required clock duty cycle maintain dynamic performance characteristics. AD9259 contains duty cycle stabilizer (DCS) that retimes nonsampling edge, providing internal clock signal with nominal duty cycle. This allows wide range clock input duty cycles without affecting performance AD9259. When noise distortion performance nearly flat wide range duty cycles. However, some applications require function off. keep mind that dynamic range performance affected when operated this mode. Memory section more details using this feature. Jitter rising edge input important concern, reduced internal stabilization circuit. duty cycle control loop does function clock rates less than nominal. loop time constant associated with that must considered applications where clock rate change dynamically. This requires wait time after dynamic clock frequency increase decrease) before loop relocked input signal. During period that loop locked, loop bypassed internal device timing dependent duty cycle input clock signal. such applications, appropriate disable duty cycle stabilizer. other applications, enabling circuit recommended maximize performance.
Another option ac-couple differential PECL signal sample clock input pins shown Figure AD9510/ family clock drivers offers excellent jitter performance.
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
0.1µF PECL DRIVER OPTIONAL.
05965-025
0.1µF CLK+
CLK+ 0.1µF
0.1µF CLK-
AD9259
CLK-
RESISTORS
Figure Differential PECL Sample Clock
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
0.1µF LVDS DRIVER OPTIONAL
05965-026
0.1µF CLK+
CLK+ 0.1µF
0.1µF CLK-
AD9259
CLK-
RESISTORS
Figure Differential LVDS Sample Clock
some applications, acceptable drive sample clock inputs with single-ended CMOS signal. such applications, CLK+ should driven directly from CMOS gate, CLK- should bypassed ground with capacitor parallel with resistor (see Figure 45). Although
Rev. Page
05965-028
AD9259
0.1µF
AD9259
CLK-
AD9259
Clock Jitter Considerations
High speed, high resolution ADCs sensitive quality clock input. degradation given input frequency (fA) only aperture jitter (tJ) calculated Degradation 10(1/2 this equation, aperture jitter represents root mean square jitter sources, including clock input, analog input signal, aperture jitter. undersampling applications particularly sensitive jitter (see Figure 47). clock input should treated analog signal cases where aperture jitter affect dynamic range AD9259. Power supplies clock drivers should separated from output driver supplies avoid modulating clock signal with digital noise. jitter, crystal-controlled oscillators best clock sources. clock generated from another type source gating, dividing, another method), should retimed original clock during last step. Refer AN-501 Application Note AN-756 Application Note more in-depth information about jitter performance relates ADCs.
(dB)
Power Dissipation Power-Down Mode
shown Figure power dissipated AD9259 proportional sample rate. digital power dissipation does vary significantly because determined primarily DRVDD supply bias current LVDS output drivers.
AVDD CURRENT
CURRENT (mA)
DRVDD CURRENT TOTAL POWER
ENCODE (MSPS)
Figure Supply Current fSAMPLE 10.3 MHz, fSAMPLE MSPS
CLOCK JITTER REQUIREMENT
BITS BITS BITS BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps ANALOG INPUT FREQUENCY (MHz) 1000
05965-038
Figure Ideal Input Frequency Jitter
Rev. Page
05965-089
POWER (mW)
AD9259
asserting PDWN high, AD9259 placed into power-down mode. this state, typically dissipates During power-down, LVDS output drivers placed into high impedance state. features changed before power-down feature enabled, chip continues function after PDWN pulled without requiring reset. AD9259 returns normal operating mode when PDWN pulled low. This both tolerant. power-down mode, power dissipation achieved shutting down reference, reference buffer, PLL, biasing networks. decoupling capacitors REFT REFB discharged when entering power-down mode must recharged when returning normal operation. result, wake-up time related time spent power-down mode: shorter cycles result proportionally shorter wake-up times. With recommended decoupling capacitors REFT REFB, approximately required fully discharge reference buffer decoupling capacitors approximately required restore full operation. There several other power-down options available when using SPI. user individually power down each channel entire device into standby mode. latter option allows user keep internal powered when fast wake-up times (~600 required. Memory section more details using these features.
05965-045
placed close receiver possible. there far-end receiver termination there poor differential trace routing, timing errors result. avoid such timing errors, recommended that trace length less than inches that differential output traces close together equal lengths. example data stream with proper trace length position shown Figure
500mV/DIV 500mV/DIV DATA 500mV/DIV
2.5ns/DIV
Figure LVDS Output Timing Example ANSI-644 Mode (Default)
Digital Outputs Timing
AD9259 differential outputs conform ANSI-644 LVDS standard default power-up. This changed power, reduced signal option (similar IEEE 1596.3 standard) SDIO/ODM SPI. LVDS standard further reduce overall power dissipation device approximately SDIO/ODM section Table Memory section more information. LVDS driver current derived on-chip sets output current each output equal nominal differential termination resistor placed LVDS receiver inputs results nominal swing receiver. AD9259 LVDS outputs facilitate interfacing with LVDS receivers custom ASICs FPGAs superior switching performance noisy environments. Single point-to-point topologies recommended with termination resistor
example LVDS output using ANSI-644 standard (default) data time interval error (TIE) jitter histogram with trace lengths less than inches standard FR-4 material shown Figure Figure shows example trace lengths exceeding inches standard FR-4 material. Notice that jitter histogram reflects decrease data opening edge deviates from ideal position. user's responsibility determine waveforms meet timing budget design when trace lengths exceed inches. Additional options allow user further increase internal termination (increasing current) four outputs order drive longer trace lengths (see Figure 52). Even though this produces sharper rise fall times data edges less prone errors, power dissipation DRVDD supply increases when this option used. addition, notice Figure that histogram improved compared with that shown Figure Memory section more details.
Rev. Page
AD9259
EYE: BITS ULS: 10000/15600
DIAGRAM VOLTAGE
EYE: BITS ULS: 9599/15599
DIAGRAM VOLTAGE
-200 -400
-500 -1.0ns -0.5ns 0.5ns 1.0ns
-1.0ns
-0.5ns
0.5ns
1.0ns
JITTER HISTOGRAM (Hits)
JITTER HISTOGRAM (Hits)
05965-043
-100ps
100ps
-150ps
-100ps
-50ps
50ps
100ps
150ps
Figure Data LVDS Outputs ANSI-644 Mode with Trace Lengths Less than Inches Standard FR-4, External Termination Only
EYE: BITS ULS: 9600/15600
Figure Data LVDS Outputs ANSI-644 Mode with Internal Termination Trace Lengths Greater than Inches Standard FR-4, External Termination Only
DIAGRAM VOLTAGE
format output data offset binary default. example output coding format found Table change output data format twos complement, Memory section. Table Digital Output Coding
Code 16383 8192 8191 (VIN (VIN Input Span +1.00 0.00 -0.000122 -1.00 Digital Output Offset Binary (D13 1111 1111 1111 0000 0000 0000 1111 1111 1111 0000 0000 0000
-200 -1.0ns -0.5ns 0.5ns 1.0ns
JITTER HISTOGRAM (Hits)
Data from each serialized provided separate channel. data rate each serial stream equal bits times sample clock rate, with maximum Mbps bits MSPS Mbps). lowest typical conversion rate MSPS. However, lower sample rates required specific application, allow encode rates MSPS. Memory section details enabling this feature.
-150ps
-100ps
-50ps
50ps
100ps
150ps
Figure Data LVDS Outputs ANSI-644 Mode with Trace Lengths Greater than Inches Standard FR-4, External Termination Only
Rev. Page
05965-044
05965-042
AD9259
output clocks provided assist capturing data from AD9259. used clock output data equal seven times sample clock (CLK) rate. Data clocked AD9259 must captured rising Table Flexible Output Test Modes
Output Test Mode Sequence 0000 0001 Pattern Name (default) Midscale short Digital Output Word 1000 0000 (8-bit) 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 1010 1010 1010 (14-bit) 1111 1111 (8-bit) 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 1111 1111 1111 (14-bit) Register 0x19 Register 0x1A 1010 1010 (8-bit) 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 1000 0110 0111 (14-bit) Digital Output Word Same Subject Data Format Select
falling edges that supports double data rate (DDR) capturing. used signal start output byte equal sample clock rate. timing diagram shown Figure more information.
0010
+Full-scale short
Same
0011
-Full-scale short
Same
0100
Checkerboard
0101 0110 0111
sequence long sequence short1 One-/zero-word toggle
1000 1001
User input 1-/0-bit toggle
0101 0101 (8-bit) 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 0101 0101 0101 (14-bit) 0000 0000 (8-bit) 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) Register 0x1B Register 0x1C
1010
sync
1011
high
1100
Mixed frequency
test mode options except sequence short sequence long support 14-bit word lengths order verify data capture receiver.
Rev. Page
AD9259
When used, phase adjusted increments relative data edge. This enables user refine system timing margins required. default DCO+ DCO- timing, shown Figure relative output data edge. 10-, 12-bit serial stream also initiated from SPI. This allows user implement test compatibility with lower resolution systems. When changing resolution 10-, 12-bit serial stream, data stream shortened. Figure 12-bit example. When used, data outputs also inverted from their nominal state. This confused with inverting serial stream LSB-first mode. default mode, shown Figure first data output serial stream. However, this inverted that first data output serial stream (see Figure There digital output test pattern options available that initiated through SPI. This useful feature when validating receiver capture timing. Refer Table output sequencing options available. Some test patterns have serial sequential words alternated various ways, depending test pattern chosen. Note that some patterns adhere data format select option. addition, custom user-defined test patterns assigned 0x19, 0x1A, 0x1B, 0x1C register addresses. test mode options except sequence short sequence long support 14-bit word lengths order verify data capture receiver. sequence short pattern produces pseudorandom sequence that repeats itself every bits. description sequence generated found Section ITU-T 0.150 (05/96) standard. only difference that starting value must specific value instead (see Table initial values). sequence long pattern produces pseudorandom sequence that repeats itself every 8,388,607 bits. description sequence generated found Section ITU-T 0.150 (05/96) standard. only differences that starting value must specific value instead (see Table initial values) AD9259 inverts stream with relation standard. Table Sequence
Sequence Sequence Short Sequence Long Initial Value 0x0df 0x26e028 First Three Output Samples (MSB First) 0x37e4, 0x3533, 0x0063 0x191f, 0x35c2, 0x2359
Consult Memory section information change these additional digital output timing features through SPI.
SDIO/ODM
SDIO/ODM applications that require mode operation. This enable power, reduced signal option (similar IEEE 1596.3 reduced range link output standard) tied AVDD during device power-up. This option should only used when digital output trace lengths less than inches from LVDS receiver. When this option used, FCO, DCO, outputs function normally, LVDS signal swing channels reduced from p-p, allowing user further reduce power DRVDD supply. applications where this used, should tied low. this case, device left open, internal pull-down resistor pulls this low. This only tolerant. applications require this driven from logic level, insert resistor series with this limit current. Table Output Driver Mode Settings
Selected Normal Operation Voltage AGND AVDD Resulting Output Standard ANSI-644 (default) power, reduced signal option Resulting ANSI-644 (default) power, reduced signal option
Rev. Page
AD9259
SCLK/DTP
SCLK/DTP applications that require mode operation. This enable single digital test pattern held high during device powerup. When SCLK/DTP tied AVDD, channel outputs shift following pattern: 0000 0000 0000. function normally while channels shift repeatable test pattern. This pattern allows user perform timing alignment adjustments among FCO, DCO, output data. normal operation, this should tied AGND through resistor. This both tolerant. Table Digital Test Pattern Settings
Selected Normal Operation Voltage AGND AVDD Resulting Normal operation 0000 0000 0000 Resulting Normal operation Normal operation
RBIAS
internal core bias current ADC, place resistor (nominally equal 10.0 ground RBIAS pin. resistor current derived on-chip sets AVDD current nominal MSPS. Therefore, imperative that least tolerance this resistor used achieve consistent performance.
Voltage Reference
stable, accurate voltage reference built into AD9259. This gained internally factor setting VREF which results full-scale differential input span p-p. VREF internally default; however, VREF driven externally with reference improve accuracy. When applying decoupling capacitors VREF, REFT, REFB pins, ceramic capacitors. These capacitors should close pins same layer AD9259. recommended capacitor values configurations AD9259 reference shown Figure Table Reference Settings
Selected Mode External Reference Internal, SENSE Voltage AVDD AGND Resulting VREF Resulting Differential Span p-p) external reference
Additional custom test patterns also observed when commanded from port. Consult Memory section information about options available.
should tied AVDD applications that require mode operation. tying high, SCLK SDIO information ignored. This both tolerant.
Rev. Page
AD9259
Internal Reference Operation
comparator within AD9259 detects potential SENSE configures reference. SENSE grounded, reference amplifier switch connected internal resistor divider (see Figure 53), setting VREF REFT REFB pins establish input span core from reference configuration. analog input fullscale range equals twice voltage reference either internal external reference configuration. reference AD9259 used drive multiple converters improve gain matching, loading reference other converters must considered. Figure depicts internal reference voltage affected loading.
REFT CORE 0.1µF 0.1µF REFB VREF 0.1µF SELECT LOGIC SENSE 0.5V
External Reference Operation
external reference necessary enhance gain accuracy improve thermal drift characteristics. Figure shows typical drift characteristics internal reference mode. When SENSE tied AVDD, internal reference disabled, allowing external reference. external reference loaded with equivalent load. internal reference buffer generates positive negative full-scale references, REFT REFB, core. Therefore, external reference must limited nominal
VREF ERROR
2.2µF
0.1µF
05965-083
CURRENT LOAD (mA)
Figure VREF Accuracy Load
05965-010
0.02 -0.02 -0.04
Figure Internal Reference Configuration
REFT CORE EXTERNAL REFERENCE VREF 1µF1 0.1µF1 AVDD SENSE SELECT LOGIC 0.5V 0.1µF 0.1µF REFB 0.1µF
VREF ERROR
-0.06 -0.08 -0.10 -0.12 -0.14 -0.16
05965-084
2.2µF
-0.18
TEMPERATURE (°C)
Figure Typical VREF Drift
1OPTIONAL.
Figure External Reference Operation
Rev. Page
05965-046
AD9259 SERIAL PORT INTERFACE (SPI)
AD9259 serial port interface allows user configure converter specific functions operations through structured register space provided ADC. This provide user with additional flexibility customization, depending application. Addresses accessed serial port written read from port. Memory organized into bytes that further divided into fields, documented Memory section. Detailed operational information found AN-877 Application Note, Interfacing High Speed ADCs SPI. There three pins that define SPI: SCLK, SDIO, (see Table 14). SCLK used synchronize read write data presented ADC. SDIO dualpurpose that allows data sent read from internal memory registers. active control that enables disables read write cycles. Table Serial Port Pins
SCLK SDIO Function Serial Clock. serial shift clock input. SCLK used synchronize serial interface reads writes. Serial Data Input/Output. dual-purpose pin. typical role this input output, depending instruction sent relative position timing frame. Chip Select (Active Low). This control gates read write cycles.
addition operation modes, port configuration influences AD9259 operates. applications that require control port, line tied held high. This places remainder pins into their secondary modes, defined SDIO/ODM SCLK/DTP sections. also tied enable 2-wire mode. When tied low, SCLK SDIO only pins required communication. Although device synchronized during power-up, user should ensure that serial port remains synchronized with line when using this mode. When operating 2-wire mode, recommended 3-byte transfer exclusively. Without active line, streaming mode entered exited. addition word length, instruction phase determines serial frame read write operation, allowing serial port used both program chip read contents on-chip memory. instruction readback operation, performing readback causes SDIO change from input output appropriate point serial frame. Data sent MSB- LSB-first mode. MSB-first mode default power-up changed adjusting configuration register. more information about this other features, AN-877 Application Note, Interfacing High Speed ADCs SPI.
HARDWARE INTERFACE
pins described Table compose physical interface between user's programming device serial port AD9259. SCLK pins function inputs when using SPI. SDIO bidirectional, functioning input during write phases output during readback. multiple SDIO pins share common connection, care should taken ensure that proper levels met. Assuming same load each AD9259, Figure shows number SDIO pins that connected together resulting level. This interface flexible enough controlled either serial PROMS mirocontrollers, providing user with alternative method, other than full controller, program (see AN-812 Application Note).
falling edge conjunction with rising edge SCLK determines start framing sequence. During instruction phase, 16-bit instruction transmitted, followed more data bytes, which determined Field Field example serial timing definitions found Figure Table During normal operation, used signal device that commands received processed. When brought low, device processes SCLK SDIO obtain instructions. Normally, remains until communication cycle complete. However, connected slow device, brought high between bytes, allowing older microcontrollers enough time transfer data into shift registers. stalled when transferring one, two, three bytes data. When device enters streaming mode continues process data, either reading writing, until taken high communication cycle. This allows complete memory transfers without requiring additional instructions. Regardless mode, taken high middle byte transfer, state machine reset device waits instruction.
Rev. Page
AD9259
1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715
user chooses SPI, these dual-function pins serve their secondary functions when strapped AVDD during device power-up. Theory Operation section details which pin-strappable functions supported pins. users wish operate without using SPI, remove connections from CSB, SCLK/DTP, SDIO/ODM pins. disconnecting these pins from control bus, function most basic operation. Each these pins internal termination that floats respective level.
NUMBER SDIO PINS CONNECTED TOGETHER
05965-093
Figure SDIO Loading
tCLK
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
DON'T CARE
Figure Serial Timing Details
Table Serial Timing Definitions
Parameter tCLK tEN_SDIO tDIS_SDIO Timing (Minimum, Description Setup time between data rising edge SCLK Hold time between data rising edge SCLK Period clock Setup time between SCLK Hold time between SCLK Minimum period that SCLK should logic high state Minimum period that SCLK should logic state Minimum time SDIO switch from input output relative SCLK falling edge (not shown Figure Minimum time SDIO switch from output input relative SCLK rising edge (not shown Figure
Rev. Page
05965-012
AD9259 MEMORY
READING MEMORY TABLE
Each memory register table (Table eight address locations. memory divided into three sections: chip configuration register (Address 0x00 Address 0x02), device index transfer register (Address 0x05 Address 0xFF), functions register (Address 0x08 Address 0x22). leftmost column memory indicates register address number, default value shown second rightmost column. (MSB) column start default hexadecimal value given. example, Address 0x09, clock register, default value 0x01, meaning that 0000 0001 binary. This setting default duty cycle stabilizer condition. writing this address followed 0x01 Register 0xFF (transfer bit), duty cycle stabilizer turns off. important follow each writing sequence with transfer update registers. more information this other functions, consult AN-877 Application Note, Interfacing High Speed ADCs SPI.
RESERVED LOCATIONS
Undefined memory locations should written except when writing default values suggested this data sheet. Addresses that have values marked should considered reserved have written into their registers during power-up.
DEFAULT VALUES
When AD9259 comes reset, critical registers preloaded with default values. These values indicated Table where refers undefined feature.
LOGIC LEVELS
explanation various registers follows: "Bit set" synonymous with "bit Logic "writing Logic bit." Similarly, "clear bit" synonymous with "bit Logic "writing Logic bit."
Rev. Page
AD9259
Table Memory Register
Addr. (MSB) (Hex) Register Name Chip Configuration Registers chip_port_config first (default) Soft reset (default) Soft reset (default) first (default) (LSB) Default Value (Hex) 0x18 Default Notes/ Comments nibbles should mirrored that LSB- MSB-first mode correctly regardless shift mode. Default unique chip This read-only register. Child used differentiate graded devices. Bits determine which on-chip device receives next write command. Synchronously transfers data from master shift register slave. Determines various generic modes chip operation. Turns internal duty cycle stabilizer off.
chip_id
8-bit Chip Bits [7:0] (AD9259 0x04), (default)
0x04 Read only Read only
chip_grade
Child [6:4] (identify device variants Chip MSPS Clock Channel (default) Clock Channel (default)
Device Index Transfer Registers device_index_A
device_update
Data Channel (default)
Data Channel (default)
Data Channel (default)
Data Channel (default) transfer (default)
0x0F
0x00
Functions modes
clock
Internal power-down mode chip (default) full power-down standby reset Duty cycle stabilizer (default)
0x00
0x01
test_io
User test mode (default) single alternate single once alternate once
Reset long (default)
Reset short (default)
Output test mode-see Table Digital Outputs Timing section 0000 (default) 0001 midscale short 0010 short 0011 short 0100 checkerboard output 0101 sequence 0110 sequence 0111 one-/zero-word toggle 1000 user input 1001 1-/0-bit toggle 1010 sync 1011 high 1100 mixed frequency (format determined output_mode)
0x00
When this register set, test data placed output pins place normal data.
Rev. Page
AD9259
Addr. (Hex) Register Name output_mode (MSB) LVDS ANSI-644 (default) LVDS power (IEEE 1596.3 similar) Output invert (default) (LSB) offset binary (default) twos complement Default Value (Hex) 0x00 Default Notes/ Comments Configures outputs format data.
output_adjust
Output driver termination none (default)
0x00
output_phase
user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb serial_control
first (default)
0011 output clock phase adjust (0000 through 1010) 0000 relative data edge 0001 relative data edge 0010 120° relative data edge 0011 180° relative data edge (default) 0100 240° relative data edge 0101 300° relative data edge 0110 360° relative data edge 0111 420° relative data edge 1000 480° relative data edge 1001 540° relative data edge 1010 600° relative data edge 1011 1111 660° relative data edge MSPS, encode rate mode (default)
0x03
Determines LVDS other output properties. Primarily functions LVDS span common-mode levels place external resistor. devices that utilize global clock divide, determines which phase divider output used supply output clock. Internal latching unaffected.
0x00 0x00 0x00 0x00 0x00
bits (default, normal stream) bits bits bits bits
User-defined pattern, LSB. User-defined pattern, MSB. User-defined pattern, LSB. User-defined pattern, MSB. Serial stream control. Default causes first native stream (global).
serial_ch_stat
Channel output reset (default)
Channel powerdown (default)
0x00
Used power down individual sections converter (local).
Rev. Page
AD9259
Power Ground Recommendations
When connecting power AD9259, recommended that separate supplies used: analog (AVDD) digital (DRVDD). only supply available, should routed AVDD first then tapped isolated with ferrite bead filter choke preceded decoupling capacitors DRVDD. user employ several different decoupling capacitors cover both high frequencies. These should located close point entry board level close parts, with minimal trace lengths. single board ground plane should sufficient when using AD9259. With proper decoupling smart partitioning board's analog, digital, clock sections, optimum performance easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
required that exposed paddle underside connected analog ground (AGND) achieve best electrical thermal performance AD9259. exposed continuous copper plane should mate AD9259 exposed paddle, copper plane should have several vias achieve lowest possible resistive thermal path heat dissipation flow through bottom PCB. These vias should solder-filled plugged. maximize coverage adhesion between PCB, partition continuous copper plane overlaying silkscreen into several uniform sections. This provides several points between during reflow process, whereas using continuous plane with partitions only guarantees point. Figure layout example. detailed information packaging layout chip scale packages, AN-772 Application Note, Design Manufacturing Guide Lead Frame Chip Scale Package (LFCSP).
SILKSCREEN PARTITION INDICATOR
Figure Typical Layout
Rev. Page
05965-013
AD9259 EVALUATION BOARD
AD9259 evaluation board provides support circuitry required operate various modes configurations. converter driven differentially using transformer (default) AD8332 driver. also driven single-ended fashion. Separate power pins provided isolate from drive circuitry AD8332. Each input configuration selected changing connection various jumpers (see Figure Figure 66). Figure shows typical bench characterization setup used evaluate performance AD9259. critical that signal sources used analog input clock have very phase noise jitter) realize optimum performance converter. Proper filtering analog input signal remove harmonics lower integrated broadband noise input also necessary achieve specified noise performance. Figure Figure complete schematics layout diagrams demonstrating routing grounding techniques that should applied system level. each section. least supply needed AVDD_DUT DRVDD_DUT; however, recommended that separate supplies used analog digital signals that each supply have current capability operate evaluation board using option, separate analog supply (AVDD_5 needed. operate evaluation board using alternate clock options, separate analog supply (AVDD_3.3 needed addition other supplies.
INPUT SIGNALS
When connecting clock analog source evaluation board, clean signal generators with phase noise, such Rohde Schwarz SMHU HP8644 signal generators equivalent, well shielded, RG-58, coaxial cable. Enter desired frequency amplitude from specifications tables. Typically, most Analog Devices evaluation boards accept approximately sine wave input clock. When connecting analog input source, recommended multipole, narrow-band, band-pass filter with terminations. Good choices such band-pass filters available from TTE, Allen Avionics, Microwave, Inc. filter should connected directly evaluation board possible.
POWER SUPPLIES
This evaluation board wall-mountable switching power supply that provides maximum output. Connect supply rated wall outlet other supply inner diameter jack that connects P503. Once board, supply fused conditioned before connecting three dropout linear regulators that supply proper bias each various sections board. When operating evaluation board nondefault condition, L504 L507 removed disconnect switching power supply. This enables user bias each section board individually. P501 connect different supply
OUTPUT SIGNALS
default setup uses Analog Devices, Inc., HSC-ADCFPGA-4/HSC-ADC-FPGA-8 high speed deserialization board deserialize digital output data convert parallel CMOS. These channels interface directly with Analog Devices standard dual-channel FIFO data capture board (HSCADC-EVALB-DC). four channels then evaluated same time. more information channel settings optional settings these boards, visit www.analog.com/FIFO.
WALL OUTLET 100V 240V 47Hz 63Hz SWITCHING POWER SUPPLY
5.0V
1.8V
1.8V
3.3V
3.3V
1.5V
3.3V
1.5V_FPGA
3.3V_D
AVDD_5V
DRVDD_DUT
AVDD_3.3V
AVDD_DUT
ROHDE SCHWARZ, SMHU, SIGNAL SYNTHESIZER ROHDE SCHWARZ, SMHU, SIGNAL SYNTHESIZER
BAND-PASS FILTER
XFMR INPUT
AD9259
EVALUATION BOARD 14-BIT SERIAL LVDS
Figure Evaluation Board Connection
Rev. Page
05965-014
HSC-ADC-FPGA-4/ HSC-ADC-FPGA-8 HIGH SPEED DESERIALIZATION BOARD 14-BIT PARALLEL CMOS
HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD CONNECTION
RUNNING ANALYZER USER SOFTWARE
AD9259
DEFAULT OPERATION JUMPER SELECTION SETTINGS
following list default optional settings modes allowed AD9259 Rev. evaluation board. POWER: Connect switching power supply that provided evaluation between rated wall outlet P503. AIN: evaluation board transformercoupled analog input with optimum impedance match bandwidth (see Figure 61). more bandwidth response, differential capacitor across analog inputs changed removed. common mode analog inputs developed from center transformer AVDD_DUT/2.
differential LVPECL clock also used clock input using AD9515 (U202). Populate R225 R227 with resistors remove R217 R218 disconnect default clock path inputs. addition, populate C207 C208 with capacitor remove C210 C211 disconnect default clock path outputs. AD9515 many pin-strappable options that default mode operation. Consult AD9515 data sheet more information about these other options. addition, on-board oscillator available OSC201 primary clock source. setup quick involves installing R212 with resistor setting enable jumper (J205) position. user wishes employ different oscillator, oscillator footprint options available (OSC201) check performance. PDWN: enable power-down feature, short J201 AVDD PDWN pin. SCLK/DTP: enable digital test pattern digital outputs ADC, J204. J204 tied AVDD during device power-up, Test Pattern 0000 0000 0000 enabled. SCLK/DTP section details. SDIO/ODM: enable power, reduced signal option (similar IEEE 1595.3 reduced range link LVDS output standard), J203. J203 tied AVDD during device power-up, enables LVDS outputs power, reduced signal option from default ANSI-644 standard. This option changes signal swing from p-p, reducing power DRVDD supply. SDIO/ODM section more details. CSB: enable processing information SDIO SCLK pins, J202 always enable mode. ignore SDIO SCLK information, J202 AVDD. Non-SPI Mode: users wish operate without using SPI, remove Jumpers J202, J203, J204. This disconnects CSB, SCLK/DTP, SDIO/ODM pins from control bus, allowing operate simplest mode. Each these pins internal termination will float respective level. alternative data capture method setup shown Figure used, optional receiver terminations, R206 R211, installed next high speed backplane connector.
-3dB CUTOFF 200MHz
AMPLITUDE (dBFS)
05965-088
FREQUENCY (MHz)
Figure Evaluation Board Full-Power Bandwidth
VREF: VREF tying SENSE ground, R237. This causes operate full-scale range. separate external reference option using ADR510 ADR520 also included evaluation board. Populate R231 R235 remove C214. Proper VREF options noted Voltage Reference section. RBIAS: RBIAS default setting (R201) ground used core bias current. CLOCK: default clock input circuitry derived from simple transformer-coupled circuit using high bandwidth impedance ratio transformer (T201) that adds very amount jitter clock path. clock input terminated ac-coupled handle single-ended sine wave types inputs. transformer converts single-ended input differential signal that clipped before entering clock inputs.
Rev. Page
AD9259
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION
following brief description alternative analog input drive configuration using AD8332 dual VGA. this drive option use, some components need populated, which case necessary components listed Table more details AD8332 dual VGA, including works optional settings, consult AD8332 data sheet. configure analog input drive instead default transformer option, following components need removed and/or changed. Remove R102, R115, R128, R141, R161, R162, R163, R164, T101, T102, T103, T104 default analog input path. Populate R101, R114, R127, R140 with resistors analog input path. Populate R105, R113, R118, R124, R131, R137, R151, R160 with resistors analog input path connect AD8332. Populate R152, R153, R154, R155, R156, R157, R158, R159, C103, C105, C110, C112, C117, C119, C124, C126 with resistors provide input common-mode level analog inputs. Remove R305, R306, R313, R314, R405, R406, R412, R424 configure AD8332.
this configuration, L301 L308 L401 L408 populated with resistors allow signal connection filter additional requirements necessary.
Rev. Page
AD9259
AVDD_DUT R105 FB102 R108 R106
CH_A P102 INPUT CONNECTION INH1 CHANNEL R101 P101 R102 64.9 R103 R104 C101 0.1µF
R152
T101
VIN_A R161 C103 C104 2.2pF R109 VIN_A FB103 R110 C105 R156
R107
R113 FB101 C102 0.1µF CH_A E101
AVDD_DUT
R111 R112
C107 0.1µF
C106
AVDD_DUT AVDD_DUT
INPUT CONNECTION INH2 CHANNEL R114 P103 R115 64.9 P104 R117
CH_B
R118 FB105 R121 R119
R153
T102
FB104 C108 0.1µF R116
VIN_B R162 C110 C111 2.2pF R123 VIN_B FB106 R122 C112 R157
R120
R124 C109 0.1µF CH_B E102
AVDD_DUT
R125 R126
C114 0.1µF
C113 AVDD_DUT R154
AVDD_DUT
CH_C P106 INPUT CONNECTION INH3 CHANNEL R127 P105 R128 64.9 R129 R130 C115 0.1µF
R131 FB108 R134 R132
T103
VIN_C R163 C117 C118 2.2pF R135 VIN_C R158
R133
R137 FB107 C116 0.1µF CH_C E103
FB109 R136 C120
C119
AVDD_DUT
R138 R139
C121 0.1µF
AVDD_DUT AVDD_DUT
INPUT CONNECTION INH4 CHANNEL R140 P107 R141 64.9 P108 R142
CH_D
R151 FB111 R146 R144
R155
T104
FB110 C122 0.1µF
VIN_D R164 C124 C125 2.2pF R148 VIN_D FB112 R147 C126 R159
R145
R160 R143 C123 0.1µF CH_D E104
AVDD_DUT
DNP: POPULATE
Figure Evaluation Board Schematic, Analog Inputs
Rev. Page
05965-015
R149 R150
C128 0.1µF
C127
AVDD_DUT
REFERENCE CIRCUIT OPTIONAL AVDD_DUT R229 4.99k R231 R234 VREF 0.5V VREF EXTERNAL
R202 100k J201
AD9259
C204 0.1µF
REFERENCE DECOUPLING
VREF_DUT
VREF SELECT VSENSE_DUT
DIGITAL OUTPUTS
U203 ADR510/20 TRIM/NC
R246 R248 R250 R252 R254 R251 R253 R255 R249 R247 R256 R258 AVDD_3.3V R260 AVDD_3.3V AVDD_3.3V R262 R264 AVDD_3.3V R257 R259 R261 R263 R265 GNDCD2 C2GNDCD1
C202 2.2µF
C203 0.1µF
R232 R235 R236 VREF 0.5V(1+R232/R233) VREF R237
AVDD_DUT
R201 R228 470k C213 0.1µF R233 C214 C212 0.1µF
R230
R206 R207 R208 R209 R210 R211
AVDD_DUT AVDD_DUT
VIN_C VIN_C
VREF_DUT VSENSE_DUT AVDD_DUT VIN_B VIN_B
C201 0.1µF
U201
AVDD AVDD REFT REFB VREF SENSE RBIAS AVDD
AVDD_DUT REMOVE C214 WHEN USING EXTERNAL VREF
PWDN ENABLE ALWAYS ENABLE
AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V R244 R245
AVDD_DUT AVDD_DUT VIN_A VIN_A AVDD_DUT
R266 100k
R267 100k
AD9259 LFCSP
AVDD AVDD AVDD PDWN J202
P202 GNDCD10 GNDCD9 GNDCD8 GNDCD7 GNDCD6 GNDCD5 GNDCD4 GNDCD3
ENABLE
CSB_DUT
FCO- FCO+ DCO- DCO+
R203 100k
R204 100k
R205
AVDD_DUT AVDD_DUT VIN_D VIN_D AVDD_DUT AVDD_DUT AVDD_DUT AVDD_DUT DRVDD_DUT
SDIO/ODM SCLK/DTP AVDD DRGND DRVDD
AVDD AVDD AVDD AVDD CLK- CLK+ AVDD AVDD DRGND DRVDD
AVDD_DUT DRVDD_DUT ENABLE
J203 SDIO_ODM J204 SCLK_DTP
GNDAB10 GNDAB9 SCLK_CHB SDI_CHB
GNDAB8
AVDD_3.3V AVDD_3.3V AVDD_3.3V
CSB3_CHB
GNDAB7
GNDAB6
R220 U202
R221
RSET
ENCODE INPUT
E201
R238
R239
VREF
T201
CR201 HSMS2812
R216
C216 0.1µF
R218 C206 0.1µF R224
Figure Evaluation Board Schematic, DUT, VREF, Clock Inputs, Digital Output Interface
R214 ENABLE J205 AVDD_3.3V OPTIONAL CLOCK DRIVE CIRCUIT R222 4.12k AVDD_3.3V C207 0.1µF LVPECL OUTPUT OUT0 OUT0B R240 OUT1 OUT1B R241 R243 C210 0.1µF C209 0.1µF E202 LVDS OUTPUT E203 C215 0.1µF CLIP SINE (DEFAULT) C217 0.1µF C218 0.1µF C219 0.1µF C220 0.1µF C221 0.1µF AVDD_3.3V SDO_CHB R242 DISABLE R219 R215 OPT_CLK GND_PAD
Rev. Page
R225
OPT_CLK
AVDD_3.3V
C224 0.1µF
GNDAB5
OPTIONAL CLOCK OSCILLATOR
GNDAB4
GNDAB3
AVDD_3.3V
C208 0.1µF CSB4_CHB
GNDAB2
SCLK_CHA SDI_CHA
GNDAB1
R226 49.9 CLKB
CSB1_CHA CSB2_CHA SDO_CHA
OSC201 VCC' OUT' GND' VFAC3H-L R212
AD9515
SIGNAL AVDD_3.3V; 17,20, SIGNAL DNC;27,28
SYNCB
P201
CONNECT
OPT_CLK
R227
HEADER 6469169-1
CLOCK CIRCUIT
R213 49.9k
C205 0.1µF
R205 R211 OPTIONAL OUTPUT TERMINATIONS
P203
OPT_CLK
R217
R223
C222 0.1µF
C223 0.1µF
DNP: POPULATE
C211 0.1µF
05965-016
AD9259
POPULATE L301 L308 WITH RESISTORS DESIGN YOUR FILTER.
CH_D
CH_D
CH_C
R301 C301 L301
R302 C302 L302 L303 L304 C304 L308 R304 C308 0.1µF C309 1000pF R310
CH_C
EXTERNAL VARIABLE GAIN DRIVE VARIABLE GAIN CIRCUIT 1.0V AVDD_5V R320 R319
JP301
POWER DOWN ENABLE DISABLE POWER)
C303 L305 R303 C305 0.1µF R305 R307 U301 ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 R308
L306 L307
OPTIONAL DRIVE CIRCUIT CHANNEL CHANNEL
AVDD_5V
R306 R309
AVDD_5V
VOL1 VPSV
AD8332
LON1 VPS1 INH1
LMD1 LMD2
C312 0.1µF
INH2 VPS2 LON2
C311 0.1µF
C313 0.1µF
C314 0.1µF
R315
C315 10µF
C316 0.1µF
R316 C317 0.018µF
C320 0.1µF
C321 0.1µF
R317 C322 0.018µF
C325 0.1µF
C326 10µF
R318
C318 22pF L309 120nH C319 0.1µF
C323 22pF L310 120nH C324 0.1µF INH3
05965-017
DNP: POPULATE
INH4
Figure Evaluation Board Schematic, Optional Analog Input Drive Interface Circuit
Rev. Page
MODE POSITIVE GAIN SLOPE 1.0V NEGATIVE GAIN SLOPE 2.25V 5.0V
HILO GAIN RANGE 2.25V 5.0V GAIN RANGE 1.0V
R313
VOL2 VOH2 COMM
COMM VOH1
R312
AVDD_5V
C310 0.1µF
R311
RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2
R314
AVDD_5V
AVDD_5V
RCLAMP HILO ±50mV HILO ±75mV
C306 C307 0.1µF 0.1µF
AD9259
CH_B
CH_B
CH_A
R401 C401 L401 CIRCUITRY FROM FIFO PROGRAMMING AVDD_5V +3.3V NORMAL OPERATION AVDD_3.3V AVDD_3.3V AVDD_5V J402 C427 0.1µF U402 R422 SDIO_ODM R423 R421 C402 L402 L403 L404
R402
POWER DOWN ENABLE DISABLE POWER)
POPULATE L401 L408 WITH RESISTORS DESIGN YOUR FILTER.
C403 L405 R403 L406 L407
C404 L408 R404
CH_A
CSB1_CHA
SCLK_CHA
SDI_CHA
C405 0.1µF
C406 C407 0.1µF 0.1µF
R407 R410
R408
AVDD_5V
R409
C412 0.1µF
R426
R428
R420
R427
R405 C411 1000pF R413
R406
C408 0.1µF
SDO_CHA
REMOVE WHEN USING PROGRAMMING (U402)
AVDD_3.3V
AVDD_5V
AVDD_5V RCLAMP HILO ±50mV HILO ±75mV
R411
U401
R433
COMM VOH1
VOL1 VPSV
VOL2 VOH2 COMM
R412
RESET/REPROGRAM
R424
MCLR/ PIC12F629 R419 CR401
R418 4.75k
S401
AVDD_DUT R431 R425 AVDD_DUT
OPTIONAL
LON1 VPS1 INH1
LMD1 LMD2
C410 0.1µF
INH2 VPS2 LON2
OPTIONAL DRIVE CIRCUIT CHANNEL CHANNEL
HILO GAIN RANGE 2.25V-5.0V GAIN RANGE 1.0V
AVDD_5V
AVDD_5V
MODE POSITIVE GAIN SLOPE 1.0V NEGATIVE GAIN SLOPE 2.25V-5.0V
R416 C420 0.018µF
Figure Evaluation Board Schematic, Optional Analog Input Drive Interface Circuit (Continued)
AD8332 C423 0.1µF RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2 C424 0.1µF R432 NC7WZ07
Rev. Page
E401 R415 C416 0.1µF C417 0.1µF C425 0.1µF C426 R417 10µF
C409 0.1µF
ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1
U403
C429 0.1µF
MCLR/GP3
J401 PICVCC
R414
C413 10µF
C414 0.1µF
C415 0.018µF
NC7WZ16 R430 R429
SCLK_DTP AVDD_DUT CSB_DUT
PICVCC
MCLR/GP3
PROGRAMMING HEADER
C418 22pF L409 120nH L410 120nH C422 0.1µF INH1 DNP: POPULATE C419 0.1µF
C421 22pF
U404
C428 0.1µF
INH2
05965-018
POWER SUPPLY INPUT MAXIMUM F501 FER501 CHOKE_COIL CR501 R501 PWR_IN SMDC110F C501 10µF D501 S2A_RECT DO-214AA P503
D502 SHOT_RECT DO-214AB
OPTIONAL POWER INPUT P501 5V_AVDD AVDD_5V C502 10µF C503 0.1µF C518 0.1µF C519 0.1µF L502 10µH AVDD_DUT C504 10µF C505 0.1µF L508 10µH AVDD_3.3V C508 10µF C509 0.1µF +3.3V AVDD_3.3V C524 0.1µF C525 0.1µF C526 0.1µF +1.8V AVDD_DUT C527 0.1µF C528 0.1µF +5.0V AVDD_5V C520 0.1µF DUT_AVDD 3.3V_AVDD DUT_DRVDD L503 10µH
DECOUPLING CAPACITORS
C521 0.1µF
C522 0.1µF
C523 0.1µF
C529 0.1µF
C530 0.1µF
C531 0.1µF
C514
U503 PWR_IN INPUT
U504 L504 10µH DUT_DRVDD PWR_IN ADP3339AKC-5 INPUT C513 C534
ADP3339AKC-1.8 OUTPUT1 OUTPUT4
C515
C532
DNP: POPULATE
05965-019
Figure Evaluation Board Schematic, Power Supply Inputs
Rev. Page
L501 10µH DRVDD_DUT +1.8V DRVDD_DUT C506 10µF C507 0.1µF U501 PWR_IN INPUT OUTPUT4 OUTPUT1 ADP3339AKC-1.8 L505 10µH DUT_AVDD PWR_IN C512
C516 0.1µF
C517 0.1µF
MOUNTING HOLES CONNECTED GROUND
U502 ADP3339AKC-3.3 INPUT OUTPUT1 OUTPUT4
L506 10µH 3.3V_AVDD C533
OUTPUT1
OUTPUT4
L507 10µH 5V_AVDD C535
AD9259
AD9259
Figure Evaluation Board Layout, Primary Side
Rev. Page
05965-020
AD9259
Figure Evaluation Board Layout, Ground Plane
Rev. Page
05965-021
AD9259
Figure Evaluation Board Layout, Power Plane
Rev. Page
05965-022
AD9259
Figure Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. Page
05965-023
AD9259
Table Evaluation Board Bill Materials (BOM)
Item Qty. Reference Designator AD9259LFCSP_REVA C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, C218, C219, C220, C221, C222, C223, C224, C310, C311, C312, C313, C314, C316, C319, C320, C321, C324, C325, C409, C410, C412, C414, C416, C417, C419, C422, C423, C424, C425, C427, C428, C429, C503, C505, C507, C509, C516, C517, C518, C519, C520, C521, C522, C523, C524, C525, C526, C527, C528, C529, C530, C531 C104, C111, C118, C125 C315, C326, C413, C426 C202 C309, C411 C317, C322, C415, C420 C318, C323, C418, C421 C501 C214, C512, C513, C514, C515, C532, C533, C534, C535 C305, C306, C307, C308, C405, C406, C407, C408 C502, C504, C506, C508 CR201 CR401, CR501 D502 D501 Device Capacitor Package Value ceramic, X5R, Manufacturer Murata Manufacturer's Part Number GRM155R71C104KA88D
Capacitor
Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor
1206
ceramic, COG, 0.25 tol, ±10% ceramic, ceramic, X5R, 1000 ceramic, X7R, 0.018 ceramic, X7R, ceramic, NPO, tol, tantalum, ceramic, X5R, ceramic, X7R, ceramic, X5R, dual Schottky Green, candela
Murata
GRM1555C1H2R2GZ01B
Murata Murata Murata Murata Rohm Murata
GRM219R60J106KE19D GRM188C70J225KE20D GRM155R71H102KA01D 0402YC183KAT2A GRM1555C1H220JZ01D TCA1C106M8R GRM188R61C105KA93D
Capacitor
Murata
GRM21BR71H104KA01L
Capacitor Diode Diode Diode
SOT-23 DO-214AB DO-214AA
Murata Agilent Technologies Panasonic Micro Commercial Micro Commercial
GRM188R60J106M HSMS2812-TRIG LNJ314G8TRA SK33-TP S2A-TP
Rev. Page
AD9259
Item Qty. Reference Designator F501 Device Fuse Package 1210 Value tripcurrent resettable fuse test freq MHz, tol, header jumper, 2-pin header jumper, 3-pin header male, triple straight header, male, double straight bead core SMD, test freq MHz, tol, Manufacturer Tyco/Raychem Manufacturer's Part Number NANOSMDC110F-2
FER501 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 JP301 J205, J402 J201 J204
Choke coil Ferrite bead
2020
Murata Murata
DLW5BSN191SQ2L BLM18BA100SN1B
Connector Connector Connector
2-pin 3-pin 12-pin
Samtec Samtec Samtec
TSW-102-07-G-S TSW-103-07-G-S TSW-104-08-G-T
J401
Connector
10-pin
Samtec
TSW-105-08-G-D
L501, L502, L503, L504, L505, L506, L507, L508 L309, L310, L409, L410
Ferrite bead
1210
Murata
BLM31PG500SN1L
Inductor
Murata
LQG15HNR12J02B
L301, L302, L303, L304, L305, L306, L307, L308, L401, L402, L403, L404, L405, L406, L407, L408 OSC201 P101, P103, P105, P107, P201 P202
Resistor
Components
NRC10ZOTRF
Oscillator Connector
Connector
Header
P503 R201, R205, R214, R215, R221, R239, R312, R315, R318, R411, R414, R417, R425, R429, R430 R103, R117, R129, R142, R216, R217, R218, R223, R224, R237, R420, R426, R427, R428 R102, R115, R128, R141 R104, R116, R130, R143
Connector Resistor
0.1", PCMT
Clock oscillator, 50.00 MHz, Side-mount 0.063" board thickness 1469169-1, right angle 2-pair, header assembly SC1153, power supply connector 1/16
Valpey Fisher Johnson Components Tyco
VFAC3H-L-50MHz 142-0710-851
6469169-1
Switchcraft Components
RAPC722X NRC04J103TRF
Resistor
1/16
Components
NRC04Z0TRF
Resistor Resistor
64.9 1/16 1/10
Components Components
NRC04F64R9TRF NRC06Z0TRF
Rev. Page
AD9259
Item Qty. Reference Designator R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R431, R432, R433 R108, R110, R121, R122, R134, R136, R146, R147 R161, R162, R163, R164 R202, R203, R204 R222 R213 R229 R230, R319 Device Resistor Package Value 1/16 Manufacturer Components Manufacturer's Part Number NRC04F1001TRF
Resistor
1/16 1/16 1/16 4.12 1/16 49.9 1/16 0.5% 4.99 1/16 cermet trimmer potentiometer, 18-turn adjust, 10%, 1/16 1/16 1/16 1/16 1/16 1/20
Components Components Components Components Susumu Components Components
NRC04J330TRF
Resistor Resistor Resistor Resistor Resistor Potentiometer
3-lead
NRC04F4990TRF NRC04F1003TRF NRC04F4121TRF RR0510R-49R9-D NRC04F4991TRF CT94EW103
R228 R320 R307, R308, R309, R310, R407, R408, R409, R410 R305, R306, R405, R406 R316, R317, R415, R416 R245, R247, R249, R251, R253, R255, R257, R259, R261, R263, R265 R418 R419 R501 R240, R241 R242, R243 S401 T101, T102, T103, T104, T201 U501, U503
Resistor Resistor Resistor
Components Components Components Components Components Panasonic
NRC04J474TRF NRC04J393TRF NRC04F1870TRF
Resistor Resistor Resistor
NRC04F3740TRF NRC04F2740TRF ERJ-1GE0R00C
Resistor Resistor Resistor Resistor Resistor Switch Transformer
CD542
SOT-223
4.75 1/16 1/16 1/16 1/16 1/16 Light touch, 100GE, ADT1-1WT, impedance ratio transformer ADP3339AKC-1.8, regulator
Components Components Components Components Components Panasonic Mini-Circuits
NRC04J472TRF NRC04F2610TRF NRC06F2610TRF NRC04F2430TRF NRC04F1000TRF EVQ-PLDA15 ADT1-1WT+
Analog Devices
ADP3339AKCZ-1.8
Rev. Page
AD9259
Item Qty. Reference Designator U301, U401 Device Package LFCSP, CP-32 SOT-223 SOT-223 LFCSP, CP-48-1 Value AD8332ACP, ultralow noise precision dual ADP3339AKC-5 ADP3339AKC-3.3 AD9259BCPZ-50, quad, 14-bit, MSPS serial LVDS ADR510ARTZ, precision noise shunt voltage reference AD9515BCPZ NC7WZ07 NC7WZ16 Flash prog size speed, PIC12F controller series Manufacturer Analog Devices Manufacturer's Part Number AD8332ACPZ
U504 U502 U201
Analog Devices Analog Devices Analog Devices
ADP3339AKCZ-5 ADP3339AKCZ-3.3 AD9259BCPZ-50
U203
SOT-23
Analog Devices
ADR510ARTZ
U202 U403 U404 U402
LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC
Analog Devices Fairchild Fairchild Microchip
AD9515BCPZ NC7WZ07P6X_NL NC7WZ16P6X_NL PIC12F629-I/SN
This RoHS compliant.
Rev. Page
AD9259 OUTLINE DIMENSIONS
7.00 0.60 0.60
0.30 0.23 0.18
INDICATOR
INDICATOR
VIEW
6.75
EXPOSED
(BOTTOM VIEW)
5.25 5.10 4.95
0.50 0.40 0.30
0.25 5.50
1.00 0.85 0.80
0.80 0.65 0.05 0.02 0.50
SEATING PLANE
0.20
COPLANARITY 0.08
COMPLIANT JEDEC STANDARDS MO-220-VKKD-2
Figure 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Body, Very Thin Quad (CP-48-1) Dimensions shown millimeters
ORDERING GUIDE
Model AD9259BCPZ-50 AD9259BCPZRL7-501 AD9259-50EBZ1
Temperature Range -40°C +85°C -40°C +85°C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape Reel Evaluation Board
Package Option CP-48-1 CP-48-1
RoHS Compliant Part.
Rev. Page
AD9259 NOTES
Rev. Page
AD9259 NOTES
©2006-2007 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D05965-0-7/07(B)
Rev. Page
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