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Octal, 10-Bit, MSPS/65 MSPS, Serial LVDS, AD9212
analog-to-digital converters (ADCs) integrated into package power channel MSPS 60.8 Nyquist) ENOB bits SFDR Nyquist) Excellent linearity ±0.3 (typical); ±0.4 (typical) Serial LVDS (ANSI-644, default) power, reduced signal option (similar IEEE 1596.3) Data frame clock outputs MHz, full-power analog bandwidth input voltage range supply operation Serial port control Full-chip individual-channel power-down modes Flexible orientation Built-in custom digital test pattern generation Programmable clock data alignment Programmable output resolution Standby mode
AVDD PDWN DRVDD DRGND
AD9212
VREF SENSE 0.5V REFT REFB SELECT SERIAL PORT INTERFACE
SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS
APPLICATIONS
Medical imaging nondestructive ultrasound Portable ultrasound digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment
FCO+ DATA RATE MULTIPLIER FCO- DCO+ DCO-
05968-001
RBIAS
AGND
SDIO/
SCLK/
CLK+
CLK-
Figure
GENERAL DESCRIPTION
AD9212 octal, 10-bit, MSPS/65 MSPS with on-chip sample-and-hold circuit designed cost, power, small size, ease use. Operating conversion rate MSPS, optimized outstanding dynamic performance power applications where small package size critical. requires single power supply LVPECL-/ CMOS-/LVDS-compatible sample rate clock full performance operation. external reference driver components required many applications. automatically multiplies sample rate clock appropriate LVDS serial data rate. data clock (DCO) capturing data output frame clock (FCO) signaling output byte provided. Individual channel power-down supported typically consumes less than when channels disabled.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
contains several features designed maximize flexibility minimize system cost, such programmable clock data alignment programmable digital test pattern generation. available digital test patterns include built-in deterministic pseudorandom patterns, along with custom userdefined test patterns entered serial port interface (SPI). AD9212 available RoHS compliant, 64-lead LFCSP. specified over industrial temperature range -40°C +85°C.
PRODUCT HIGHLIGHTS
Small Footprint. Eight ADCs contained small package. Power Channel MSPS. Ease Use. data clock output (DCO) operates supports double data rate (DDR) operation. User Flexibility. control offers wide range flexible features meet specific system requirements. Pin-Compatible Family. This includes AD9222 (12-bit) AD9252 (14-bit).
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006-2007 Analog Devices, Inc. rights reserved.
AD9212 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Product Highlights Revision History Specifications. Specifications. Digital Specifications Switching Specifications Timing Diagrams. Absolute Maximum Ratings. Thermal Impedance Caution. Configuration Function Descriptions. Equivalent Circuits Typical Performance Characteristics Theory Operation Analog Input Considerations. Clock Input Considerations. Serial Port Interface (SPI). Hardware Interface. Memory Reading Memory Table. Reserved Locations Default Values Logic Levels. Applications Information Design Guidelines Evaluation Board Power Supplies. Input Signals. Output Signals Default Operation Jumper Selection Settings. Alternative Analog Input Drive Configuration. Outline Dimensions Ordering Guide
REVISION HISTORY
12/07-Rev. Rev. Changes Features. Changes Figure Changes Crosstalk Parameter. Changes Logic Output (SDIO/ODM). Changes Figure Figure Changes Figure Changes Table Endnote. Changes Digital Outputs Timing Section Added Table Changes Table Table Changes RBIAS Section Deleted Figure Figure Moved Figure Changes Serial Port Interface (SPI) Section Changes Hardware Interface Section Changes Table Changes Reading Memory Table Section. Added Applications Information Design Guidelines Sections. Changes Input Signals Section Changes Output Signals Section. Changes Figure Changes Default Operation Jumper Selection Settings Section. Changes Alternative Analog Input Drive Configuration Section. Changes Figure Change Figure Changes Figure Changes Figure Changes Table Updated Outline Dimensions. Changes Ordering Guide 10/06-Revision Initial Version
Rev. Page
AD9212 SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter RESOLUTION ACCURACY Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage Mode) REFERENCE Output Voltage Error (VREF Load Regulation (VREF Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation CROSSTALK -0.5 dBFS Overrange
Temperature
AD9212-40
AD9212-65
Unit Bits
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Guaranteed ±1.5 ±0.4 ±0.3 ±0.1 ±0.15 AVDD/2 49.5
±1.2 ±0.7 ±0.4 ±0.5
Guaranteed ±1.5 ±3.2 ±0.4 ±0.3 ±0.4
±4.3 ±0.9 ±0.65
ppm/°C ppm/°C ppm/°C
AVDD/2
AN-835 Application Note, Understanding High Speed Testing Evaluation, complete definitions these tests were completed. controlled SPI. Overrange condition specific with full-scale input range.
Rev. Page
AD9212
SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter SIGNAL-TO-NOISE RATIO (SNR) 19.7 SIGNAL-TO-NOISE DISTORTION RATIO (SINAD) 19.7 EFFECTIVE NUMBER BITS (ENOB) 19.7 SPURIOUS-FREE DYNAMIC RANGE (SFDR) 19.7 WORST HARMONIC (SECOND THIRD) 19.7 WORST OTHER (EXCLUDING SECOND THIRD) 19.7 TWO-TONE INTERMODULATION DISTORTION (IMD)- AIN1 AIN2 -7.0 dBFS fIN1 MHz, fIN2 fIN1 MHz, fIN2
Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full Full Full Full 25°C Full Full Full Full Full
AD9212-40 61.2 61.2 61.2 61.0 61.2 61.0 61.0 60.8 9.87 9.87 9.87 9.84
AD9212-65 60.8 60.8 60.8 60.7 60.7 60.6 60.5 60.4 9.81 9.81 9.81 9.79
Unit Bits Bits Bits Bits
60.2
58.5
60.0
57.0
9.71
9.43
25°C 25°C
80.0 77.0
77.0 77.0
AN-835 Application Note, Understanding High Speed Testing Evaluation, complete definitions these tests were completed.
Rev. Page
AD9212
DIGITAL SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) Logic Voltage (IOH Logic Voltage (IOL DIGITAL OUTPUTS (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (LOW POWER, REDUCED SIGNAL OPTION) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default)
Temperature
AD9212-40 CMOS/LVDS/LVPECL
AD9212-65 CMOS/LVDS/LVPECL
Unit
Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full
1.79 0.05 LVDS DRVDD
1.79 0.05 LVDS 1.125 1.375 Offset binary DRVDD
Full Full
1.125
1.375 Offset binary
LVDS Full Full 1.10 1.30 Offset binary 1.10
LVDS 1.30 Offset binary
AN-835 Application Note, Understanding High Speed Testing Evaluation, complete definitions these tests were completed. This specified LVDS LVPECL only. This specified SDIO pins sharing same connection.
Rev. Page
AD9212
SWITCHING SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
AD9212-40 Parameter CLOCK Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width (tEL) OUTPUT PARAMETERS2, Propagation Delay (tPD) Rise Time (tR) (20% 80%) Fall Time (tF) (20% 80%) Propagation Delay (tFCO) Propagation Delay (tCPD) Data Delay (tDATA)4 Delay (tFRAME)4 Data-to-Data Skew (tDATA-MAX tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time Temp Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Full 12.5 12.5 tFCO (tSAMPLE/20) (tSAMPLE/20) (tSAMPLE/20) tFCO (tSAMPLE/20) (tSAMPLE/20) (tSAMPLE/20) AD9212-65 Unit MSPS MSPS cycles cycles
(tSAMPLE/20) (tSAMPLE/20)
(tSAMPLE/20) (tSAMPLE/20) ±200
(tSAMPLE/20) (tSAMPLE/20)
(tSAMPLE/20) (tSAMPLE/20) ±200
25°C 25°C 25°C
AN-835 Application Note, Understanding High Speed Testing Evaluation, complete definitions these tests were completed. adjusted interface. Measurements were made using part soldered FR-4 material. tSAMPLE/20 based number bits divided because delays based half duty cycles.
Rev. Page
AD9212
TIMING DIAGRAMS
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tDATA
05968-002
Figure 10-Bit Data Serial Stream (Default), First
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tDATA
05968-003
Figure 3.12-Bit Data Serial Stream, First
Rev. Page
AD9212
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tDATA
05968-004
Figure 10-Bit Data Serial Stream, First
Rev. Page
AD9212 ABSOLUTE MAXIMUM RATINGS
Table
Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs DCO+, DCO-, FCO+, FCO-) CLK+, CLK- SDIO/ODM PDWN, SCLK/DTP, REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, sec) With Respect AGND DRGND DRGND DRVDD DRGND Rating -0.3 +2.0 -0.3 +2.0 -0.3 +0.3 -2.0 +2.0 -0.3 +2.0
THERMAL IMPEDANCE
Table
Flow Velocity (m/s)
17.7 15.5 13.9
Unit °C/W °C/W °C/W
4-layer with solid ground plane (simulated). Exposed soldered PCB.
CAUTION
AGND AGND AGND AGND AGND AGND -0.3 +3.9 -0.3 +2.0 -0.3 +2.0 -0.3 +3.9 -0.3 +2.0 -0.3 +2.0 -40°C +85°C -65°C +150°C 150°C 300°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Rev. Page
AD9212 CONFIGURATION FUNCTION DESCRIPTIONS
INDICATOR
AVDD AVDD REFT REFB VREF SENSE RBIAS AVDD
AVDD AVDD AVDD AVDD CLK- CLK+ AVDD AVDD DRGND DRVDD
EXPOSED PADDLE, (BOTTOM PACKAGE)
AD9212
VIEW (Not Scale)
AVDD AVDD AVDD PDWN SDIO/ODM SCLK/DTP AVDD DRGND DRVDD
Figure 64-Lead LFCSP Configuration, View
Table Function Descriptions
Mnemonic AGND AVDD Description Analog Ground (Exposed Paddle) Analog Supply
DRGND DRVDD CLK- CLK+ DCO- DCO+ FCO- FCO+
Digital Output Driver Ground Digital Output Driver Supply Analog Input True Analog Input Complement Analog Input Complement Analog Input True Input Clock Complement Input Clock True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Data Clock Digital Output Complement Data Clock Digital Output True Frame Clock Digital Output Complement Frame Clock Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True
Rev. Page
DCO- DCO+ FCO- FCO+
05968-005
AD9212
Mnemonic SCLK/DTP SDIO/ODM PDWN RBIAS SENSE VREF REFB REFT Description Digital Output Complement Digital Output True Serial Clock/Digital Test Pattern Serial Data Input-Output/Output Driver Mode Chip Select Power-Down Analog Input True Analog Input Complement Analog Input Complement Analog Input True Analog Input True Analog Input Complement Analog Input Complement Analog Input True External Resistor Internal Core Bias Current Reference Mode Selection Voltage Reference Input/Output Negative Differential Reference Positive Differential Reference Analog Input True Analog Input Complement Analog Input Complement Analog Input True
Rev. Page
AD9212 EQUIVALENT CIRCUITS
DRVDD
05968-006
DRGND
Figure Equivalent Analog Input Circuit
Figure Equivalent Digital Output Circuit
CLK+
1.25V CLK-
SCLK/DTP PDWN
05968-007
05968-009
Figure Equivalent Clock Input Circuit
Figure Equivalent SCLK/DTP PDWN Input Circuit
RBIAS
SDIO/ODM
05968-008
Figure Equivalent SDIO/ODM Input Circuit
Figure Equivalent RBIAS Circuit
Rev. Page
05968-011
05968-010
AD9212
AVDD
VREF
05968-012
Figure Equivalent Input Circuit
Figure Equivalent VREF Circuit
SENSE
Figure Equivalent SENSE Circuit
05968-013
Rev. Page
05968-014
AD9212 TYPICAL PERFORMANCE CHARACTERISTICS
-0.5dBFS 60.08dB ENOB 9.61 SFDR 71.68dBc
-0.5dBFS 60.41dB ENOB SFDR 76.11dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
-100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with MHz, AD9212-40
Figure Single-Tone with MHz, AD9212-65
-0.5dBFS 61.17dB ENOB 9.85 SFDR 81.27dBc
-0.5dBFS 60.25dB ENOB 9.66 SFDR 72.45dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
-100
05968-038
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with 19.7 MHz, AD9212-40
Figure Single-Tone with MHz, AD9212-65
-0.5dBFS 60.48dB ENOB 9.72 SFDR 76.84dBc
-0.5dBFS 60.08dB ENOB 9.61 SFDR 71.68dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
-100
05968-039
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with MHz, AD9212-65
Figure Single-Tone with MHz, AD9212-65
Rev. Page
05968-042
-120
-120
05968-041
-120
-120
05968-040
05968-037
-120
-120
AD9212
SNR/SFDR (dB) SNR/SFDR (dB)
SFDR
SFDR
05968-043
ENCODE RATE (MSPS)
ENCODE RATE (MSPS)
Figure SNR/SFDR fSAMPLE, 10.3 MHz, AD9212-40
Figure SNR/SFDR fSAMPLE, MHz, AD9212-65
SFDR
SNR/SFDR (dB)
SNR/SFDR (dB)
70dB REFERENCE SFDR
05968-044
ENCODE RATE (MSPS)
ANALOG INPUT LEVEL (dBFS)
Figure SNR/SFDR fSAMPLE, 19.7 MHz, AD9212-40
Figure SNR/SFDR Analog Input Level, 10.3 MHz, AD9212-40
SFDR
SNR/SFDR (dB)
SNR/SFDR (dB)
70dB REFERENCE SFDR
05968-045
ENCODE RATE (MSPS)
ANALOG INPUT LEVEL (dBFS)
Figure SNR/SFDR fSAMPLE, 10.3 MHz, AD9212-65
Figure SNR/SFDR Analog Input Level, MHz, AD9212-40
Rev. Page
05968-048
05968-047
05968-046
AD9212
AMPLITUDE (dBFS)
AIN1 AIN2 -7dBFS SFDR 76.7dB IMD2 83.38dBc IMD3 77.21dBc
SNR/SFDR (dB)
SFDR
05968-049
70dB REFERENCE
-100
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure SNR/SFDR Analog Input Level, 10.3 MHz, AD9212-65
Figure Two-Tone with fIN1 fIN2 MHz, AD9212-40
AMPLITUDE (dBFS)
AIN1 AIN2 -7dBFS SFDR 77.4dB IMD2 77.92dBc IMD3 76.9dBc
SNR/SFDR (dB)
SFDR
05968-050
70dB REFERENCE
-100
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure SNR/SFDR Analog Input Level, MHz, AD9212-65
Figure Two-Tone with fIN1 fIN2 MHz, AD9212-65
AIN1 AIN2 -7dBFS SFDR 84.8dB IMD2 83.66dBc IMD3 84.6dBc
AIN1 AIN2 -7dBFS SFDR 72.5dB IMD2 77.14dBc IMD3 72.55dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
-100
05968-051
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Two-Tone with fIN1 fIN2 MHz, AD9212-40
Rev. Page
Figure Two-Tone with fIN1 fIN2 MHz, AD9212-
05968-054
-120
-120
05968-053
-120
05968-052
-120
AD9212
SFDR
SNR/SFDR (dB)
(LSB)
-0.1 -0.2 -0.3 -0.4 CODE 1000
05968-058
05968-061
ANALOG INPUT FREQUENCY (MHz)
1000
Figure SNR/SFDR fIN, AD9212-65
05968-055
-0.5
Figure INL, MHz, AD9212-65
SINAD/SFDR (dB)
SFDR
(LSB)
-0.1 -0.2 -0.3
SINAD
05968-056
-0.4 CODE 1000
05968-060
TEMPERATURE (°C)
-0.5
Figure SINAD/SFDR Temperature, 10.3 MHz, AD9212-40
Figure DNL, MHz, AD9212-65
SINAD/SFDR (dB)
SFDR
05968-057
SINAD
CMRR (dB)
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure SINAD/SFDR Temperature, 10.3 MHz, AD9212-65
Figure CMRR Frequency, AD9212-65
Rev. Page
AD9212
0.096
-3dB BANDWIDTH 325MHz
NUMBER HITS (Millions)
AMPLITUDE (dBFS)
05968-062
CODE
FREQUENCY (MHz)
Figure Input-Referred Noise Histogram, AD9212-65
Figure Full Power Bandwidth Frequency, AD9212-65
51.13dB NOTCH 18.0MHz NOTCH WIDTH 3.0MHz
AMPLITUDE (dBFS)
-100
FREQUENCY (MHz)
Figure Noise Power Ratio (NPR), AD9212-
05968-063
-120
Rev. Page
05968-064
AD9212 THEORY OPERATION
AD9212 architecture consists pipelined divided into three sections: 4-bit first stage followed eight 1.5-bit stages 3-bit flash. Each stage provides sufficient overlap correct flash errors preceding stage. quantized outputs from each stage combined into final 10-bit result digital correction logic. pipelined architecture permits first stage operate with input sample while remaining stages operate with preceding samples. Sampling occurs rising edge clock. Each stage pipeline, excluding last, consists resolution flash connected switched-capacitor interstage residue amplifier (for example, multiplying digital-to-analog converter (MDAC)). residue amplifier magnifies difference between reconstructed output flash input next stage pipeline. redundancy used each stage facilitate digital correction flash errors. last stage simply consists flash ADC. output staging block aligns data, corrects errors, passes data output buffers. data then serialized aligned frame data clocks. clock signal alternately switches input circuit between sample mode hold mode (see Figure 42). When input circuit switched into sample mode, signal source must capable charging sample capacitors settling within one-half clock cycle. small resistor series with each input help reduce peak transient current injected from output stage driving source. addition, low-Q inductors ferrite beads placed each input reduce high differential capacitance analog inputs therefore achieve maximum bandwidth ADC. Such lowQ inductors ferrite beads required when driving converter front high frequencies. Either shunt capacitor single-ended capacitors placed inputs provide matching passive network. This ultimately creates low-pass filter input limit unwanted broadband noise. AN-742 Application Note, Frequency Domain Response Switched-Capacitor ADCs; AN-827 Application Note, Resonant Approach Interfacing Amplifiers Switched-Capacitor ADCs; Analog Dialogue article "Transformer-Coupled Front-End Wideband Converters" (Volume April 2005) more information. general, precise values depend application. analog inputs AD9212 internally dc-biased. Therefore, ac-coupled applications, user must provide this bias externally. Setting device that AVDD/2 recommended optimum performance, device function over wider range with reasonable performance, shown Figure Figure
ANALOG INPUT CONSIDERATIONS
analog input AD9212 differential switchedcapacitor circuit designed processing differential input signals. This circuit support wide common-mode range while maintaining excellent performance. input common-mode voltage midsupply minimizes signal-dependent errors provides optimum performance.
CPAR
CSAMPLE
CSAMPLE
CPAR
05968-017
Figure Switched-Capacitor Input Circuit
Rev. Page
AD9212
SFDR (dBc)
SNR/SFDR (dB)
SNR/SFDR (dB)
SFDR
(dB)
05968-065
ANALOG INPUT COMMON-MODE VOLTAGE
ANALOG INPUT COMMON-MODE VOLTAGE
Figure SNR/SFDR Common-Mode Voltage, MHz, AD9212-40
Figure SNR/SFDR Common-Mode Voltage, MHz, AD9212-65
SNR/SFDR (dB) SFDR (dBc) (dB) SNR/SFDR (dB)
SFDR
05968-066
ANALOG INPUT COMMON-MODE VOLTAGE
ANALOG INPUT COMMON-MODE VOLTAGE
Figure SNR/SFDR Common-Mode Voltage, 19.7 MHz, AD9212-40
Figure SNR/SFDR Common-Mode Voltage, MHz, AD9212-65
Rev. Page
05968-068
05968-067
AD9212
best dynamic performance, source impedances driving should matched such that common-mode settling errors symmetrical. These errors reduced common-mode rejection ADC. internal reference buffer creates positive negative reference voltages, REFT REFB, respectively, that define span core. output common mode reference buffer midsupply, REFT REFB voltages span defined REFT (AVDD VREF) REFB (AVDD VREF) Span (REFT REFB) VREF seen from these equations that REFT REFB voltages symmetrical about midsupply voltage and, definition, input span twice value VREF voltage. Maximum performance achieved setting largest span differential configuration. case AD9212, largest input span available p-p.
ADT1-1WT RATIO
49.9 AVDD
CDIFF1
AD9212
AGND
DIFF
OPTIONAL.
Figure Differential Transformer-Coupled Configuration Baseband Applications
16nH ADT1-1WT 0.1F RATIO 16nH 16nH AVDD
05968-019
2.2pF
VIN+
AD9212
VIN-
0.1F
Differential Input Configurations
There several ways drive AD9212 either actively passively; however, optimum performance achieved driving analog input differentially. example, using AD8334 differential driver drive AD9212 provides excellent performance flexible interface (see Figure baseband applications. This configuration commonly used medical ultrasound systems. applications where parameter, differential transformer coupling recommended input configuration (see Figure Figure 48), because noise performance most amplifiers adequate achieve true performance AD9212. Regardless configuration, value shunt capacitor, dependent input frequency need reduced removed.
Figure Differential Transformer-Coupled Configuration Applications
Single-Ended Input Configuration
single-ended input provide adequate performance cost-sensitive applications. this configuration, SFDR distortion performance degrade large input commonmode swing. application requires single-ended input configuration, ensure that source impedances each input well matched order achieve best possible performance. full-scale input still applied ADC's while terminated. Figure details typical single-ended input configuration.
AVDD 49.9 0.1µF AVDD 0.1µF
CDIFF1
AD9212
05968-020
DIFF OPTIONAL.
Figure Single-Ended Input Configuration
0.1F
0.1F 120nH 22pF
0.1F 1.0k 1.0k
AD8334
AD9212
05968-021
0.1F
VREF
0.1F 0.1F
18nF
0.1F
Figure Differential Input Configuration Using AD8334
Rev. Page
05968-018
0.1F
AD9212
CLOCK INPUT CONSIDERATIONS
optimum performance, AD9212 sample clock inputs (CLK+ CLK-) should clocked with differential signal. This signal typically ac-coupled into CLK+ CLK- pins transformer capacitors. These pins biased internally require additional biasing. Figure shows preferred method clocking AD9212. jitter clock source converted from single-ended differential using transformer. back-to-back Schottky diodes across secondary transformer limit clock excursions into AD9212 approximately differential. This helps prevent large voltage swings clock from feeding through other portions AD9212, preserves fast rise fall times signal, which critical jitter performance.
Mini-Circuits® ADT1-1WT, 1:1Z 0.1µF XFMR 0.1µF 0.1µF SCHOTTKY DIODES: HSM2812
some applications, acceptable drive sample clock inputs with single-ended CMOS signal. such applications, CLK+ should driven directly from CMOS gate, CLK- should bypassed ground with capacitor parallel with resistor (see Figure 54). Although CLK+ input circuit supply AVDD (1.8 this input designed withstand input voltages making selection drive logic voltage very flexible.
0.1µF CLK+ CMOS DRIVER 0.1µF 0.1µF
RESISTOR OPTIONAL.
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
OPTIONAL 0.1µF
CLK+
AD9212
CLK-
05968-025
0.1µF CLK+
Figure Single-Ended CMOS Sample Clock
CLK+
AD9212
CLK+
05968-022
CLK-
0.1µF
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
OPTIONAL 0.1µF
CMOS DRIVER
CLK+
Figure Transformer-Coupled Differential Clock
Another option ac-couple differential PECL signal sample clock input pins shown Figure AD9510/ family clock drivers offers excellent jitter performance.
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
0.1µF CLK+ PECL DRIVER OPTIONAL.
05968-023
0.1µF
0.1µF
AD9212
05968-026
CLK-
RESISTOR OPTIONAL.
Figure Single-Ended CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs both clock edges generate variety internal timing signals. result, these ADCs sensitive clock duty cycle. Commonly, tolerance required clock duty cycle maintain dynamic performance characteristics. AD9212 contains duty cycle stabilizer (DCS) that retimes nonsampling edge, providing internal clock signal with nominal duty cycle. This allows wide range clock input duty cycles without affecting performance AD9212. When noise distortion performance nearly flat wide range duty cycles. However, some applications require function off. keep mind that dynamic range performance affected when operated this mode. Memory section more details using this feature. duty cycle stabilizer uses delay-locked loop (DLL) create nonsampling edge. result, changes sampling frequency require approximately eight clock cycles allow acquire lock rate.
0.1µF CLK+ 0.1µF
0.1µF CLK-
AD9212
CLK-
RESISTORS
Figure Differential PECL Sample Clock
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
0.1µF LVDS DRIVER OPTIONAL.
05968-024
0.1µF CLK+
CLK+ 0.1µF
0.1µF CLK-
AD9212
CLK-
RESISTORS
Figure Differential LVDS Sample Clock
Rev. Page
AD9212
Clock Jitter Considerations
High speed, high resolution ADCs sensitive quality clock input. degradation given input frequency (fA) only aperture jitter (tJ) calculated Degradation 10(1/2 this equation, aperture jitter represents root mean square jitter sources, including clock input, analog input signal, aperture jitter specifications. undersampling applications particularly sensitive jitter (see Figure 56).
CURRENT
Power Dissipation Power-Down Mode
shown Figure Figure power dissipated AD9212 proportional sample rate. digital power dissipation does vary much because determined primarily DRVDD supply bias current LVDS output drivers.
0.30 0.60 0.58 0.25 AVDD CURRENT 0.20 0.56 0.54 0.52 0.15 TOTAL POWER 0.10 0.50 0.48 0.46 DRVDD CURRENT 0.44 0.42 ENCODE (MHz)
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clock input should treated analog signal cases where aperture jitter affect dynamic range AD9212. Power supplies clock drivers should separated from output driver supplies avoid modulating clock signal with digital noise. jitter crystal-controlled oscillators make best clock sources. clock generated from another type source gating, dividing, other methods), should retimed original clock last step. Refer AN-501 Application Note AN-756 Application Note more in-depth information about jitter performance relates ADCs.
CLOCK JITTER REQUIREMENT
0.05
0.40
Figure Supply Current fSAMPLE 10.3 MHz, AD9212-40
0.40 AVDD CURRENT 0.35 0.30 0.85 0.80 0.90
CURRENT
(dB)
BITS BITS BITS BITS BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps ANALOG INPUT FREQUENCY (MHz) 1000
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TOTAL POWER 0.20 0.15 0.10 0.05 DRVDD CURRENT 0.70 0.65 0.60 0.55 0.50
POWER
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0.25
0.75
ENCODE (MHz)
Figure Supply Current fSAMPLE 10.3 MHz, AD9212-65
Figure Ideal Input Frequency Jitter
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POWER
AD9212
asserting PDWN high, AD9212 placed into power-down mode. this state, typically dissipates During power-down, LVDS output drivers placed into high impedance state. AD9212 returns normal operating mode when PDWN pulled low. This both tolerant. power-down mode, power dissipation achieved shutting down reference, reference buffer, PLL, biasing networks. decoupling capacitors REFT REFB discharged when entering power-down mode must recharged when returning normal operation. result, wake-up time related time spent power-down mode: shorter cycles result proportionally shorter wake-up times. With recommended decoupling capacitors REFT REFB, approximately required fully discharge reference buffer decoupling capacitors, approximately required restore full operation. There several other power-down options available when using SPI. user individually power down each channel entire device into standby mode. latter option allows user keep internal powered when fast wake-up times (~600 required. Memory section more details using these features.
500mV/DIV 500mV/DIV 500mV/DIV DATA 5ns/DIV
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recommended that trace length longer than inches that differential output traces kept close together equal lengths. example data stream when AD9212 used with traces proper length position shown Figure
Figure LVDS Output Timing Example ANSI-644 Mode (Default), AD9212-65
Digital Outputs Timing
AD9212 differential outputs conform ANSI-644 LVDS standard default upon power-up. This changed power, reduced signal option (similar IEEE 1596.3 standard) SDIO/ODM SPI. This LVDS standard further reduce overall power dissipation device approximately SDIO/ODM section Table Memory section more information. LVDS driver current derived chip sets output current each output equal nominal differential termination resistor placed LVDS receiver inputs results nominal swing receiver. AD9212 LVDS outputs facilitate interfacing with LVDS receivers custom ASICs FPGAs superior switching performance noisy environments. Single point-to-point topologies recommended with termination resistor placed close receiver possible. there far-end receiver termination there poor differential trace routing, timing errors result. avoid such timing errors,
example LVDS output using ANSI-644 standard (default) data time interval error (TIE) jitter histogram with trace lengths less than inches standard FR-4 material shown Figure Figure shows example trace length exceeding inches standard FR-4 material. Notice that jitter histogram reflects decrease data opening edge deviates from ideal position. user's responsibility determine waveforms meet timing budget design when trace lengths exceed inches. Additional options allow user further increase internal termination (increasing current) eight outputs order drive longer trace lengths (see Figure 62). Even though this produces sharper rise fall times data edges less prone errors, power dissipation DRVDD supply increases when this option used. cases that require increased driver strength DCO± FCO± outputs because load mismatch, Register 0x15 allows user increase drive strength this, first appropriate Register 0x05. Note that this feature cannot used with Register 0x15. take precedence over this feature. Memory section more details.
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AD9212
-100 -200 -300 -400 -500 -1.5ns -1.0ns -0.5ns 0.5ns 1.0ns 1.5ns EYE: BITS ULS: 12071/12071
EYE: BITS
ULS: 12072/12072
DIAGRAM VOLTAGE (mV)
DIAGRAM VOLTAGE (mV)
-100 -200 -300 -400 -1.5ns -1.0ns -0.5ns 0.5ns 1.0ns 1.5ns
JITTER HISTOGRAM (Hits)
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JITTER HISTOGRAM (Hits)
-150ps
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-150ps
-100ps
-50ps
50ps
100ps
150ps
-100ps
-50ps
50ps
100ps
150ps
Figure Data LVDS Outputs ANSI-644 Mode with Trace Lengths Less Than Inches Standard FR-4
EYE: BITS ULS: 12067/12067
Figure Data LVDS Outputs ANSI-644 Mode with Termination Trace Lengths Greater Than Inches Standard FR-4
DIAGRAM VOLTAGE (mV)
-100 -200 -300 -400 -500 -1.5ns -1.0ns -0.5ns 0.5ns 1.0ns 1.5ns
format output data offset binary default. example output coding format found Table change output data format twos complement, Memory section. Table Digital Output Coding
Code 1023 (VIN (VIN Input Span +1.00 0.00 -0.001953 -1.00 Digital Output Offset Binary 1111 1111 0000 0000 1111 1111 0000 0000
JITTER HISTOGRAM (Hits)
-200ps -100ps 100ps 200ps
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Data from each serialized provided separate channel. data rate each serial stream equal bits times sample clock rate, with maximum Mbps bits MSPS Mbps). lowest typical conversion rate MSPS. However, lower sample rates required specific application, allow encode rates MSPS. Memory section information about enabling this feature.
Figure Data LVDS Outputs ANSI-644 Mode with Trace Lengths Greater Than Inches Standard FR-4
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AD9212
output clocks provided assist capturing data from AD9212. used clock output data equal five times sample clock (CLK) rate. Data clocked AD9212 must captured rising falling edges that supports double data rate (DDR) capturing. used signal start output byte equal sample clock rate. timing diagram shown Figure more information.
Table Flexible Output Test Modes
Output Test Mode Sequence 0000 0001 Subject Data Format Select
Pattern Name (default) Midscale short
0010
+Full-scale short
0011
-Full-scale short
0100
Checkerboard
0101 0110 0111
sequence long sequence short1 One-/zero-word toggle
1000 1001
User input 1-/0-bit toggle
1010
sync
1011
high
1100
Mixed frequency
Digital Output Word 1000 0000 (8-bit) 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 1010 1010 1010 (14-bit) 1111 1111 (8-bit) 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 1111 1111 1111 (14-bit) Register 0x19 Register 0x1A 1010 1010 (8-bit) 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 1000 0110 0111 (14-bit)
Digital Output Word Same
Same
Same
0101 0101 (8-bit) 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 0101 0101 0101 (14-bit) 0000 0000 (8-bit) 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) Register 0x1B Register 0x1C
test mode options except sequence short sequence long support 14-bit word lengths order verify data capture receiver.
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AD9212
When used, phase adjusted increments relative data edge. This enables user refine system timing margins required. default DCO+ DCO- timing, shown Figure relative output data edge. 12-, 14-bit serial stream also initiated from SPI. This allows user implement different serial stream test device's compatibility with lower higher resolution systems. When changing resolution 12-bit serial stream, data stream lengthened. Figure 12-bit example. However, when using 12-bit option, data stream stuffs 10-bit serial data. When used, data outputs inverted from their nominal state. This confused with inverting serial stream LSB-first mode. default mode, shown Figure first data output serial stream. However, this inverted that first data output serial stream (see Figure There digital output test pattern options available that initiated through SPI. This feature useful when validating receiver capture timing. Refer Table output sequencing options available. Some test patterns have serial sequential words alternated various ways, depending test pattern chosen. Note that some patterns adhere data format select option. addition, customer user-defined test patterns assigned 0x19, 0x1A, 0x1B, 0x1C register addresses. test mode options except sequence short sequence long support 14-bit word lengths order verify data capture receiver. sequence short pattern produces pseudorandom sequence that repeats itself every bits. description sequence generated found Section ITU-T 0.150 (05/96) standard. only difference that starting value must specific value instead (see Table initial values). sequence long pattern produces pseudorandom sequence that repeats itself every 8,388,607 bits. description sequence generated found Section ITU-T 0.150 (05/96) standard. only differences that starting value must specific value instead (see Table initial values) AD9212 inverts stream with relation standard. Table Sequence
Sequence Sequence Short Sequence Long Initial Value 0x0df 0x29b80a First Three Output Samples (MSB First) 0xdf9, 0x353, 0x301 0x591, 0xfd7, 0xa3
SDIO/ODM
SDIO/ODM applications that require mode operation. This enable power, reduced signal option (similar IEEE 1596.3 reduced range link output standard) tied AVDD during device power-up. This option should only used when digital output trace lengths less than inches from LVDS receiver. When this option used, FCO, DCO, outputs function normally, LVDS signal swing channels reduced from p-p, allowing user further reduce power DRVDD supply. applications where this used, should tied low. this case, device left open, internal pull-down resistor pulls this low. This only tolerant. applications require this driven from logic level, insert resistor series with this limit current. Table Output Driver Mode Settings
Selected Normal Operation Voltage AGND pulldown resistor) AVDD Resulting Output Standard ANSI-644 (default) power, reduced signal option Resulting ANSI-644 (default) power, reduced signal option
SCLK/DTP
SCLK/DTP applications that require mode operation. This enable single digital test pattern held high during device power-up. When SCLK/DTP tied AVDD, channel outputs shift following pattern: 0000 0000. function normally while channels shift repeatable test pattern. This pattern allows user perform timing alignment adjustments among FCO, DCO, output data. normal operation, this should tied AGND through resistor. This both tolerant. Table Digital Test Pattern Settings
Selected Normal Operation Voltage AGND pulldown resistor) AVDD Resulting Normal operation 0000 0000 Resulting Normal operation
Normal operation
Additional custom test patterns also observed when commanded from port. Consult Memory section information about options available.
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AD9212
should tied AVDD applications that require mode operation. tying high, SCLK SDIO information ignored. This both tolerant.
REFT CORE 0.1µF 0.1µF REFB VREF 0.1µF SELECT LOGIC SENSE 0.5V 0.1µF
2.2µF
RBIAS
internal core bias current ADC, place resistor that nominally equal 10.0 between RBIAS ground. resistor current derived chip sets AVDD current nominal MSPS. Therefore, imperative that least tolerance this resistor used achieve consistent performance.
Voltage Reference
stable, accurate voltage reference built into AD9212. This gained internally factor setting VREF which results full-scale differential input span p-p. VREF internally default; however, VREF driven externally with reference improve accuracy. When applying decoupling capacitors VREF, REFT, REFB pins, ceramic low-ESR capacitors. These capacitors should close pins same layer AD9212. recommended capacitor values configurations AD9212 reference shown Figure Table Reference Settings
Selected Mode External Reference Internal, SENSE Voltage AVDD AGND Resulting VREF Resulting Differential Span p-p) external reference
Figure Internal Reference Configuration
REFT CORE EXTERNAL REFERENCE VREF 1µF1 0.1µF1 AVDD SENSE SELECT LOGIC 0.5V 0.1µF 0.1µF REFB 0.1µF
2.2µF
1OPTIONAL.
Figure External Reference Operation
comparator within AD9212 detects potential SENSE configures reference. SENSE grounded, reference amplifier switch connected internal resistor divider (see Figure 63), setting VREF REFT REFB pins establish their input span core from reference configuration. analog input fullscale range equals twice voltage reference either internal external reference configuration. reference AD9212 used drive multiple converters improve gain matching, loading reference other converters must considered. Figure depicts internal reference voltage affected loading.
VREF ERROR
Internal Reference Operation
CURRENT LOAD (mA)
Figure VREF Accuracy Load
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AD9212
External Reference Operation
external reference necessary enhance gain accuracy improve thermal drift characteristics. Figure shows typical drift characteristics internal reference mode. When SENSE tied AVDD, internal reference disabled, allowing external reference. external reference loaded with equivalent load. internal reference buffer generates positive negative full-scale references, REFT REFB, core. Therefore, external reference must limited nominal voltage
0.02 -0.02 -0.04
VREF ERROR
-0.06 -0.08 -0.10 -0.12 -0.14 -0.16
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-0.18
TEMPERATURE (°C)
Figure Typical VREF Drift
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AD9212 SERIAL PORT INTERFACE (SPI)
AD9212 serial port interface allows user configure converter specific functions operations through structured register space provided inside ADC. This provide user with additional flexibility customization, depending application. Addresses accessed serial port written read from port. Memory organized into bytes that further divided into fields, documented Memory section. Detailed operational information found AN-877 Application Note, Interfacing High Speed ADCs SPI. Three pins define SPI: SCLK, SDIO, pins (see Table 14). SCLK used synchronize read write data presented ADC. SDIO dual-purpose that allows data sent read from internal memory registers. active control that enables disables read write cycles. Table Serial Port Pins
SCLK SDIO Function Serial Clock. serial shift clock input, which used synchronize serial interface reads writes. Serial Data Input/Output. dual-purpose that typically serves input output, depending instruction sent relative position timing frame. Chip Select (Active Low). This control gates read write cycles.
Regardless mode, taken high middle byte transfer, state machine reset device waits instruction. addition operation modes, port configuration influences AD9212 operates. applications that require control port, line tied held high. This places remainder pins into their secondary modes, defined SDIO/ODM SCLK/DTP sections. also tied enable 2-wire mode. When tied low, SCLK SDIO only pins required communication. Although device synchronized during power-up, user should ensure that serial port remains synchronized with line when using this mode. When operating 2-wire mode, recommended that 3byte transfer used exclusively. Without active line, streaming mode entered exited. addition word length, instruction phase determines serial frame read write operation, allowing serial port used both program chip read contents on-chip memory. instruction readback operation, performing readback causes SDIO change from input output appropriate point serial frame. Data sent MSB- LSB-first mode. MSB-first mode default power-up changed adjusting configuration register. more information about this other features, AN-877 Application Note, Interfacing High Speed ADCs SPI.
falling edge conjunction with rising edge SCLK determines start framing sequence. During instruction phase, 16-bit instruction transmitted, followed more data bytes, which determined Field Field example serial timing definitions found Figure Table During normal operation, used signal device that commands received processed. When brought low, device processes SCLK SDIO execute instructions. Normally, remains until communication cycle complete. However, connected slow device, brought high between bytes, allowing older microcontrollers enough time transfer data into shift registers. stalled when transferring one, two, three bytes data. When device enters streaming mode continues process data, either reading writing, until taken high communication cycle. This allows complete memory transfers without requiring additional instructions.
HARDWARE INTERFACE
pins described Table constitute physical interface between user's programming device serial port AD9212. SCLK pins function inputs when using SPI. SDIO bidirectional, functioning input during write phases output during readback. multiple SDIO pins share common connection, care should taken ensure that proper levels met. Assuming same load each AD9212, Figure shows number SDIO pins that connected together resulting level. This interface flexible enough controlled either serial PROMs mirocontrollers, providing user with alternative method, other than full controller, program (see AN-812 Application Note). user chooses SPI, these dual-function pins serve their secondary functions when strapped AVDD during device power-up. Theory Operation section details which pin-strappable functions supported pins.
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AD9212
1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715
NUMBER SDIO PINS CONNECTED TOGETHER
Figure SDIO Loading
tCLK
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SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
DON'T CARE
Figure Serial Timing Details
Table Serial Timing Definitions
Parameter tCLK tEN_SDIO tDIS_SDIO Timing (Minimum, Description Setup time between data rising edge SCLK Hold time between data rising edge SCLK Period clock Setup time between SCLK Hold time between SCLK Minimum period that SCLK should logic high state Minimum period that SCLK should logic state Minimum time SDIO switch from input output relative SCLK falling edge (not shown Figure Minimum time SDIO switch from output input relative SCLK rising edge (not shown Figure
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AD9212 MEMORY
READING MEMORY TABLE
Each memory register table (Table eight address locations. memory divided into three sections: chip configuration register (Address 0x00 Address 0x02), device index transfer register (Address 0x04, Address 0x05, Address 0xFF), functions register (Address 0x08 Address 0x22). leftmost column memory indicates register address number; default value shown second rightmost column. column start default hexadecimal value given. example, Address 0x09, clock register, default value 0x01, meaning 0000 0001 binary. This setting default duty cycle stabilizer condition. writing this address followed writing 0x01 Register 0xFF (transfer bit), duty cycle stabilizer turns off. important follow each writing sequence with transfer update registers. registers, except Register 0x00, Register 0x04, Register 0x05, Register 0xFF, buffered with master-slave latch require writing transfer bit. more information this other functions, consult AN-877 Application Note, Interfacing High Speed ADCs SPI.
RESERVED LOCATIONS
Undefined memory locations should written except when writing default values suggested this data sheet. Addresses that have values marked should considered reserved have written their registers during power-up.
DEFAULT VALUES
When AD9212 comes reset, critical registers preloaded with default values. These values indicated Table where refers undefined feature.
LOGIC LEVELS
explanation various registers follows: "bit set" synonymous with "bit Logic "writing Logic bit." Similarly, "clear bit" synonymous with "bit Logic "writing Logic bit."
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AD9212
Table Memory Register
Addr. (MSB) (Hex) Parameter Name Chip Configuration Registers chip_port_config first (default) Soft reset (default) Soft reset (default) first (default) (LSB) Default Value (Hex) 0x18 Notes/ Comments nibbles should mirrored that LSB- MSB-first mode correctly regardless shift mode. Default unique chip different each device. This readonly register. Child used differentiate graded devices.
chip_id
10-bit Chip Bits [7:0] (AD9212 0x08), (default)
Read only
chip_grade
Child [6:4] (identify device variants Chip MSPS MSPS
Read only
Device Index Transfer Registers device_index_2
device_index_1
device_update
Clock Channel (default)
Clock Channel (default)
Data Channel (default) Data Channel (default)
Data Channel (default) Data Channel (default)
Data Channel (default) Data Channel (default)
Data Channel (default) Data Channel (default) transfer (default)
0x0F
Bits determine which on-chip device receives next write command. Bits determine which on-chip device receives next write command. Synchronously transfers data from master shift register slave. Determines various generic modes chip operation. Turns internal duty cycle stabilizer off.
0x0F
0x00
Functions Registers modes
clock
Internal power-down mode chip (default) full power-down standby reset Duty cycle stabilizer (default)
0x00
0x01
test_io
User test mode (default) single alternate single once alternate once
Reset long (default)
Reset short (default)
Output test mode-see Table Digital Outputs Timing section 0000 (default) 0001 midscale short 0010 short 0011 short 0100 checkerboard output 0101 sequence 0110 sequence 0111 one-/zero-word toggle 1000 user input 1001 1-/0-bit toggle 1010 sync 1011 high 1100 mixed frequency (format determined output_mode)
0x00
When this register set, test data placed output pins place normal data.
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AD9212
Addr. (Hex) Parameter Name output_mode (MSB) LVDS ANSI-644 (default) LVDS power, (IEEE 1596.3 similar) Output invert (default) (LSB) offset binary (default) twos complement Default Value (Hex) 0x00 Notes/ Comments Configures outputs format data.
output_adjust
Output driver termination none (default)
drive strength (default)
0x00
output_phase
user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb serial_control
first (default)
0011 output clock phase adjust (0000 through 1010) 0000 relative data edge 0001 relative data edge 0010 120° relative data edge 0011 180° relative data edge (default) 0100 240° relative data edge 0101 300° relative data edge 0110 360° relative data edge 0111 420° relative data edge 1000 480° relative data edge 1001 540° relative data edge 1010 600° relative data edge 1011 1111 660° relative data edge MSPS, encode rate mode (default)
0x03
Determines LVDS other output properties. Primarily functions LVDS span common-mode levels place external resistor. devices that utilize global clock divide, this register determines which phase divider output used supply output clock. Internal latching unaffected.
0x00 0x00 0x00 0x00 0x00
bits (default, normal stream) bits bits bits bits
User-defined pattern, LSB. User-defined pattern, MSB. User-defined pattern, LSB. User-defined pattern, MSB. Serial stream control. Default causes first native stream (global).
serial_ch_stat
Channel output reset (default)
Channel powerdown (default)
0x00
Used power down individual sections converter (local).
undefined feature
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AD9212 APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design layout AD9212 system, recommended that designer become familiar with these guidelines, which discuss special circuit connections layout requirements needed certain pins.
Exposed Paddle Thermal Heat Slug Recommendations
required that exposed paddle underside connected analog ground (AGND) achieve best electrical thermal performance AD9212. exposed continuous copper plane should mate AD9212 exposed paddle, copper plane should have several vias achieve lowest possible resistive thermal path heat dissipation flow through bottom PCB. These vias should solder-filled plugged. maximize coverage adhesion between PCB, partition continuous copper plane overlaying silkscreen into several uniform sections. This provides multiple points between during reflow process, whereas using continuous plane with partitions guarantees only point. Figure layout example. detailed information packaging layout chip scale packages, AN-772 Application Note, Design Manufacturing Guide Lead Frame Chip Scale Package (LFCSP).
SILKSCREEN PARTITION INDICATOR
Power Ground Recommendations
When connecting power AD9212, recommended that separate supplies used: analog (AVDD) digital (DRVDD). only supply available, should routed AVDD first then tapped isolated with ferrite bead filter choke preceded decoupling capacitors DRVDD. user employ several different decoupling capacitors cover both high frequencies. These capacitors should located close point entry board level close parts, with minimal trace lengths. single board ground plane should sufficient when using AD9212. With proper decoupling smart partitioning board's analog, digital, clock sections, optimum performance easily achieved.
Figure Typical Layout
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AD9212 EVALUATION BOARD
AD9212 evaluation board provides support circuitry required operate various modes configurations. converter driven differentially using transformer (default) AD8334 driver. also driven single-ended fashion. Separate power pins provided isolate from drive circuitry AD8334. Each input configuration selected changing connections various jumpers (see Figure Figure 78). Figure shows typical bench characterization setup used evaluate performance AD9212. critical that signal sources used analog input clock have very phase noise jitter) realize optimum performance converter. Proper filtering analog input signal remove harmonics lower integrated broadband noise input also necessary achieve specified noise performance. Figure Figure complete schematics layout diagrams demonstrating routing grounding techniques that should applied system level. each section. least supply needed AVDD_DUT DRVDD_DUT; however, recommended that separate supplies used both analog digital signals that each supply have current capability operate evaluation board using option, separate analog supply (AVDD_5 needed. operate evaluation board using alternate clock options, separate analog supply (AVDD_3.3 needed addition other supplies.
INPUT SIGNALS
When connecting clock analog sources evaluation board, clean signal generators with phase noise, such Rohde Schwarz HP8644 signal generators equivalent, well shielded, RG-58, coaxial cable. Enter desired frequency amplitude from specifications tables. Typically, most Analog Devices, Inc., evaluation boards accept approximately sine wave input clock. When connecting analog input source, recommended multipole, narrow-band, band-pass filter with terminations. Good choices such band-pass filters available from TTE, Allen Avionics, Microwave, Inc. filter should connected directly evaluation board possible.
POWER SUPPLIES
This evaluation board wall-mountable switching power supply that provides maximum output. Connect supply rated wall outlet other supply inner diameter jack that connects P701. Once board, supply fused conditioned before connecting three dropout linear regulators that supply proper bias each various sections board. When operating evaluation board nondefault condition, L701 L704 removed disconnect switching power supply. This enables user bias each section board individually. P702 connect different supply
WALL OUTLET 100V 240V 47Hz 63Hz SWITCHING POWER SUPPLY
OUTPUT SIGNALS
default setup uses Analog Devices HSC-ADC-FPGA-8Z high speed deserialization board deserialize digital output data convert parallel CMOS. These channels interface directly with Analog Devices standard dual-channel FIFO data capture board (HSC-ADC-EVALB-DCZ). eight channels then evaluated same time. more information channel settings their optional settings, visit www.analog.com/FIFO.
5.0V
1.8V
1.8V
3.3V
3.3V
1.5V
3.3V
1.5V_FPGA
AVDD_5V
DRVDD_DUT
AVDD_3.3V
AVDD_DUT
3.3V_D
ROHDE SCHWARZ, SMA, SIGNAL SYNTHESIZER ROHDE SCHWARZ, SMA, SIGNAL SYNTHESIZER
BAND-PASS FILTER
XFMR INPUT AD9212 10-BIT EVALUATION BOARD SERIAL LVDS
HSC-ADC_FPGA-8Z HIGH SPEED DESERIALIZATION BOARD 2-CH 10-BIT PARALLEL CMOS
Figure Evaluation Board Connection
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HSC-ADC-EVALB-DCZ FIFO DATA CAPTURE BOARD CONNECTION
RUNNING ANALYZER USER SOFTWARE
AD9212
DEFAULT OPERATION JUMPER SELECTION SETTINGS
following list default optional settings modes allowed AD9212 Rev. evaluation board. Power: Connect switching power supply that provided with evaluation between rated wall outlet P701. AIN: evaluation board transformercoupled analog input with optimum impedance match bandwidth (see Figure 71). more bandwidth response, differential capacitor across analog inputs changed removed. common mode analog inputs developed from center transformer AVDD_DUT/2.
05968-086
differential LVPECL clock also used clock input using AD9515 (U401). Populate R406 R407 with resistors, remove R215 R216 disconnect default clock path inputs. addition, populate C205 C206 with capacitor, remove C409 C410 disconnect default clock path outputs. AD9515 many pin-strappable options that default mode operation. Consult AD9515 data sheet more information about these other options. addition, on-board oscillator available OSC401 primary clock source. setup quick involves installing R403 with resistor setting enable jumper (J401) position. user wishes employ different oscillator, oscillator footprint options available (OSC401) check performance. PDWN: enable power-down feature, short J301 position (AVDD) PDWN pin. SCLK/DTP: enable digital test pattern digital outputs ADC, J304. J304 tied AVDD during device power-up, Test Pattern 0000 0000 enabled. SCLK/DTP section details. SDIO/ODM: enable power, reduced signal option (similar IEEE 1595.3 reduced range link LVDS output standard), J303. J303 tied AVDD during device power-up, enables LVDS outputs power, reduced signal option from default ANSI-644 standard. This option changes signal swing from p-p, reducing power DRVDD supply. SDIO/ODM section more details. CSB: enable processing information SDIO SCLK pins, J302 always enable mode. ignore SDIO SCLK information, J302 AVDD. Non-SPI Mode: users wish operate without using SPI, simply remove Jumpers J302, J303, J304. This disconnects CSB, SCLK/DTP, SDIO/ODM pins from control bus, allowing operate simplest mode. Each these pins internal termination will float respective level. alternative data capture method setup shown Figure used, optional receiver terminations, R318 R320 R328, installed next high speed backplane connector.
-3dB CUTOFF 186MHz
AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure Evaluation Board Full-Power Bandwidth
VREF: VREF tying SENSE ground, R317. This causes operate full-scale range. separate external reference option using ADR510 ADR520 also included evaluation board. Populate R312 R313, remove C307. Proper VREF options noted Voltage Reference section. RBIAS: RBIAS default setting (R301) ground used core bias current. Clock: default clock input circuitry derived from simple transformer-coupled circuit using high bandwidth impedance ratio transformer (T401) that adds very amount jitter clock path. clock input terminated ac-coupled handle single-ended sine wave types inputs. transformer converts single-ended input differential signal that clipped before entering clock inputs.
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AD9212
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION
following brief description alternative analog input drive configuration using AD8334 dual VGA. this drive option use, some components need populated, which case necessary components listed Table more details AD8334 dual VGA, including works optional settings, consult AD8334 data sheet. configure analog input drive instead default transformer option, following components need removed and/or changed. Remove R102, R115, R128, R141, R161, R162, R163, R164, R202, R208, R218, R225, R234, R241, R252, R259, T101, T102, T103, T104, T201, T202, T203, T204 default analog input path. Populate R101, R114, R127, R140, R201, R217, R233, R251 with resistors analog input path.
AMPLITUDE (dBFS)
this example, MHz, two-pole low-pass filter applied AD8334 outputs. following components need removed and/or changed: Remove L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, L620 AD8334 analog outputs. Populate L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, L620 with inductors. Populate C543, C547, C551, C555, C643, C647, C651, C655 with capacitor.
680nH
05968-091
680nH
68pF
Figure Example Filter Configured MHz, Two-Pole Low-Pass Filter
Populate R152, R153, R154, R155, R156, R157, R158, R159, R215, R216, R229, R230, R247, R248, R263, R264, C103, C105, C110, C112, C117, C119, C124, C126, C203, C205, C210, C212, C217, C219, C224, C226 with resistors provide input common-mode level analog inputs. Populate R105, R113, R118, R124, R131, R137, R151, R160, R205, R213, R221, R222, R237, R238, R255, R256 with resistors analog input path connect outputs. Remove R515, R520, R527, R532, R615, R620, R627, R632 AD8334 analog outputs. Remove R512, R524, R612, R624 AD8334 mode AD8334 HILO low. Some applications require this different. Consult AD8334 data sheet more information these functions.
fSAMPLE 65MSPS 3.5MHz AD8334 GAIN SETTING
-100
10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz)
Figure AD9212 Example Results Using MHz, Two-Pole Low-Pass Filter Applied AD8334 Outputs (Analog Input Signal -1.03 dBFS, 56.75 dBc, SFDR 64.4 dBc)
this configuration, L505 L520 L605 L620 populated with resistors allow signal connection filter additional requirements necessary.
Rev. Page
05968-092
-120
AVDD_DUT P106 R105 0-DNP CH_A VIN_A FB107 C116 0.1µF CH_C E103 AVDD_DUT AVDD_DUT R112 C107 0.1µF R138 R139 C121 0.1µF R128 64.9 R129 R137 0-DNP R161 R110 C103 VIN_A C105 R156 C104 2.2pF R109 R107 FB103 R106 Channel P105 R127 0-DNP CH_A C106 R111 0-DNP R113 T101 R133 R132 R163 T103 FB102 R108 R130 CH_C C115 0.1µF R152 R131 0-DNP FB108 R134 Input Connection INH3
AVDD_DUT
P102
Input Connection
INH1
R104
C101 0.1µF
R154
Channel P101
R101 0-DNP
VIN_C C117 C118 2.2pF FB109
C102 0.1µF
R102 64.9 E101
FB101
R135 VIN_C R136 C119
R103
R158 C120 AVDD_DUT
AVDD_DUT
Input Connection AVDD_DUT INH4 R153 FB105 R121 VIN_B P108 R141 64.9 VIN_B R120 FB106 C112 R157 R122 C110 C111 2.2pF R123 R119 R162 Channel P107 R140 0-DNP Input Connection
AVDD_DUT
INH2
Channel CH_B CH_B 0-DNP R124 T102
P103
R114 0-DNP
R118 0-DNP
R151 0-DNP FB110 C122 0.1µF CH_D R143 R142 C123 0.1µF E104 AVDD_DUT C127 T104 R160 CH_D 0-DNP R145 FB112 R144 FB111 R146
R155
FB104
DNP: POPULATE.
05968-072
Figure Evaluation Board Schematic, Analog Inputs
E102 C113 AVDD_DUT C114 0.1µF R125 R126 R149 R150 C128 0.1µF
Rev. Page
C108 0.1µF
VIN_D R164 C124 C125 2.2pF R148 VIN_D R147
R115 64.9
P104
C109 0.1µF
R116
R117
C126
R159
AVDD_DUT
AVDD_DUT
AD9212
AD9212
AVDD_DUT P206 R236 CH_G R234 64.9k R235 E203 AVDD_DUT AVDD_DUT R249 R250 AVDD_DUT Input Connection INH8 R251 0-DNP R255 0-DNP FB210 P208 R253 C223 0.1µF E204 AVDD_DUT AVDD_DUT R254 C222 0.1µF CH_H T204 CH_H R256 0-DNP R258 R257 C221 0.1µF C220 FB207 C216 0.1µF CH_G T203 R240 R239 R241 FB209 C215 0.1µF R237 0-DNP FB208 R242
AVDD_DUT
P202 C201 0.1µF CH_E VIN_E R207 VIN_E C205 R215 FB203 R208 R210 R238 0-DNP P205 C203 C204 2.2pF R214 Channel R206 R233 0-DNP FB201 C202 0.1µF E201 R211 AVDD_DUT C207 0.1µF R212 C206 R213 0-DNP CH_E T201 FB202 R209 R204 R205 0-DNP R216 Input Connection INH7
Input Connection INH5
R248 VIN_G C217 R245 C218 2.2pF R246 VIN_G C219 R247
Channel
P201
R201 0-DNP
R202 64.9
R203
AVDD_DUT
Input Connection INH6 R221 0-DNP T202 R225 C210 VIN_F R227 C212 R229 C211 2.2pF R228 R252 64.9 FB206 R224 C209 0.1µF E202 AVDD_DUT R231 C214 0.1µF R232 C213 R222 0-DNP CH_F VIN_F R223 FB205 R226 Channel P207 R230
AVDD_DUT
Channel FB204 R220 C208 0.1µF CH_F
P203
R217 0-DNP
Figure Evaluation Board Schematic, Analog Inputs (Continued)
DNP: POPULATE.
05968-073
Rev. Page
R219
FB211 R259 FB212 C227 R265 R266 C228 0.1µF
R260 C224 R261 C225 2.2pF
R264 VIN_H R262 VIN_H C226 R263
R218 64.9
P204
AVDD_DUT
C301 0.1µF
Reference Decoupling
C303 4.7µF C304 0.1µF
C302 0.1µF
R301 AVDD_DUT VIN_E
AVDD_DUT
VIN_E
VIN_F
VIN_F
Digital Outputs
P301
GNDCD10
VIN_D VIN_D AVDD_DUT VIN_C VIN_C
VSENSE_DUT
VREF_DUT
GNDCD9
GNDCD8
R318 R320
GNDCD7
R321
REFT VREF
REFB
AVDD
AVDD
SLUG VIN+E VIN+D VIN+C VIN-C VIN-D RBIAS
AVDD
VIN-E
VIN+F
VIN-F
SENSE
AVDD_DUT AVDD_DUT
AVDD VIN+B VIN_B
AVDD
R303 100k
PDWN ENABLE
AVDD_DUT
GNDCD6
R322
GNDCD5
VIN_G
R302
VIN-B AVDD AVDD_DUT VIN_A VIN_A
VIN+G VIN_B R304 AVDD_DUT CSB_DUT J302
GNDCD4
R323
R318,R320-R328 Optional Output Terminations
GNDCD3
VIN_G
VIN-G
R324
GNDCD2
AVDD_DUT VIN-A VIN+A AVDD J301
AVDD
R325
VIN_H
VIN-H
VIN_H
R326
GNDCD1
VIN+H
AVDD_DUT
GNDAB10
GNDAB9
R327
AVDD
AVDD_DUT
PDWN R319 J303 SDIO_ODM
R328
GNDAB8
AVDD
AD9212BCPZ-65
ALWAYS ENABLE
CLK-
SCLK/DTP AVDD
SDIO/ODM AVDD_DUT DRVDD_DUT
R307 R305 100k R306 100k
CLK+
U301
J304
Enable
AVDD_DUT SCLK_DTP
AVDD
Enable
GNDAB7
AVDD_DUT DRGND DRVDD
AVDD
SCLK_CHB SDI_CHB CSB3_CHB CSB4_CHB SDO_CHB
GNDAB6
DRGND
GNDAB5
AD9212
DNP: POPULATE.
Remove C214 when using external Vref
05968-074
Figure Evaluation Board Schematic, DUT, VREF, Digital Output Interface
Rev. Page
DCO- DCO+ FCO- FCO+
DRVDD_DUT
DRVDD
GNDAB4
SCLK_CHA
GNDAB3
SDI_CHA
GNDAB2
CSB1_CHA
GNDAB1
CSB2_CHA
SDO_CHA
AVDD_DUT
OPTIONAL U302 TRIM/NC VOUT
Reference Circuitry
R311 VREF_DUT
R309 4.99k
Vref Select R314 VREF 0.5V R315
AVDD_DUT
VSENSE_DUT
ADR510ARTZ 1.0V
R312 C305 0.1µF C306 0.1µF R310
VREF External C307 R313 R317
R308 470k
VREF 0.5V(1 R219/R220)
VREF
AD9212
AVDD_3.3V
C401 0.1µF AVDD_3.3V ENABLE OSC401 J401 DISABLE OSC401 OPT_CLK U401 R424 OUT0 OUT0B R426 AVDD_3.3V R428 AVDD_3.3V R423 LVDS OUTPUT C407 0.1µF R430 AVDD_3.3V R417 C408 0.1µF R446 R432 AVDD_3.3V CLIP SINE (DEFAULT) R434 AVDD_3.3V R420 R421 R422 LVPECL OUTPUT AVDD_3.3V R427 0.1µF C406 R408 0.1µF C405 R409 R410 R414 4.12k AVDD_3.3V
R401
OPTIONAL CLOCK DRIVE CIRCUIT
AVDD_3.3V
Optional Clock Oscillator OSC401
R425
GND_PAD
RSET
R411 49.9 CLKB SYNCB SIGNAL=DNC;27,28 OUT1B OUT1
R402
R406
AD9515 Pin-strap settings
R436 AVDD_3.3V R429 R438 AVDD_3.3V R431 R440 AVDD_3.3V R433 R442 AVDD_3.3V R435 R444 AVDD_3.3V R445 R443 R441 R439 R437
OPT_CLK R413
AD9515BCPZ
Encode OPT_CLK R407 R412
CRYSTAL_3
Input
R403
VREF
P401
C402 0.1µF E401
R404 49.9
Clock Circuit
OPT_CLK R415 T401 CR401 HSMS-2812-TR1G
P402
R416
0.1µF C409
05968-075
Figure Evaluation Board Schematic, Clock Circuitry
Rev. Page
R418 C411 0.1µF C410 0.1µF AVDD_3.3V 0.1µF C413 0.1µF
R405
C403 0.1µF
0.1µF
0.1µF
C416 0.1µF
C417 0.1µF
0.1µF
DNP: POPULATE.
R506 Rclamp HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV R505 C510 10µF C543 C547 L508 L511 L512 AVDD_5V L507 C509 0.1µF R517 R529 R522 AVDD_5V CH_D CH_B CH_D CH_C CH_C CH_B
C507 1000pF C508 0.1µF
JP501
Power Down Enable (0-1V=Disable Power)
Populate L505-L520 with resistors design your filter. CH_A CH_A
VG12 C551 L515 C502 0.018µF R503 C505 0.1µF C542 C546 L506 L509 L510 R521 L505 R516 C512 10µF C550 L513 R528 0.1µF C501 R504 AVDD_5V C506 VG12 L501 120nH 0.1µF C503 22pF C504 0.1µF U501 C540 0.1µF R515 R514 R518 C511 0.1µF VIN1 VIP1 EN34 EN12 LON1 VPS1 LOP1 LMD1 VCM1 VCM2 INH1 COM1 CLMP12 COM2 GAIN12 COM1X C541 0.1µF C544 0.1µF C545 0.1µF C548 0.1µF R527 R520 R519 R525 AVDD_5V R523 VOH3 VOL3 VPS34 VOL4 VOH4 COM34 CLMP34 GAIN34 COM4X COM4 VCM3 VCM4 LON4 VPS4 LOP4 LMD4 AVDD_5V AVDD_5V R526 R513 INH2 LMD2 VOH1 VOL1 VPS12 VOL2 VOH2 COM12 COM2X LON2 LOP2 VIP2 VIN2 VPS2 MODE COM34 VPS3 VIN3 VIP3 LOP3 LON3 COM3X LMD3 INH3 COM3 COM12 C537 0.1µF C518 AVDD_5V AVDD_5V 0.1µF C522 C523 0.1µF C524 0.1µF C538 0.1µF 0.1µF R507 C515 0.018µF C514 22pF R524
R534
VG12
R501
External Variable Gain Drive
C555 L516 L519 L520
R502
Variable Gain Circuit (0-1.0V
C554 L514 L517 L518 R533
INH3
AVDD_5V
INH4
C549 0.1µF
C552 0.1µF R532 R530
C553 0.1µF
0.1µF C513
R531
L502 120nH
AD8334ACPZ-REEL
05968-076
Figure Evaluation Board Schematic, Optional Analog Input Drive
MODE Positive Gain Slope 0-1.0V Negitive Gain Slope 2.25-5.0V
Rev. Page
R508 C521 0.018µF HILO INH4 VIN4 VIP4 C520 22pF C533 10µF C529 VG34 AVDD_5V C528 0.1µF 0.1µF C534 0.1µF L504 120nH C535 10µF INH1 0.1µF C525 AVDD_5V C530 0.1µF R509 C527 0.018µF R512 C526 22pF C536 0.1µF Rclamp C531 1000pF C532 0.1µF HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV R510 R511
L503 120nH
INH2
0.1µF C519
JP502
VG34
VG34
R535
DNP: POPULATE.
External Variable Gain Drive
R536
Variable Gain Circuit (0-1.0V
AVDD_5V
AD9212
AD9212
MODE Power Down Enable (0-1V=Disable Power) C607 1000pF C608 0.1µF Rclamp HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV
R605 C610 10µF
AVDD_5V CH_H CH_H CH_F CH_E CH_G CH_F CH_G
Positive Gain Slope 0-1.0V Negative Gain Slope 2.25-5.0V
Populate L605-L620 with resistors design your filter. CH_E
JP601 R606 R617 R622 R629
VG56
R636
VG56
R601 C643 C647 L608 L611 L612 L615
AVDD_5V
External Variable Gain Drive
C651 L616 L619
C655 L620
L607
C609 0.1µF
R602
C602 0.018µF R603 C605 0.1µF
Variable Gain Circuit (0-1.0V
C642 L605 L610 R621 R616
C612 10µF
C646 L606 L609
C650 L613 R628 L614 L617
C654 L618 R633
0.1µF C601
INH7 INH2 LMD2 VOH1 VOL1 VPS12 VOL2 VOH2 COM12 VOL3 VPS34 VOL4 VOH4 COM34
CLMP34 COM4X GAIN34 COM4 VCM3 VCM4 LON4 VPS4 LOP4
AVDD_5V AVDD_5V
R604
VG56
INH8
L601 120nH
C606 0.1µF
C603 22pF
C604 0.1µF U601
C640 0.1µF
C641 0.1µF
C644 0.1µF
C645 0.1µF R620 R618 R619
C648 0.1µF
C649 0.1µF R627 R625 R626
C652 0.1µF R632 R630 R631
C653 0.1µF
C611 0.1µF
VIN1
VIP1
EN12
EN34
LON1
VPS1
LOP1
VCM2
VCM1
LMD1
INH1
CLMP12
COM2 COM1 GAIN12 COM1X
0.1µF C613
COM12 AVDD_5V
C615 0.018µF
R615 R614
R613
L602 120nH
AVDD_5V
C616 0.1µF COM2X LON2 LOP2 VIP2 VIN2 VPS2 MODE COM34 VOH3 VPS3 VIN3 VIP3 LOP3 LON3 COM3X LMD3 INH3
COM3
C614 22pF R607
C618 C617 0.1µF 0.1µF AVDD_5V AVDD_5V 0.1µF C622 C623 0.1µF C624 0.1µF
R624
05968-077
Figure Evaluation Board Schematic, Optional Analog Input Drive (Continued)
AD8334ACPZ-REEL
R623
Rev. Page
R608 C621 0.018µF LMD4 HILO INH4 VIN4 VIP4 C620 22pF
AVDD_5V
L603 120nH
INH6
0.1µF C619
C629
VG78 AVDD_5V
JP602
C633 10µF
C628 0.1µF
0.1µF
VG78 L604 120nH
C634 0.1µF
VG78
R634 INH5
AVDD_5V C630 0.1µF
R609 C635 10µF R612 C627 0.018µF
DNP: POPULATE.
External Variable Gain Drive 0.1µF C625 C626 22pF
R635
C636 0.1µF
Variable Gain Circuit (0-1.0V
C631 1000pF
C632 0.1µF
Rclamp HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV R610
R611
AVDD_5V
CIRCUITRY FROM FIFO
Power Supply Input REMOVE WHEN USING PROGRAMMING (U402) F701 FER701 NANOSMDC110F-2 C704 D701 10µF
SDI_CHA CSB1_CHA SCLK_CHA SDO_CHA
PROGRAMMING AVDD_5V +3.3V NORMAL OPERATION AVDD_3.3V
AVDD_3.3V P701
R708 R709 R706 R707
AVDD_5V
D702 PWR_IN SK33-TP
AVDD_3.3V S2A-TP
J701
CR702
GREEN
C701
0.1µF R710 R703 0-DNP 0-DNP 0-DNP Optional Power Input P702 SDIO_ODM NC7WZ07P6X_NL AVDD_DUT U702
C702 0.1µF
U701
7.5V POWER CON005 2.5MM JACK
R704 R705
S701
R701 4.7k
R716
MCLR/GP3
PIC12F629-I/SNG
RESET/ REPROGRAM
R702 3.3V_AVDD
DUT_DRVDD DUT_AVDD 5V_AVDD
L703 10µH AVDD_3.3V C709 10µF C710 0.1µF +3.3V
CR701
PROGRAMMING HEADER
OPTIONAL GREEN
R712 AVDD_DUT R713
E701 R711
L701 10µH AVDD_5V C705 10µF C706 0.1µF +5.0V
MCLR/GP3
PICVCC
J702
L702 10µH AVDD_DUT C707 10µF Decoupling Capacitors SCLK_DTP AVDD_DUT CSB_DUT AVDD_5V C723 0.1µF C724 0.1µF C725 0.1µF C726 0.1µF C727 0.1µF L704 10µH DRVDD_DUT
C703
+1.8V
NC7WZ16P6X_NL
05968-078
Figure Evaluation Board Schematic, Power Supply Inputs Interface Circuitry
0.1µF
Rev. Page
U703 R714 R715 AVDD_DUT C730 0.1µF C731 0.1µF C732 0.1µF C733 0.1µF U705 L705 10µH ADP3339AKCZ-3.3-RL DUT_AVDD
C708 0.1µF
PICVCC
MCLR/GP3
+1.8V C711 10µF C712 0.1µF
C734 0.1µF
C735 0.1µF AVDD_5V
U707 PWR_IN C719
PWR_IN
ADP3339AKCZ-1.8-RL
L707 10µH 3.3V_AVDD AVDD_DUT C720 C745 0.1µF C744 0.1µF C746 0.1µF C747 0.1µF C748 0.1µF
C749 0.1µF
C750 0.1µF
C751 0.1µF
C752 0.1µF
C753 0.1µF
C715
C714
U704 U706 L706 10µH ADP3339AKCZ-5-RL7 DUT_DRVDD
PWR_IN C717 C721
PWR_IN
ADP3339AKCZ-1.8-RL
L708 10µH 5V_AVDD C722
AVDD_3.3V C740 0.1µF C741 0.1µF
DRVDD_DUT C742 0.1µF C743 0.1µF
C716
DNP: POPULATE.
AD9212
AD9212
Figure Evaluation Board Layout, Primary Side
Rev. Page
05968-079
AD9212
Figure Evaluation Board Layout, Ground Plane
Rev. Page
05968-045
AD9212
Figure Evaluation Board Layout, Power Plane
Rev. Page
05968-046
AD9212
Figure Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. Page
05968-082
AD9212
Table Evaluation Board Bill Materials (BOM)
Board Reference Designator AD9212LFCSP_REVA C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, C222, C223, C228, C301, C302, C304, C305, C306, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C501, C504, C505, C506, C508, C509, C511, C513, C518, C519, C522, C523, C524, C525, C528, C529, C530, C532, C534, C536, C537, C538, C601, C604, C605, C606, C608, C609, C611, C613, C616, C617, C618, C619, C622, C623, C624, C625, C628, C629, C630, C632, C634, C636, C701, C702, C703, C706, C708, C710, C712, C723, C724, C725, C726, C727, C730, C731, C732, C733, C734, C735, C740, C741, C742, C743, C744, C745, C746, C747, C748, C749, C750, C751, C752, C753 C104, C111, C118, C125, C204, C211, C218, C225 C510, C512, C533, C535, C610, C612, C633, C635 C303 C507, C531, C607, C631 C502, C515, C521, C527, C602, C615, C621, C627 Manufacturer Part Number GRM155R71C104KA88D
Item
Device Capacitor
Package
Value ceramic, X5R,
Manufacturer Murata
Capacitor
ceramic, COG, 0.25 tol, ±10%, ceramic, ceramic, X5R, 1000 ceramic, X7R, 0.018 ceramic, X7R,
Murata
GRM1555C1H2R20CZ01D
Capacitor
Murata
GRM219R60J106KE19D
Capacitor Capacitor Capacitor
Murata Murata
GRM188R60J475KE19D GRM155R71H102KA01D 0402YC183KAT2A
Rev. Page
AD9212
Item Board Reference Designator C503, C514, C520, C526, C603, C614, C620, C626 C704 C307, C714, C715, C716, C717, C719, C720, C721, C722 C540, C541, C544, C545, C548, C549, C552, C553, C640, C641, C644, C645, C648, C649, C652, C653 C705, C707, C709, C711 CR401 CR701, CR702 D702 D701 F701 FER701 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212 JP501, JP502, JP601, JP602 J301, J302, J303, J304, J401, J701 J702 L701, L702, L703, L704, L705, L706, L707, L708 L501, L502, L503, L504, L601, L602, L603, L604 Device Capacitor Package Value ceramic, NPO, tol, tantalum, ceramic, X5R, ceramic, X7R, Manufacturer Murata Manufacturer Part Number GRM1555C1H220JZ01D
Capacitor Capacitor
1206
ROHM Co., Ltd. Murata
TCA1C106M8R GRM188R61C105KA93D
Capacitor
Murata
GRM21BR71H104KA01L
Capacitor Diode Diode Diode Fuse Choke coil Ferrite bead
SOT-23 DO214AB DO214AA 1210 2020
ceramic, X5R, dual Schottky Green, candela trip-current resettable fuse test frequency MHz, tol,
Murata Avago Technologies Panasonic Micro Commercial Micro Commercial Tyco/Raychem Murata Murata
GRM188R60J106ME47D HSMS-2812-TR1G LNJ314G8TRA SK33-TP S2A-TP NANOSMDC110F-2 DLW5BSN191SQ2L BLM18BA100SN1D
Connector Connector Connector Ferrite bead
2-pin 3-pin 10-pin 1210
header jumper, 2-pin header jumper, 3-pin header, male, double straight bead core SMD, test freq MHz, tol,
Samtec Samtec Samtec Murata
TSW-102-07-G-S TSW-103-07-G-S TSW-105-08-G-D BLM31PG500SN1L
Inductor
Murata
LQG15HNR12J02D
Rev. Page
AD9212
Item Board Reference Designator L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 OSC401 Device Resistor Package Value Manufacturer Components Corp. Manufacturer Part Number NRC04Z0TRF
Oscillator
P101, P103, P105, P107, P201, P203, P205, P207, P401 P301
Connector
Clock oscillator, 65.00 MHz, duty cycle Side-mount 0.063" board thickness 1469169-1, right angle 2-pair, header assembly RAPC722, power supply connector 1/16
Valpey Fisher
VFAC3-BHL-65MHz
Johnson Components Tyco
142-0701-851
Connector
HEADER
6469169-1
P701 R301, R307, R401, R402, R410, R413, R504, R505, R511, R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715 R103, R117, R129, R142, R203, R219, R235, R253, R317, R405, R415, R416, R417, R418, R706, R707, R708, R709 R102, R115, R128, R141, R202, R218, R234, R252 R104, R116, R130, R143, R204, R220, R236, R254 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713 R108, R110, R121, R122, R134, R136, R146, R147, R209, R210, R226, R227, R242, R245, R260, R261
Connector Resistor
0.1", PCMT
Switchcraft Components Corp.
RAPC722X NRC04J103TRF
Resistor
1/16
Components Corp.
NRC04Z0TRF
Resistor
64.9 1/16
Resistor
1/10
Resistor
1/16
Components Corp. Components Corp. Components Corp.
NRC04F64R9TRF
NRC06Z0TRF
NRC04F1001TRF
Resistor
1/16
Components Corp.
NRC04J330TRF
Rev. Page
AD9212
Item Board Reference Designator R161, R162, R163, R164, R208, R225, R241, R259 R303, R305, R306 Device Resistor Package Value 1/16 Manufacturer Components Corp. Components Corp. Components Corp. Susumu Components Corp. Copal Electronics Corp. Components Corp. Components Corp. Components Corp. Manufacturer Part Number NRC04F4990TRF
Resistor
1/16
NRC04F1003TRF
R414
Resistor
4.12 1/16W,
NRC04F4121TRF
R404 R309
Resistor Resistor
49.9 1/16 0.5% 4.99 1/16
RR0510R-49R9-D NRC04F4991TRF
R310, R501, R535, R601, R634 R308
Potentiometer
3-lead
Resistor
Cermet trimmer potentiometer, 18-turn adjust, 10%, 1/16
CT94EW103
NRC04J474TRF
R502, R536, R602, R635 R513, R514, R518, R519, R525, R526, R530, R531, R613, R614, R618, R619, R625, R626, R630, R631 R515, R520, R527, R532, R615, R620, R627, R632 R503, R507, R508, R509, R603, R607, R608, R609 R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445 R701
Resistor
1/16
NRC04J393TRF
Resistor
1/16
NRC04F1870TRF
Resistor
1/16
Resistor
1/16
Resistor
1/20
Components Corp. Components Corp. Components Corp. Components Corp. Components Corp. Components Corp. Components Corp. Components Corp. Panasonic
NRC04F3740TRF
NRC04F2740TRF
NRC02Z0TRF
Resistor
1/16
NRC04J472TRF
R702
Resistor
1/16
NRC04F2610TRF
R716
Resistor
1/16
NRC06F261OTRF
R420, R421
Resistor
1/16
NRC04J241TRF
R422, R423
Resistor
1/16
NRC04F1000TRF
S701
Switch
Light Touch,
EVQPLDA15
Rev. Page
AD9212
Item Board Reference Designator T101, T102, T103, T104, T201, T202, T203, T204, T401 U704, U707 Device Transformer Package CD542 Value ADT1-1WT+, impedance ratio transformer ADP3339AKC-1.8-RL, regulator AD8334ACPZ-REEL, ultralow noise precision dual ADP3339AKC-5-RL7 ADP3339AKC-3.3-RL AD9212BCPZ-65, octal, 10-bit, MSPS serial LVDS ADR510ARTZ, precision noise shunt voltage reference AD9515BCPZ, clock distribution NC7WZ07P6X_NL, dual buffer NC7WZ16P6X_NL, dual buffer Flash prog size speed, PIC12F controller series Manufacturer Mini-Circuits Manufacturer Part Number ADT1-1WT+
SOT-223
Analog Devices
ADP3339AKCZ-1.8-RL
U501, U601
CP-64-3
Analog Devices
AD8334ACPZ-REEL
U706 U705 U301
SOT-223 SOT-223 CP-64-3
Analog Devices Analog Devices Analog Devices
ADP3339AKCZ-5-RL7 ADP3339AKCZ-3.3-RL AD9212BCPZ-65
U302
SOT-23
Analog Devices
ADR510ARTZ
U401 U702 U703 U701
LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC
Analog Devices Fairchild Fairchild Microchip
AD9515BCPZ NC7WZ07P6X_NL NC7WZ16P6X_NL PIC12F629-I/SNG
This RoHS compliant.
Rev. Page
AD9212 OUTLINE DIMENSIONS
9.00 0.60 0.60
INDICATOR
INDICATOR
VIEW
8.75
0.50
EXPOSED
(BOTTOM VIEW)
7.25 7.10 6.95
0.50 0.40 0.30 0.80 0.65 0.05 0.02 0.30 0.23 0.18 0.20
7.50
0.25
1.00 0.85 0.80
SEATING PLANE
COMPLIANT JEDEC STANDARDS MO-220-VMMD-4
Figure 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Body, Very Thin Quad (CP-64-3) Dimensions shown millimeters
ORDERING GUIDE
Model AD9212BCPZ-40 AD9212BCPZRL7-401 AD9212BCPZ-651 AD9212BCPZRL7-651 AD9212-65EBZ1
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape Reel 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape Reel Evaluation Board
051007-C
Package Option CP-64-3 CP-64-3 CP-64-3 CP-64-3
RoHS Compliant Part.
Rev. Page
AD9212 NOTES
©2006-2007 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D05968-0-12/07(A)
Rev. Page
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