MONOLITHIC GATED DELAY LINE OSCILLATOR (SERIES 3D7702) All-silico
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3D7702
MONOLITHIC GATED DELAY LINE OSCILLATOR (SERIES 3D7702)
All-silicon, low-power CMOS technology TTL/CMOS compatible inputs outputs Vapor phase, wave solderable Auto-insertable (DIP pkg.) Frequency range: 0.3MHz through 100MHz Frequency tolerance: 0.5% typical Temperature stability: ±1.5% typical (-40C 85C) stability: ±0.5% typical (4.75V 5.25V) 14-pin available drop-in replacements hybrid delay line oscillator (DLO32F)
PACKAGES
3D7702-xx 3D7702K-xx
3D7702Z-xx SOIC-8
DIP-14 pins removed
mechanical dimensions, click here. package marking details, click here.
FUNCTIONAL DESCRIPTION
DESCRIPTIONS
3D7702 Delay Line Oscillator product family consists fixedEN Oscillator Enable frequency CMOS integrated circuit oscillators. Each package contains Oscillator Output single oscillator, which gated therefore synchronized Oscillator Output external signal. device frequency range from 0.3MHz through Volts 100MHz. 3D7702 outputs that 180° out-of-phase when Ground oscillator running, used drop-in replacement DLO32F hybrid oscillator. 3D7702 TTL- CMOS-compatible, capable driving 74LS-type loads. offered standard 14-pin auto-insertable space saving surface mount 8-pin SOIC package.
#06024
12/5/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7702
TABLE PART NUMBER SPECIFICATIONS
DASH NUMBER -0.3 -0.4 -0.5 -0.75 -2.5 -7.5 -100 NOTE: OUTPUT FREQUENCY (MHz) -40C Vdd=5.00V 4.75<Vdd<5.25 0.002 0.008 0.002 0.010 0.003 0.013 0.75 0.004 0.75 0.019 0.005 0.025 0.010 0.050 0.013 0.063 0.015 0.075 0.020 0.100 0.025 0.125 0.038 0.188 10.0 0.05 10.0 0.25 20.0 0.10 20.0 0.50 25.0 0.13 25.0 0.63 30.0 0.15 30.0 0.75 40.0 0.20 40.0 1.00 50.0 0.25 50.0 1.25 75.0 0.38 75.0 3.75 100.0 0.50 100.0 7.00 2006 Data Delay Devices
dash number between shown also available standard.
#06024
12/5/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7702
APPLICATION NOTES
OPERATIONAL DESCRIPTION
3D7702 delay line oscillator architecture shown Figure internal delay line composed number delay cells connected series compensated thermal supply voltage variations. low-going edge input starts oscillator, with output responding immediately. output delayed cycle. response output when oscillator disabled depends status when signal goes high, shown Figure low, will remain low, final pulse will period. high, will soon goes high, final pulse both outputs will have width smaller than period.
Temp Compensation
Delay Line
Figure 3D7702 Functional Diagram
Figure 3D7702 Timing Diagrams
#06024
12/5/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7702
APPLICATION NOTES (CONT'D)
POWER SUPPLY TEMPERATURE CONSIDERATIONS
delay CMOS integrated circuits strongly dependent power supply temperature. monolithic 3D7702 oscillator utilizes novel innovative compensation circuitry minimize frequency variations induced fluctuations power supply and/or temperature. thermal coefficient reduced PPM/C, which equivalent variation, over -40C operating range, ±1.5% from roomtemperature frequency setting. power supply coefficient reduced, over 4.75V 5.25V operating range, ±0.5% frequency setting nominal 5.0VDC power supply. These specifications hold lower frequencies only. higher dash numbers, variations will slightly greater, noted Table essential that power supply adequately bypassed filtered. addition, power should impedance construction possible. Power planes preferred.
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 -1.0 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 UNITS NOTES
-35.0 15.0
4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/output (pf) Device frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
#06024
12/5/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7702
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V OUTPUT: Rload: Cload: Threshold: 1.5V (Rising Falling)
Device Under Test
Digital Scope
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT)
TRIG FREQUENCY/ TIME INTERVAL COUNTER
Figure Test Setup
tFALL
2.4V 1.5V 0.6V
tRISE 1/fOSC
1.5V
2.4VVIH 1.5V 0.6V
tENB
1.5V
tDIS
1.5V
Figure Timing Diagram
#06024
12/5/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
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