MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7424) Fou

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MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7424) Fou

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3D7424
MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7424)
Four indep't programmable lines single chip All-silicon CMOS technology quiescent current (5mA typical) Leading- trailing-edge accuracy Vapor phase, wave solderable Increment range: 0.75ns through 400ns Delay tolerance: (see Table Line-to-line matching: typical Temperature stability: ±1.5% typical (-40C 85C) stability: ±0.5% typical (4.75V 5.25V) Minimum input pulse width: total delay
PACKAGES
SOIC-14 3D7424D-xx
mechanical dimensions, click here. package marking details, click here.
FUNCTIONAL DESCRIPTION
3D7424 device small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed serial interface, independently varied over equal steps. step size determined device dash number. Each input reproduced corresponding output without inversion, shifted time user selection. each line, delay time given
DESCRIPTIONS
I1-I4 O1-O4 Signal Inputs Signal Outputs Address Latch Serial Clock Serial Data Serial Data 5.0V Ground
where inherent delay, delay address n-th line delay increment (dash number). desired addresses shifted into device inputs, addresses latched using input. serial interface also used enable/disable each delay line. 3D7424 operates volts typical 6ns. 3D7424 TTL/CMOS-compatible, capable sourcing sinking loads, features both rising- falling-edge accuracy. device offered space saving surface mount 14-pin SOIC.
TABLE PART NUMBER SPECIFICATIONS
Part Number 3D7424D-.75 3D7424D-1 3D7424D-1.5 3D7424D-2 3D7424D-4 3D7424D-5 3D7424D-10 3D7424D-15 3D7424D-20 3D7424D-40 3D7424D-50 3D7424D-100 3D7424D-200 3D7424D-400 Delay Step DELAYS TOLERANCES (NS) Inherent Total Relative Delay Delay Tolerance 17.25 0.50ns 21.0 0.50ns 28.5 0.50ns 36.0 0.75ns 66.0 0.75ns 81.0 0.75ns 1.25ns 1.88ns 2.50ns 5.00ns 6.25ns 1506 12.5ns 3006 25.0ns 6006 50.0ns INPUT RESTRICTIONS Frequency Pulse Width Recom'd Absolute Recom'd Absolute 15.0 22.5 30.0 60.0 75.0
0.19 0.25 0.38 0.50 1.00 1.25 2.50 3.75 5.00 10.0 10.0 12.5 20.0 40.0
NOTE: increment between 0.75ns 400ns shown also available standard page details regarding input restrictions 2007 Data Delay Devices
#06019
6/25/2007
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7424
APPLICATION NOTES
THEORY OPERATION
quad 4-bit programmable 3D7424 device architecture comprised four independently operating delay lines. Each delay line produces output replica signal present input, shifted time. single delay line comprised number delay cells connected series. Delay selection achieved routing output each string cells respective output (O1-O4). delay each four lines controlled independently, serial interface, described next section. change delay from address setting next called increment, LSB. nominally equal device dash number. minimum delay, achieved setting address line zero, called inherent delay. best performance, essential that power supply adequately bypassed filtered. addition, power should impedance construction possible. Power planes preferred. Also, signal traces should kept short possible.
DELAY LINE DELAY LINE DELAY LINE DELAY LINE
ADDR4 ADDR3 ADDR2 ADDR1 ENABLES
PROGRAMMED DELAY INTERFACE
Figure illustrates main functional blocks 3D7424 device. Since device CMOS design, unused input pins must returned well defined logic levels (VDD GND). delays adjusted first shifting 20-bit programming word into device pins, then strobing signal latch values. sequence shown Table associated timing diagram shown Figure Each line associated with enable bit. Setting this will force corresponding delay line output high impedance state, while setting high returns line normal operation. device contains output, which used cascade multiple devices, shown Figure TABLE SEQUENCE
Delay Line Function Output Enable Output Enable Output Enable Output Enable Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address
20-BIT LATCH 20-BIT SHIFT REGISTER
Figure Functional block diagram
LATCH (AL) CLOCK (SC) SERIAL INPUT (SI) SERIAL OUTPUT (SO) DELAY TIMES
tCSL
tDSC
tDHC
tPCQ
tLDX
PREVIOUS VALUES
tLDV
VALUES
Figure Serial interface timing diagram
#06019
6/25/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7424
APPLICATION NOTES (CONT'D)
DELAY ACCURACY
There number ways characterizing delay accuracy programmable line. first differential nonlinearity (DNL), also referred increment error. defined deviation delay step given address from nominal value. dash numbers, within every address (see Table Delay Step). integrated nonlinearity (INL) determined first constructing least-squares best straight line through delay-versus-address data. then deviation given delay from this line. dash numbers, within every address. relative error defined follows: erel Tinc where address, measured delay i'th address, measured inherent delay, Tinc nominal increment. very similar INL, simpler calculate. most dash numbers, relative error less than every address (see Table Relative Tolerance). absolute error defined follows: eabs (Tinh Tinc) where Tinh nominal inherent delay. absolute error tolerance given addresses (see Table Inherent Delay, Total Delay, respectively). intermediate address, tolerance found linear interpolation address address tolerances. matching error measure well delay four lines track each other when they programmed same address. lines typically matched within 1ns, whichever greater, addresses dash numbers.
DELAY STABILITY
delay CMOS integrated circuits strongly dependent power supply temperature. 3D7424 utilizes novel compensation circuitry minimize delay variations induced fluctuations power supply and/or temperature. With regard stability, delay 3D7424 given address, split into components: inherent delay (T0) relative delay T0). These components exhibit very different stability coefficients, both which must considered very critical applications. thermal coefficient relative delay limited ±250 PPM/C, which equivalent variation, over -40C operating range, ±1.5% from room-temperature delay settings. This holds dash numbers greater than smaller dash numbers, thermal drift will larger will always positive. thermal coefficient inherent delay nominally +15ps/C dash numbers. power supply sensitivity relative delay ±0.5% over 4.75V 5.25V operating range, with respect delay settings nominal 5.0V power supply. This holds dash numbers greater than smaller dash numbers, voltage sensitivity will greater will always negative. sensitivity inherent delay nominally -1ps/mV dash numbers.
3D7424
3D7424
3D7424
FROM WRITING DEVICE
NEXT DEVICE
Figure Cascading Multiple Devices
#06019
6/25/2007
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7424
APPLICATION NOTES (CONT'D)
INPUT SIGNAL CONSIDERATIONS
frequency and/or pulse width (high low) operation adversely impact specified delay increment accuracy particular device. reasons dependency output delay accuracy input signal characteristics varied complex. Therefore, recommended absolute maximum operating input frequency recommended absolute minimum operating pulse width have been specified. OPERATING FREQUENCY absolute maximum operating frequency specification, tabulated Table determines highest frequency delay line input signal that reproduced, shifted time device output, with acceptable duty cycle distortion. recommended maximum operating frequency specification determines highest frequency delay line input signal which output delay accuracy guaranteed. Operation above recommended maximum frequency will cause delays shift slighty with respect their values low-frequency operation. magnitudes these deviations will increase absolute maximum frequency approached. However, input frequency pulse width remain constant, device will exhibit same delays from period next (ie, appreciable jitter). OPERATING PULSE WIDTH absolute minimum operating pulse width (high low) specification, tabulated Table determines smallest pulse width delay line input signal that reproduced, shifted time device output, with acceptable pulse width distortion. minimum operating pulse width (high low) specification determines smallest pulse width delay line input signal which output delay accuracy tabulated Table guaranteed. Operation below recommended minimum pulse width will cause delays shift slighty with respect their values long-pulse-width operation. magnitudes these deviations will increase absolute minimum pulse width approached. However, input pulse width frequency remain constant, device will exhibit same delays from period next (ie, appreciable jitter).
PROGRAMMED DELAY UPDATE
delay line memory device. stores information present input time equal delay setting before presenting output. Each 4-bit delay line 3D7424 represented serially connected delay elements (individually addressed programming data), each capable storing data time equal device increment (step time). delay line memory property, conjunction with operational requirement "instantaneously" connecting delay element addressed programming data output, inject spurious information onto output data stream. order ensure that spurious outputs occur, essential that input signal idle (held high low) short duration prior updating programmed delay. This duration given maximum programmable delay. Satisfying this requirement allows delay line "clear" itself spurious edges. Once address loaded, input signal begin switch.
#06019
6/25/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7424
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -0.1 -0.1 -8.0 -6.0 UNITS NOTES 5.25V 4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/line (pf) Input frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Latch Width Data Setup Clock Data Hold from Clock Clock Width (High Low) Clock Setup Latch Clock Serial Output Latch Delay Valid Latch Delay Invalid Input Pulse Width Input Period Input Output Delay SYMBOL tDSC tDHC tCSL tPCQ tLDV tLDX Period tPLH, tPHL UNITS Total Delay Total Delay NOTES
Table Table Text
NOTES: Refer PROGRAMMED DELAY UPDATE section
#06019
6/25/2007
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7424
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (VDD): 5.0V 0.1V Input Pulse: High 3.3V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.7V Pulse Width: PWIN 1.25 Total Delay Period: PERIN Total Delay OUTPUT: Rload: Cload: Threshold: 1.65V (Rising Falling)
Device Under Test
Digital Scope
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) OUT1 OUT2 OUT3 OUT4 TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER
Figure Test Setup
PERIN tRISE INPUT SIGNAL
2.7V 1.65V 0.6V
tFALL
2.7V 1.65V 0.6V
tPHL
tPLH OUTPUT SIGNAL
1.65V
1.65V
Figure Timing Diagram
#06019
6/25/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7424) Fou

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