APEX Devices December 2001, ver. Application Note communicat

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SRAM Controller Reference Design
APEX Devices
December 2001, ver. Application Note
communication systems require more low-latency, high-bandwidth interfaces peripheral components, designs need high-throughput memory with efficient utilization. previous generation static memory types inefficient when they frequently switch between reading from writing memory. address this problem, IDT, Micron, Motorola have developed zero-bus turnaround (ZBT) SRAM architecture. implement this memory, Altera developed SRAM controller reference design with APEXII devices. This application note describes functionality Altera SRAM controller reference design explains data tree structure, along with installation, compilation, simulation, design file.
General Description
SRAM synchronous burst (SyncBurst) SRAM with simplified interface that allows take advantage full bandwidth eliminating turnaround cycles idle cycles between read write operations. Turnaround cycles, which necessary standard SyncBurst SRAM, significantly reduce available bandwidth. Figure compares read-to-write transition using SyncBurst SRAM SRAM. Figure Comparison Read-to-Write Transitions
Standard SyncBurst SRAM
COMMAND read
write
SRAM
COMMAND read write read write
Note Figure
shaded sections represent no-operation cycles.
Altera Corporation
A-AN-183-1.0
183: SRAM Controller Reference Design APEX Devices
SRAM available with pipelined flow-through interface. pipelined interface, read data available clock cycles after read command issued, write data required clock cycles after write command. flow-through interface, data-latency requirement clock cycle read write operations. Pipelined SRAM provides faster clock-to-data access, therefore clocked faster than flow-through SRAM. However, flow-through SRAM provides clock cycle less latency than pipelined variety. Both pipelined flow-through SRAM devices load address each clock cycle advance device's internal counter. device sequence internal counter linear interleaved fashion. SRAM supports either LVTTL LVCMOS pins. SRAM devices have higher chance contention than standard SyncBurst SRAM devices. contention results when devices (for example, bus) attempt drive opposite logic values same time. During write operation, controller drives data SRAM receives that data, during read operation controller must tri-state output drivers receive data being driven SRAM. controller executes read followed write operation SRAM does stop driving before controller begins drive bus, contention occurs opposite logic levels being driven. Alternatively, during write followed read operation turn-off time controller longer than turn-on time SRAM, contention result. effects short-term contention minimal; very small amount power increase extra heating occurs. more in-depth discussion contention effects, refer document Application Brief AN-203 (ZBT SRAMS: System Design Issues Timing), available site http://www.idt.com. Altera's SRAM controller provides simplified interface SRAM devices. controller available either Verilog VHDL, optimized Altera APEX device architecture. APEX devices interface with SRAM MHz.
Reference Design Description
reference design SRAM memory controller demonstrates generating SRAM interface control signals. This design optimized APEX devices. addition, APEX device buffers have programmable delay avoid contention. delay allows device quickly release control slowly take control bus. delay logic option Altera Quartus software.
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
implement Altera SRAM controller reference design APEX device provide simplified interface SRAM device. reference design implements SRAM controller EP2A15F672C7 device. Figure shows simplified system-level block diagram which SRAM controller connects SRAM module. Figure Controller System-Level Diagram
CLKIN RD_WR_N ADDR ADDR_ADV_LD_N DATA_IN DATA_OUT Controller
ADV_LD_N BW_N RW_N Memory
Controller Structure Operation
SRAM controller reference design made five lower-level modules: pipe_delay, addr_ctrl_out, data_inout, pipe_stage, clk_ctrl. Figure shows block diagram controller. Figure Controller Block Diagram
CLKIN clk_ctrl (PLL) Clock modules
ADDR ADDR_ADV_LD_N RD_WR_N pipe_stage addr_ctrl_out
ADV_LD_N BW_N RW_N
DATA_IN pipe_delay DATA_OUT data_inout
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Table describes function five controller modules. Table Controller Functional Operation Module
pipe_delay addr_ctrl_out data_inout pipe_stage clk_ctrl
Function
Provides proper delay input data, depending whether controller configured pipelined flow-through SRAM Registers address control signals before outputting them SRAM Registers outgoing data SRAM provides bidirectional control SRAM Registers input output user signals speed purposes stand-alone controller configuration Instantiates phase-locked loop (PLL) double input clock de-skew internal external clocks SRAM
write operations, controller aligns write data write command. controller also handles turnaround transitioning between write read operations. following sections provide detailed descriptions read write operations.
Read Operation
following guidelines read operations:
ADDR, ADDR_ADV_LD_N, DATAIN signals appropriate values, RD_WR_N high. data read available DATA_OUT clock cycle both pipelined flow-through operations. bits used read operations. Asserting ADDR_ADV_LD_N causes SRAM write data ADDR address. Asserting ADDR_ADV_LD_N high causes SRAM internal two-bit counter increment next address (i.e., internal two-bit counter takes place ADDR's lower bits). SRAM performs burst read operation number cycles that ADDR_ADV_LD_N high.
Figure shows timing diagram single read operation. perform multiple reads, change input signals (i.e., ADDR, ADDR_ADV_LD_N, each cycle while keeping RD_WR_N high.
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Figure Read Operation (Pipelined)
ADDR DATA_OUT RD_WR_N ADD_ADV_LD_N RW_N BW_N ADV_LD_N
Note
Note Figure
Crosshatched areas represent don't care bits.
Write Operation
following guidelines write operations:
ADDR, ADDR_ADV_LD_N, DATAIN, signals appropriate values, RD_WR_N low. device clocks data into SRAM four clock cycles later pipelined operation three clock cycles later flow-through operation. controller handles latency requirements that data presented clock cycles after address control signals flow-through pipelined operations, respectively. bits high each byte line (either eight nine bits, depending SRAM used) written SRAM. write data ADDR address, designers should assert ADDR_ADV_LD_N low. Asserting ADDR_ADV_LD_N high causes SRAM internal two-bit counter increment next address performing burst write operation number cycles that ADDR_ADV_LD_N high.
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Figure shows timing diagram single write operation. perform multiple writes, change input signals (i.e., ADDR, ADDR_ADV_LD_N, DATAIN, each cycle while keeping RD_WR_N low. Figure Write Operation (Pipelined)
ADDR DATA_IN RD_WR_N ADD_ADV_LD_N RW_N BW_N ADV_LD_N
Note
Note Figure
Crosshatched areas represent don't care bits.
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Interface Signals
Table describes controller port interface signals. Table Interface Signals Signal
CLKIN RESET_N ADDR[ASIZE-1.0] RD_WR_N ADDR_ADV_LD_N Clock Reset Memory Address Read/Write Address Advance/Load
Name
Active
Input Input Input Input Input
Description
System clock System reset Memory address read/write requests; width ASIZE SRAM read/write input; high indicates read, indicates write Address advance/load input. When high, SRAM controller's internal address counter advanced. When low, address loaded. Input data bus; width DSIZE Output data bus; width DSIZE Masks individual bytes during data write; width BWSIZE Address outputs SRAM ADV_LD_N output SRAM Controller byte write enables Controller read/write output; high indicates read, indicates write Bidirectional data port
DATAIN[DSIZE-1.0] DATAOUT[DSIZE-1.0] DM[BWSIZE-1.0] SA[11.0] ADV_LD_N BW_N[BWSIZE-1.0] RW_N DQ[DSIZE-1.0]
Input Data Output Data Data Mask Address Advance/Load Byte Write Enables Read/Write Data
High
Input Output Input Output Output Output Output Input/ Output
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Parameters
Table summarizes parameters SRAM controller function. configure these parameters file. Table SRAM Controller Parameters Parameter
ASIZE DSIZE BWSIZE FLOWTHROUGH
Description
Specifies number address bits interface. Specifies number data bits interface. Specifies number byte enables interface. Value determines whether controller operates flow-through pipelined mode. pipelined operation this parameter flow-through operation,
Constraints
ensure proper logic placement controller, following constraints Quartus software. These constraints reference file provided Altera.
Turn Remove Duplicate Register logic option (Options Parameters menu). LogicLockincremental design capability place logic into block seven logic array blocks (LABs) within MegaLABstructure bottom right corner device (MegaLAB block reference design). Ensure that Quartus software placed input, output, output enable (OE) registers element (IOE) fastest timing using fast register assignments. phase shift feature APEX decrease times. However, this feature increase times. example, phase shift resulted 3.525-ns 1.11-ns times.
Clock Generation
controller clocking scheme maintains consistent robust highfrequency operation. Altera SRAM controller reference design uses dedicated input clock (inclk). This input clock feeds four general-purpose PLLs APEX device. This boosts input clock de-skews internal external clocks SRAM controller interface.
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Post-Route Performance
post-route performance results SRAM controller shown Tables Table Post-Route Performance Device
EP2A15F672C7
Note (ns)
3.525
Internal fMAX (MHz)
(ns)
1.11
Throughput (Mbytes second)
Total Logic Elements (LEs)
Table Data Byte Timing Byte
DQ[7.0] BW_N[0] DQ[15.8] BW_N[1] DQ[23.16] BW_N[2] DQ[31.24] BW_N[3]
Note (ns)
3.525 1.58 3.525 1.58 3.525 1.58 3.525 1.58 1.11 1.11 1.11
(ns)
1.11
Note Tables Timing numbers preliminary were calculated using Quartus software version service pack These timing numbers were calculated using circuit with phase shift
Contention Analysis
APEX Programmable Logic Device Family Data Sheet states that clock-to-output buffer disable enable delays respectively. Increase delay output logic option Quartus software increase APEX device turn-on time IDT's IDT71V3548S133 133-MHz pipelined SRAM 1.5-ns turn-on time 3.0-ns turn-off time. Using these values, controller performs read followed write operation, there contention because SRAM turn-off time faster than controller turn-on time. write followed read operation, there possibility more than contention (2.1 ns).
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Likewise, IDT71V3557S75 100-MHz flow-through SRAM 3.0-ns turn-on time 5.0-ns turn-off time. Using these values, controller performs read followed write transaction, there will contention (5.0 ns). There contention write followed read operation because turn-off time APEX device faster than turn-on time SRAM.
Getting Started
Altera SRAM controller reference design provides solutions integrating SRAM into your digital system. This section describes install reference design your These instructions assume that:
using with Quartus software version higher) installed default location. familiar with Quartus software. ModelSim software installed your system simulation.
Design Installation
Altera provides SRAM controller reference design compressed files, VHDL Verilog HDL. download either Verilog VHDL version reference design from Altera site http://www.altera.com. install files, perform following steps: Create directory your hard drive save files. Save file, zbt_rd_vhdl_v1.0.0p1.zip, into directory just created. delete this file after finish installation. Decompress contents zbt_rd_vhdl_v1.0.0p1.zip file directory created step
Figure shows directory structure created reference design displays selected VHDL files (Figure shows VHDL design files only; Verilog files have similar functionality).
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Figure SRAM Controller Directory File Structure
Contains documentation file an183.pdf (this document). Contains Quartus files place route. addr_ctrl_out.vhd: address control signal generation circuitry. data_inout.vhd: control signal bidirectional bus. pipe_delay.vhd: delay generation circuitry. pipe_stage.vhd: pipeline stand-alone configuration. zbt_ctrl_top.vhd: controller without PLL. top.vhd: top-level files that instantiate zbt_ctrl_top. top.quartus: Quartus software project file. top.htm: Quartus software report file. simulation modelsim top.vo: gate-level output netlist file. top.sdo: back-annotated Standard Delay Format (SDF) File. sim_lib Contains ModelSim files simulation. zbt_ctrl_top_flow_tb.vhd zbt_ctrl_top_pipe_tb.vhd mt55l64l36f.vhd mt55l64l36p.vhd functional zbt_ctrl_top_pipe_tb.do: pipeline version script. zbt_ctrl_top_flow_tb.do: flowthrough version script.
Compile Simulate Reference Designs
Altera provides reference design source files synthesize, place-androute, simulate design. This section takes through design flow reference design, including compiling synthesizing Quartus software simulating ModelSim software. results each step included reference design; therefore, need perform each step unless have altered design files. example, view simulation results without first compiling design because Quartus software place-and-route results included with reference design. compilation simulation results sim-lib directories, respectively.
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Compile Quartus Software
This section describes compile place-and-route design using Quartus software. directory contains Quartus software version project files, including constraint files needed design meet required clock frequencies timing. Altera provides project files listed Table directory. Table Project File Descriptions File
pll.vhd
Description
instantiation file created Quartus MegaWizard® Plug-In Manager. This file instantiates parameterized altclocklock function, which generates APEX device. This instantiated top-level top.vhd file feeds lower-level modules. Controls input/output functions controller Contains pipeline delay module flowthrough pipelined SRAM Transmits receives signals Instantiates files described above top-level file
addr_ctrl_out.vhd Registers address control bits data_inout.vhd pipe_delay.vhd pipe_stage.vhd top.vhd
compile Altera-provided project files, following steps: Quartus software. Choose Open Project (File menu). Select top.quartus file from <work dir>\lib directory click Open. Choose Compile Mode (Processing menu). Choose Start Compilation (Processing menu).
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Simulate ModelSim Software
sim_lib directory contains testbench file (zbt_ctrl_top_flow_tb.vhd) that instantiates SRAM controller SRAM model (<work dir>\sim_lib\mt55l64l36f.vhd). testbench demonstrates functionality controller first writing into memory then reading from memory comparing data. Because SRAM model behavioral does contain timing information, additional delay added signals from SRAM testbench account board delay clock-to-output time. model different board-delay scenarios changing these delays. Altera provides script (zbt_ctrl_top_flow_tb.do) perform functional simulation ModelSim software. This script creates work library pre-compiles correct simulation libraries functional simulation. also compiles controller source files, model, testbench, displays appropriate waveforms. your files default installation locations, must update script that paths point locations installed reference design Quartus software. following steps perform functional simulation: ModelSim version 5.5c software. Change your working directory <work dir>\sim_lib\functional directory. Type following commands Command window: zbt_ctrl_top_flow_tb.do
Conclusion
SRAM addresses need high-throughput, low-latency static memory useful designs with many successive read write transactions. transition latency minimized because SRAM does require turnaround cycles between reads writes. Altera APEX devices support SRAM system frequency MHz. APEX device buffers further enhanced programmable delay logic option minimize contention during read write transitions device. Altera SRAM controller reference design ready-to-use memory controller that interfaces APEX devices with SRAM device MHz.
Altera Corporation
183: SRAM Controller Reference Design APEX Devices
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com
Printed Recycled Paper.
Copyright 2001 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services
Altera Corporation

APEX Devices December 2001, ver. Application Note communicat

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