APEXII devices, enhanced embedded system blocks (ESBs) support memory

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APEXII devices, enhanced embedded system blocks (ESBs) support memory

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Designing with ESBs APEX Devices
APEXII devices, enhanced embedded system blocks (ESBs) support memory structures, such single-port dual-port RAM. Additionally, APEX devices, ESBs support bidirectional dual-port RAM. this mode, each ports that allow different read write operations simultaneously. APEX devices, split into separate single-port blocks. This application note explains basic operation APEX ESB, implement different memory configurations ESBs, some applications using ESBs, initialization file Altera Quartus® software. This application note also includes timing diagram each memory configuration type.
Memory Configurations Features
This application note discusses following memory configurations:
single-port dual-port dual-port+ (bidirectional dual-port RAM) FIFO
Single-Port Configuration
single-port configuration shown Figure following features:
Uses port that supports either read write. Read during write always uses same address reading writing. only uses write clock. result, output depends synchronous write cycle time, which slower than read cycle time. Therefore, read cycle runs slower frequency compared dual-port configuration. Data widths definable bits input output buses. Registered inputs outputs each have clock, clock enable, clear ports.
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A-AN-179-1.0 A-AN 179-1.0
179: Designing with ESBs APEX Devices
Figure Single-Port Memory Configuration
Partitioning into separate 2K-bit single-port blocks increases total number memory blocks device. Each block read write port, maximum data-width 8-bits. configurations 1024 2048 Figure divisions must have same configuration.
Figure Single-Port Partitioned
Dual-Port Configuration
dual-port configuration shown Figure following features:
simultaneously read write data. supports variable-width data ports reading writing RAM. example, written 1-bit mode port while being read 16-bit mode from port Table lists supported variable width configurations dual-port mode. read write address ports have independent clock, clock enable, clear ports. Uses both read write clock. When performing synchronous read writes, read cycle time faster than write cycle time. output depends read cycle time, performance higher than single-port configuration, which depends write cycle time.
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Figure Dual-Port Memory Configuration
Table Variable Width Configuration Dual-Port Read Port Width
bits, bits, bits, bits
Write Port Width
bits, bits, bits, bits
Bidirectional Dual-Port Configuration
bidirectional dual-port configuration shown Figure following features:
independent ports, port port simultaneously perform reads, writes, read write Data width definable bits Independent clock, clock enable, clear signals port port
Figure Bidirectional Dual-Port Configuration
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FIFO Buffer Configuration
FIFO buffer configuration shown Figures following features:
Data transferred between design subsystems uses FIFO memory buffers. instance, FIFO buffers hold data that driven from multiple sources shared bus. When busy, FIFO buffer stores data; when busy, FIFO buffer sends data bus. implement single- dual-clock FIFO buffer data between systems communicating same different clock frequencies.
Figure Single Clock FIFO
Figure Dual Clock FIFO
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Configuration
configuration shown Figure following features:
memory contents written during configuration before device enters user mode. Allows registered bypassed outputs. read operation identical single-port RAM.
Figure Memory Configuration
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Read/Write Combinations
separate ports: Different modes different combination these ports. Table shows read/write width/depth different memory modes ESB. These events occur within clock cycle. Table Read/Write Width/Depth Combinations APEX Mode
Bidirectional Dual-port
Port
read read write write
Port
read write read write read write
Size
4096 1024 4096 1024
Dual-port
write read
Single-port
read/write
4096 1024 2048
Single-port (packed mode)
write/read
read/write
read
4096 1024 4096 1024
FIFO
read
write
Note Table
Supports mismatch input/output data widths. Packed mode when split into single-port memory blocks.
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Using MegaWizard Implement Memory Configurations
This section describes MegaWizard Quartus software implement memory configurations through megafunctions:
LPM_RAM_DQ LPM_RAM_DP LPM_RAM_DP+ LPM_FIFO LPM_ROM
Selecting Megafunction Customize
Select customize megafunction design using MegaWizard Plug-In Manager. following steps select instance megafunction using Quartus software: Select MegaWizard Plug-In Manager (Tools menu). Turn Create custom megafunction variation option. Figure Click Next.
Figure MegaWizard Plug-In Manager [page
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Choose megafunction from storage folder Available Megafunction list. Figure
Figure MegaWizard Plug-In Manager [page
Turn type output file create: AHDL, VHDL, Verilog. Type file name function. Click Next.
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LPM_RAM_DQ Megafunction
LPM_RAM_DQ single-port function shown Figure following features:
Implements either synchronous asynchronous single-port inclock register data and/or address inputs separate outclock register output data LE-based ESB-based
Synchronous write operations into memory block address[] data[] ports, triggered rising edge inclock while write enable (we) port enabled. outclock port read operation optional. asynchronous operations, setup hold times have valid with respect both edges write enable signal (we). data address lines should change while active. Figure Single-Port Block Diagram
Instantiating LPM_RAM_DQ Megafunction Design
following steps create instance lpm_ram_dq function: Follow instructions "Selecting Megafunction Customize" section, choosing lpm_ram_dq from storage folder Available Megafunction list. Choose data output address widths using wide should output wide should `address' input lists. Figure change made automatically reflected symbol graphic.
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Turn options ports register Which ports should registered? section. registered, inclock clocks data address ports; while outclock clocks output port. Figure
Figure MegaWizard Plug-In Manager LPM_RAM_DQ [page
Turn Yes, this file memory content data option initialize memory block with hexadecimal (Intel-format) file (.hex) memory initialization file (.mif) file. Figure Turn leave blank option initialize memory block zero. Figure
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Figure MegaWizard Plug-In Manager LPM_RAM_DQ [page
Click Finish complete procedure. Figure
Figure MegaWizard Plug-In Manager LPM_RAM_DQ [page Summary
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LPM_RAM_DP Megafunction
LPM_RAM_DP dual-port function shown Figure following features:
Fully parameterized function Allows simultaneous read write access memory cells register combination EAB/ESB inputs LE-based EAB/ESB-based Four clocking modes Single clock Shared clock Separate clock Asynchronous
Clocking Modes
lpm_ram_dp four modes: single clock, shared clock, separate clock, asynchronous. clocking method section MegaWizard Plug-in Manager interface select different modes. Single Clock single clock mode, read write operations synchronous same clock. Shared Clock shared clock mode, addition having read write operations synchronous same clock, separate clock used output port, q[]. This also referred having separate input output clocks. Separate Clock separate clock mode, there independent clocks, rdclock wrclock, read write operations, respectively (See Figure 14). Asynchronous asynchronous mode requires clock. write operation dependent wren signal. read operation dependent rden signal. present, rden default.
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Figure Dual-Port Block Diagram
Instantiating LPM_RAM_DP Megafunction Design
following steps create instance lpm_ram_dp function: Follow instructions "Selecting Megafunction Customize" section, choosing lpm_ram_dp from storage folder Available Megafunction list. Figure Choose data output address widths using wide should output wide should `address' input lists. change made automatically reflected symbol graphic. Turn clocking method Which clocking method want use? section. Optionally, turn Create `rden' read enable signal option. rden signal tied (active), signal created. Figure
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Figure MegaWizard Plug-In Manager Dual-Port [page
Turn options Which ports should registered?. Click More Options. register ports individually. Figure page Optionally, turn Create clock enable signal each clock signal. using dual clocks, there separate clock enable signals. Create `aclr' asynchronous clear registered ports option unavailable. order enable this option altdpram function.
Click Next.
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Figure MegaWizard Plug-In Manager Dual-Port [page
Turn Yes, this file memory content data option initialize memory block with hexadecimal (Intel-format) file (.hex) memory initialization file (.mif) file. Figure Turn leave blank option initialize memory block zero.
Click Next summary files that MegaWizard creates. Click Finish complete process.
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Figure MegaWizard Plug-In Manager Dual-Port [page
LPM_RAM_DP+ (Bidirectional Dual-Port RAM) Megafunction
LPM_RAM_DP+ bidirectional dual-port function following features:
Fully parameterized function Capable simultaneous read write access memory cells Capable registering combination inputs LE-based ESB-based Three clocking modes Single clock Separate clock Asynchronous
Clocking Modes
clocking method section MegaWizard Plug-in Manager interface select three LPM_RAM_DP+ clocking modes. three clock modes follows: Single Clock single clock mode, read write operations synchronous same clock.
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Separate Clock separate clock mode, there independent clocks, clock_a clock_b port port respectively. Asynchronous asynchronous mode requires clock. write operation dependent wren signal, read operation independent wren continuous regardless write operation.
Instantiating Bidirectional Dual Port Design
following steps create instance lpm_ram_dp+ function: Follow instructions "Selecting Megafunction Customize" section, choosing lpm_ram_dp+ from storage folder Available Megafunction list. Select APEX device family from Create which device family? list. Turn With read/write ports option will using dual port ram? section. This option bidirectional dual port configuration. Turn either memory size option number words number bits want specify memory size? section. Figure Click Next.
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Figure MegaWizard Plug-In Manager Dual-Port [page
Select many words memory?. Figure Select width output port from Read/Write Ports section. Click Next.
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Figure MegaWizard Plug-In Manager Dual-Port [page
Turn Single clock option clocking method Which clocking method want use? section. using asynchronous mode, turn Clock. Figure
Click Next.
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Figure MegaWizard Plug-In Manager Dual-Port [page
Check Write input ports Read output ports registered. Figure Click More Options. Turn required options Port Registers dialog box.
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Figure MegaWizard Plug-In Manager Dual-Port [page
Turn Yes, this file memory content data option initialize memory block with hexadecimal (Intel-format) file (.hex) memory initialization file (.mif) file. Figure Turn leave blank option initialize memory block zeros. Click Next summary files that MegaWizard creates. Click Finish complete process.
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Figure MegaWizard Plug-In Manager Dual-port [page
LPM_FIFO+ Megafunction
LPM_FIFO+ single- dual-clock FIFO megafunction with following features:
Fully parameterized function Single- dual-clock modes Simultaneous reads writes Full, empty, used words output signals Fully optimized Altera architecture LE-based EAB/ESB-based
lpm_fifo+ function parameterized, single dual clock FIFO megafunction that used buffer data between systems communicating same different clock frequencies. lpm_fifo+ function actually functions single clock FIFO (lpm_fifo) dual clock FIFO (lpm_fifo_dc). Select which FIFO megafunction create MegaWizard PlugIn Manager interface.
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Single Clock Mode
single clock mode, lpm_fifo+ megafunction instantiates scfifo megafunction single clock FIFO functions. megafunction single clock port writing reading data from FIFO. Simultaneous reads writes done same clock cycle. parameterization lpm_fifo+ megafunction implement width/depth combination. function also customizable output signals, such empty/full flags number used words outputs. also gives choice asynchronous synchronous clear signal. Either ESBs implement megafunction. However, implementing large FIFO dramatically increase overall use.
Dual Clock Mode
dual clock mode, lpm_fifo+ megafunction instantiates dcfifo megafunction dual-clock FIFO functions. megafunction independent clock ports used writing reading data from FIFO buffer. Simultaneous reads writes done same clock cycle. parameterization lpm_fifo+ megafunction implement width/depth combination. function also customizable output signals, such empty/full flags number used words outputs, that synchronized either read write clock. last three words dcfifo available writing because synchronization pipelines between clock domains. These pipelines intended avoid internal metastability. Because these pipelines, information available clock domain regarding when read write conditions occur temporarily unavailable other clock. wrfull rdfull ports lpm_fifo+ megafunction must high slightly before dcfifo completely full, order avoid overshooting FIFO. This process cause several words FIFO become unavailable. Depending write rate FIFO, wrfull rdfull ports high with three words remaining, with words remaining, with word remaining FIFO. However, this process necessary both accommodate clock synchronization ensure overflow does take place. maintain specific number words, specify number LPM_NUMWORDS parameter that three words greater than amount needed.
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synchronization internal logic dcfifo delay information wrempty, wrfull, wrusedw[], rdempty, rdfull, rdusedw[] ports clock cycle latency. Setup hold violations synchronization registers during timing analysis occur rdclock wrclock signals unrelated. This normal behavior multi-clock designs.
Common Both Dual Single Clock Modes
read-request port lpm_fifo+ megafunction configuration modes: legacy synchronous FIFO show-ahead synchronous FIFO. These modes configure read-request port either read request read acknowledge. default read request (legacy) mode, requested data comes FIFO first clock cycle after read request asserted. read acknowledge (show-ahead) mode, first piece data written into FIFO immediately shows output reads from FIFO acknowledged instead requested (See Figure 23). Figure FIFO
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Instantiating LPM_FIFO+ Megafunction Design
This section list steps needed create instance lpm_fifo+ megafunction single-clock dual-clock mode.
Single-Clock FIFO
following steps create instance lpm_fifo+ megafunction single-clock mode: Follow instructions "Selecting Megafunction Customize" section, choosing lpm_fifo+ from storage folder Available Megafunction list. Select number bits wide should FIFO number words deep should FIFO be?. Figure Turn Yes, synchronize both reading writing `clock' option. Click Next.
Figure MegaWizard Plug-In Manager LPM_FIFO [page
Turn desired options Which optional output control signals want? section. Figure Click Next.
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Figure MegaWizard Plug-In Manager LPM_FIFO [page
Turn which rdreq signal mode (legacy synchronous showahead synchronous) Which kind read access want with `rdreq' signal? section. Figure Click Next.
Figure MegaWizard Plug-In Manager LPM_FIFO [page
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Turn Quartus software optimization (default, speed, area) with megafunction Which type optimization want? section.
Optionally, turn Disable overflow checking and/or Disable underflow checking disable circuitry protection. Optionally, turn Implement FIFO function with logic cells only, even device contains EABs ESBs compiler option. default place FIFO ESBs. Figure Click Next summary files that MegaWizard creates. Click Finish complete process. Figure MegaWizard Plug-In Manager LPM_FIFO [page
Dual-Clock FIFO
following steps create instance lpm_fifo megafunction dual-clock mode: Follow instructions "Selecting Megafunction Customize" section, choosing lpm_fifo from storage folder Available Megafunction list.
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Select number bits wide should FIFO number words deep should FIFO be?. Turn synchronize reading writing `rdclock' `wrclock', respectively". Figure Turn option latency option latency want FIFO pipeline output flags? section. Click Next.
Figure MegaWizard Plug-In Manager LPM_FIFO [page
Turn required read-side write-side Which optional output control signals want? options. Each full, empty usedw[] signals synchronized either read write clock. Figure required, turn Asynchronous clear. Figure Click Next.
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Figure MegaWizard Plug-In Manager LPM_FIFO [page
Turn which rdreq signal mode (legacy synchronous showahead synchronous) Which kind read access want with `rdreq' signal? section. Figure
Click Next. Figure MegaWizard Plug-In Manager LPM_FIFO [page
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Turn desired optimization type Which type optimization want? section. Optionally, turn whether want disable overflow underflow checking Would like disable circuitry protection? section. Optionally, turn Implement FIFO function with logic cells only, even device contains EABs ESBs compiler option. default place FIFO ESBs. Figure Figure MegaWizard Plug-In Manager LPM_FIFO [page
Click Next summary files that MegaWizard creates. Click Finish complete process.
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LPM_ROM Megafunction
LPM_ROM function that following features:
Fully parameterized function Supports synchronous asynchronous memory modes Allows control address input output with separate clocks Fully optimized Altera architecture
parameterized lpm_rom function implement functions. implement these functions APEX devices. lpm_rom megafunction supports both synchronous asynchronous modes operation. address[] input port and/or output port registered controlled inclock outclock, inputs respectively. Totally asynchronous memory operations occur when both inclock outclock ports unused. Further, lpm_rom megafunction provides optional memory enable signal memenab port. When memory enabled (memenab low), output high-impedance (See Figure 32). lpm_rom must have memory initialization file (.mif) hexadecimal (.hex) file with same name project directory that contains data written during configuration. more information creating these files "Initialization Files" page
Figure Block Diagram
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Instantiating LPM_ROM Megafunction Design
following steps create instance lpm_rom megafunction single-clock mode: Follow instructions "Selecting Megafunction Customize" section, choosing lpm_rom from storage folder Available Megafunction list. Specify size selecting number bits wide should output section number bits wide should `address' input section. synchronous implementation, Which ports should registered? section, turn `address' input port option and/or output port option. Figure Click Next.
Figure MegaWizard Plug-In Manager LPM_ROM [page
initialize memory block with hexadecimal (Intel-format) file (.hex) memory initialization file (.mif) file, browse file location What name file containing memory initialization data? section. Figure
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Click Next summary files that MegaWizard creates. Click Finish complete process.
Figure MegaWizard Plug-In Manager LPM_ROM [page
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Timing Diagrams
Figures show timing diagram different modes, such single-port, dual-port, bidirectional dual-port ROM.
Single-Port
Synchronous write operations into memory block uses address[] data[] port, triggered rising edge inclock while write enable (we) port enabled. outclock port read operation optional. largest usage dual-port RAMs communications, which includes exchange data between processors systems. Figures show synchronous asynchronous timing diagrams single-port RAM. Figure Synchronous Read/Write Cycle Timing Single-Port (Unregistered Output))
Figure Synchronous Read/Write Block Diagram Single-Port (Unregistered Output)
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Figure Synchronous Read/Write Cycle Timing Single-Port (Registered Output)
Figure Synchronous Read/Write Block Diagram Single-Port (Registered Output)
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Figure Asynchronous Read/Write Cycle Timing Single-Port Note
Note Figure
asynchronous mode, when (write enable) asserted, address cannot change.
Figure Asynchronous Read/Write Block Diagram Single-Port
Dual-Port
Figures show dual-port read/write configurations timing diagrams.
Read/Write
following situations occur when simultaneously reading writing same address dual-port RAM:
Unregistered output port read clock's frequency greater than write clock's frequency. write clock written data this point; therefore, data value read.
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Dual-port uses same clock reading writing. newly written data appears output after delay tESBDD after falling edge clock. slower clock frequencies, data value appear shortly after rising edge clock followed newly written data, which appears tESBDD nanoseconds after falling edge.
Check data sheet value tESBDD timing model section.
Registered output port read clock very fast (frequency 1/tEABDD). output reads data value. Dual-port uses same clock reading writing. output reads newly written data value. read write clocks unrelated, read clock frequency less than 1/tEABDD. output reads newly written data value.
Figure Dual-Port Read/Write Cycle Timing Single Clock Mode (Unregistered Output)
Note Figure
read write operations targeting same memory location, newly written data will available output port falling edge clock.
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When read occurs same address location with write operations progress (write completed), there possibility having unknown output from ESB. prevent this potential contention, read operation should start until write operation completed. this occur, read operation should activated minimum amount time specified maximum write cycle time ESB. This parameter tESBSRC specified data sheet timing model section each device.
Figure Dual-Port Read/Write Block Diagram Single Clock Mode (Unregistered Output)
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Figure Dual-Port Read/Write Cycle Timing Single Clock Mode (Registered Output)
Figure Dual-Port Read/Write Block Diagram Single Clock Mode (Registered Output)
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Figure Dual-Port Read/Write Cycle Timing Shared Clock Mode (Registered Output)
Notes Figure
both read write operations targeting same memory location, present read cycle will result data that previously written into that memory location. newly written data only present next read cycle. rden deasserted that newly written data into valid output port q[]. data memory location driven output port because next read cycle retrieving data from previous memory location
Figure Dual-Port Read/Write Block Diagram Shared Clock Mode (Registered Output)
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Figure Dual-Port Read/Write Cycle Timing Separate Clock Mode (Registered Output)
Note Figure
During this simultaneous read/write operation data written memory location falling edge wrclock. Since output port registered, this newly written data, available output port only during next rdclock cycle.
Figure Dual-Port Read/Write Block Diagram Separate Clock Mode (Registered Output)
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Figure Dual-Port Read/Write Cycle Timing Separate Clock Mode (Unregistered Output)
Note Figure
Since output port unregistered, newly written data memory location available falling edge wrclock.
Figure Dual-Port Read/Write Block Diagram Separate Clock Mode (Unregistered Output)
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Figure Dual-Port Read/Write Cycle Timing Asynchronous Clock Mode Note
Note Figure
asynchronous mode, when (write enable) asserted, address cannot changed.
Figure Dual-Port Read/Write Block Diagram Asynchronous Clock Mode
Bidirectional Dual-Port
Figures show bidirectional dual-port read write operations both ports
Read/ Write
bidirectional dual-port RAM, each port read write. result, port port write same time, read same time, read write alternately. might happen that both ports write same address location same time, which causes invalid data. prevent this potential write contention, make sure that writes occur same address simultaneously.
Single Clock Mode
Only clock used input, output, write, read signals. output available clock cycle later because inputs outputs registered.
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Figure Bidirectional Dual-Port Write Read Cycle TIming Single Clock Mode (Inputs Outputs Registered)
Figure Bidirectional Dual-Port Write Read Block Diagram Single Clock Mode (Inputs Outputs Registered)
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Figure Bidirectional Dual-Port Write Read Cycle Timing Single Clock Mode (Only Inputs Registered)
Figure Bidirectional Dual-Port Write Read Single Clock Mode (Only Inputs Registered)
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Double Clock Mode
Each port have separate clock. same clock performs writes reads each port. Figures Figure Bidirectional Dual-Port Write Read Cycle Timing Dual Clock Mode (Inputs Outputs Registered)
Figure Bidirectional Dual-Port Write Read Block Diagram Dual Clock Mode (Inputs Outputs Registered)
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Asynchronous Bidirectional Dual-Port
Figures show asynchronous bidirectional dual-port timing diagram. Figure Asynchronous Bidirectional Dual-Port Cycle Timing with Simultaneous Write Read Ports
Notes Figure
Data written into address Output port reads data Write enable port should high write read from memory should stay during address transition.
Figure Asynchronous Bidirectional Dual-Port Block Diagram with Simultaneous Write Read Ports
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FIFO
Figures show read/write cycle single double clock FIFO. Figure Single-Clock FIFO: Write, Empty Flag, Simultaneous Read/Write Cycle Waveform (Legacy Synchronous FIFO Mode)
Figure Single-Clock FIFO Full Flag Waveform (Legacy Synchronous FIFO Mode)
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Figure Single-Clock FIFO Full Flag Waveform (Legacy Synchronous FIFO Mode)
Figure Single-Clock FIFO: Read Cycle Empty Flag (Legacy Synchronous FIFO Mode)
Note Figure
There clock cycles latency rdempty flag. This number changed changing delay parameters listed earlier.
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Figure Dual-Clock FIFO Read Cycle Waveform (Legacy Synchronous FIFO Mode)
Note Figure
There clock cycles from first rdclock edge after data written when data available read. This number changed changing delay parameters. Also, note that rdempty flag went high after second read done (reading This relationship between read write frequencies.
Figure Dual-Clock FIFO Full Flag Waveform (Legacy Synchronous FIFO Mode)
Note Figure
this case, FIFO words deep. Note that when 31st word written into FIFO, wfull flag goes high. explanation, please "Dual Clock Mode" page
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Figure Dual-Clock FIFO Read-Acknowledge Waveform (Show-Ahead Mode)
Note Figure
first piece data that written into FIFO flows through output next clock edge rdclock. this type FIFO, read acknowledged requested. Therefore, even though data port after second read done, still been read.
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Figures show operation lpm_rom function following modes
Asynchronous Synchronous with output registered Synchronous with address[] ports registered
Figure Read Timing During Asynchronous Memory Operation
Note: Figure
During this asynchronous memory operation, data output changes after certain delay following change address[] input. file used this function specifies data locations FFFF 3333, respectively.
Figure Read Timing During Asynchronous Memory Operation
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Figure Read Timing With Registered Output
Note: Figure
When output port registered, output register loaded with contents memory location pointed address[] every rising edge outclock.
Figure Read Timing With Registered Output
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Figure Read Timing With Registered address[] Input Output Using Same Clock
Note Figure
memenab port tri-states output when logic level. Although, memenab port does affect address[] input from being registered. After memenab logic high level, output register captures data from location pointed registered address[] input.
Figure Read Timing With Registered address[] Input Output Using Same Clock
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Initialization Files
memory initialization file (MIF) hexadecimal file (HEX) specifies initial value each memory address.
Memory Initialization File
ASCII text file with extension .mif specifies initial content memory block. These initial values each address .mif file used during project compilation and/or simulation. Memory Editor Quartus software create .mif files. Each memory block requires separate .mif file. must also specify memory depth width values. Optionally, specify radixes used display interpret addresses data values. multiple values specified same address, only last value used.
Figure shows sample .mif file. Figure Sample File DEPTH WIDTH ADDRESS_RADIX HEX; DATA_RADIX HEX;
Memory depth width required. Enter decimal number. Address value radixes required. Enter BIN, DEC, HEX, OCT, unless otherwise specified, radixes HEX.
Specify values addresses, which single address range. CONTENT BEGINS [0.F] 3FFFF;
Range-Every address from 3FFFF. Single address. Address Range starting from specific address. Addr[8] Addr[9] Addr[A]
(Intel-Format) File
Quartus software ASCII text file with extension .hex Intel-format store configuration data more Altera devices, store initial memory values memory block implemented Altera device, build software project executables.
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file used input file memory initialization Compiler Simulator. Memory Editor create File. Software mode file output file. software application built File.
Creating File
create (.mif) (.hex): Choose (File menu). dialog box, click Other Files tab. create MIF, select Memory Initialization File create File, select Hexadecimal File. Click Number Words Word Size dialog box, type number words Number words box. Word size box, type size words. Click
Figure shows sample table.
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Figure 8-bit Table
Applications Memory
APEX memory configurations suitable variety applications. following paragraphs suggest possible applications different memory configurations.
Configurations
memory used communication between systems. these applications, partitioned into virtual data-storage areas, buffers, usually storing least data packets. buffers shared between communications controller intelligent host that assembles packets stores them-usually microprocessor. system contains only processor, data buffers shared system needs neither virtual physical dual-port RAM.
Single-Port
Single-port used applications that require parallel data transfer because write read ports same width.
Dual-Port Configuration
Dual-port applications general areas wide area networks, storage networks, wireless infrastructures. Some specific applications switches routes, RAID directors, host adapters, cellular base stations. Dual-port used applications that require parallel data transfer, because independent clock ports allow different access rates read write operations. Also, presence dual-addressing enables simultaneous read write operations same clock cycle.
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Width Mismatch simple dual-port used APEX devices read write width mismatch since cells have independent read write ports. This feature used serialization deserialization some high-speed applications that blocks. Because speed some signals high used internal logic, they need slowed down. Deserializing serialized incoming signals method used slow down signals. ESB's dual-port feature perform deserialization serialization because supports mismatched width configuration ports.
Bidirectional Dual-Port
Because bidirectional dual-port read write simultaneously both ports, used applications that require quick data access, such switches routers.
Configuration
used implement functions that only need perform read operations.
FIFO Configuration
Using FIFO increase data throughput interface while minimizing central processing unit (CPU) wait states. FIFO buffers transfer data between host peripheral systems. Some common applications using FIFO buffers SCSI integrated drive electronics (IDE) interfaces, bus-width conversion applications (e.g., 8-bit 32-bit conversions), asynchronous transfer mode (ATM) network interface cards.
Conclusion
With bidirectional dual-port becoming desired preferred choice market, ESBs APEX devices have been enhanced accommodate this memory structure. Bidirectional dual-port used different applications where ability access data simultaneously different processes requirement. addition, APEX with enhanced memory structure able divide into identical single-port blocks applications that required more memory blocks.
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179: Designing with ESBs APEX Devices
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APEXII devices, enhanced embedded system blocks (ESBs) support memory

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