16-bit SMBus Port with Interrupt FEATURES 400kHz compatible* 2.3V

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16-bit SMBus Port with Interrupt FEATURES 400kHz compatible* 2.3V

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CAT9555
16-bit SMBus Port with Interrupt FEATURES
400kHz compatible* 2.3V 5.5V operation stand-by current tolerant I/Os pins that default inputs power-up High drive capability Individual configuration Polarity inversion register Active interrupt output Internal power-on reset glitch power-up Noise filter SDA/SCL inputs Cascadable devices Industrial temperature range RoHS-compliant 24-lead SOIC TSSOP,
CAT9555 CMOS device that provides 16-bit parallel input/output port expansion SMBus compatible applications. These expanders provide simple solution applications where additional I/Os needed: sensors, power switches, LEDs, pushbuttons, fans. CAT9555 consists 8-bit Configuration ports (input output), Input, Output Polarity inversion registers, I2C/SMBus-compatible serial interface. sixteen I/Os configured input output writing configuration register. system master invert CAT9555 input data writing active-high polarity inversion register. CAT9555 features active interrupt output which indicates system master that input state changed. three address input pins provide device's extended addressing capability allow eight devices share same bus. fixed part slave address same CAT9554, allowing eight these devices combination connected same bus.
24-pad TQFN packages
APPLICATIONS
White goods (dishwashers, washing machines) Handheld devices (cell phones, PDAs, digital
cameras)
Data Communications (routers, hubs
servers)
Ordering Information details, page
BLOCK DIAGRAM
8-BIT INPUT/ OUTPUT PORTS I/O1.0 I/O1.1 I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7 I2C/SMBUS CONTROL I/O0.0 I/O0.1 INPUT FILTER 8-BIT INPUT/ OUTPUT PORTS I/O0.2 I/O0.3 I/O0.4 I/O0.5 I/O0.6 I/O0.7 POWER-ON RESET VINT FILTER
WRITE pulse READ pulse
WRITE pulse READ pulse
NOTE: I/Os INPUTS RESET
Catalyst Semiconductor licensed Philips Corporation carry Protocol.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-8551, Rev.
CAT9555
CONFIGURATION SOIC TSSOP
I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 I/O0.6 I/O0.7 I/O1.7 I/O1.6 I/O1.5 I/O1.4 I/O1.3 I/O1.2 I/O1.1 I/O1.0
TQFN (HV6)
I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5
I/O1.0 I/O1.2 I/O1.1 I/O0.6 I/O0.7
I/O1.7 I/O1.6 I/O1.5 I/O1.4 I/O1.3
View
SOIC TSSOP 4-11 13-20 TQFN 10-17 NAME I/O0.0 I/O0.7 I/O1.0 I/O1.7 FUNCTION Interrupt Output (open drain) Address Input Address Input Port Port Ground Port Port Address Input Serial Clock Serial Data Power Supply
Doc. MD-8551, Rev.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT9555
ABSOLUTE MAXIMUM RATINGS(1)
with Respect Ground -0.5V +6.5V Voltage with Respect Ground -0.5V +5.5V Current I/O0 I/O7 Input Current Supply Current 160mA Supply Current 200mA Package Power Dissipation Capability 25°C) 1.0W Junction Temperature +150°C Storage Temperature -65°C +150°C
RELIABILITY CHARACTERISTICS
Symbol VZAP(2) ILTH(2) Parameter Susceptibility Latch-up Reference Test Method JEDEC Standard JESD22 JEDEC JESD78A 2000 Units Volts
Notes: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability. This parameter tested initially after design process change that affects parameter.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-8551, Rev.
CAT9555
D.C. OPERATING CHARACTERISTICS
-40°C +85°C, unless otherwise specified
Symbol Supplies Istbl Istbh VPOR Supply voltage Supply current Standby current Standby current Power-on reset voltage Operating mode; load; fSCL Standby mode; load; VSS; fSCL kHz; inputs Standby mode; load; VCC; fSCL kHz; inputs load; 0.75 1.65 Parameter Conditions Unit
SCL, SDA, VIL(1) VIH(1) I/Os level input voltage High level input voltage level output current High level output voltage 4.75 4.75 Input leakage current Input leakage current Input capacitance Output capacitance -100 -0.5 level input voltage High level input voltage Input leakage current -0.5 level input voltage High level input voltage level output current Leakage current Input capacitance Output capacitance 0.4V -0.5
Notes: reference values only tested. This parameter characterized initially after design process change that affects parameter. 100% tested. Each I/Os must externally limited maximum each octal (I/O0.0 I/O0.7 I/O1.0 I/O1.7) must limited maximum current device total total current sourced I/Os must limited
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2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT9555
A.C. CHARACTERISTICS
2.3V 5.5V, -40°C +85°C, unless otherwise specified (Note
Symbol fSCL tLOW tHIGH
Parameter Clock Frequency Input Filter Spike Suppression (SDA, SCL) Clock Period Clock High Period Rise Time Fall Time Start Condition Hold Time Start Condition Setup Time (for Repeated Start) Data Input Hold Time Data Setup Time Stop Condition Setup Time Data Valid Data Hold Time Time must Free Before Transmission Start
Units
tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF
Port Timing Output Data Valid Input Data Setup Time Input Data Hold Time
Interrupt Timing Interrupt Valid Interrupt Reset
Notes: Test conditions according Test Conditions" table. This parameter characterized initially after design process change that affects parameter. 100% tested.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-8551, Rev.
CAT9555
TEST CONDITIONS
Input Rise Fall time CMOS Input Voltages CMOS Input Reference Voltages Output Reference Voltages Output Load: SDA, Output Load: I/Os 10ns 0.2VCC 0.8VCC 0.3VCC 0.7VCC 0.5VCC Current Souce 3mA; 100pF Current Source: IOL/IOH 10mA; 50pF
tLOW tSU:STA tHD:STA
tHIGH tLOW
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Figure 2-Wire Serial Interface Timing
Doc. MD-8551, Rev.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT9555
SCL: Serial Clock serial clock input clocks data transferred into device. line requires pull-up resistor driven open drain output. SDA: Serial Data/Address bidirectional serial data/address used transfer data into device. open drain output wire-ORed with other open drain open collector outputs. pull-up resistor must connected from line VCC. value pull-up resistor, calculated based minimum maximum values from Figure Figure (see Note).
Device Address Inputs These inputs used extended addressing capability. pins should hardwired VSS. When hardwired, eight CAT9555s addressed single system. levels these inputs compared with corresponding bits, from slave address byte. 0.7, 1.7: Input Output Ports these pins configured input output. simplified schematic I/Os shown Figure When configured input, output transistors creating high impedance input with weak pull-up resistor (typical kohm). configured output, push-pull output stage enabled. Care should taken external voltage applied configured output impedance paths that exist between either VSS.
8.00
(Kohm)
(Kohm)
7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00
CBUS (pF)
Figure Minimum Function Supply Voltage (IOL max)
Figure Maximum Value versus Capacitance (Fast Mode 300ns)
Note: According Fast Mode specification, capacitance 200pF, pull device resistor. loads between 200pF 400pF, pull-up device current source (Imax 3mA) switched resistor circuit.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
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CAT9555
INT: Interrupt Output open-drain interrupt output activated when port pins configured input changes state (differs from corresponding input port register state). interrupt deactivated when input returns previous state input port register read. Since there 8-bit ports that read independently, interrupt caused Port will cleared read Port vice versa. Changing from output input cause false interrupt state does match contents input port register.
Data from Shift Register Data from Shift Register
Configuration Register
Output Port Register Data
Write Configuration Pulse
Write Pulse
Input Port Register Output Port Register
Input Port Register Data
LATCH
Read Pulse
Data from Shift Register Write Polarity Register
Polarity Register Data
Polarity Inversion Register
Figure Simplified Schematic I/Os
Doc. MD-8551, Rev.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT9555
FUNCTIONAL CAT9555 general purpose input/output (GPIO) peripheral provides sixteen ports, controlled through compatible serial interface CAT9555 supports data transmission protocol. This Inter-Integrated Circuit protocol defines device that sends data transmitter device receiving data receiver. transfer controlled Master device which generates serial clock START STOP conditions access. CAT9555 operates Slave device. Both Master device Slave device operate either transmitter receiver, Master device controls which mode activated. Protocol features protocol defined follows: Data transfer initiated only when busy. During data transfer, data line must remain stable whenever clock line high. changes data line while clock line high will interpreted START STOP condition (Figure
START STOP Conditions START Condition precedes commands device, defined HIGH transition when HIGH. CAT9555 monitors lines will respond until this condition met. HIGH transition when HIGH determines STOP condition. operations must with STOP condition. Device Addressing After Master sends START condition, slave address byte required enable CAT9555 read write operation. four most significant bits slave address fixed binary 0100 (Figure CAT9555 uses next three bits address bits. address bits used select which device accessed from maximum eight devices same bus. These bits must compare their hardwired input pins. following 7-bit slave address that specifies whether read write operation performed. When this "1", read operation initiated, when "0", write operation selected. Following START condition slave address byte, CAT9555 monitors responds with acknowledge line) when address matches transmitted slave address. CAT9555 then performs read write operation depending state bit.
START CONDITION STOP CONDITION
Figure Start/Stop Timing
SLAVE ADDRESS
FIXED
PROGRAMMABLE HARDWARE SELECTABLE
Figure CAT9555 Slave Address
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-8551, Rev.
CAT9555
Acknowledge After successful data transfer, each receiving device required generate acknowledge. acknowledging device pulls down line during ninth clock cycle, signaling that received bits data. line remains stable during HIGH period acknowledge related clock pulse (Figure CAT9555 responds with acknowledge after receiving START condition slave address. device been selected along with write operation, responds with acknowledge after receiving each data byte. When CAT9555 begins READ mode transmits bits data, releases line, monitors line acknowledge. Once receives this acknowledge, CAT9555 will continue transmit data. acknowledge sent Master, device terminates data transmission waits STOP condition. master must then issue stop condition return CAT9555 standby power mode place device known state. Registers Transactions CAT9555 internal registers their address function shown Table Table Register Command Byte
Command (hex) Register
default N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
command byte first byte follow device address byte during write/read transaction. register command byte acts pointer determine which register will written read. input port register read only port. reflects incoming logic levels pins, regardless whether defined input output configuration register. Writes input port register ignored. Table Registers Input Port Registers
default default IO.7 I1.7 IO.6 I1.6 IO.5 I1.5 IO.4 I1.4 IO.3 I1.3 IO.2 I1.2 IO.1 I1.1 IO.0 I1.0
default value determined externally applied logic lavel Table Registers Output Port Registers
default default O0.7 O1.7 O0.6 O1.6 O0.5 O1.5 O0.4 O1.4 O0.3 O1.3 O0.2 O1.2 O0.1 O1.1 O0.0 O1.0
Table Registers Polarity Inversion Registers
N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Input Port
Input Port
default
Output Port Output Port Polarity Inversion Port Polarity Inversion Port Configuration Port Configuration Port
Table Registers Configuration Registers
default default C0.7 C1.7 C0.6 C1.6 C0.5 C1.5 C0.4 C1.4 C0.3 C1.3 C0.2 C1.2 C0.1 C1.1 C0.0 C1.0
RELEASE DELAY (TRANSMITTER) FROM MASTER
RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START SETUP tSU:DAT) DELAY tAA)
Figure Acknowledge Timing
Doc. MD-8551, Rev.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT9555
output port register sets outgoing logic levels ports, defined outputs configuration register. values this register have effect pins defined inputs. Reads from output port register reflect value that flip-flop controlling output, actual value. polarity inversion register allows user invert polarity input port register data. this register ("1") corresponding input port data inverted. polarity inversion register cleared ("0"), original input port polarity retained. configuration register sets directions ports. configuration register enable corresponding port input with high impedance output driver. this register cleared, corresponding port enabled output. power-up, I/Os configured inputs with weak pull-up resistor VCC. Writing Port Registers Data transmitted CAT9555 registers using write mode shown Figure Figure CAT9555 registers configured operate four register pairs: Input Ports, Output Ports, Polarity Inversion Ports Configuration Ports. After sending data register, next data byte will sent other register pair. example, first byte data sent Configuration Port (register next byte will stored Configuration Port (register Each 8-bit register updated independently other registers. Reading Port Registers CAT9555 registers read according timing diagrams shown Figure Figure Data from register, defined command byte, will sent serially line. Data clocked into register failing edge acknowledge clock pulse. After first byte read, additional data bytes read, second read will reflect data from other register pair. example, first read data from Input Port next read data will from Input Port transfer stopped when master will acknowledge data byte received issue STOP condition.
command byte data port DATA acknowledge from slave data port DATA stop condition
slave address
start condition
acknowledge from slave
acknowledge from slave
WRITE PORT DATA FROM PORT DATA FROM PORT DATA VALID
Figure Write Output Port Registers
slave address
command byte
data configuration acknowledge from slave DATA
data configuration DATA
start condition
acknowledge from slave
acknowledge from slave
Figure Write Configuration Registers
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-8551, Rev.
CAT9555
Power-On Reset Operation When power supply applied pin, internal power-on reset pulse holds CAT9555 reset state until reaches VPOR level. this point, reset condition released internal state machine CAT9555 registers initialized their default state.
slave address
acknowledge from slave
acknowledge from slave
slave address
acknowledge from slave
data from lower upper byte register
acknowledge from master
COMMAND BYTE
DATA
this moment master-transmitter becomes master-receiver slave-receiver becomes slave-transmitter
first byte
data from upper lower byte register
DATA
acknowledge from master
NOTE: Transfer stopped time STOP condition.
last byte
Figure Read from Register
I0.x I1.x DATA I0.x DATA I1.x DATA
DATA
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MASTER
READ FROM PORT
DATA INTO PORT
DATA
DATA
DATA
DATA
READ FROM PORT
DATA INTO PORT
DATA
DATA
DATA
NOTE:
Transfer data stopped moment STOP condition. When this occurs, data present latest acknowledge phase valid (output mode). assumed that command byte previously been (read input port register).
Figure Read Input Port Register
Doc. MD-8551, Rev.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT9555
PACKAGE DIMENSIONS 24-LEAD 300MIL WIDE SOIC
SYMBOL
0.10 2.35 0.33 0.23 15.20 10.00 7.40 0.25 0.40
2.49 0.41 0.27 15.40 10.32 7.50 1.27 0.73
0.30 2.65 0.51 0.32 15.60 10.65 7.60 0.75 1.27
24-Lead_SOIC_(300mil).eps
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC Standard MS-013
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-8551, Rev.
CAT9555
24-LEAD TSSOP
DETAIL
GAGE PLANE 0.25 DETAIL
SYMBOL
0.05 0.80 0.19 0.09 7.70 4.30 0.45 0.00
1.20 0.15 1.05 0.30 0.20 7.90 4.50 0.75 8.00
1.00
7.80 6.40 4.40 0.65 0.60 1.00
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC Standard MO-153
Doc. MD-8551, Rev.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT9555
24-PAD TQFN (4X4) (HV6)
INDEX AREA
SYMBOL
0.70 0.00 0.20 3.95 2.40 3.95 2.40 0.30
0.75 0.02 0.20 0.25 4.00 2.50 4.00 2.50 0.50 0.40
0.80 0.05 0.30 4.05 2.60 4.05 2.60 0.50
TQFN_24-Lead_4X4.eps
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC Standard MO-220
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-8551, Rev.
CAT9555
ORDERING INFORMATION
Prefix Optional Company Device 9555 Suffix
Product Number 9555
Temperature Range Industrial (-40°C +85°C)
Tape Reel Tape Reel 1000/Reel SOIC Only 2000/Reel
Package SOIC TSSOP HV6: TQFN
Notes: packages RoHS-compliant (Lead-free, Halogen-free). standard lead finish Matte-Tin. device used above example CAT9555WI-T1 (SOIC, Industrial Temperature, Matte-Tin, Tape Reel). additional package temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Ordering Part Number CAT9555WI CAT9555WI-T1 CAT9555YI CAT9555YI-T2 CAT9555HV6I CAT9555HV6I-T2
Package SOIC SOIC TSSOP TSSOP TQFN TQFN
Lead Finish Matte-Tin Matte-Tin Matte-Tin Matte-Tin Matte-Tin Matte-Tin
Doc. MD-8551, Rev.
2007 Catalyst Semiconductor, Inc. Characteristics subject change without notice
REVISION HISTORY
Date 12/9/2004 1/7/2005 03/11/05 Rev. Reason Advance Information Initial Issue Advance Information Minor changes
Advance Information Edit Features Edit Ordering Information
Initial Release Update Ordering Information: Tape Reel SOIC package Update Figure
09/25/06 03/12/07 06/07/07
Copyrights, Trademarks Patents Trademarks registered trademarks Catalyst Semiconductor include each following: Beyond MemoryTM, EZDimTM, LDDTM, MiniPotand Quad-ModeCatalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products.
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Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
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Publication Revison: Issue date:
MD-8551 06/07/07

16-bit SMBus Port with Interrupt FEATURES 400kHz compatible* 2.3V

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