BH616UV1611 Wide operation voltage 1.65V 3.6V Ultra power consump

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BH616UV1611 Wide operation voltage 1.65V 3.6V Ultra power consump

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Ultra Power/High Speed CMOS SRAM
BH616UV1611
Wide operation voltage 1.65V 3.6V Ultra power consumption 3.6V Operation current 12mA (Max.)at 55ns (Max.) 1MHz Standby current 5.0uA (Typ.) 3.0V/25 1.2V Data retention current 2.5uA(Typ.) 55ns (Max.) VCC=1.65~3.6V 70ns (Max.) VCC=1.65~3.6V
DESCRIPTION
BH616UV1611 high performance, ultra power CMOS Static Random Access Memory organized 1,048,576 bits operates wide range 1.65V 3.6V supply voltage. Advanced CMOS technology circuit techniques provide both high speed power features with typical operating current 1.5mA 1MHz 3.0V/25 maximum access time 55ns 1.65V/85 Easy memory expansion provided active chip enable (CE1), active HIGH chip enable (CE2) active output enable (OE) three-state output drivers. BH616UV1611 automatic power down feature, reducing power consumption significantly when chip deselected. BH616UV1611 made with chips 8Mbit SRAM stacked multi-chip-package. BH616UV1611 available 48-ball package.
High speed access time
Automatic power down when chip deselected Easy expansion with CE1, options Configuration x8/x16 selectable pin. Three state outputs compatible Fully static operation, clock, refresh Data retention supply voltage 1.0V
POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY OPERATING TEMPERATURE
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
TYPE
VCC=1.8V 10MHz fMax.
VCC=3.6V
VCC=1.8V
1MHz
VCC=3.6V 10MHz
fMax.
1MHz
BH616UV1611AI
Industrial
30uA
25uA
12mA
1.5mA
BGA-48-0608
CONFIGURATIONS
DQ14 DQ15 DQ10 DQ11 DQ12 DQ13
BLOCK DIAGRAM
Address Input Buffer
Decoder
1024
Memory Array
1024 16384
16384 DQ15 CE2, Data Input Buffer Data Output Buffer 1024 Column Decoder Control Address Input Buffer Column Write Driver Sense
48-ball view
Brilliance Semiconductor, Inc. reserves right change products specifications without notice.
Detailed product characteristic test report available upon request being accepted.
R0201-BH616UV1611
Revision Jul. 2006
BH616UV1611
DESCRIPTIONS
Name
A0-A19 Address Input Chip Enable Input Chip Enable Input Write Enable Input
Function
These address inputs select 1,048,576
active active HIGH. Both chip enables must active when data read from write device. either chip enable active, device deselected standby power mode. pins will high impedance state when device deselected. write enable input active controls read write operations. With chip selected, when HIGH LOW, output data will present pins; when LOW, data present pins will written into selected memory location.
Output Enable Input
output enable input active LOW. output enable active while chip selected write enable inactive, data will present pins they will enabled. pins will high impendence state when inactive.
Data Byte Control Input DQ0-DQ15 Data Input/Output Ports
Lower byte upper byte data input/output control pins.
bi-directional ports used read data from write data into RAM.
Power Supply
Ground
TRUTH TABLE MODE
Chip De-selected (Power Down)
DQ0~DQ7 DQ8~DQ15 CURRENT
High High High High High DOUT High DOUT High High High High High DOUT DOUT High ICCSB, ICCSB1 ICCSB, ICCSB1 ICCSB, ICCSB1
Output Disabled
Read
Write
NOTES: means VIH; means VIL; means don't care (Must state)
R0201-BH616UV1611
Revision Jul. 2006
BH616UV1611
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG IOUT
OPERATING RANGE
UNITS
PARAMETER
Terminal Voltage with Respect Temperature Under Bias Storage Temperature Power Dissipation Output Current
RATING
-0.5
RANG
Industrial
AMBIENT TEMPERATURE
1.65V 3.6V
4.6V
+125 +150
CAPACITANCE 25OC, 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input Capacitance Input/Output Capacitance
VI/O
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. -2.0V case pulse width less than
This parameter guaranteed 100% tested.
ELECTRICAL CHARACTERISTICS -40OC +85OC)
PARAMETER NAME ICC1 ICCSB ICCSB1 PARAMETER
Power Supply
VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V
TEST CONDITIONS
MIN.
1.65
TYP.(1)
MAX.
VCC+0.3
UNITS
Input Voltage
-0.3
Input High Voltage VCC, VI/O VCC, Output Leakage Current
Input Leakage Current
Max, 0.2mA Max, 2.0mA Min, -0.1mA Min, -1.0mA VIH, 0mA, FMAX
Output Voltage
VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V
-VCC-0.2
Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current
-5.0
VIH, 0mA, 1MHz VIH, VIL, CE1VCC-0.2V CE20.2V, VCC-0.2V 0.2V
Standby Current CMOS
Typical characteristics TA=25 100% tested. Undershoot: -1.0V case pulse width less than Overshoot: VCC+1.0V case pulse width less than FMAX=1/tRC. VCC=3.0V R0201-BH616UV1611
Revision Jul. 2006
BH616UV1611
DATA RETENTION CHARACTERISTICS -40OC +85OC)
SYMBOL ICCDR tCDR PARAMETER
Data Retention Data Retention Current Chip Deselect Data Retention Time Retention Waveform Operation Recovery Time
TEST CONDITIONS
CE1VCC-0.2V CE20.2V, VINVCC-0.2V VIN0.2V CE1VCC-0.2V CE20.2V, VINVCC-0.2V VIN0.2V
VCC=1.2V
MIN.
TYP.
MAX.
UNITS
Typical characteristics TA=25 100% tested. Read Cycle Time.
DATA RETENTION WAVEFORM (CE1 Controlled)
Data Retention Mode
VDR1.0V
tCDR
CE1VCC 0.2V
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
VDR1.0V
tCDR
CE20.2V
TEST CONDITIONS
(Test Load Input/Output Reference) Input Pulse Levels Input Rise Fall Times Input Output Timing Reference Level tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1, tCHZ2, tBDO, tOHZ, tWHZ, Output Load Others 1V/ns 0.5Vcc 5pF+1TTL 30pF+1TTL INPUT PULSES Output
SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST STEADY CHANGE FROM CHANGE FROM DON'T CARE CHANGE PERMITTED DOES APPLY OUTPUTS MUST STEADY WILL CHANGE FROM WILL CHANGE FROM CHANGE STATE UNKNOW CENTER LINE HIGH INPEDANCE "OFF" STATE
Rise Time: 1V/ns
Fall Time: 1V/ns
Including scope capacitance.
R0201-BH616UV1611
Revision Jul. 2006
BH616UV1611
ELECTRICAL CHARACTERISTICS -40OC +85OC) READ CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable Output Valid Chip Select Output Chip Select Output Data Byte Control Output Output Enable Output Chip Deselect Output High Chip Deselect Output High (CE1) (CE2) (CE1) (CE2) (LB, (CE1) (CE2) (LB, CYCLE TIME 55ns MIN. TYP. -MAX. -CYCLE TIME 70ns MIN. TYP. -MAX. -UNITS
tAVAX tAVQX tE1LQV tE2LQV tBLQV tGLQV tE1LQX tE2LQX tBLQX tGLQX tE1HQZ tE2HQZ tBHQZ tGHQZ tAVQX
tACS1 tACS2 tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tBDO tOHZ
Data Byte Control Output High (LB, Output Disable Output High Data Hold from Address Change
SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE (1,2,4) ADDRESS DOUT
R0201-BH616UV1611
Revision Jul. 2006
BH616UV1611
READ CYCLE (1,3,4)
tACS1 tCLZ tACS2(6)
(5,6)
tCHZ(5,
DOUT
READ CYCLE ADDRESS tOLZ tACS1 tCLZ1(5) tCLZ2(5) tCHZ(1,5) tOHZ(5)
tACS2
tCHZ2(2,5)
tBDO
DOUT
NOTES: high read Cycle. Device continuously selected when CE2= VIH. Address valid prior coincident with transition and/or transition high. VIL. Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested.
R0201-BH616UV1611
Revision Jul. 2006
BH616UV1611
ELECTRICAL CHARACTERISTICS -40OC +85OC) WRITE CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Write Cycle Time Address Time Address Valid Write Chip Select Write Data Byte Control Write Write Pulse Width Write Recovery Time Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Disable Output High Write Output Active (CE1, (CE2) (LB, CYCLE TIME 55ns MIN. TYP. -MAX. -CYCLE TIME 70ns MIN. TYP. -MAX. -UNITS
tAVAX tAVWL tAVWH tELWH tBLWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWR1 tWR2 tWHZ tOHZ
SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE ADDRESS
(11)
tWR1(3)
tCW(11)
tWR2(3)
tOHZ(4,10) DOUT
R0201-BH616UV1611
tWP(2)
Revision Jul. 2006
BH616UV1611
WRITE CYCLE (1,6) ADDRESS tCW(11)
tCW(11)
(12)
tWR(3)
tWP(2)
(8,9)
tWHZ(4,10)
DOUT
NOTES: must high during address transitions. internal write time memory defined overlap active low. signals must active initiate write signal terminate write going inactive. data input setup hold timing should referenced second transition edge signal that terminates write. measured from earlier going high going write cycle. During this period, pins output state that input signals opposite phase outputs must applied. transition high transition occurs simultaneously with transitions after transition, output remain high impedance state. continuously VIL). DOUT same phase write data this write cycle. DOUT read data next address. high during this period, pins output state. Then data input signals opposite phase outputs must applied them. 10.Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested. 11.tCW measured from later going going high write.
R0201-BH616UV1611
Revision Jul. 2006
BH616UV1611
ORDERING INFORMATION
BH616UV1611
SPEED 55ns 70ns MATERIAL Normal Green, RoHS Compliant free, RoHS Compliant GRADE
PACKAGE BGA-48-0608
Note: Brilliance Semiconductor Inc. (BSI) assumes responsibility application product circuit described herein. does authorize products critical components application which failure product expected result significant injury death, including life-support systems critical medical instruments.
PACKAGE DIMENSIONS
NOTES: CONTROLLING DIMENSIONS MILLIMETERS. PIN#1 MARKING LASER PRINT. SYMBOL NUMBER SOLDER BALLS.
Max.
BALL PITCH 0.75 5.25 3.75
VIEW
mini-BGA
R0201-BH616UV1611
Revision Jul. 2006
BH616UV1611
Revision History Revision History Initial Production Version Change I-grade operation temperature range from -25OC -40OC Part Number 70ns Change No.E3 from Draft Date 10,2006 May. 2006 Remark Initial
July 2006
R0201-BH616UV1611
Revision Jul. 2006

BH616UV1611 Wide operation voltage 1.65V 3.6V Ultra power consump

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