CMOS Image Sensor Table Performance Parameters (continued) Parame
|
|
|
Top Searches for this datasheet
IBIS4-A-6600 CYII4SM6600AB
CMOS Image Sensor
Table Performance Parameters (continued) Parameter Operating temperature Color Filter Array Packaging Typical Value Mono, Bayer Pattern 68-pins
Description
IBIS4-6600 solid -state CMOS image sensor that integrates functionality complete analog image acquisition, digitizer digital signal processing system single chip. image sensor compromises MPixel resolution with 2210x3002 active pixels. image size fully programmable user-defined windows interest. pixels 3.5-µm pitch. sensor available Monochrome version Bayer (RGB) patterned color filter array. User-programmable column start/stop positions allow windowing down pixel window digital zoom. sampling reduces resolution while maintaining constant field view. analog video output pixel array processed on-chip analog signal pipeline. Double Sampling (DS) eliminates fixed pattern noise. programmable gain offset amplifier maps signal swing input range. 10-bit converts analog data 10-bit digital word stream. sensor uses 3-wire Serial-Parallel (SPI) interface. operates with single 2.5V power supply requires only master clock operation MHz. housed 68-pin ceramic package. This data sheet allows user develop camera system based described timing interfacing.
Features
Table Performance Parameters Parameter Active Pixels Pixel Size Optical format Active Imager Size Shutter Type Maximum Data Rate/Master Clock Frame rate resolution Sensitivity Dynamic Range Full Well Charge Temporal Noise Dark current High Dynamic Range Modes Supply Voltage Power consumption Typical Value 2210 3002 inch 7.74 10.51 Electronic Rolling Shutter MPS/40 (2210 3002) (640 480) resolution V.m2/W.s, 4.83 V/lux.s Full Well Charge e3.37 mV/s Double Slope, Destructive Read (NDR). Analog: 2.5V-3.3V, Digital: 2.5V, I/O: 2.5V mWatt
Applications
Machine vision Biometry Document scanning
Cypress Semiconductor Corporation Document Number: 001-02366 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised January 2007
TABLE CONTENTS
IBIS4-A-6600 CYII4SM6600AB
Features Description Applications Specifications General Specifications Electro-optical specifications Features General Specifications Electrical Specifications Sensor Architecture Operation Floor Plan Pixel Pixel Rate Region Interest (ROI) Read Output Amplifier Analog Digital Converter Subsample Modes Electronic Shutter High Dynamic Range Modes Sequencer Registers Timing diagrams Sequencer Control Signals Basic Frame Line Timing Pixel Output Timing List Packaging Bare Package Drawing Glass Specifications Storage Handling Storage Conditions Handling Soldering Conditions RoHS (lead free) Compliance Ordering Information Disclaimer Document History Page
Document Number: 001-02366 Rev.
Page
LIST FIGURES
IBIS4-A-6600 CYII4SM6600AB
Spectral Response Curve Electro-voltaic Response Curve Floor Plan Pixel Architecture Bayer Alignment Typical Response Curve Filters Floor Plan Pixel Array Output Amplifier Architecture Offset Channels through DAC_RAW DAC_FINE resistor ladder X-subsampling Y-subsampling Pixel Readout Various Subsample Modes Electronic Rolling Shutter Operation Double Slope Response Principle Non-destructive Readout Syncing Y-shift Registers. Interface Relative Timing Control Signals Basic Frame Line Timing Pixel Output Timing using Analog Outputs Pixel Output Timing Multiplexing Analog Output Timing using Analog Outputs Timing using Analog Output Bare Dimensions Package View (all dimensions inch) Package Side View (all dimensions inch) Package Back View (all dimensions inch) Bonding Scheme IBIS4-A-6600 Package Transmittance Curve D263 Cover Glass Reflow Soldering Temperature Profile
Document Number: 001-02366 Rev.
Page
LIST TABLES
IBIS4-A-6600 CYII4SM6600AB
Performance Parameters General Specifications. Electro-optical Specifications Features General Specifications Absolute Maximum Ratings Recommended Operating Conditions Electrical Conditions Frame Rate Resolution Gain Settings specifications resistor values Subsample Patterns Frame Rate Subsample Mode Pros Cons List Internal Registers Overview Modes. Granularity X-Sequencer Clock Corresponding Blanking Time (for Delay added Changing Settings DELAY Register Delay added Changing Settings DELAY_CLK_AMP Bits List Package Side View Dimensions. Storage conditions. Chemical Substances Information about Intentional Content Ordering Information.
Document Number: 001-02366 Rev.
Page
Specifications
General Specifications Table General Specifications. Parameter Pixel architecture Pixel size Resolution Pixel rate Shutter type Full frame rate Electro-optical specifications Overview Table Electro-optical Specifications Parameter (local) PRNU (local) Conversion gain Output signal amplitude Saturation charge Sensitivity (peak) Sensitivity (visible) Peak Peak Spectral Resp. Fill factor Dark current Dark Signal Uniformity Temporal noise Ratio Spectral sensitivity range Optical cross talk Power dissipation <0.20% <1.5% Conversion gain 0.6V 21.500 e411V.m2/W.s 4.83 V/lux.s V.m2/W.s 2.01 V/lux.s 0.13 3.37 mV/s e-/s 8.28 mV/s e-/s e895:1 1000 mWatt first neighboring pixel. second neighboring pixel. Typical (including ADCs). W/m2). 400-700 (163 W/m2). Specification signal level. output (measured). nominal conditions. 3T-pixel 2210 x3002 Electronic rolling shutter frames/second Specification
IBIS4-A-6600 CYII4SM6600AB
Remarks resolution pixel size results 7.74 10.51 optical active area. Using system clock parallel outputs. Increases with read and/or sampling.
Remarks RMS% saturation signal.
Average QE*FF (visible range). Average SR*FF (visible range). spectral response curve. Light sensitive part pixel (measured). Typical value average dark current whole pixel array °C). Dark current value °C). Measured digital output dark). Measured digital output dark).
Document Number: 001-02366 Rev.
Page
Spectral Response Curve Figure Spectral Response Curve
0.14
IBIS4-A-6600 CYII4SM6600AB
0.12
Spectral response [A/W]
0.08
0.06
0.04
0.02
Wavelenght [nm]
1000
Spectral Response Curve page shows spectral response characteristic. curve measured directly pixels. includes effects non-sensitive areas pixel, e.g., interconnection lines. sensor light sensitive
between 1000 peak approximately around view fill factor 35%, thus close between
Document Number: 001-02366 Rev.
Page
Electro-voltaic Response Curve Figure Electro-voltaic Response Curve
IBIS4-A-6600 CYII4SM6600AB
Output swing
5000 10000 electrons 15000 20000 25000
Electro-voltaic Response Curve page shows pixel response curve linear response mode. This curve relation between electrons detected pixel Features General Specifications Table Features General Specifications Feature Electronic shutter type Integration time control Windowing (ROI) Sub-sampling modes: Extended dynamic range Analog output Digital output Supply voltage Logic levels Interface Package
output signal. resulting voltage-electron curve independent parameters (integration time, etc). voltage electrons conversion gain µV/electron.
Specification/Description Rolling shutter. 1/frame period. Randomly programmable read out. Several sample modes programmed (see 2.6). Dual slope optical dynamic range) non-destructive read mode. output rate Mpixels/s achieved with analog outputs each working Mpixel/s. on-chip 10-bit ADCs Msamples/s multiplexed digital output Msamples/s. Nominal 2.5V (some supplies require 3.3V extended dynamic range). 2.5V. Serial-to Parallel Interface (SPI). 68-pins LCC.
Document Number: 001-02366 Rev.
Page
Electrical Specifications Absolute Maximum Ratings Table Absolute Maximum Ratings Symbol VOUT supply voltage input voltage output voltage current drain pin; single input output. Lead temperature seconds soldering). Storage temperature Humidity (relative) susceptibility Parameter -0.5 Value
IBIS4-A-6600 CYII4SM6600AB
Unit
-0.5 (VDD 0.5) -0.5 (VDD 0.5) 2000
VDDD VDDA (VDDD supply digital circuit, VDDA analog circuit). Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated Recommended Operating Conditions Table Recommended Operating Conditions Symbol Parameter supply voltage Commercial operating temperature. Min. Typ. Max. Max. operational sections implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
parameters characterized conditions after thermal equilibrium been established. Unused inputs must always tied appropriate logic level, e.g., either GND. Electrical Conditions Table Electrical Conditions Symbol Characteristic Input high voltage Input voltage Input leakage current Output high voltage Output voltage Operating current
This device contains circuitry protect inputs against damage high static voltages electric fields; however recommended that normal precautions taken avoid application voltages higher than maximum rated voltages this high-impedance circuit.
Condition
Min. VDD-0.5 -0.6
Max.
Unit
VDD=min; IOH= -100 VDD=min; IOH= System clock
VDD-0.5
Document Number: 001-02366 Rev.
Page
Sensor Architecture Operation
Floor Plan Figure Floor Plan
IBIS4-A-6600 CYII4SM6600AB
IMAG
addres able hift regis ub-s ampling
addres able hift regis ub-s ampling
elect
pixel array
elect drivers
2210 3002 (excl. dark dummy pixels
elect drivers
ixel (0,0)
clk_y ync_yr
clk_y ync_yl
column amplifiers clk_x ync_x
addres able hift regis ub-s ampling
addres data
Dig. logic
analog output
Dig. logic
Floor Plan page shows architecture image sensor that been designed. consists basically pixel array, shift registers readout direction, parallel analog output amplifiers, column amplifiers that correct fixed pattern noise caused threshold voltage non-uniformities. Reading pixel array starts applying clock pulse select row, followed calibration sequence calibrate column amplifiers (row blanking time). Depending external bias resistors timing, typically this sequence takes about line (baseline). This sequence necessary remove Fixed Pattern Noise pixel column amplifiers themselves means Double Sampling technique). Pixels also read non-destructive manner. DACs have been added make offset level pixel values adjustable equal output busses. third used connect busses stable voltage during blanking period Document Number: 001-02366 Rev.
reset busses continuously case non-destructive readout). 10-bit ADCs running Msamples/s will convert analog pixel values. digital outputs will multiplexed digital 10-bit output Msamples/s. Note that these blocks electrically completely isolated from sensor part (except multiplexer which settings uploaded through shared address data bus). shift registers have programmable starting point. starting point's possibilities limited limitations imposed sub-sampling requirements. upload start address done through serial parallel interface. Most signals image core Floor Plan page generated chip sequencer. This sequencer also allows running sensor basic modes, fully autonomously. Page
equencer
Pixel Architecture pixel architecture classical three-transistor pixel shown Pixel Architecture page pixel been implemented using high fill factor technique patented FillFactory patent 6,225,670 others). Figure Pixel Architecture
IBIS4-A-6600 CYII4SM6600AB
chip. Measurements indicate that typical PRNU about 1.5% signal level. Color filter array IBIS4-6600 also processed with Bayer color pattern. Pixel (0,0) green filter situated green-red row. Green1 green2 separately processed color filters have different spectral response. Green1 pixels located blue-green row, green2 pixels located green-red row. Figure Bayer Alignment
reset
selec
output (column)
PRNU Fixed Pattern Noise correction done on-chip. images taken sensor typically feature residual (local) 0.35% saturation voltage. Photo Response Uniformity (PRNU), caused mismatch photodiode node capacitances, corrected Typical Response Curve Filters page below shows response color filter array function wavelength. Note that this response curve includes optical cross talk filter color glass well (see
Figure Typical Response Curve Filters
Document Number: 001-02366 Rev.
Page
Dark Dummy Pixels Floor Plan Pixel Array page shows plan pixel array. sensor been designed "portrait" orientation. ring dummy pixels surrounds active pixels. Figure Floor Plan Pixel Array
IBIS4-A-6600 CYII4SM6600AB
Black pixels implemented "optical" black pixels.
Dummy ring pixels urrounding complete pixel array. read
dummy pixels covered with black layer, readable dummy pixels illuminated, readable
3002
array active pixels read 3002x 2210
3014
2222
Pixel Rate
2210
RBT: Blanking Time (typical). Pixel period: 1/40 Example: read time full resolution nominal speed pixel rate): Frame period (3002 (7.2 2210)) 187.5 5.33 fps. Region Interest (ROI) Read Windowing easily achieved uploading starting point y-shift registers sensor registers (see 2.9.1). This downloaded starting point initiates shift register y-direction triggered Y_START (initiates Y-shift register) Y_CLK (initiates X-shift register) pulse. minimum step size x-address (only even start addresses chosen) Y-address (every line addressed). frame rate increases almost linearly when fewer pixels read out. Table gives overview achievable frame rates with read out.
pixel rate this sensor high enough support frame rate window size pixels (VGA format) pixels over scan both directions. Taking into account blanking time baseline, also 2.10.2.1.g.), this requires minimum pixel rate nearly MHz. final bandwidth column amplifiers, output stage etc. determined external bias resistors. Taken into account pixel rate full frame rate little more than frames/s will obtained. frame period IBIS4-6600 sensor calculated follows: Frame period (Nr. Lines (RBT pixel period Pixels)) With: Lines: Number Lines read each frame (Y). Pixels: Number pixels read each line (X). Table Frame Rate Resolution Image Resolution (Y*X) 3002 2210 1501 1104 Frame rate [frames/s]
Frame readout time [ms] 187.5
Comment Full resolution. read out.
Document Number: 001-02366 Rev.
Page
Output Amplifier output amplifier subtracts reset signal voltages from each other cancel much possible (Figure 8.). that used offset adjustment consists DACs. used main offset (DAC_raw) other allows fine tuning compensate offset difference between signal paths arriving amplifiers (DAC_fine). With analog multiplexer signals from busses combined pixel output full pixel rate MHz). analog signals
IBIS4-A-6600 CYII4SM6600AB
can, however, also available separate output pins allow higher pixel rate. third (DAC_dark) puts value busses during calibration output amplifier. case non-destructive readout double sampling), bus1_R bus2_R continuously connected output DAC_fine provide reference signals bus1_S bus2_S. complete output amplifier standby setting corresponding AMPLIFIER register.
Figure Output Amplifier Architecture
programmable gain amplifiers bus1 bus1_R bus2 bus2_R analog multiplexer
output drivers Pixel output
Stage Stage
Pixel output
Stage
DAC_raw DAC_fine DAC_dark
Stage Offset, Correction Multiplexing first stage, signals from busses subtracted offset from DACs added. After system reset, analog multiplexer configured outputs (see settings AMPLIFIER register). case ONE_OUT signals multiplexed output (output amplifiers stage stage second output path then standby. speed power consumption first stage controllable through resistor connected CMD_OUT_1. Stage Programmable Gain Amplifier second stage provides gain, which will adjustable between 1.36 17.38 steps roughly 20.25 (~1.2). overview gain settings given Table speed power consumption second stage controllable through resistor connected CMD_OUT_2.
Table Gain Settings Bits 0000 0001 0010 0011 0100 0101 0110 0111 Gain 1.36 1.64 1.95 2.35 2.82 3.32 3.93 4.63 Bits 1000 1001 1010 1011 1100 1101 1110 1111 Gain 5.40 6.35 7.44 8.79 10.31 12.36 14.67 17.38
Document Number: 001-02366 Rev.
Page
Stage Output Drivers speed power consumption third stage controllable through resistor connected CMD_OUT_3. output drivers designed drive 20-pF output load Msamples/s with bias resistor Offset DACs
IBIS4-A-6600 CYII4SM6600AB
Figure shows registers influence black reference voltages different channels. offset mainly given through DAC_raw. DAC_fine used shift reference voltage down compensate different offsets channels.
Figure Offset Channels through DAC_RAW DAC_FINE
DAC_RAW_REG<0:7 DAC_raw 200K blackref bus1
rcal
RCAL
VCAL
RCAL_DAC_OUT
VDDA
blackref bus2
DAC_FINE_REG<0:7
DAC_fine rcal
200K
floating
GNDA
Assume that Voutfull voltage that depends values that applied ranges from
Voutfull (bit values 00000000
VDDA
(bit values 11111111
image sensor. inputs should tied externally outputs output amplifiers. will sample even columns other will sample columns. Alternatively, sample pixels well. Table specifications Parameter Input range Quantization Nominal data rate (linear conversion mode) Input capacitance Conversion Specification external resistors (see next section) Bits 20Msamples/s Typ. Linear/Gamma-corrected
Externally, output range DAC_raw changed connecting resistor Rcal RCAL_DAC_OUT applying voltage Vcal. output voltage Vout DAC_raw follows relation
Vout
Special case:
Rcal Voutfull Rcal
Rcal
Vcal
Rcal then Vout Voutfull (e.g. DAC_fine) Rcal Vcal GND. then Vout Voutfull/2 similar relation holds output range DAC_DARK (RCAL_DAC_DARK used tune output range this DAC). Analog Digital Converter IBIS4-6600 flash analog digital converters. ADC's electrically separated from
DNL(Linear conversion mode) Typ. 0.4LSB
Document Number: 001-02366 Rev.
Page
Setting reference voltages Figure resistor ladder
VDDA_ADC
IBIS4-A-6600 CYII4SM6600AB
VHIGH_ADC 1.5V
RADC (ESD)
Internal
High reference voltage used
reference voltage used (ESD) VLOW_ADC 0.42V
internal resistance value approximately Only this internal resistance actually used reference internal ADC. This causes actual voltage range half voltage difference between VHIGH_ADC VLOW_ADC. This results following values external resistors: Table resistor values Resistor RVHIGH_ADC RInternal RVLOWADC Subsample Modes increase frame rate lower resolution and/or regions interest, number sampling modes have been implemented. possible sample modes listed Table bits programmed IMAGE_CORE register (see 2.9.2.8). preserve color information, adjacent pixels read mode, while number pixels that read, varies from mode mode. This will designed repeated block pixels wide, which Value
lowest common multiple modes described above. Including dummy pixels additional rows/columns, number starting coordinates shift register thus direction. total number pixels, excluding dummy pixels, multiple additional pixels have same window edges independently sub-sampling mode. direction, columns always addressed same moment since signals from even columns must simultaneously corresponding bus. direction, rows addressed one. This results slightly different implementations sub-sampling modes directions (Figure Figure 12.). Table Subsample Patterns Mode Bits Read Step Default mode (Skip (Skip (Skip (Skip
Document Number: 001-02366 Rev.
Page
Shift register Logic selecting collumns Shift register Logic selecting collumns
scan direction
Logic selecting collumns
Document Number: 001-02366 Rev.
Shift register Shift register Logic selecting collumns Shift register Logic selecting collumns Shift register Logic selecting collumns Shift register Logic selecting collumns
Figure X-subsampling
column amplifiers
Shift register
Logic selecting collumns
Shift register
Logic selecting collumns
Shift register
Logic selecting collumns
Shift register
Logic selecting collumns
Shift register
Logic selecting collumns
IBIS4-A-6600 CYII4SM6600AB
bus1_S bus1_R bus2_S bus2_R
Page
Figure Y-subsampling
IBIS4-A-6600 CYII4SM6600AB
shift registers pixel pitch scan direction
Logic selecting
Table Frame Rate Subsample Mode Mode 63.2 VGA(l) Ratio 1:16 1:36 Resolution (Y*X) 3002 2210 1502 1106 1002 Frame time [ms] 187.4 52.3 25.7 15.8 12.3 13.1 11.1 11.9 Frame time [ms] 19.1 38.9 63.2 121.2 81.5 76.4 89.9 83.7
Figure shows pixels read each color sub-sampling mode.
Document Number: 001-02366 Rev.
Page
Figure Pixel Readout Various Subsample Modes
IBIS4-A-6600 CYII4SM6600AB
Mode
Mode
Mode
Mode
Mode
Document Number: 001-02366 Rev. Page
Electronic Shutter curtain-like (rolling) electronic shutter been implemented on-chip. seen Figure 14., there shift registers. them points that currently being read out. other shift register points that currently being reset. Both pointers shifted same Y-clock move over focal plane. integration time delay between both pointers.
Readout pointer
IBIS4-A-6600 CYII4SM6600AB
case mechanical shutter, shift registers combined apply pulses from both sides pixel array simultaneously. This halve influence parasitic times reset select lines pixel array (which result reduction blanking time). This case when FAST_RESET SEQUENCER register non-destructive readout modes
Integration time
Reset pointer
Figure Electronic Rolling Shutter Operation
Line number
Reset sequence
Time axis Frame time
High Dynamic Range Modes Double Slope Integration IBIS4-6600 feature increase optical dynamic range sensor; called double slope integration. pixel response extended over larger range light intensities using "dual slope integration" (patents pending). This obtained addition charge packets from long short integration time pixel during same exposure time. Figure shows response curve pixel dual slope integration mode. curve also shows response same pixel linear integration mode, with long short integration time, same light levels. Dual slope integration obtained Feeding lower supply voltage VDD_RESET_DS (e.g., apply 2.0V 2.5V). Note that normal (single slope Document Number: 001-02366 Rev.
Integration time
operation VDD_RESET_DS should have same value VDD_RESET. difference between VDD_RESET_DS VDD_RESET determines range high sensitivity, thus output signal level which transition between high sensitivity occurs. amplifier gain lowest value where analog output swing covers ADC's digital input swing. Increasing amplification much will likely boost high sensitivity part over whole range. electronic shutter determines ratio integration times slopes. high sensitivity ramp corresponds electronic shutter", thus maximal integration time (frame read time). sensitivity ramp corresponds electronic shutter value that would have been obtained normal operation.
Page
Figure Double Slope Response
IBIS4-A-6600 CYII4SM6600AB
Output signal
Dual slope operation
Long integration time Short integration time
Relative exposure (arbitrary scale) 100%
Non-destructive Read (NDR) default mode operation sensor with correction (double sampling). However, sensor also read non-destructive way. After pixel initially reset, read multiple times, without resetting. initial reset level intermediate signals recorded. High light levels will saturate pixels quickly, useful signal
obtained from early samples. light levels, later latest samples. Essentially active pixel array read multiple times, reset only once. external system intelligence takes care interpretation data. Table summarizes advantages disadvantages non-destructive readout.
Figure Principle Non-destructive Readout
time
Table Pros Cons Advantages noise true CDS. order below. High sensitivity conversion capacitance kept rather low. High dynamic range results includes signal short long integrations times. Disadvantages System memory required record reset level intermediate samples. Requires multiples readings each pixel, thus higher data throughput. Requires system level digital calculations.
Document Number: 001-02366 Rev.
Page
Sequencer Registers Figure showed number control signals that needed operate sensor particular sub-sampling mode, with certain integration time, output amplifier gain, etc. Most these signals generated on-chip sequencer that uses only control signals. These control signals should generated external system: SYS_CLOCK, which defines pixel rate (nominal MHz), Y_START pulse, which indicates start frame,
IBIS4-A-6600 CYII4SM6600AB
Y_CLOCK, which selects will start blanking sequence, including synchronization loading X-register. relative position pulses will determined number data bits that uploaded internal registers through Serial Parallel interface (SPI). Internal Registers Table shows list internal registers with short description. next section, registers explained more detail.
Table List Internal Registers Register (0000) 11:0 Name SEQUENCER register Description Selection mode, granularity sequencer clock, calibration, Default value <11:0>:"000100000000" Mode readout: normal readout (double sampling) non-destructive readout different modes non-destructive readout influence normal operation reset pixels before readout electronic shutter operation addressing from both sides fast slow fast slow normal mode 'continuous precharge' Granularity sequencer clock normal mode disconnects column amplifiers from busses, output amplifier equals dark reference level normal mode continuous reset pixels Number pixels count direction). Max. 2222/2 (2210 real dummy pixels). Default value <10:0>:"01000000000" Number lines count direction). Max. 3014 (3002 real dummy pixels). Default value <11:0>:"101111000110" Integration time. Default value <11:0>:"000000000001" Delay sequencer pulses Default value <7:0>:"00000011" Delay PIX_VALID pulse Delay EOL/EOF pulses start position 98). Default value <6:0>:"0000000" start position 137). Default value <7:0>:"00000000"
NDR_mode RESET_BLACK FAST_RESET FRAME_CAL_MODE LINE_CAL_MODE CONT_CHARGE GRAN_X_SEQ_LSB GRAN_X_SEQ_MSB BLACK
(0001) (0010) 10:0 11:0
RESET_ALL NROF_PIXELS NROF_LINES
(0011) (0100)
11:0
INT_TIME DELAY DELAY_PIX_VALID DELAY_EOL/EOF X_REG Y_REG
(0101) (0110)
Document Number: 001-02366 Rev.
Page
Table List Internal Registers (continued) Register (0111) (1000) (1001) Name IMAGE CORE register TEST_mode X_SUBSAMPLE Y_SUBSAMPLE AMPLIFIER register GAIN<3:0> UNITY ONE_OUT STANDBY DELAY_CLK_AMP DAC_RAW_REG DAC_FINE_REG DAC_DARK_REG register STANDBY_1 STANDBY_2 SWITCH multiplexing outputs disable multiplexing LSB: odd, MSB: even normal operation sub-sampling mode X-direction sub-sampling mode X-direction Default value <9:0>:"0000010000" Output amplifier gain setting gain setting GAIN<3:0> unity gain setting analog outputs multiplexing output (out_1) normal operation amplifier standby mode. Delay pixel clock output amplifier. Amplifier offset. Default value <7:0>:"10000000" Amplifier fine offset. Default value <7:0>:"10000000" dark reference output bus. Default value <7:0>:"10000000" Default value <10:0>:"00000000000" normal operation standby Description Default value <7:0>:"00000000"
IBIS4-A-6600 CYII4SM6600AB
(1010) (1011) (1100) 10:0
delay output with (EXT_CLK half (EXT_CLK clock cycle switch between ADCs internal clock (same clock shift register output amplifier) external clock normal operation outputs tristate mode Delay clock ADCs digital multiplexer linear conversion 'gamma' conversion inversion bits inversion bits
(1101) (1110) (1111)
EXT_CLK TRISTATE DELAY_CLK_ADC GAMMA BITINVERT Reserved. Reserved. Reserved.
Detailed Description Registers SEQUENCEHR Register (bit normal operation (NDR sensor operates double sampling mode. start each readout, signals from pixels sampled, reset signals Document Number: 001-02366 Rev.
from pixels sampled again. values subtracted output amplifier. When sensor operates non-destructive readout (NDR) mode (see Table NDR_mode (bit
Page
These bits only influence operation sensor case (bit There basically modes non-destructive readout (mode Each mode needs different frame readouts (setting mode setting mode First reset/readout sequence (called reset_seq hereafter) then several pure readout sequences (called read_seq hereafter). Table gives overview different modes. Table Overview Modes. Setting Mode this mode, sensor readout same non-destructive readout. However, electronic shutter control possible this case, i.e., minimal (integration) time between readings equal number lines that read (frame read time). lines clocked simultaneously (left right clock pulses equal). Mode mode possible have shorter integration time than frame read time. Rows alternating read with left right pointer. These pointers point different rows (see INT_TIME register). (integration) time between readings same equal number lines that INT_TIME register times plus minimal line read time. setting that read left pointer reset read (first Y_CLOCK), that read right pointer read without resetting (second Y_CLOCK). setting both rows read without resetting first Y_CLOCK read left pointer; second Y_CLOCK read right pointer). both modes, signals read through same path with destructive readout (double sampling) busses that carrying reset signals destructive readout, non-destructive readout voltage given DAC_DARK. Reset_black (bit RESET_BLACK each line reset before read (except that read right pointer mode This might useful obtain black pixels. Fast_reset (bit Bits mode Sequence reset read reset read
IBIS4-A-6600 CYII4SM6600AB
fast reset option (FAST_RESET might useful case mechanical camera shutter used. fast reset done row-by-row basis, global reset. global reset means charging pixels same time, which result huge peak current. Therefore, rows scanned rapidly while left right shift registers both controlled identically, that reset lines over pixel array driven from both sides. This reduces reset (row blanking) time (when FAST_RESET smallest X-granularity used). After blanking time reset Y_CLOCK asserted reset next row. After certain integration time, read done similar way. shift registers again synchronized first row. Both shift registers driven identically, rows columns scanned (destructive) readout. FAST_RESET puts sequencer such mode that left right shift registers both controlled identically. Output amplifier calibration (bit Bits FRAME_CAL_MODE LINE_CAL_MODE define calibration mode output amplifier. During every row-blanking period, calibration done output amplifier. There calibration modes. FAST mode force calibration cycle accurate suffers from noise, while SLOW mode only make incremental adjustments noise free. Approximately more "slow" calibrations will have same effect "fast" calibration. Different calibration modes beginning frame (FRAME_CAL_MODE bit) every subsequent that read (LINE_CAL_MODE bit). Continuous charge (bit some applications might necessary continuous charging pixel columns instead precharge every sample operation. Setting CONT_CHARGE will activate this function. resistor connected CMD_COL used control current level every pixel column. Internal clock granularities system clock divided several times on-chip. X-shift-register that controls column/pixel readout, clocked half system clock rate. even pixel columns switched separate busses. output amplifier pixel signals busses combined pixel stream MHz. clock that drives X-sequencer multiple times system clock. Table gives settings granularity X-sequencer clock corresponding blanking time (for blanking time 7.18 baseline almost applications
Document Number: 001-02366 Rev.
Page
IBIS4-A-6600 CYII4SM6600AB
Table Granularity X-Sequencer Clock Corresponding Blanking Time (for Gran_x_seq_msb/lsb Black (bit case BLACK internal black signal will held high continuously. consequence, column amplifiers disconnected from busses, busses voltage given DAC_DARK output amplifier equals voltages from offset DACs. Reset_all (bit case RESET_ALL pixels simultaneously 'reset' state. this state, pixels behave logarithmically with light intensity. this state combined with modes, sensor used non-integrating, logarithmic mode with high dynamic range. Nrof_pixels Register After internal X_SYNC generated (start pixel readout particular row), PIXEL_VALID signal goes high. PIXEL_VALID signal goes when pixel counter reaches value loaded NROF_PIXEL register pulse generated. fact that pixels addressed each internal clock cycle amount pixels read 2*(NROF_PIXEL X-sequencer clock sys_clock sys_clock sys_clock sys_clock blanking time TSYS_CLOCK TSYS_CLOCK TSYS_CLOCK 1122 TSYS_CLOCK Nrof_lines Register After internal YL_SYNC generated (start frame readout with Y_START), line counter increases with each Y_CLOCK pulse until reaches value loaded NROF_LINES register pulse generated. mode line counter increments only every Y_CLOCK pulses pulse shows only after readout indicated right shift register INT_TIME Register When Y_START pulse applied (start frame readout), sequencer will generate YL_SYNC pulse left Y-shift register. This loads left Y-shift register with pointer loaded Y_REG register. each Y_CLOCK pulse, pointer shifts next integration time counter increases (increment only every Y_CLOCK pulses mode until reaches value loaded INT_TIME register. that moment, YR_SYNC pulse right Y-shift register generated which loads right Y-shift register with pointer loaded Y_REG register (Figure 17.). blanking time [µs] 3.55 7.05 14.05 1122 TSYS_CLOCK
Figure Syncing Y-shift Registers.
Sync left shift-register
Sync right shift-register
Last line, followed sync left shift-register
Sync Line Treg_int Tint
Treg_int: Difference between left right pointer integration counter until value INT_TIME register reached INT_TIME register. case actual integration time Tint given TintL: Integration time lines] NROF_LINES register INT_TIME register case mode time Tint between readings same given Tint: Integration time lines]
NROF_LINES register case mode times Tint1 Tint2 between readings same (alternatingly) given Tint1:. Integration time lines] INT_TIME register Tint2:. Integration time lines] (NROF_LINES register INT_TIME register DELAY register DELAY register used delay PIXEL_VALID pulse (bits 0:3) EOL/EOF pulses (bits 4:7) Page
Document Number: 001-02366 Rev.
synchronize them real pixel values analog output output (which give additional delays depending
IBIS4-A-6600 CYII4SM6600AB
their settings). settings corresponding delay indicated Table
Table Delay added Changing Settings DELAY Register bits 0000 0001 0010 0011 0100 0101 0110 0111 X_REG Register X_REG register determines start position window X-direction. this direction, there 2208 readable pixels. active pixel array sub-sampling blocks pixels wide columns read therefore, number start positions equals 2208/24 +2/2 +12/2 Y_REG Register Y_REG register determines start position window Y-direction. this direction, there 3000 readable pixels. active pixel array sub-sampling blocks pixels wide rows read therefore, number start positions equals 3000/24 138. Image_core Register Bits IMAGE_CORE register defines several test modes image core. Setting default normal operation mode. case (bit even (bit columns tight VDD. These test modes used tune sampling point ADCs optimal position. Bits IMAGE_CORE register define sub-sampling mode X-direction (bits 2:4) Y-direction (bits 5:7). sub-sampling modes corresponding setting given Analog Digital Converter page AMPLIFIER Register Gain (bits 0:3) gain bits determine gain setting output amplifier. They only effective UNITY gains corresponding setting given Table Stage Programmable Gain Amplifier page Unity (bit case UNITY gain setting GAIN bypassed gain amplifier unity feedback. One_out ONE_OUT output amplifiers active. ONE_OUT signals from busses Delay SYS_CLOCK periods] bits 1000 1001 1010 1011 1100 1101 1110 1111 Delay SYS_CLOCK periods]
multiplexed output OUT1. gain amplifier output driver second path standby. Standby STANDBY complete output amplifier standby (this reduces power consumption significantly) Delay_clk_amp clock that acts output amplifier delayed compensate delay that introduced path from shift register, column selection logic, column amplifier busses output amplifier. Setting '000' used baseline.
Table Delay added Changing Settings DELAY_CLK_AMP Bits Bits Delay [ns] Bits Delay [ns] Inversion Inversion Inversion 11.1 Inversion 12.3
Dac_raw_reg Dac_fine_reg Register These registers determine black reference level output output amplifier. setting 11111111 DAC_RAW_REG register gives highest offset voltage; setting 00000000 DAC_RAW_REG register gives lowest offset voltage. Ideally, output paths have offset mismatch, DAC_FINE_REG register must 10000000. Deviation from this value used compensate internal mismatch (see Offset DACs page 13). Dac_raw_dark Register This register determines voltage level that internal busses during calibration output stage. This voltage level also continuously reset busses case non-destructive readout reset level double sampling correction).
Document Number: 001-02366 Rev.
Page
Register Standby_1 standby_2 case only none ADCs used, other both ADCs standby setting (this reduces power consumption significantly). case OUT1 OUT2 both used connected ADC_IN1 ADC_IN2 respectively, must both ADCs multiplex their output ADC_D<9:0>. multiplexing disabled. Switch case ADCs used (ONE internal pixel clock (EXT_CLK output delayed with system clock cycle SWITCH case ADCs used (ONE external clock (EXT_CLK applied, output delayed with half clock cycle SWITCH case only used, digital multiplexing disabled SWITCH selects which output ADC_D<9:0> (SWITCH ADC_1, SWITCH ADC_2). Ext_clk case EXT_CLK internal pixel clock (that drives X-shift registers output amplifier, i.e. half system clock) used input clock. case EXT_CLK external clock must applied ADC_CLK_EXT (pin 46). Tristate case TRISTATE ADC_D<9:0> outputs tri-state mode. Delay_clk_adc
IBIS4-A-6600 CYII4SM6600AB
clock that finally acts ADCs delayed compensate delay that introduced path from analog outputs input stage ADCs. same settings apply delay that given clock acting output amplifier (see Table best setting will also depend delay output amplifier clock load output amplifier. must used optimize sampling moment ADCs with respect analog pixel input signals. Setting '000' used baseline. Gamma GAMMA input output conversion linear, otherwise conversion follows 'gamma' (more contrast dark parts window, lower contrast bright parts). Bitinvert BITINVERT 0000000000 conversion lowest possible input voltage, otherwise bits inverted. Serial Parallel Interface upload sequencer registers dedicated serial parallel interface (SPI) implemented. bits address bits data bits) must uploaded serially. address must uploaded first (MSB first), then data (also first). elementary unit cell shown Figure these cells connected series, having common SPI_CLK form entire uploadable parameter block, where Dout cell connected SPI_DATA next cell (max. speed MHz). uploaded settings address/data loaded into correct register sensor rising edge signal REG_CLOCK become effective immediately.
Figure Interface
outputs address/data
REG_CLOCK
SPI_DATA SPI_CLK
address/data SPI_DATA SPI_CLK Dout
REG_CLOCK
ntire uploadable addres block
SPI_CLK
Unity
SPI_DATA REG_CLOCK
Internal register upload
Document Number: 001-02366 Rev.
Page
Timing Diagrams
Sequencer Control Signals There control signals that operate image sensor: Sys_clock Y_clock Y_start Figure Relative Timing Control Signals
IBIS4-A-6600 CYII4SM6600AB
These control signals should generated external system with following time constraints SYS_CLOCK (rising edge active edge): TSETUP >7.5 THOLD important that these signals free glitches.
Basic Frame Line Timing basic frame line timing IBIS4-6600 sensor shown Figure pulse width Y_CLOCK should minimum clock cycle clock cycles Y_START. long Y_CLOCK applied, sequencer stays suspended state. blanking time: During this period, X-sequencer generates control signals sample pixel signal pixel reset levels, start readout line. depends granularity X-sequencer clock (see Table Pixels counted pixel counter until value Nrof_pixels register reached. Pixel_valid goes high when internal X_sync signal generated, other words when readout pixels started. Pixel_valid goes when pixel counter reaches value loaded Nrof_pixels register. goes high Sys_clock cycle after falling edge Pixel_valid.
goes high when line counter reaches value loaded NROF_LINES register line read (PIXEL_VALID goes low). time delay between successive Y_CLOCK pulses needs equal avoid horizontal illumination (integration) discrepancies image.
Both tied Y_START (EOF) Y_CLOCK (EOL) both signals delayed with least SYS_CLOCK periods sensor fully automatic way.
Document Number: 001-02366 Rev.
Page
Figure Basic Frame Line Timing
IBIS4-A-6600 CYII4SM6600AB
Pixel Output Timing Using Analog Outputs Figure Pixel Output Timing using Analog Outputs
pixel signal OUT1 (OUT2) output becomes valid after SYS_CLOCK cycles when internal X_SYNC start PIXEL_VALID output) appeared (see Figure 21.). PIXEL_VALID EOL/EOF pulses delayed user through DELAY register. blanking time (see Table SYS_CLOCK cycles.
Multiplexing Analog Output pixel signal OUT1 output becomes valid after SYS_CLOCK cycles when internal X_SYNC start PIXEL_VALID output) appeared (see Figure 22.). PIXEL_VALID EOL/EOF pulses delayed user through DELAY register. blanking time SYS_CLOCK cycles.
Document Number: 001-02366 Rev.
Page
IBIS4-A-6600 CYII4SM6600AB
Figure Pixel Output Timing Multiplexing Analog Output
Timing Analog Outputs Figure Timing using Analog Outputs
Figure shows timing using analog outputs. Internally, ADCs sample falling edge ADC_CLOCK case internal clock, clock half SYS_CLOCK).
Each pipeline delay ADC_CLOCK cycles. This results total pipeline delay pixels. Analog Output
Figure Timing using Analog Output
Figure shows timing using analog output. Internally, samples falling edge ADC_CLOCK. Document Number: 001-02366 Rev.
pipeline delay ADC_CLOCK cycles.
Page
List
Table list pins their function. total, there pins. pins with same name connected together. Table List Name CMD_COL_CTU CMD_COL CMD_COLAMP CMD_COLAMP_CTU RCAL_DAC_DARK Type Input Input Input Input Input Expected Voltage 1.08 0.66 0.37 1.27 code DAC_DARK 0.78
IBIS4-A-6600 CYII4SM6600AB
Description Biasing columns (ctu). Decouple with GNDA. Biasing columns. Connect VDDA with decouple GNDA with Biasing column amplifiers. Connect VDDA with decouple GNDA with Biasing column amplifiers. Connect VDDA with decouple GNDA with Biasing dark reference. used output range DAC. Default: decouple GNDA with Biasing output dark level. used output range DAC. Default: connect GNDA. analog part [2.5V]. (&substrate) analog part. digital part [2.5V]. (&substrate) digital part. Biasing first stage output amplifiers. Connect VDDAMP with decouple GNDAMP with Biasing second stage output amplifiers. Connect VDDAMP with decouple GNDAMP with Biasing third stage output amplifiers. Connect VDDAMP with decouple GNDAMP with Clock digital parameter upload. Shifts rising edge. Serial address data input. word. Address first. first. analog output [2.5V] (Can connected VDDA). Biasing first stage ADC. Connect VDDA_ADC with decouple GNDA_ADC with Biasing second stage ADC. Connect VDDA_ADC with decouple GNDA_ADC. Biasing input stage ADC. Connect VDDA_ADC with decouple GNDA_ADC with (&substrate) analog output. Analog output
RCAL_DAC_OUT VDDA GNDA VDDD GNDD CMD_OUT_1
Input Power Power Power Power Input
CMD_OUT_2
Input
0.97
CMD_OUT_3
Input
0.67
SPI_CLK SPI_DATA VDDAMP CMD_FS_ADC CMD_SS_ADC CMD_AMP_ADC GNDAMP OUT1
Input Input Power Input Input input Ground Output
0.73 0.73 0.59 Black level: code DAC_RAW reg. OUT1.
ADC_IN1 VDDAMP
Input Power
Analog input analog output [2.5V] (Can connected VDDA).
Document Number: 001-02366 Rev.
Page
Table List (continued) OUT2 Name Type Output Expected Voltage Black level: code DAC_RAW reg. OUT2. Analog output
IBIS4-A-6600 CYII4SM6600AB
Description
ADC_IN2 VDDD GNDD GNDA VDDA REG_CLOCK SYS_CLOCK SYS_RESET Y_CLK Y_START GNDD_ADC VDDD_ADC GNDA_ADC VDDA_ADC VHIGH_ADC
Input Power Power Power Power Input Input Input Input Input Power Power Power Power Input
Analog input digital part [2.5V]. (&substrate) digital part. (&substrate) analog part. analog part [2.5V]. Register clock. Data internal copied corresponding registers rising edge. System clock defining pixel rate (nominal MHz, duty cycle). Global system reset (active high). Line clock. Start frame readout. (&substrate) digital part ADC. digital part [2.5V] ADC. (&substrate) analog part. analog part [2.5 high reference voltage (e.g. connect VDDA_ADC with decouple GNDA_ADC with reference voltage (e.g. connect GNDA_ADC with decouple GNDA_ADC with (&substrate) analog part. analog part [2.5 (&substrate) digital part ADC. digital part [2.5 ADC. Variable reset voltage (dual slope). External clock. Diagnostic line signal (produced sequencer), used Y_CLK. Diagnostic frame signal (produced sequencer), used Y_START. Diagnostic signal. High during pixel readout. Temperature measurement. Output voltage varies linearly with temperature. data output (MSB). pixel core [2.5V]. Anti-blooming ground. improved anti-blooming behavior. data output. data output. data output. Page
VLOW_ADC
Input
0.42
GNDA_ADC VDDA_ADC GNDD_ADC VDDD_ADC VDD_RESET_DS ADC_CLK_EXT PIX_VALID TEMP ADC_D<9> VDD_PIX GND_AB ADC_D<8> ADC_D<7> ADC_D<6>
Power Power Power Power Power Input Output Output Output Output Output Power Power Output Output Output
(for dual slope)
Document Number: 001-02366 Rev.
Table List (continued) Name ADC_D<5> ADC_D<4> ADC_D<3> VDD_RESET ADC_D<2> ADC_D<1> ADC_D<0> BS_RESET BS_CLOCK BS_DIN BS_BUS CMD_DEC Type Output Output Output Power Output Output Output Input Input Input Output Input Expected Voltage 0.74 data output. data output. data output.
IBIS4-A-6600 CYII4SM6600AB
Description
Reset voltage [2.5V]. Highest voltage chip. extended dynamic range 'hard reset'. data output. data output. data output (LSB). Boundary scan (allows debugging internal nodes): reset. used. Boundary scan (allows debugging internal nodes): clock. used. Boundary scan (allows debugging internal nodes): used. Boundary scan (allows debugging internal nodes): bus. Leave floating used. Biasing decoder. Connect VDDD with decouple GNDD with Y_CLOCK pulse. Prior this X_SYNC, chip draw more current from analog power supply VDDA. therefore favorable have separate analog digital supplies. current spike there will any) also avoided slower ramp-up analog power supply disconnecting resistor (CMD_COLAMP) start-up.
Note Power-on Behavior power-on, chip undefined state. advised that power-on accompanied assertion SYS_CLOCK SYS_RESET pulse that puts internal registers their default state (all bits X-shift registers defined state after first X_SYNC which occurs microseconds after first Y_START
Document Number: 001-02366 Rev.
Page
Packaging
Bare IBIS4-6600 image sensor pins, pins each side. size from pad-edge pad-edge (without
IBIS4-A-6600 CYII4SM6600AB
scribe-line) 9120.10 11960.10 (Y). Scribe lines will take about extra each side. located middle left side, indicated layout. logo some identification tags found lower right (see Figure 25.).
Figure Bare Dimensions
Bonding
Probe
7777.00 (2222 3.5) 10549.00 (3014 3.5)
11960
4404.47 Origin (0,0) Pixel array center Test diodes 6427.00
Bonding
Probe
Probe Identification Bonding Pixel
Probe Bonding 9120.10
Document Number: 001-02366 Rev.
Page
Package Drawing Technical Drawing 68-pin Package Figure Package View (all dimensions inch)
IBIS4-A-6600 CYII4SM6600AB
Document Number: 001-02366 Rev.
Page
Figure Package Side View (all dimensions inch)
IBIS4-A-6600 CYII4SM6600AB
Table Package Side View Dimensions. Inch Dimension Description Glass (thickness) (thickness) attach (thickness) Glass attach (thickness) Imager lid-outer surface Imager lid-inner surface Imager seating plane 0.060 0.002 0.002 Min. 0.037 Typ. 0.039 0.029 0.004 0.004 0.081 0.039 0.061 0.062 1.512 0.006 0.006 0.030 0.030 Max. 0.039 Min. 0.950 (mm) Typ. 1.000 0.740 0.060 0.070 2.048 0.978 1.562 1.612 0.090 0.110 Max. 1.050
Document Number: 001-02366 Rev.
Page
Figure Package Back View (all dimensions inch)
IBIS4-A-6600 CYII4SM6600AB
Document Number: 001-02366 Rev.
Page
Bonding IBIS4-A-6600 68-pin Package
IBIS4-A-6600 CYII4SM6600AB
Figure Bonding Scheme IBIS4-A-6600 Package
middle corresponds with middle package cavity µm).
Pixel located -4023 -4806 (mechanical centre die/package
Document Number: 001-02366 Rev.
Page
Glass Specifications Monochrome Sensor D263 glass will used protection glass IBIS4-6600 monochrome sensors. refraction index Figure Transmittance Curve D263 Cover Glass
IBIS4-A-6600 CYII4SM6600AB
D263 glass 1.52. Figure shows transmission characteristics D263 glass.
Transmission
Wavelength [nm]
Storage Handling
Storage Conditions Table Storage conditions. Description Temperature Minimum Maximum Maximum
protected workstations recommended including ionized blowers. tools should protected. Manual Soldering: When soldering iron used following conditions should observed: soldering iron with temperature control tip. soldering iron temperature should exceed 350°C. soldering period each should less than seconds. Reflow Soldering: Figure shows maximum recommended thermal profile reflow soldering system. temperature/time profile exceeds these recommendations damage image sensor occur. Figure more details. Precautions cleaning: Avoid spilling solder flux cover glass; bare glass particularly glass with antireflection filters adversely affected flux. Avoid mechanical particulate damage cover glass. recommended that isopropyl alcohol (IPA) used solvent cleaning image sensor glass lid. When using other solvents, should confirmed beforehand whether solvent will dissolve package and/or glass not.
Handling Soldering Conditions Special care should taken when soldering image sensors with color filter arrays (RGB color filters), onto circuit board, since color filters sensitive high temperatures. Prolonged heating elevated temperatures result deterioration performance sensor. following recommendations made ensure that sensor performance compromised during end-users' assembly processes. Board Assembly: Device placement onto boards should done accordance with strict controls Class JESD22 Human Body Model, Class JESD22 Machine Model devices. Assembly operators should always wear designated approved grounding equipment; grounded wrist straps
Document Number: 001-02366 Rev.
Page
Figure Reflow Soldering Temperature Profile
IBIS4-A-6600 CYII4SM6600AB
RoHS (lead free) Compliance This paragraph reports Hazardous chemical substances required RoHS Directive (excluding packing material). Table Chemical Substances Information about Intentional Content Chemical Substance Lead Cadmium Mercury Hexavalent chromium (Polybrominated biphenyls) PBDE (Polybrominated diphenyl ethers) Information lead free soldering: IBIS4-A-6600-M2 (serial numbers beyond 3694): product tested successfully lead-free soldering processes, using reflow temperature profile with maximum 260°C, minimum 255°C minimum 217°C. IBIS4-A-6600-C2: product will withstand lead free soldering process. Maximum allowed reflow wave soldering temperature 220°C. Hand soldering recommended this part type. Note: "Intentional content" defined material demanding special attention contained into inquired product following cases: intentional content there intentional content, which portion contained? case that above material added chemical composition into inquired product intentionally order produce maintain required performance function intended product case that above material, which used intentionally manufacturing process, contained adhered inquired product following case treated "intentional content": case that above material contained impurity into materials parts intended product. impurity defined substance that cannot removed industrially, produced process such chemical composing reaction cannot removed technically.
Document Number: 001-02366 Rev.
Page
Ordering Information
Table Ordering Information. Cypress Part number CYII4SC6600AB-QDC CYII4SM6600AB-QDC CYII4SC6600AB-HDC CYII4SM6600AB-HDC JLCC package evaluation kits only. D263 used monochrome glass (see Figure spectral transmittance). Other packaging combinations available upon special request. Package 68-pin 68-pin 84-pinJLCC 84-pin JLCC Glass D263 D263 D263 D263
IBIS4-A-6600 CYII4SM6600AB
Mono/Color Bayer pattern Bayer pattern
Disclaimer
IBIS4-6600 sensor only used non-low vision applications. strict exclusivity agreement prevents sell IBIS4-6600 sensor customers intend above specified applications.
products company names mentioned this document trademarks their respective holders.
Document Number: 001-02366 Rev.
Page
Cypress Semiconductor Corporation, 2006. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges.
Document History Page
Document Title: IBIS4-A-6600 CMOS image sensor Document Number: 001-02366 REV. ECN. 384900 402976 418669 Issue Date Orig. Change Origination.
IBIS4-A-6600 CYII4SM6600AB
Description Change Preliminary notice removed. Electro-optical spec updated characterization data. Table resistor values changed section added Figure corrected Converted Frame file Ordering information update
502551 642596
Document Number: 001-02366 Rev.
Page
Other recent searches
SNC15120 - SNC15120 SNC15120 Datasheet
SNC15120P - SNC15120P SNC15120P Datasheet
MPX100 - MPX100 MPX100 Datasheet
CIC-56TS-40D-A6-YAM-S - CIC-56TS-40D-A6-YAM-S CIC-56TS-40D-A6-YAM-S Datasheet
AN-530 - AN-530 AN-530 Datasheet
HI-6110 - HI-6110 HI-6110 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
