This document provides guidelines integrating AT85C51SND3Bx high speed

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This document provides guidelines integrating AT85C51SND3Bx high speed

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High Speed Design Guidelines
This document provides guidelines integrating AT85C51SND3Bx high speed device controller onto 4-layer PCB. material covered broken into main categories: board design guidelines layout examples. High speed operation described Specification
AT85C51SND3Bx Microcontrollers
Application Note
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Layout Guidelines
General Routing Placement
following general routing placement guidelines when laying design. These guidelines will help minimize signal quality problems. Place high-speed host controller major components unrouted board. With minimum trace lengths, route high-speed clock high-speed differential pairs. Maintain maximum possible distance between high-speed clocks/periodic signals high speed differential pairs connector leaving (such connectors, control signal headers, power connectors). Route high-speed signals using minimum vias corners. This reduces signal reflections impedance changes. When becomes necessary turn 90°, turns instead making single turn. This reduces reflections signal minimizing impedance discontinuities. route traces under crystals, oscillators, clock synthesizers, magnetic devices that and/or duplicate clocks. Stubs high speed signals should avoided, stubs will cause signal reflections affect signal quality. Route traces over continuous plane with interruptions.
High Speed Trace Spacing
Figure provides illustration recommended trace spacing while Table gives some trace calculation examples. following guidelines. impedance calculator determine trace width spacing required specific board stack-up being used. calculated achieve trace impedance (Z0) ~50W calculated achieve differential trace impedance 90W. These impedances depend first approximation following parameters delivered manufacturer:
dielectric relative permittivity
dielectric height trace thickness Maintain parallelism between differential signals with trace spacing calculated achieve differential impedance. Deviations will normally occur package breakout routing connector pins. Ensure amount length deviations kept minimum. Minimize length high-speed clock periodic signal traces that parallel high speed signal lines minimize crosstalk. Based testing experience, minimum suggested spacing clock signals mils. Based simulation data, 20-mil minimum spacing between high-speed signal pairs other signal traces optimal signal quality. This helps prevent crosstalk.
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Figure 2-1. speed/ periodic signal
Recommended Trace Spacing High speed/ clock periodic signal
mils
mils
Dielectric Analog Ground Plane
Table 2-1.
Trace Characteristics Examples
Characteristics Trace Characteristics T(mils) W(mils) S(mils)
H(mils)
High Speed Termination
AT85C51SND3Bx high-speed design requires termination resistor both pins. Place termination resistors close possible AT85C51SND3Bx signal pins.
High Speed Trace Length Matching
High-speed signal pair traces should trace-length matched. trace-length mismatch between high-speed signal pairs should greater than mils.
High Speed Bias Filter
AT85C51SND3Bx high-speed design requires 6.81KW resistor parallel 10pF capacitor connected from UBIAS ground. resistor defines master biasing AT85C51SND3Bx high-speed should placed close possible UBIAS taking care minimize noise injection this point.
High Speed Protection
Full-speed provide suppression using in-line ferrites capacitors that form pass filter. This technique doesn't work high-speed much higher signal rate high-speed data. recommended device that been tested successfully LittelFuse® component, PulseGuard PGB0010603MR (0603 package size). Proper placement devices data lines close possible connector. Other low-capacitance protection devices work well. recommend including footprints this device, some other proven solution, stuffing option case needed pass testing event that problem occurs (general routing placement guidelines should followed).
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High Speed Connectors
order provide direct connection high-speed signals, recommend through AT85C51SND3Bx capability requested, recommend through hole mini-B surface mount reversed mini-B receptacle connector surface mount std-A plug.
Layout Examples
Figure Figure show some examples AT85C51SND3Bx high-speed routing. order allow direct connection AT89C51SND3 controller, reversed mini-AB connector better used avoid signal crossing. Figure 3-1. Reversed Mini Receptacle Routing Example
UVSS Termination Resistors
Analog Ground Plane
Protections Vias ground plane Reversed Mini VBUS connection
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UVSS UBIAS Bias Filter
Figure 3-2.
Reversed Mini Receptacle Routing Example
UVSS Termination Resistors
Protections Vias ground plane Reversed Mini
Analog Ground Plane
VBUS connection
UVSS UBIAS Bias Filter
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Figure 3-3.
Standard Mini Receptacle Routing Example
UVSS UVSS UBIAS
Termination Resistors
Bias Filter
Analog Ground Plane
Protections VBUS connection Standard Mini Vias ground plane
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Figure 3-4.
Standard Mini Receptacle Routing Example
UVSS Termination Resistors
Vias bottom
Analog Ground Plane
Vias ground plane Standard Mini Bottom
VBUS connection
UVSS UBIAS Bias Filter
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7633A-MP3-06/06

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