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Getting Started with AT91SAM7X Microcontrollers
This application note aimed helping reader become familiar with Atmel ARM® Thumb®-based AT91SAM7X microcontroller. describes detail simple project that uses several important features present AT91SAM7X chips. This includes setup microcontroller prior executing application, well functionalities themselves. After going through this guide, reader should able successfully start project from scratch. This document also explains setup toolchain order compile software project. Note that Getting Started example been ported included EWARM 4.41A; reader should disregard section "Building Project" page when using this version. able this document efficiently, reader should experienced using core. more information about core architecture, please refer appropriate documents available from http://www.arm.com.
AT91 Thumb Microcontrollers Application Note
Requirements
software provided with this application notes requires several components: AT91SAM7X Evaluation computer running Microsoft® Windows® 2000/XP cross-compiler toolchain (such YAGARTO) AT91-ISP V1.8 later
6296A-ATARM-27-Mar-07
Getting Started with Software Example
This section describes program basic application that helps become familiar with AT91SAM7X microcontrollers. divided into main sections: first covers specification example (what does, what peripherals used); other details programming aspect.
3.1.1
Specification
Features demonstration program makes LEDs board blink fixed rate. This rate generated using timer first LED; second uses Wait function based tick. blinking stopped using buttons (one each LED). While this software look simple, uses several peripherals which make basis operating system. such, makes good starting point someone wanting become familiar with AT91SAM microcontroller series.
3.1.2
Peripherals order perform operations described previous section, software example uses following peripherals: Parallel Input/Output (PIO) controller Timer Counter (TC) Periodic Interval Timer (PIT) Advanced Interrupt Controller (AIC) Debug Unit (DBGU) LEDs buttons board connected standard input/output pins chip; those managed controller. addition, possible have controller generate interrupt when status pins changes; buttons configured have this behavior. used generate time bases, order obtain blinking rates. They both used interrupt mode: triggers interrupt fixed rate, each time toggling state (on/off). triggers interrupt every millisecond, incrementing variable tick; Wait function monitors this variable provide precise delay toggling second state. Using required manage interrupts. allows configuration separate vector each source; three different functions used handle PIO, interrupts. Finally, additional peripheral used output debug traces serial line: DBGU. Having firmware send debug traces points code greatly help debugging process.
3.1.3 3.1.3.1
Evaluation Booting AT91SAM7X256 found AT91SAM7X-EK evaluation boards features internal memories: Flash SRAM. Getting Started example software compiled loaded both.
Application Note
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3.1.3.2
Buttons AT91SAM7X Evaluation features 5-way joystick, connected pins PA21 (up), PA22 (down), PA23 (left), PA24 (right) PA25 (push). When pressed, they force logical level corresponding line. Getting Started example uses Left (PA23) Right (PA24) joystick positions buttons.
3.1.3.3
LEDs There four general-purpose green LEDs AT91SAM7X-EK; they wired pins PB19, PB20, PB21 PB22. Setting logical level these lines turns corresponding example application uses first LEDs (PB19 PB20).
3.1.3.4
Debug Unit AT91SAM7X, Debug Unit uses pins PA27 PA28 DRXD DTXD signals, respectively.
Implementation
stated previously, example defined above requires several peripherals. must also provide necessary code starting microcontroller. Both aspects described detail this section, with commented source code when appropriate.
3.2.1
C-Startup Most code embedded application written This makes program easier understand, more portable modular. However, using language requires initialization several components. These initialization procedures must performed using assembly language, grouped into file referred C-startup. C-startup code must: Provide exception vectors Initialize critical peripherals Initialize stacks Initialize memory segments These steps described following paragraphs. More information about startup code found AT91 Assembler Code Startup Sequence Code Applications Software application note (literature 2644), available http://www.atmel.com.
3.2.1.1
Exception Vectors When exception occurs (e.g., data abort, undefined instruction, IRQ, etc.), core instantly jumps instructions located between addresses 0x00 0x1C. program does need handle exception, then corresponding instruction simply infinite loop, i.e. branch same address. vectors which handled, branch instruction function must provided. Since address 0x00 used after Reset, associated branch must always jump beginning code. this example, only relevant vector IRQs (excluding Reset vector). must simply branch handler, which described Section 3.2.1.2 page code eight vectors looks like this:
Application Note
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reset_vector: =reset_handler undef_vector: undef_vector Undefined Instruction swi_vector: swi_vector Software Interrupt pabt_vector: =pabt_handler Prefetch Abort dabt_vector: =dabt_handler Data Abort rsvd_vector: rsvd_vector reserved irq_vector: irq_handler read fiq_vector: fiq_vector
3.2.1.2
Exception Vectors: Handler main purpose handler fetch correct jump address pending interrupt. This information held Interrupt Vector Register (IVR) (see Section 3.2.3 page more information about AIC). Once address loaded, handler just branches This done follows:
r14, =AT91C_BASE_AIC [r14, #AIC_IVR]
Registers banked, which means they shared between (almost) modes. Since r0-r3 defined scratch registers calling convention, they must saved prior jump. addition, contains interrupt handler return address plus must also decremented then saved. following code saves registers stack jumps interrupt vector:
r14, r14, stmfd sp!, {r0-r3, r12, r14} r14, =AT91C_BASE_AIC [r14, #AIC_IVR]
final step acknowledge pending interrupt writing anything Interrupt Command Register), restore registers then jump back main program:
r14, =AT91C_BASE_AIC r14, [r14, #AIC_EOICR] ldmfd sp!, {r0-r3, r12, pc}^
Note that such handler does allow nested interrupts (since IRQs masked when core enters mode). 3.2.1.3 Low-Level Initialization first step initialization process configure critical peripherals: Embedded Flash Controller (EFC)
Application Note
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Main oscillator Advanced Interrupt Controller Watchdog These operations often grouped into function. Since likely function tries access stack, stack pointer (r13) must memory address before call:
=STACK_ADDR =AT91C_LowLevelInit
After carrying these actions, program jump main application. following sections explain these peripherals considered critical, detail required operations configure them properly. 3.2.1.4 Low-Level Initialization: Embedded Flash Controller Whenever microcontroller core runs fast internal Flash, uses more wait states, i.e. cycles during which does nothing wait memory. number wait states configured EFC. After reset, chip uses internal slow clock (cadenced kHz), there need wait state. However, before switching main oscillator order full-speed), correct number wait states must set. not, core longer able read code from Flash. Configuring number wait states done Flash Mode Register (FMR) EFC. example, operation requires wait state:
AT91C_BASE_MC->MC_FMR AT91C_FMR_FWS_1FWS;
more information about required number wait states depending operating frequency microcontroller, please refer Electrical Characteristics section corresponding datasheet. 3.2.1.5 Low-Level Initialization: Main Oscillator After reset, chip running using slow clock, which cadenced kHz. main oscillator Phase Lock Loop (PLL) must configured order full speed. Both configured Power Management Controller (PMC). first step enable main oscillator wait stabilize. Writing oscillator startup time MOSCEN Main Oscillator Register (MOR) starts oscillator; stabilization occurs when MOSCS Status Register becomes set. following piece code performs these operations:
AT91C_BASE_PMC->PMC_MOR (AT91C_CKGR_OSCOUNT (0x8 AT91C_CKGR_MOSCEN; while (!(AT91C_BASE_PMC->PMC_SR AT91C_PMC_MOSCS));
Calculation correct oscillator startup time value done looking characteristics given datasheet product. Note that internal slow clock AT91SAM7X generated using oscillator; this must taken into account this impacts slow clock accuracy. Here example: oscillator frequency range kHz:
Application Note
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Oscillator frequency range MHz: Osc20 Oscillator frequency
18.432MHz
Oscillator startup time: Startup1.4ms Value startup: OSCOUNT 42000 0.0014
Once oscillator started stabilized, configured. made chained blocks: first divides input clock, while second multiplies factors Register (PLLR) PMC. These values must chosen according main oscillator (input) frequency desired main clock (output) frequency. addition, multiplication block minimum input frequency, master clock maximum allowed frequency; these constraints have taken into account. calculator (available http://www.atmel.com) used compute best values. Example given AT91SAM7X-EK:
Input 18.432 18.432 Output 96.109MHz
Like main oscillator, startup time must also provided. Again, calculated looking characteristics given datasheet corresponding microcontroller. After PLLR modified with configuration values, software must wait become locked; this done monitoring Status Register PMC.
AT91C_BASE_PMC->PMC_PLLR AT91C_CKGR_OUT_0 (AT91C_CKGR_PLLCOUNT (AT91C_CKGR_MUL 16)) (AT91C_CKGR_DIV 14); while(!(AT91C_BASE_PMC->PMC_SR AT91C_PMC_LOCK));
Finally, prescaling value main clock must set, output selected. Note that prescaling value must first, avoid having chip frequency higher than maximum operating frequency defined characteristics. such, this step done using register writes, with loops wait main clock ready:
AT91C_BASE_PMC->PMC_MCKR AT91C_PMC_PRES_CLK_2; while (!(AT91C_BASE_PMC->PMC_SR AT91C_PMC_MCKRDY)); AT91C_BASE_PMC->PMC_MCKR AT91C_PMC_CSS_PLL_CLK; while (!(AT91C_BASE_PMC->PMC_SR AT91C_PMC_MCKRDY));
this point, chip configured main clock with PLL, desired frequency. 3.2.1.6 Low-Level Initialization: Advanced Interrupt Controller properly described Section 3.2.3 page Low-Level Initialization: Watchdog Watchdog peripheral enabled default after processor reset. application does which case this example, then shall disabled Watchdog Mode Register (WDMR):
3.2.1.7
Application Note
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AT91C_BASE_WDTC->WDTC_WDMR AT91C_WDTC_WDDIS;
3.2.1.8
Initializing Stacks Each mode stack pointer (register sp); thus, each mode which used application must have stack initialized. Since stacks descending, i.e. stack pointer decreases value when data stored, first stack pointer located internal SRAM. particular length reserved each mode, depending uses. Supervisor user modes usually have stacks, modes have medium-sized stack, other modes most often have only bytes. this example, only Supervisor (SVC) modes used. Stack initialization done entering each mode after another, setting correct value. memory address stored register, decremented each time stack pointer set. Note that interrupts masked (i.e., bits set) during this whole process, except last mode (only set). This results following code:
Load memory address =IRAMEND Enter Interrupt mode, setup stack CPSR_c, #ARM_MODE_IRQ I_BIT F_BIT r13, #IRQ_STACK_SIZE Enter Supervisor mode, setup stack, IRQs unmasked CPSR_c, #ARM_MODE_SVC F_BIT r13,
3.2.1.9
Initializing Data Segments binary file usually divided into segments: first holds executable code application, well read-only data (declared const second segment contains read/write data, i.e., data that modified. These sections called text data, respectively. Variables data segment said either uninitialized initialized. first case, programmer particular value when declaring variable; conversely, variables fall second case when they have been declared with value. Unitialized variables held special subsection called (for Block Started Symbol). Whenever application loaded internal Flash memory chip, Data segment must initialized startup. This necessary because read/write variables located SRAM, Flash. Depending toolchain used, there might library function doing this; example, Embedded Workbench® provides _segment_init(). Initialized data contained binary file loaded with rest application memory. Usually, located right after text segment. This makes easy retrieve starting ending address data copy. load these addresses faster, they explicitly stored code using compiler-specific instruction. Here example toolchain:
_lp_data: .word _etext .word _sdata .word _edata
Application Note
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actual copy operation consists loading these values several registers, looping through data:
_init_data: ldrcc [r1], =_lp_data _branch_main ldmia {r1,
strcc [r3],
addition, both safer more useful debug purposes initialize segment filling with zeroes. Theoretically, this operation unneeded; however, have several benefits. example, makes easier when debugging which memory regions have been modified. This valuable tool spotting stack overflow similar problems. Initialization Data segments similar, except register initialized zero after ldmia instruction never modified (c.f. above code). 3.2.2 3.2.2.1 Generic Peripheral Usage Initialization Most peripherals initialized performing three actions Enabling peripheral clock Enabling control peripheral pins Configuring interrupt source peripheral Enabling interrupt source peripheral level Most peripherals clocked default. This makes possible reduce power consumption system startup. However, requires that programmer explicitly enable peripheral clock. This done Power Management Controller (PMC). Exception made System Controller (which comprises several different controllers), continuously clocked. peripherals which need more pins chip external inputs/outputs, necessary configure Parallel Input/Output controller first. This operation described more detail Section 3.2.6 page Finally, interrupt generated peripheral, then source must configured properly Advanced Interrupt Controller. Please refer Section 3.2.3 page more information. 3.2.3 3.2.3.1 Using Advanced Interrupt Controller Purpose manages internal external interrupts system. enables definition handler each interrupt source, i.e., function which called whenever corresponding event occurs. Interrupts also individually enabled masked, have several different priority levels.
Application Note
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example software, using required because several interrupt sources present (see Section 3.1.2 page 3.2.3.2 Initialization Unlike most other peripherals, always clocked cannot shut down. Therefore, there need enable peripheral clock PMC. only mandatory action perform this point disable clear interrupts. This done with these instructions:
Disable interrupts AT91C_BASE_AIC->AIC_IDCR 0xFFFFFFFF; Clear interrupts AT91C_BASE_AIC->AIC_ICCR 0xFFFFFFFF;
debug purposes, good practice dummy handlers (i.e., which loop indefinitely) interrupt sources. This way, interrupt triggered before being configured, debugger stuck handler instead jumping random address. addition, application which perform processor reset (i.e., reset core without resetting peripherals) must write Interrupt Command Register (EOICR) eight times. This necessary clear interrupt which have been pushed internal hardware stack during previous execution program. 3.2.3.3 Configuring Interrupt Configuring interrupt source requires five steps: Disable interrupt case enabled Configure interrupt Source Mode Register Configure interrupt Source Vector Register Enable interrupt peripheral level Enable interrupt level first step disable interrupt source. interrupt triggering same time that mode vector registers read result unpredictable behavior system. Interrupt Disable Command Register (IDCR) must written with interrupt source mask Please refer corresponding datasheet list peripheral IDs. There parameters Source Mode Register: interrupt priority trigger mode. former completely programmer; interrupt have priority between (lowest) (highest). Internal interrupts (i.e., coming from peripherals) must always configured level-sensitive; external interrupt (i.e., IRQ[0.3], FIQ) shall setup depending they have been wired chip. Source Vector Register contains address handler function interrupt. function pointer must cast unsigned long value avoid generating warning when setting SVR. Finally, interrupt source enabled, both peripheral mode register usually) Interrupt Enable Command Register (IECR) AIC. this point, interrupt fully configured operational.
Application Note
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3.2.4 3.2.4.1
Using Timer Counter Purpose Timer Counters AT91SAM chips perform several functions, e.g., frequency measurement, pulse generation, delay timing, Pulse Width Modulation (PWM), etc. this example, single Timer Counter channel going provide fixed-period delay. interrupt generated each time timer expires, toggling associated off. This makes blink fixed rate.
3.2.4.2
Initialization order reduce power consumption, most peripherals clocked default. Writing peripheral Peripheral Clock Enable Register (PCER) Power Management Controller (PMC) activates clock. This first step when initializing Timer Counter. then disabled, case been turned previous execution program. This done setting CLKDIS corresponding Channel Control Register (CCR). example, timer channel used. next step configure Channel Mode Register (CMR). channels operate different modes. first one, which referred Capture mode, normally used performing measurements input signals. second one, Waveform mode, enables generation pulses. example, purpose generate interrupt fixed rate. Actually, such operation possible both Capture Waveform mode. Since signal being sampled generated, there reason choose mode over other. However, setting Waveform mode outputting tick TIOA TIOB helpful debugging purpose. Setting CPCTRG resets timer restarts clock every time counter reaches value programmed Register Generating specific delay thus done choosing correct value also possible choose between several different input clocks channel, which practice makes possible prescale MCK. Since timer resolution bits, using high prescale factor necessary bigger delays. Consider following example: timer must generate delay with main clock frequency. must equal number clock cycles generated during delay period; here results with different prescaling factors:
Clock 24000000 12000000 Clock 6000000 3000000 Clock 375000 187500 Clock 46875 23437.5 1024 Clock 32kHz, 32768 16384
Since maximum value 65535, clear from these results that using divided 1024 internal slow clock necessary generating long (about delays. example, delay used; this means that slowest possible input clock selected CMR, corresponding value written following operations configure period selecting slow clock dividing frequency
Application Note
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AT91C_BASE_TC0->TC_CMR AT91C_TC_CLKS_TIMER_DIV5_CLOCK AT91C_TC_CPCTRG; AT91C_BASE_TC0->TC_RC AT91B_SLOW_CLOCK
last initialization step configure interrupt whenever counter reaches value programmed level, this easily done setting CPCS Interrupt Enable Register. Refer Section 3.2.3.3 page more information configuring interrupts AIC. 3.2.4.3 Interrupt Handler first action handler acknowledge pending interrupt from peripheral. Otherwise, latter continues assert line. case Timer Counter channel, acknowledging done reading corresponding Status Register (SR). Special care must taken avoid having compiler optimize away dummy read this register. this done declaring volatile local variable setting register content. volatile keyword tells compiler never optimize accesses (read/write) variable. rest interrupt handler straightforward. simply toggles state off) blinking LED. Refer Section 3.2.6 page more details control LEDs with controller. 3.2.5 3.2.5.1 Using Periodic Interval Timer Purpose primary goal Peripheral Interval Timer (PIT) generate periodic interrupts. This most often used provide base tick operating system. uses divided input clock, well 20-bit counter. Each time counter reaches programmable value, interrupt generated, second counter increments. latter makes possible never miss tick, even when system overloaded. getting started example uses provide time base. Each time interrupt triggered, 32-bit counter incremented. Wait function uses this counter provide precise application suspend itself specific amount time. 3.2.5.2 Initialization Since part System Controller, continuously clocked. such, there need enable peripheral clock PMC. Mode Register contains Periodic Interval Value (PIV) which indicates when reset internal counter. must programmed number ticks generated MCK/16 millisecond:
This done with following line code:
AT91C_BASE_PITC->PITC_PIMR AT91B_MCK 1000)
Before starting timer, interrupt must configured AIC. Please refer Section 3.2.3.3 page more information about that step. Once configuration done, interrupt enabled Mode Register setting PITIEN; also started same operation setting PITEN.
Application Note
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3.2.5.3
Interrupt Handler Acknowledging interrupt implicitly done when reading Value Register. This register contains values: current value internal counter (CPIV), number ticks that have been generated since last read PIVR (Periodic Interval Counter, PICNT). second register, Image Register, contains same values does acknowledge pending interrupt. interrupt handler thus very simple. First, PIVR value read retrieve PICNT. global variable incremented with number ticks read. Note that necessary check whether there really pending interrupt PIT; since system controller interrupt shared several peripheral, them have triggered This verified reading Status Register PIT; PITS when interrupt pending. Finally, using 32-bit counter always appropriate, depending long system should stay tick period. example, tick overflows counter after about days; this enough real application. that case, larger counter implemented.
3.2.5.4
Wait Function Using global counter, wait function taking number milliseconds parameter very easy implement. When called, function first saves current value global counter local variable. adds requested number milliseconds which been given argument. Then, simply loops until global counter becomes equal greater than computed value. proper implementation, global counter must declared with volatile keyword Otherwise, compiler might decide that being empty loop prevents modification counter; obviously, this case since altered interrupt handler.
3.2.6 3.2.6.1
Using Parallel Input/Output controller Purpose Most pins AT91SAM microcontrollers either used peripheral function (e.g. USART, SPI, etc.) used generic input/outputs. those pins managed more Parallel Input/Output (PIO) controllers. controller enables programmer configure each used associated peripheral generic second case, level read/written using several registers controller. Each also have internal pull-up activated individually. addition, controller detect status change more pins, optionally triggering interrupt whenever this event occurs. Note that generated interrupt considered internal AIC, must configured level-sensitive (see Section 3.2.3.3). this example, controller manages LEDs buttons. buttons configured trigger interrupt when pressed defined Section 3.1.1 page
3.2.6.2
Initialization There step initializing controller. First, peripheral clock must enabled PMC. After that, interrupt source configured AIC.
Application Note
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3.2.6.3
Configuring LEDs PIOs connected LEDs must configured outputs, order turn them off. First, PIOC control must enabled Enable Register (PER) writing value corresponding logical between IDs. direction controlled using registers: Output Enable Register (OER) Output Disable Register (ODR). Since this case PIOs must output, same value before shall written OER. Note that there individual internal pull-ups each pin. These pull-ups enabled default. Since they useless driving LEDs, they should disabled, this reduces power consumption. This done through Pull Disable Register (PUDR) PIOC. Here code configuration:
Configure pins outputs AT91C_BASE_PIOA->PIO_OER (LED_A LED_B); Enable PIOC control pins*/ AT91C_BASE_PIOA->PIO_PER (LED_A LED_B); Disable pull-ups AT91C_BASE_PIOA->PIO_PPUDR (LED_A LED_B);
3.2.6.4
Controlling LEDs LEDs turned changing level PIOs which they connected. After those PIOs have been configured, their output values changed writing Output Data Register (SODR) Clear Output Data Register (CODR) controller. addition, register indicates current level each (Pin Data Status Register, PDSR). used create toggle function, i.e. when according PDSR, then turned off, vice-versa.
Turn AT91C_BASE_PIOA->PIO_SODR LED_A; Turn AT91C_BASE_PIOA->PIO_CODR LED_A;
3.2.6.5
Configuring Buttons stated previously, PIOs connected switches board shall inputs. Also, "state change" interrupt configured both buttons. This triggers interrupt when button pressed released. After PIOC control been enabled PIOs writing PER), they configured inputs writing their ODR. Conversely LEDs, necessary keep pull-ups enabled. Enabling interrupts pins simply done Interrupt Enable Register (IER). However, controller interrupt must configured described Section 3.2.3.3 page
Application Note
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3.2.6.6
Interrupt Handler interrupt handler controller must first check which button been pressed. PDSR indicates level each pin, show each button currently pressed not. Alternatively, Interrupt Status Register (ISR) reports which PIOs have their status changed since last read register. example software, combined detect state change interrupt well particular level pin. This corresponds either press release action button. said application description (Section 3.1.1 page each button enables disables blinking LED. variables used boolean values, indicate either blinking. When status which toggled Timer Counter modified, clock either stopped restarted interrupt handler well. Note that interrupt must acknowledged PIOC. This done implicitly when read software. However, conversely Timer Counter (see Section 3.2.4.3 page 11), since value actually used several operations, there need worry about compiler inadvertantly
3.2.7 3.2.7.1
Using Debug Unit Purpose Debug Unit provides two-pins Universal Asynchronous Receiver Transmitter (UART) well several other debug functionalities. UART ideal outputting debug traces terminal, In-System Programming (ISP) communication port. Other features include chip identification registers, management debug signals from core, DBGU used example output single string text whenever application starts. configured with baudrate 115200, bits data, parity, stop flow control.
3.2.7.2
Initialization Debug Unit part System Controller peripheral, there need enable clock PMC. DBGU continuously clocked cannot disabled. However, necessary configure pins (DTXD DRXD) controller. Writing both Disable Register (PDR) corresponding controller enables peripheral control those pins. However, some PIOs shared between different peripherals; Peripheral Select Register (ASR) Peripheral Selected Register (BSR) used switch control between two. very next action perform disable receiver transmitter logic, well disable interrupts. This enables smooth reconfiguration peripheral case already been initialized during previous execution application. Setting bits RSTRX RSTTX Control Register (CR) DBGU resets disables received transmitter, respectively. Setting bits Interrupt Disable Register (IDR) disable interrupts coming from Debug Unit.
Application Note
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baud rate clock must input clock equal divided programmable factor. Clock Divisor value held Baud Rate Generate Register (BRGR). following values possible: Table 3-1.
Value 65535
Possible Values Clock Divisor field BRGR
Comment Baud rate clock disabled Baud rate clock divided Baud rate clock divided
following formula used compute value given microcontroller operating frequency desired baud rate:
Baudrate
example, 115200 baud rate obtained with 48MHz master clock frequency writing value Obviously, there slight deviation from desired baudrate; these values yield true rate 115384 bauds. However, mere 1.6% error, does have impact practice. Mode Register (MR) configurable values. first Channel Mode which DBGU operating. Several modes available testing purpose; this example, only normal mode interest. Setting CHMODE field null-value selects normal mode. also possible configure parity Mode Register. Even, odd, mark space parity calculations supported. example, parity being used (PAR value 1xx). DBGU features Peripheral Controller. enables faster transfer data reduces processor overhead taking care most transmission reception operations. used this example, should disabled setting bits RXTDIS TXTDIS Transfer Control Register (PTCR) DBGU. this point DBGU fully configured. last step enable transmitter; received being used this demo application, useless (but harmful) enable well. Transmitter enabling done setting TXEN Control Register. 3.2.7.3 Sending Character Transmitting character DBGU line simple: writing character value Transmit Holding Register (THR) starts transfer. However, transmitter must ready this time. bits DBGU Status Register (SR) indicate transmitter state. TXEMPTY indicates transmitter enabled sending characters. set, character being currently sent DBGU line. second meaningful TXRDY. When this set, transmitter finished copying value internal shift register that uses sending data. practice, this means that written when TXRDY set, regardless value TXEMPTY. When TXEMPTY rises, whole transfer finished. 3.2.7.4 String Print Function dbgu_print_ascii() function defined example application. takes string pointer argument, sends across DBGU.
Application Note
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operation quite simple. C-style strings simple byte arrays terminated null value. Thus, function just loops outputs characters array until zero encountered. 3.2.7.5 Hexadecimal Print Function Another print function, dbgu_print_hex8(), outputs word bits) value hexadecimal format. This function takes unsigned value argument. loop displays each byte, starting with upper one. This done shifting byte rightmost (lowest) position masking
Building Project
development environment this getting started running Microsoft® Windows® required software tools building project loading binary file are: cross-compiler toolchain AT91-ISP v1.8 later (available www.atmel.com).
connection between board achieved with cable.
Compiler Toolchain
generate binary file downloaded into target, YAGARTO compiler toolchain (www.yagarto.de). This toolchain provides assembler, compiler, linker tools. Useful programs debug also included. also require another software that included into Yagarto package: make utility. installing unxutils package available unxutils.sourceforge.net.
4.1.1
Makefile Makefile contains rules indicating assemble, compile link project source files create binary file ready downloaded target. makefile divided into parts, variables settings, other rules implementation.
4.1.1.1
Variables first part Makefile contains variables (uppercase), used some environment parameters, such compiler toolchain prefix program names, options used with compiler.
CROSS_COMPILE=arm-elf-
Defines cross-compiler toolchain prefix.
Outfile name (without extension).
Application Note
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INCL=././include
Paths header files.
OPTIM
Level optimization used during compilation (-Os optimizes size).
AS=$(CROSS_COMPILE)gcc CC=$(CROSS_COMPILE)gcc LD=$(CROSS_COMPILE)gcc $(CROSS_COMPILE)nm SIZE=$(CROSS_COMPILE)size OBJCOPY=$(CROSS_COMPILE)objcopy OBJDUMP=$(CROSS_COMPILE)objdump
Names cross-compiler toolchain binutils (assembler, compiler, linker, symbol list extractor, etc.).
$(OPTIM)CCFLAGS=-g -mcpu=arm7tdmi $(OPTIM) -Wall -I$(INCL)
Compiler options: generate debugging information usage. -mcpu arm7tdmi type core. indicates only compile file, link (link done later, when code files compiled). -Wall: displays warnings. -I$(INCL): paths include files.
ASFLAGS=-D_ASSEMBLY_ -mcpu=arm7tdmi -Wall -I$(INCL)
Assembler options: -D_ASSEMBLY_ defines _ASSEMBLY_ symbol, which used header files distinguish inclusion file assembly code code.
LDFLAGS+=-nostartfiles -Wl,-cref LDFLAGS+=-lc -lgcc LDFLAGS+=-T elf32-littlearm.lds
Linker options: -nostartfile: standard system startup files when linking. -Wl,-cref: Pass -cref option linker (generates cross-reference file this requested). -lc: standard library. -lgcc: library. elf32-littlearm.lds: file elf32-littlearm.lds linker file.
Application Note
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OBJS=cstartup.o OBJS+= lowlevel.o main.o
List object file names.
more detailed information about options, please refer documentation (gcc.gnu.org). 4.1.1.2 Rules second part contains rules. Each rule composed same line target name, files needed create this target. first rule, `all', default rule used make command none specified command line.
all: sram flash
following rules create object files from corresponding source files. option tells compiler assembler, linker.
main.o: main.c $(CC) $(CCFLAGS) main.c main.o lowlevel.o: lowlevel.c $(CC) $(CCFLAGS) lowlevel.c lowlevel.o cstartup.o: cstartup.S $(AS) $(ASFLAGS) cstartup.S cstartup.o
last rules describe compile source files link object files together generate binary file configuration: program running Flash program running RAM. describes compile source files link object files together. first line calls linker with previously defined flags, addresses text data segments -Ttext address -Tdata address options. This generates format file, which converted binary file without debug information using objcopy program.
sram: $(OBJS) $(LD) $(LDFLAGS) -Ttext 0x201000 -Tdata 0x200000 $(OUTFILE_SRAM).elf $(OBJS) $(OBJCOPY) -strip-debug -strip-unneeded $(OUTFILE_SRAM).elf binary $(OUTFILE_SRAM).bin $(OUTFILE_FLASH).bin flash: $(OBJS) $(LD) $(LDFLAGS) -Ttext 0x100000 -Tdata 0x200000 $(OUTFILE_FLASH).elf $(OBJS) $(OBJCOPY) -strip-debug -strip-unneeded $(OUTFILE_FLASH).elf binary $(OUTFILE_FLASH).bin
Application Note
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4.1.2
Linker File link stage, elf32-littlearm.lds file sent option linker. This file describes order which linker must different memory sections into binary file. addresses indicated -Ttext -Tdata options linker command line (see Makefile chapter).
4.1.2.1
Header
"elf32-littlearm", "elf32-littlearm")
object file format elf32-littlearm.
OUTPUT_ARCH(arm)
Specify machine architecture.
ENTRY(reset)
symbol `reset' entry point program. 4.1.2.2 Section Organization SECTION part deals with different sections code used project. tells linker where sections finds while parsing project object files. .vectors: exception vector table handler .text: code .data: initialized data .bss: uninitialized data
SECTIONS .text _stext *(.text) *(.rodata) *(.rodata*) ALIGN(4); _etext collect initialized .data sections that into FLASH .data ADDR (.text) SIZEOF (.text) _sdata *(.vectors) *(.data) _edata collect uninitialized .bss sections that into FLASH .bss (NOLOAD) ALIGN(4); _sbss
Application Note
6296A-ATARM-27-Mar-07
*(.bss) _ebss
.text section, _stext symbol order retrieve this address runtime, then .text, .rodata sections found object file placed here, finally _etext symbol aligned byte address. same operation done with .data .bss sections. .data section, (ADDR (.text) SIZEOF(.text)) command specifies that load address (the address binary file after link step) this section just after .text section. Thus there hole between these sections. .vectors section (defined cstartup.S file) placed just before .data section. Providing link address beginning internal allows this section automatically copied right place when reset handler copies .data section RAM.
Loading Code
Once build step completed, .bin file available ready loaded into board. AT91-ISP solution offers easy download files into AT91 products Atmel Evaluation Kits through USB, J-TAG link. Target programming done here SAM-BAtools. batch files (prog_sram.bat prog_flash.bat) script files (prog_sram.tcl prog_flash.tcl) provided process loading binary file. .bat file launches SAM-BA command line mode. Parameters provided SAM-BA are: connection link used, target board, .tcl script file use. .tcl script file contains indications about name file load, which memory module used, address code loading, operates command code start address. file displayed loading process. Follow steps below load code: Shut down board. jumper board erase internal Flash. Plug cable between board wait seconds. Shut down board remove jumper. Plug cable between board. Execute prog_sram.bat file test code running internal SRAM. Execute prog_flash.bat file test code running internal Flash.
code then starts running, LEDs controlled push buttons.
Application Note
6296A-ATARM-27-Mar-07
Application Note
Debug Support
When debugging Getting Started example with GDB, best disable compiler optimizations. Otherwise, source code will correctly match actual execution program. that, simply comment (with `#') "OPTIM -Os" line makefile rebuild project. more information debugging with GDB, refer Atmel application note GNU-Based Software Development manual available gcc.gnu.org.
6296A-ATARM-27-Mar-07
Revision History
Table 5-1.
Document Ref. 6296A Comments First issue. Change Request Ref.
Application Note
6296A-ATARM-27-Mar-07
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