AT91 Thumb-based Microcontrollers AT91SAM7SE512 AT91SAM7SE256 AT91SAM7
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High-performance 32-bit RISC Architecture High-density 16-bit Instruction Leader MIPS/Watt EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash Kbytes, Organized Contiguous Banks 1024 Pages Bytes Dual Plane (AT91SAM7SE512) Kbytes (AT91SAM7SE256) Organized Bank 1024 Pages Bytes Single Plane (AT91SAM7SE256) Kbytes (AT91SAM7SE32) Organized Bank Pages Bytes Single Plane (AT91SAM7SE32) Single Cycle Access Worst Case Conditions Prefetch Buffer Optimizing Thumb Instruction Execution Maximum Speed Page Programming Time: Including Page Auto-erase, Full Erase Time: 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Fast Flash Programming Interface High Volume Production Kbytes (AT91SAM7SE512/256) Kbytes (AT91SAM7SE32) Internal High-speed SRAM, Single-cycle Access Maximum Speed External Interface (EBI) Supports SDRAM, Static Memory, Glueless Connection CompactFlash® ECC-enabled NAND Flash Memory Controller (MC) Embedded Flash Controller Memory Protection Unit Abort Status Misalignment Detection Reset Controller (RSTC) Based Power-on Reset Cells Low-power Factory-calibrated Brownout Detector Provides External Reset Signal Shaping Reset Source Status Clock Generator (CKGR) Low-power Oscillator, On-chip Oscillator Power Management Controller (PMC) Power Optimization Capabilities, Including Slow Clock Mode (Down Idle Mode Three Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) Two-wire UART Support Debug Communication Channel interrupt, Programmable Access Prevention Periodic Interval Timer (PIT) 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) 12-bit key-protected Programmable Counter Provides Reset Interrupt Signals System
AT91 Thumb-based Microcontrollers AT91SAM7SE512 AT91SAM7SE256 AT91SAM7SE32 Preliminary
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Counter Stopped While Processor Debug State Idle Mode
Real-time Timer (RTT)
32-bit Free-running Counter with Alarm Runs Internal Oscillator Three Parallel Input/Output Controllers (PIO) Eighty-eight Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up Resistor Synchronous Output Schmitt Trigger inputs Eleven Peripheral Controller (PDC) Channels Full Speed Mbits second) Device Port On-chip Transceiver, Eight Endpoints, 2688-byte Configurable Integrated FIFOs Synchronous Serial Controller (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation Support ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Full Modem Line Support USART1 Master/Slave Serial Peripheral Interfaces (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three-channel 16-bit Timer/Counter (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Four-channel 16-bit Controller (PWMC) Two-wire Interface (TWI) Master, Multi-Master Slave Mode Support, Two-wire Atmel EEPROMs Supported General Call Supported Slave Mode 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os SAM-BA- Default Boot program Interface with SAM-BA Graphic User Interface IEEE® 1149.1 JTAG Boundary Scan Digital Pins Four High-current Drive lines, Each Power Supplies Embedded 1.8V Regulator, Drawing Core External Components 1.8V 3,3V VDDIO Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply 1.8V VDDCORE Core Power Supply with Brownout Detector Fully Static Operation: 1.8V 85°C Worst Case Conditions 1.65V 85°C Worst Case Conditions Available 128-lead LQFP Green Package, 144-ball LFBGA RoHS-compliant Package
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Description
Atmel's AT91SAM7SE Series member Smart Microcontroller family based 32-bit ARM7RISC processor high-speed Flash memory. AT91SAM7SE512 features Kbyte high-speed Flash Kbyte SRAM. AT91SAM7SE256 features Kbyte high-speed Flash Kbyte SRAM. AT91SAM7SE32 features Kbyte high-speed Flash Kbyte SRAM. also embeds large peripherals, including device, External Interface (EBI), complete system functions minimizing number external components. incorporates controllers synchronous DRAM (SDRAM) Static memories features specific circuitry facilitating interface NAND Flash, SmartMedia CompactFlash. device ideal migration path 8/16-bit microcontroller users looking additional performance, extended memory higher levels system integration. embedded Flash memory programmed in-system JTAG-ICE interface parallel interface production programmer prior mounting. Built-in lock bits security protect firmware from accidental overwrite preserve confidentiality. AT91SAM7SE Series system controller includes reset controller capable managing power-on sequence microcontroller complete system. Correct device operation monitored built-in brownout detector watchdog running integrated oscillator. combining ARM7TDMI processor with on-chip Flash SRAM, wide range peripheral functions, including USART, SPI, External Interface, Timer Counter, Analog-to-Digital Converters monolithic chip, AT91SAM7SE512/256/32 powerful device that provides flexible, cost-effective solution many embedded control applications.
Configuration Summary AT91SAM7SE512, AT91SAM7SE256 AT91SAM7SE32
AT91SAM7SE512, AT91SAM7SE256 AT91SAM7SE32 differ memory sizes organization. Table below summarizes configurations three devices.
Table 1-1.
Device
Configuration Summary
Flash Size 512K bytes 256K bytes bytes Flash Organization dual plane single plane single plane Size bytes bytes bytes
AT91SAM7SE512 AT91SAM7SE256 AT91SAM7SE32
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Block Diagram
Figure 2-1. AT91SAM7SE512/256/32 Block Diagram Signal Description
JTAGSEL
JTAG SCAN
ARM7TDMI Processor 1.8V Voltage Regulator Memory Controller Embedded Address Flash Decoder Controller Abort Status Misalignment Detection Flash
Kbytes (SE512) Kbytes (SE256) Kbytes (SE32) VDDFLASH ERASE VDDIN VDDOUT VDDCORE
System Controller
IRQ0-IRQ1
SRAM
Kbytes (SE512/256) Kbytes (SE32)
VDDIO
DRXD DTXD
DBGU
PCK0-PCK2 PLLRC XOUT
RCOSC
Memory Protection Unit
Peripheral Bridge
VDDFLASH VDDCORE VDDCORE NRST
Reset Controller
Peripheral Controller Channels
PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1
Fast Flash Programming Interface
SAM-BA
PIOA PIOB PIOC
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 ADTRG ADVREF
USART0 USART1 CompactFlash NAND Flash
SDRAM Controller
Timer Counter
Static Memory Controller
Controller
Transciever
D[31:0] A0/NBS0 A1/NBS2 A[15:2], A[20:18] A21/NANDALE A22/REG/NANDCLE A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2/CFCS1 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NBS3/CFIOW SDCKE SDWE SDA10 CFRNW NCS4/CFCS0 NCS5/CFCE1 NCS6/CFCE2 NCS7 NANDOE NANDWE NWAIT SDCK
FIFO Device
PWMC
PWM0 PWM1 PWM2 PWM3 TWCK
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Signal Description
Table 3-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL
Voltage Regulator Power Supply Input Voltage Regulator Output Flash Power Supply Lines Power Supply Core Power Supply Ground
Power Power Power Power Power Power Ground
3.6V 1.85V 3.6V 3.6V 1.65V 1.95V 1.65V 1.95V 1.65V 1.95V
Clocks, Oscillators PLLs XOUT PLLRC PCK0 PCK2 Main Oscillator Input Main Oscillator Output Filter Programmable Clock Output Input Output Input Output JTAG JTAGSEL Test Clock Test Data Test Data Test Mode Select JTAG Selection Input Input Output Input Input Flash Memory ERASE Flash Configuration Bits Erase Command Input Reset/Test NRST Microcontroller Reset Test Mode Select Input Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data IRQ0 IRQ1 External Interrupt Inputs Fast Interrupt Input Input Input Input Output High Open drain with pull-up resistor Pull-down resistor High Pull-down resistor pull-up resistor. Pull-down resistor pull-up resistor pull-up resistor
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Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Active Level Comments
PA31 PB31 PC23
Parallel Controller Parallel Controller Parallel Controller
Device Port
Pulled-up input reset Pulled-up input reset Pulled-up input reset
Device Port Data Device Port Data
Analog Analog USART
SCK0 SCK1 TXD0 TXD1 RXD0 RXD1 RTS0 RTS1 CTS0 CTS1 DCD1 DTR1 DSR1
Serial Clock Transmit Data Receive Data Request Send Clear Send Data Carrier Detect Data Terminal Ready Data Ready Ring Indicator
Input Output Input Input Output Input Input Synchronous Serial Controller
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input Timer/Counter
TCLK0 TCLK2 TIOA0 TIOA2 TIOB0 TIOB2
External Clock Inputs Timer Counter Line Timer Counter Line
Input Controller
PWM0 PWM3
Channels
Output Serial Peripheral Interface
MISO MOSI SPCK NPCS0 NPCS1-NPCS3
Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select
Output
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Two-Wire Interface Active Level Comments
TWCK
Two-wire Serial Data Two-wire Serial Clock
Analog-to-Digital Converter
AD0-AD3 AD4-AD7 ADTRG ADVREF
Analog Inputs Analog Inputs Trigger Reference
Analog Analog Input Analog Fast Flash Programming Interface
Analog Inputs Digital pulled-up inputs reset
PGMEN0-PGMEN2 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD
Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command
Input Input Output Output Input Input Input External Interface High
D[31:0] A[22:0] NWAIT
Data Address External Wait Signal
Output Input Static Memory Controller
NCS[7:0] NWR[1:0]
Chip Select Lines Write Signals Read Signal Write Enable NUB: Upper Byte Select NLB: Lower Byte Select
Output Output Output Output Output Output CompactFlash Support
CFCE[2:1] CFOE CFWE CFIOR CFIOW CFRNW CFCS[1:0]
CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read Signal CompactFlash Write Signal CompactFlash Read Write Signal CompactFlash Chip Select Lines
Output Output Output Output Output Output Output
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Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type NAND Flash Support Active Level Comments
NANDCS NANDOE NANDWE NANDCLE NANDALE
NAND Flash Chip Select Line NAND Flash Output Enable NAND Flash Write Enable NAND Flash Command Line Enable NAND Flash Address Line Enable
Output Output Output Output Output
SDRAM Controller SDCK SDCKE SDCS BA[1:0] SDWE NBS[3:0] SDA10 Note: SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Line Bank Select SDRAM Write Enable Column Signal Byte Mask Signals SDRAM Address Line Refer Section "I/O Lines Considerations" Output Output Output Output Output Output Output Output High Tied after reset
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Package
AT91SAM7SE512/256/32 available 128-lead LQFP package with lead pitch. 144-ball LFBGA package with lead pitch
128-lead LQFP Package Outline
Figure shows orientation 128-lead LQFP package detailed mechanical description given Mechanical Characteristics section full datasheet.
Figure 4-1.
128-lead LQFP Package Outline (Top View)
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128-lead LQFP Pinout
Pinout 128-lead LQFP Package
ADVREF VDDOUT VDDIN PA20/PGMD8/AD3 PA19/PGMD7/AD2 PA18/PGMD6/AD1 PA17/PGMD5/AD0 PA16/PGMD4 PA15/PGMD3 PA14/PGMD2 PA13/PGMD1 PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 VDDIO VDDCORE PA8/PGMM0 PA7/PGMNVALID PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD PA2/PGMEN2 PA1/PGMEN1 PA0/PGMEN0 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 VDDIO VDDCORE PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 VDDIO VDDCORE NRST ERASE JTAGSEL PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 VDDIO VDDCORE SDCK PA31 PA30 PA29 PA28 PA27/PGMD15 PA26/PGMD14 PA25/PGMD13 PA24/PGMD12 PA23/PGMD11 PA22/PGMD10 PA21/PGMD9 VDDCORE VDDIO VDDFLASH XIN/PGMCK XOUT PLLRC VDDPLL
Table 4-1.
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
144-ball LFBGA Package Outline
Figure shows orientation 144-ball LFBGA package detailed mechanical description given Mechanical Characteristics section. Figure 4-2. 144-ball LFBGA Package Outline (Top View)
Ball
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144-ball LFBGA Pinout
SAM7SE512/256/32 Pinout 144-ball LFBGA Package
Signal Name VDDCORE VDDCORE PB17 PB26 PA14/PGMD2 PA12/PGMD0 PA11/PGMM3 PA8/PGMM0 PA7/PGMNVALID PC22 PC23 NRST ERASE TEST VDDCORE VDDCORE PA9/PGMM1 PA10/PGMM2 PA13/PGMD1 PC21 PC20 PC19 JTAGSEL VDDIO PA15/PGMD3 PA16/PGMD4 Signal Name PC18 PC16 PC17 VDDIO VDDIN VDDOUT PC15 PC14 PC13 VDDCORE VDDCORE PA19/PGMD7/AD2 PA20/PGMD8/AD3 VDDIO PC12 PC10 PA30 PA28 PA23/PGMD11 PA22/PGMD10 VDDCORE VDDCORE VDDCORE VDDIO Signal Name PC11 PA27/PGMD15 PA26/PGMD14 VDDCORE VDDFLASH VDDIO VDDIO PA18/PGMD6/AD1 SDCK PA29 PA24/PGMD12 PA21/PGMD9 ADVREF VDDFLASH VDDFLASH PA17/PGMD5/AD0 PA31 PA25/PGMD13 XIN/PGMCK XOUT PLLRC VDDPLL
Table 4-2.
Signal Name PB12 PB13 PB16 PB22 PB23 PB25 PB29 PB30 PB31 PB10 PB14 PB18 PB20 PB24 PB28 PA4/PGMNCMD PA0/PGMEN0 PA1/PGMEN1 PB11 PB15 PB19 PB21 PB27 PA6/PGMNOE PA5/PGMRDY PA2/PGMEN2
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Power Considerations
Power Supplies
AT91SAM7SE512/256/32 types power supply pins integrates voltage regulator, allowing device supplied with only voltage. power supply types are: VDDIN pin. powers voltage regulator ADC; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDOUT pin. output 1.8V voltage regulator. VDDIO pin. powers lines; voltage ranges supported: from 3.0V 3.6V, 3.3V nominal from 1.65V 1.95V, 1.8V nominal. VDDFLASH pin. powers transceivers part Flash. required Flash operate correctly; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDCORE pins. They power logic device; voltage ranges from 1.65V 1.95V, 1.8V typical. connected VDDOUT with decoupling capacitor. VDDCORE required device, including embedded Flash, operate correctly. VDDPLL pin. powers oscillator PLL. connected directly VDDOUT pin. order decrease current consumption, voltage regulator used, VDDIN, ADVREF, AD4, AD5, should connected GND. this case VDDOUT should left unconnected. separate ground pins provided different power supplies. Only pins provided should connected shortly possible system ground plane.
Power Consumption
AT91SAM7SE512/256/32 static current less than VDDCORE 25°C, including oscillator, voltage regulator power-on reset when brownout detector deactivated. Activating brownout detector adds static current. dynamic power consumption VDDCORE less than full speed when running Flash. Under same conditions, power consumption VDDFLASH does exceed
Voltage Regulator
AT91SAM7SE512/256/32 embeds voltage regulator that managed System Controller. Normal Mode, voltage regulator consumes less than static current draws output current. voltage regulator also Low-power Mode. this mode, consumes less than static current draws output current. Adequate output supply decoupling mandatory VDDOUT reduce ripple avoid oscillations. best achieve this capacitors parallel:
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external capacitor should connected between VDDOUT close chip possible. external capacitor should connected between VDDOUT GND. Adequate input supply decoupling mandatory VDDIN order improve startup stability reduce source voltage drop. input decoupling capacitor should placed close chip. example, capacitors used parallel: X7R.
Typical Powering Schematics
AT91SAM7SE512/256/32 supports 3.3V single supply mode. internal regulator input connected 3.3V source output feeds VDDCORE VDDPLL. Figure shows power schematics used bus-powered systems. Figure 5-1. 3.3V System Single Power Supply Schematic
VDDFLASH Power Source ranges from 4.5V (USB)
VDDIO DC/DC Converter VDDIN 3.3V VDDOUT Voltage Regulator
VDDCORE
VDDPLL
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Lines Considerations
JTAG Port Pins
TMS, Schmitt trigger inputs. TMS, integrate pull-up resistor. output, driven VDDIO, pull-up resistor. JTAGSEL used select JTAG boundary scan when asserted high level. JTAGSEL integrates permanent pull-down resistor about eliminate risk spuriously entering JTAG boundary scan mode noise JTAGSEL, should tied externally boundary scan used, place external value resistor (such
Test
used manufacturing test fast programming mode AT91SAM7SE512/256/32 when asserted high. integrates permanent pull-down resistor about GND. eliminate risk entering test mode noise pin, should tied FFPI used, place external value resistor (such enter fast programming mode, pins should tied high tied low. Driving high level while driven leads unpredictable results.
Reset
NRST bidirectional with open-drain output buffer. handled on-chip reset controller driven provide reset signal external components asserted externally reset microcontroller. There constraint length reset pulse, reset controller guarantee minimum pulse length. This allows connection simple push-button NRST system user reset, NRST signal reset components system. external power-on reset drive this during start-up instead using internal power-on reset circuit. NRST integrates permanent pull-up about resistor VDDIO. This Schmitt trigger input.
ERASE
ERASE used re-initialize Flash content some bits. integrates permanent pull-down resistor about GND. eliminate risk erasing Flash noise ERASE pin, shoul tied externally GND, which prevents erasing Flash from applicatiion, place external value resistor (such This debounced oscillator improve glitch tolerance. When tied high during less than ERASE taken into account. must tied high during more than perform re-initialization Flash.
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SDCK
SDCK dedicated SDRAM Clock output-only without pull-up. Maximum Output Frequency this 3.0V 1.65V with maximum load
Controller lines
lines PA31, PB31, PC23 integrate programmable pull-up resistor. Programming this pull-up resistor performed independently each line through controllers. Typical pull-up value lines have schmitt trigger inputs.
Lines Current Drawing
lines high-drive current capable. Each these lines drive permanently. remaining lines draw only However, total current drawn lines cannot exceed
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Processor Architecture
ARM7TDMI Processor
RISC processor based ARMv4T Neumann architecture Runs MHz, providing MIPS/MHz (core supplied with 1.8V) instruction sets ARM® high-performance 32-bit instruction Thumb® high code density 16-bit instruction Three-stage pipeline architecture Instruction Fetch Instruction Decode Execute
Debug Test EmbeddedICE(Integrated embedded in-circuit emulator) watchpoint units Test access port accessible through JTAG protocol Debug communication channel Debug Unit Two-pin UART Debug communication channel interrupt handling Chip Register IEEE1149.1 JTAG Boundary-scan digital pins
Memory Controller
Programmable Arbiter Handles requests from ARM7TDMI Peripheral Controller Address decoder provides selection signals Four internal Mbyte memory areas 256-Mbyte embedded peripheral area Eight external 256-Mbyte memory areas Abort Status Registers Source, Type parameters access leading abort saved Facilitates debug detection pointers Misalignment Detector Alignment checking data accesses Abort generation case misalignment Remap Command Remaps SRAM place embedded non-volatile memory Allows handling dynamic exception vectors 16-area Memory Protection Unit (Internal Memory peripheral protection only)
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Individually programmable size between Byte Byte Individually programmable protection against write and/or user access Peripheral protection against write and/or user access Embedded Flash Controller Embedded Flash interface, three programmable wait states Prefetch buffer, buffering anticipating 16-bit requests, reducing required wait states Key-protected program, erase lock/unlock sequencer Single command erasing, programming locking operations Interrupt generation case forbidden operation
External Interface
Integrates Three External Memory Controllers: Static Memory Controller SDRAM Controller Controller Additional Logic NAND Flash CompactFlash® Support NAND Flash support: 8-bit well 16-bit devices supported CompactFlash support: modes (Attribute Memory, Common Memory, I/O, True IDE) supported signals _IOIS16 (I/O True modes) -ATA (True mode) handled. Optimized External Bus: 32-bit Data (32-bit Data SDRAM only) 23-bit Address Bus, 8-Mbytes Addressable Chip Selects, each reserved eight Memory Areas Optimized multiplexing reduce latencies External Memories Configurable Chip Select Assignment: Static Memory Controller NCS0 SDRAM Controller Static Memory Controller NCS1 Static Memory Controller NCS2, Optional CompactFlash Support Static Memory Controller NCS3, NCS5 NCS6, Optional NAND Flash Support Static Memory Controller NCS4, Optional CompactFlash Support Static Memory Controller NCS7
Static Memory Controller
External memory mapping, 512-Mbyte address space 16-bit Data Chip Select Lines Multiple Access Modes supported Byte Write Byte Select Lines different Read Protocols each Memory Bank
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Multiple device adaptability Compliant with Module Compliant with PSRAM synchronous operations Programmable Setup Time Read/Write Programmable Hold Time Read/Write Multiple Wait State Management Programmable Wait State Generation External Wait Request Programmable Data Float Time
SDRAM Controller
Numerous configurations supported Address Memory Parts SDRAM with four Internal Banks SDRAM with 32-bit Data Path Programming facilities Word, half-word, byte access Automatic page break when Memory Boundary been reached Multibank Ping-pong Access Timing parameters specified software Automatic refresh operation, refresh rate programmable Energy-saving capabilities Self-refresh, Low-power Modes supported Error detection Refresh Error Interrupt SDRAM Power-up Initialization software Latency clocks (CAS Latency Supported) Auto Precharge Command used Mobile SDRAM supported (except low-power extended mode deep power-down mode)
Error Corrected Code Controller
Tracking accesses NAND Flash device triggering corresponding chip select Single error correction 2-bit Random detection. Automatic Hamming Code Calculation while writing value available register Automatic Hamming Code Calculation while reading Error Report, including error flag, correctable error flag word address being detected erroneous Supports 16-bit NAND Flash devices with 512-, 1024-, 2048- 4096-byte pages
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Peripheral Controller
Handles data transfer between peripherals memories Eleven channels each USART Debug Unit Serial Synchronous Controller Serial Peripheral Interface Analog-to-digital Converter arbitration overhead Master Clock cycle needed transfer from memory peripheral Master Clock cycles needed transfer from peripheral memory Next Pointer management reducing interrupt latency requirements Peripheral Controller (PDC) priority follows (from highest priority lowest):
Receive Receive Receive Receive Receive Receive Transmit Transmit Transmit Transmit Transmit DBGU USART0 USART1 DBGU USART0 USART1
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Memories
Kbytes Flash Memory (AT91SAM7SE512) dual plane contiguous banks 1024 pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, each protecting lock regions pages Protection Mode secure contents Flash Kbytes Flash Memory (AT91SAM7SE256) single plane bank 1024 pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 cycles, 10-year data retention capability lock bits, each protecting lock regions pages Protection Mode secure contents Flash Kbytes Flash Memory (AT91SAM7SE32) single plane bank pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 cycles, 10-year data retention capability lock bits, each protecting lock regions pages Protection Mode secure contents Flash Kbytes Fast SRAM (AT91SAM7SE512/256) Single-cycle access full speed Kbytes Fast SRAM (AT91SAM7SE32) Single-cycle access full speed
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Figure 8-1.
0x0000 0000
AT91SAM7SE Memory Mapping
Address Memory Space
0x0000 0000
Internal Memory Mapping Boot Memory Flash before Remap SRAM after Remap
Note: ROM, Flash SRAM depending GPNVM2 REMAP
Internal Memories
0x0FFF FFFF
MBytes
0x000F FFFF 0x0010 0000
MBytes
0x1000 0000 Chip Select
0x1FFF FFFF
MBytes
0x001F FFFF 0x0020 0000
Internal Flash
MBytes
0x2000 0000 Chip Select SDRAMC Chip Select Compact Flash Chip Select SMC/NANDFlash/ SmartMedia Chip Select Compact Flash Chip Select Chip Select
0x7FFF FFFF
MBytes
Internal SRAM
0x002F FFFF 0x0030 0000
MBytes
0x2FFF FFFF
0x3000 0000
Internal MBytes
0x003F FFFF 0x0040 0000
MBytes
0x3FFF FFFF
0x4000 0000
MBytes
0x0FFF FFFF
Reserved
MBytes System Controller Mapping 0xFFFF F000
0x4FFF FFFF
0x5000 0000
MBytes
0xFFFF F1FF 0xFFFF F200 DBGU 0xFFFF F3FF 0xFFFF F400 Peripheral Mapping 0xF000 0000 PIOA Reserved 0xFFFF F5FF 0xFFFF F600 PIOB 0xFFFF F7FF 0xFFFF F800 PIOC Kbytes 0xFFFF F9FF 0xFFFF FA00 Reserved Kbytes Kbytes 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F PWMC Reserved Reserved 0xFFFF FD60 Reserved SYSC 0xFFFF FFFF Kbytes 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 Kbytes Kbytes Kbytes 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FBFF 0xFFFF FC00 Bytes/64 registers Bytes/128 registers Bytes/128 registers Bytes/128 registers Bytes/128 registers Bytes/128 registers
0x5FFF FFFF
0x6000 0000 MBytes
0x6FFF FFFF
0x7000 0000 MBytes
0x8000 0000 Chip Select
0x8FFF FFFF
MBytes
0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF 0xFFFA 4000 0xFFFA FFFF 0xFFFB 0000 0xFFFB 3FFF 0xFFFB 4000
TC0, TC1, Reserved Reserved
Kbytes
0x9000 0000
Kbytes
0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000 0xFFFB FFFF 0xFFFC 0000
Reserved USART0 USART1 Reserved
Undefined (Abort)
MBytes 1,536 MBytes
0xFFFC 3FFF 0xFFFC 4000 0xFFFC 7FFF 0xFFFC 8000 0xFFFC BFFF 0xFFFC C000 0xFFFC FFFF 0xFFFD 0000 0xFFFD 3FFF 0xFFFD 4000 0xFFFD 7FFF 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 0xFFFD FFFF 0xFFFE 0000
RSTC Reserved Reserved VREG Reserved
Bytes/4 registers
Bytes/4 registers Bytes/4 registers Bytes/4 registers
Bytes/1 register
0xEFFF FFFF
0xF000 0000 Internal Peripherals
0xFFFF FFFF
0xFFFE 3FFF 0xFFFE 4000
MBytes
0xFFFF EFFF 0xFFFF F000 0xFFFF FFFF
Bytes/64 registers
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
first level address decoding performed Memory Controller, i.e., implementation Advanced System (ASB) with additional features. Decoding splits bytes address space into areas 256M bytes. areas directed that associates these areas external chip selects NCS7. area reserved addressing internal memories, second level decoding provides byte internal memory area. area reserved peripherals provides access Advanced Peripheral (APB). Other areas unused performing access within them provides abort master requesting such access.
8.1.1 8.1.1.1
Embedded Memories
Internal Memories Internal SRAM AT91SAM7SE512/256 embeds high-speed 32-Kbyte SRAM bank. AT91SAM7SE32 embeds high-speed 8-Kbyte SRAM bank. After reset until Remap Command performed, SRAM only accessible address 0x0020 0000. After Remap, SRAM also becomes available address 0x0. Internal AT91SAM7SE512/256/32 embeds Internal ROM. time, mapped address 0x30 0000. contains FFPI SAM-BA boot program. Internal Flash AT91SAM7SE512 features banks Kbytes Flash. AT91SAM7SE256 features bank Kbytes Flash. AT91SAM7SE32 features bank Kbytes Flash. time, Flash mapped address 0x0010 0000. general purpose (GPNVM) used boot either (default) from Flash. This GPNVM cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface. Setting GPNVM selects boot from Flash, clearing selects boot from ROM. Asserting ERASE clears GPNVM thus selects boot from default.
8.1.1.2
8.1.1.3
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Figure 8-2.
Internal Memory Mapping with GPNVM (default)
0x0000 0000
0x000F FFFF
Before Remap SRAM After Remap Internal FLASH
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes Bytes Bytes
Internal
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
Figure 8-3.
Internal Memory Mapping with GPNVM
0x0000 0000
0x000F FFFF
Flash Before Remap SRAM After Remap Internal FLASH
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes Bytes Bytes
Internal
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
8.1.2 8.1.2.1
Embedded Flash Flash Overview Flash AT91SAM7SE512 organized banks (dual plane) 1024 pages bytes. reads 131,072 32-bit words. Flash AT91SAM7SE256 organized 1024 pages (single plane) bytes. reads 65,536 32-bit words. Flash AT91SAM7SE32 organized pages (single plane) bytes. reads 8192 32-bit words. Flash AT91SAM7SE32 contains 128-byte write buffer, accessible through 32-bit interface. Flash AT91SAM7SE512/256 contains 256-byte write buffer, accessible through 32-bit interface.
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Flash benefits from integration power reset cell from brownout detector. This prevents code corruption during power supply changes, even worst conditions. 8.1.2.2 Embedded Flash Controller Embedded Flash Controller (EFC) manages accesses performed masters system. enables reading Flash writing write buffer. also contains User Interface, mapped within Memory Controller APB. User Interface allows: programming access parameters Flash (number wait states, timings, etc.) starting commands such full erase, page erase, page program, set, clear, etc. getting status last command getting error status programming interrupts last commands errors Embedded Flash Controller also provides dual 32-bit Prefetch Buffer that optimizes 16-bit access Flash. This particularly efficient when processor running Thumb mode. EFCs (EFC0 EFC1) embedded SAM7SE512 control each plane KBytes. Dual plane organization allows concurrent Read Program. (EFC0) embedded SAM7SE256 control single plane KBytes. (EFC0) embedded SAM7SE32 control single plane KBytes. 8.1.2.3 Lock Regions AT91SAM7SE512 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7SE512 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. AT91SAM7SE256 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7SE256 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. AT91SAM7SE32 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7SE32 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. locked-region's erase program command occurs, command aborted trigs interrupt. (AT91SAM7SE512), (AT91SAM7SE256) (AT91SAM7SE32) bits software programmable through User Interface. command "Set Lock Bit" enables protection. command "Clear Lock Bit" unlocks lock region. Asserting ERASE clears lock bits, thus unlocking entire Flash. 8.1.2.4 Security Feature AT91SAM7SE512/256/32 features security bit, based specific NVM-bit. When security enabled, access Flash, either through interface through Fast Flash Programming Interface, forbidden.
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security only enabled through Command "Set Security Bit" User Interface. Disabling security only achieved asserting ERASE after full flash erase performed. When security deactivated, accesses flash permitted. important note that assertion ERASE should always longer than ERASE integrates permanent pull-down, left unconnected during normal operation. However, safer connect directly final application. 8.1.2.5 Non-volatile Brownout Detector Control general purpose (GPNVM) bits used controlling brownout detector (BOD), that even after power loss, brownout detector operations remain their state. These GPNVM bits cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface. GPNVM used brownout detector enable bit. Setting GPNVM enables BOD, clearing disables BOD. Asserting ERASE clears GPNVM thus disables brownout detector default. GPNVM used brownout reset enable signal reset controller. Setting GPNVM enables brownout reset when brownout detected, Clearing GPNVM disables brownout reset. Asserting ERASE disables brownout reset default. 8.1.2.6 Calibration Bits Sixteen bits used calibrate brownout detector voltage regulator. These bits factory configured cannot changed user. ERASE effect calibration bits. Fast Flash Programming Interface Fast Flash Programming Interface allows programming device through either serial JTAG interface through multiplexed fully-handshaked parallel port. allows gang-programming with market-standard industrial programmers. FFPI supports read, page program, page erase, full erase, lock, unlock protect commands. Fast Flash Programming Interface enabled Fast Programming Mode entered when pins tied high tied low. Flash AT91SAM7SE512 organized 2048 pages bytes (dual plane). reads 131,072 32-bit words. Flash AT91SAM7SE256 organized 1024 pages bytes (single plane). reads 65,536 32-bit words. Flash AT91SAM7SE32 organized pages bytes (single plane). reads 32,768 32-bit words. Flash AT91SAM7SE512/256 contains 256-byte write buffer, accessible through 32-bit interface. Flash AT91SAM7SE32 contains 128-byte write buffer, accessible through 32bit interface.
8.1.3
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8.1.4 SAM-BABoot SAM-BA Boot default Boot Program which provides easy program in-situ on-chip Flash memory. SAM-BA Boot Assistant supports serial communication DBGU Device Port. Communication DBGU supports wide range crystals from software auto-detection. Communication Device Port limited 18.432 crystal. SAM-BA Boot provides interface with SAM-BA Graphic User Interface (GUI). SAM-BA Boot mapped Flash address when GPNVM
External Memories
external memories accessed through External Interface. Refer memory Figure page
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System Controller
System Controller manages vital blocks microcontroller: interrupts, clocks, power, time, debug reset. System Controller peripherals mapped highest Kbytes address space, between addresses 0xFFFF F000 0xFFFF FFFF. Figure page shows System Controller Block Diagram. Figure page shows mapping User Interface System Controller peripherals. Note that Memory Controller configuration user interface also mapped within this address space.
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Figure 9-1. System Controller Block Diagram
System Controller
jtag_nreset
Boundary Scan Controller
irq0-irq1 periph_irq[2.18]
nirq
Advanced Interrupt Controller
nfiq proc_nreset debug
ARM7TDMI
pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq
power_on_reset force_ntrst
periph_nreset dbgu_rxd debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset gpnvm[0] gpnvm[1] flash_wrdis power_on_reset jtag_nreset
Debug Unit
dbgu_irq force_ntrst dbgu_txd security_bit
Periodic Interval Timer Real-Time Timer Watchdog Timer
wdt_fault WDRPROC bod_rst_en
pit_irq flash_poe rtt_irq flash_wrdis wdt_irq gpnvm[0.2]
Embedded Flash
proc_nreset
Memory Controller
flash_poe
Reset Controller
periph_nreset proc_nreset
NRST SLCK
rstc_irq
Voltage Regulator Mode Controller
standby
Voltage Regulator
RCOSC
SLCK
periph_clk[2.18] pck[0-3]
UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend
XOUT
MAINCK
Power Management Controller
UDPCK
Device Port
PLLRC
PLLCK pmc_irq idle periph_clk[4.18] periph_nreset
periph_nreset usb_suspend
periph_nreset periph_clk[2-3] dbgu_rxd
periph_irq{2-3] irq0-irq1
Embedded Peripherals
Controller
dbgu_txd
periph_irq[4.18]
PA0-PA31 PB0-PB31 PC0-PC29 enable
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Reset Controller
Based power-on reset cell double brownout detector Status last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset Controls internal resets NRST output Allows shape signal NRST line, guaranteeing that length pulse meets requirement.
9.1.1
Brownout Detector Power Reset AT91SAM7SE512/256/32 embeds brownout detection circuit power-on reset cell. power-on reset supplied with monitors VDDCORE. Both signals provided Flash prevent code corruption during power-up powerdown sequences brownouts occur VDDCORE power supply. power-on reset cell limited-accuracy threshold around 1.5V. output remains during power-up until VDDCORE goes over this voltage level. This signal goes reset controller allows full re-initialization device. brownout detector monitors VDDCORE VDDFLASH levels during operation comparing fixed trigger level. secures system operations most difficult environments prevents code corruption case brownout VDDCORE VDDFLASH. When brownout detector enabled VDDCORE decreases value below trigger level (Vbot18-, defined Vbot18 hyst/2), brownout output immediately activated. When VDDCORE increases above trigger level (Vbot18+, defined Vbot18 hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. VDDCORE threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 1.68V with accuracy factory calibrated. When brownout detector enabled VDDFLASH decreases value below trigger level (Vbot33-, defined Vbot33 hyst/2), brownout output immediately activated. When VDDFLASH increases above trigger level (Vbot33+, defined Vbot33 hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. VDDFLASH threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 2.80V with accuracy 3.5% factory calibrated. brownout detector low-power, consumes less than static current. However, deactivated save static current. this case, consumes less than 1µA. deactivation configured through GPNVM Flash.
Clock Generator
Clock Generator embeds low-power Oscillator, Main Oscillator with following characteristics: Oscillator ranges between
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Main Oscillator frequency ranges between Main Oscillator bypassed output ranges between provides SLCK, MAINCK PLLCK. Figure 9-2. Clock Generator Block Diagram
Clock Generator
Embedded Oscillator
Slow Clock SLCK
XOUT
Main Oscillator
Main Clock MAINCK
PLLRC
Divider
Clock PLLCK
Status
Control
Power Management Controller
Power Management Controller
Power Management Controller uses Clock Generator outputs provide: Processor Clock Master Clock Clock UDPCK peripheral clocks, independently controllable three programmable clock outputs Master Clock (MCK) programmable from hundred maximum operating frequency device. Processor Clock (PCK) switches when entering processor idle mode, thus allowing reduced power consumption while waiting interrupt.
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Figure 9-3.
Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64 Peripherals Clock Controller ON/OFF Idle Mode
periph_clk[2.14]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64
pck[0.2]
Clock Controller ON/OFF PLLCK Divider /1,/2,/4
usb_suspend
UDPCK
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) Other sources control peripheral interrupts external interrupts Programmable edge-triggered level-sensitive internal sources Programmable positive/negative edge-triggered high/low level-sensitive external sources 8-level Priority Controller Drives normal interrupt nIRQ processor Handles priority interrupt sources Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes interrupt service routine branch execution 32-bit vector register interrupt source Interrupt vector register reads corresponding current interrupt vector Protect Mode Easy debugging preventing automatic operations Fast Forcing Permits redirecting interrupt source fast interrupt General Interrupt Mask Provides processor synchronization events without triggering interrupt
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Debug Unit
Comprises: two-pin UART Interface Debug Communication Channel (DCC) support Chip Registers Interface providing Access Prevention Two-pin UART USART-compatible User Interface Programmable Baud Rate Generator Parity, Framing Overrun Error Automatic Echo, Local Loopback Remote Loopback Channel Modes Debug Communication Channel Support Offers visibility COMMRX COMMTX signals from Processor Chip Registers Identification device revision, sizes embedded memories, peripherals Chip 0x272A 0A40 (VERSION AT91SAM7SE512 Chip 0x272A 0940 (VERSION AT91SAM7SE256 Chip 0x2728 0340 (VERSION AT91SAM7SE32
Periodic Interval Timer
20-bit programmable counter plus 12-bit interval counter
Watchdog Timer
12-bit key-protected Programmable Counter running prescaled SLCK Provides reset interrupt signals system Counter stopped while processor debug state idle mode
Real-time Timer
32-bit free-running counter with alarm running prescaled SLCK Programmable 16-bit prescaler SLCK accuracy compensation
Controllers
Three Controllers. each control lines controls lines. Fully programmable through set/clear registers Multiplexing peripheral functions line each line (whether assigned peripheral used general-purpose I/O) Input change interrupt Half clock period glitch filter Multi-drive option enables driving open drain Programmable pull-up each line data status register, supplies visibility level time
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Synchronous output, provides Clear several lines single write
9.10
Voltage Regulator Controller
purpose this controller select Power Mode Voltage Regulator between Normal Mode (bit cleared) Standby Mode (bit set).
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Peripherals
10.1 User Interface
User Peripherals mapped MBytes address space between 0xF000 0000 0xFFFF EFFF. Each peripheral allocated Kbytes address space. complete memory presented Figure page
10.2
Peripheral Identifiers
AT91SAM7SE512/256/32 embeds wide range peripherals. Table 10-1 defines Peripheral Identifiers AT91SAM7SE512/256/32. Unique peripheral identifiers defined both Advanced Interrupt Controller Power Management Controller. Table 10-1.
Peripheral 16-28
Peripheral Identifiers
Peripheral Mnemonic SYSC PIOA PIOB PIOC PWMC
Peripheral Name Advanced Interrupt Controller
External Interrupt
Parallel Controller Parallel Controller Parallel Controller Serial Peripheral Interface USART USART Synchronous Serial Controller Two-wire Interface Controller Device Port Timer/Counter Timer/Counter Timer/Counter Analog-to Digital Converter
reserved Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1
Note:
Setting SYSC bits clock set/clear registers effect. System Controller continuously clocked. clock automatically started first conversion. Sleep Mode clock automatically stopped after each conversion.
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10.3
Peripheral Multiplexing Lines
AT91SAM7SE512/256/32 features three controllers, PIOA, PIOB PIOC, that multiplex lines peripheral set. Controller control lines; Controller controls lines. Each line assigned peripheral functions, Some them also multiplexed with analog inputs Controller. Table 10-2 page defines lines peripherals analog inputs multiplexed Controller columns "Function" "Comments" have been inserted user's comments; they used track pins defined application. Note that some peripheral functions that output only duplicated table. reset, lines automatically configured input with programmable pull-up enabled, that device maintained static state soon reset detected.
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10.4 Controller Multiplexing
Multiplexing Controller
Controller Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral PWM0 PWM1 PWM2 TWCK RXD0 TXD0 RTS0 CTS0 DRXD DTXD NPCS0 MISO MOSI SPCK RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DTR1 DSR1 IRQ1 NPCS1 Peripheral A0/NBS0 A1/NBS2 A16/BA0 A17/BA1 NBS3/CFIOW NCS4/CFCS0 NCS2/CFCS1 NCS6/CFCE2 NCS5/CFCE1 NWR1/NBS1/CFIOR SDA10 SDCKE NCS1/SDCS SDWE Comments High-Drive High-Drive High-Drive High-Drive Application Usage Function Comments
Table 10-2.
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10.5
Controller Multiplexing
Multiplexing Controller
Controller Application Usage Comments Function Comments
Table 10-3.
Line PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31
Peripheral TIOA0 TIOB0 SCK0 NPCS3 TCLK0 NPCS3 PCK0 PWM3 ADTRG NPCS1 NPCS2 PWM0 PWM1 PWM2 PWM3 TIOA1 TIOB1 PCK1 PCK2 IRQ0 PCK1 NPCS3 PWM0 PWM1 PWM2 TIOA2 TIOB2 TCLK1 TCLK2 NPCS2 PCK2
Peripheral A0/NBS0 A1/NBS2 A16/BA0 A17/BA1
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10.6 Controller Multiplexing
Multiplexing Controller
Controller Line PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 CFRNW Peripheral A21/NANDALE A22/REG/NANDCLE NCS7 NWR0/NWE/CFWE NRD/CFOE NCS0 NPCS1 NCS3/NANDCS NWAIT NANDOE NANDWE RTS1 DTR1 PCK0 PCK1 PCK2 Peripheral Comments Application Usage Function Comments
10.7
Serial Peripheral Interface
Supports communication with external serial devices Four chip selects with external decoder allow communication with peripherals Serial memories, such DataFlash® 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface
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16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays chip select, between consecutive transfers between clock data Programmable delay between consecutive transfers Selectable mode fault detection Maximum frequency Master Clock
10.8
Wire Interface
Master, Multi-Master Slave Mode Operation Compatibility with standard two-wire serial memories One, three bytes slave address Sequential read/write operations Rate: Kbit/s General Call Supported Slave Mode
10.9
USART
Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection first Optional break generation detection over-sampling receiver frequency Hardware handshaking Modem Signals Management DTR-DSR-DCD-RI USART1 Receiver time-out transmitter timeguard Multi-drop Mode with address generation detection RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit IrDA® modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo
10.10 Serial Synchronous Controller
Provides serial synchronous communication links used audio telecom applications Contains independent receiver transmitter common clock divider
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Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal
10.11 Timer Counter
Three 16-bit Timer Counter Channels Three output compare input capture Wide range functions including: Frequency measurement Event counting Interval measurement Pulse generation Delay timing Pulse Width Modulation Up/down capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs, defined Table 10-4 Table 10-4. Timer Counter Clocks Assignment
Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
multi-purpose input/output signals global registers that three channels
10.12 Controller
Four channels, 16-bit counter channel Common clock generator, providing thirteen different clocks Modulo counter providing eleven clocks independent linear dividers working modulo counter outputs Independent channel programming Independent enable/disable commands Independent clock selection Independent period duty cycle, with double buffering Programmable selection output waveform polarity Programmable center left aligned output waveform
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10.13 Device Port
V2.0 full-speed compliant,12 Mbits second. Embedded V2.0 full-speed transceiver Embedded 2688-byte dual-port endpoints Eight endpoints Endpoint 64bytes Endpoint bytes ping-pong Endpoint bytes Endpoint bytes ping-pong Endpoint bytes ping-pong Ping-pong Mode (two memory banks) Isochronous bulk endpoints Suspend/resume logic Integrated Pull-up
10.14 Analog-to-Digital Converter
8-channel 10-bit Ksamples/sec. 8-bit Ksamples/sec. Successive Approximation Register Integral Linearity, Differential Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs External voltage reference better accuracy voltage inputs Individual enable disable each channel Multiple trigger sources Hardware software trigger External trigger Timer Counter outputs TIOA0 TIOA2 trigger Sleep Mode conversion sequencer Automatic wakeup trigger back sleep mode after conversions enabled channels Each analog input shared with digital signals
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ARM7TDMI Processor Overview
11.1 Overview
ARM7TDMI core executes both 32-bit 16-bit Thumb instruction sets, allowing user trade between high performance high code density.The ARM7TDMI processor implements Neuman architecture, using three-stage pipeline consisting Fetch, Decode, Execute stages. main features ARM7tDMI processor are: ARM7TDMI Based ARMv4T Architecture Instruction Sets High-performance 32-bit Instruction Thumb High Code Density 16-bit Instruction Three-Stage Pipeline Architecture Instruction Fetch Instruction Decode Execute
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11.2
ARM7TDMI Processor
further details ARM7TDMI, refer following documents: Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B)
11.2.1
Instruction Type Instructions either bits long state) bits long THUMB state). Data Type ARM7TDMI supports byte (8-bit), half-word (16-bit) word (32-bit) data types. Words must aligned four-byte boundaries half words two-byte boundaries. Unaligned data access behavior depends which instruction used where.
11.2.2
11.2.3
ARM7TDMI Operating Mode ARM7TDMI, based architecture v4T, supports seven processor modes: User: normal program execution state FIQ: Designed support high-speed data transfer channel process IRQ: Used general-purpose interrupt handling Supervisor: Protected mode operating system Abort mode: Implements virtual memory and/or memory protection System: privileged user mode operating system Undefined: Supports software emulation hardware coprocessors Mode changes made under software control, brought about external interrupts exception processing. Most application programs execute User mode. non-user modes, privileged modes, entered order service interrupts exceptions, access protected resources.
11.2.4
ARM7TDMI Registers ARM7TDMI processor total 37registers: general-purpose 32-bit registers status registers These registers accessible same time. processor state operating mode determine which registers available programmer. time registers visible user. remainder synonyms used speed exception processing. Register Program Counter (PC) used instructions reference data relative current instruction. holds return address after subroutine call. used software convention) stack pointer.
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Table 11-1.
User System Mode
ARM7TDMI Modes Registers Layout
Supervisor Mode
R13_SVC R14_SVC
Abort Mode
R13_ABORT R14_ABORT
Undefined Mode
R13_UNDEF R14_UNDEF
Interrupt Mode
R13_IRQ R14_IRQ
Fast Interrupt Mode
R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ
CPSR
CPSR SPSR_SVC
CPSR SPSR_ABORT
CPSR SPSR_UNDEF
CPSR SPSR_IRQ
CPSR SPSR_FIQ
Mode-specific banked registers
Registers unbanked registers. This means that each them refers same 32bit physical register processor modes. They general-purpose registers, with special uses managed architecture, used wherever instruction allows generalpurpose register specified. Registers banked registers. This means that each them depends current mode processor. 11.2.4.1 Modes Exception Handling exceptions have banked registers R13. After exception, holds return address exception processing. This address used return after exception processed, well address instruction that caused exception. banked across exception modes provide each exception handler with private stack pointer. fast interrupt mode also banks registers that interrupt processing begin without having save these registers.
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seventh processing mode, System Mode, does have banked registers. uses User Mode registers. System Mode runs tasks that require privileged processor mode allows them invoke classes exceptions. 11.2.4.2 Status Registers other processor states held status registers. current operating processor status Current Program Status Register (CPSR). CPSR holds: four flags (Negative, Zero, Carry, Overflow) interrupt disable bits (one each type interrupt) indicate Thumb execution five bits encode current processor mode five exception modes also have Saved Program Status Register (SPSR) that holds CPSR task immediately preceding exception. 11.2.4.3 Exception Types
ARM7TDMI supports five types exception privileged processing mode each type.
types exceptions are: fast interrupt (FIQ) normal interrupt (IRQ) memory aborts (used implement memory protection virtual memory) attempted execution undefined instruction software interrupts (SWIs) Exceptions generated internal external sources. More than exception occur same time. When exception occurs, banked version SPSR exception mode used save state. return after handling exception, SPSR moved CPSR, moved This done ways: using data-processing instruction with S-bit set, destination using Load Multiple with Restore CPSR instruction (LDM) 11.2.5 Instruction Overview instruction divided into: Branch instructions Data processing instructions Status register transfer instructions Load Store instructions Coprocessor instructions Exception-generating instructions instructions executed conditionally. Every instruction contains 4-bit condition code field (bit[31:28]).
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Table 11-2 gives instruction mnemonic list. Table 11-2.
Mnemonic
SMULL SMLAL LDRSH LDRSB LDRH LDRB LDRBT LDRT
Instruction Mnemonic List
Operation
Move Subtract Reverse Subtract Compare Test Logical Logical Exclusive Multiply Sign Long Multiply Signed Long Multiply Accumulate Move Status Register Branch Branch Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move Coprocessor Load Coprocessor
Mnemonic
UMULL UMLAL STRH STRB STRBT STRT SSWPB
Operation
Coprocessor Data Processing Move with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Clear Logical (inclusive) Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor
11.2.6
Thumb Instruction Overview Thumb instruction re-encoded subset instruction set. Thumb instruction divided into: Branch instructions Data processing instructions Load Store instructions Load Store Multiple instructions Exception-generating instruction Thumb mode, eight general-purpose registers, available that same physical registers when executing instructions. Some Thumb instructions also
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access Program Counter (ARM Register 15), Link Register (ARM Register Stack Pointer (ARM Register 13). Further instructions allow limited access registers Table 11-3 gives Thumb instruction mnemonic list. Table 11-3.
Mnemonic
LDRH LDRB LDRSH LDMIA PUSH
Thumb Instruction Mnemonic List
Operation
Move Subtract Compare Test Logical Logical Exclusive Logical Shift Left Arithmetic Shift Right Multiply Branch Branch Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register stack STRH STRB LDRSB STMIA Branch Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Register from stack
Mnemonic
Operation
Move with Carry Subtract with Carry Compare Negated Negate Clear Logical (inclusive) Logical Shift Right Rotate Right
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Debug Test 12.1 Overview
AT91SAM7SE Series Microcontrollers feature number complementary debug test capabilities. common JTAG/ICE (Embedded ICE) port used standard debugging functions, such downloading code single-stepping through programs. Debug Unit provides two-pin UART that used upload application into internal SRAM. manages interrupt handling internal COMMTX COMMRX signals that trace activity Debug Communication Channel. dedicated debug test input/output pins gives direct access these capabilities from PC-based test environment.
12.2
Block Diagram
Figure 12-1. Debug Test Block Diagram
Boundary
ICE/JTAG
JTAGSEL
Reset Test
ARM7TDMI
DTXD DRXD
DBGU
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12.3
12.3.1
Application Examples
Debug Environment Figure 12-2 shows complete debug environment example. ICE/JTAG interface used standard debugging functions, such downloading code single-stepping through program. Figure 12-2. Application Debug Environment Example
Host Debugger ICE/JTAG Interface
ICE/JTAG Connector
AT91SAMSExx
RS232 Connector
Terminal
AT91SAM7Sxx-based Application Board
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12.3.2 Test Environment Figure 12-3 shows test environment example. Test vectors sent interpreted tester. this example, "board test" designed using number JTAG-compliant devices. These devices connected form single scan chain. Figure 12-3. Application Test Environment Example
Test Adaptor
Tester
JTAG Interface
ICE/JTAG Connector
Chip
Chip
AT91SAM7SExx
Chip
AT91SAM7SExx-based Application Board Test
6222C-ATARM-21-Nov-07
12.4
Debug Test Description
Table 12-1.
Name
Debug Test List
Function Reset/Test Type Active Level
NRST
Microcontroller Reset Test Mode Select JTAG
Input/Output Input
High
JTAGSEL
Test Clock Test Data Test Data Test Mode Select JTAG Selection Debug Unit
Input Input Output Input Input
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
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12.5
12.5.1
Functional Description
Test dedicated pin, TST, used define device operating mode. user must make sure that this tied level ensure normal operating conditions. Other values associated with this reserved manufacturing test.
12.5.2
EmbeddedICE(Embedded In-circuit Emulator) ARM7TDMI EmbeddedICE supported ICE/JTAG port.The internal state ARM7TDMI examined through ICE/JTAG port. ARM7TDMI processor contains hardware extensions advanced debugging features: halt mode, store-multiple (STM) inserted into instruction pipeline. This exports contents ARM7TDMI registers. This data serially shifted without affecting rest system. monitor mode, JTAG interface used transfer data between debugger simple monitor program running ARM7TDMI processor. There three scan chains inside ARM7TDMI processor that support testing, debugging, programming Embedded ICE. scan chains controlled ICE/JTAG port. Embedded mode selected when JTAGSEL low. possible switch directly between JTAG operations. chip reset must performed after JTAGSEL changed. further details Embedded ICE, ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).
12.5.3
Debug Unit Debug Unit provides two-pin (DXRD TXRD) USART that used several debug trace purposes offers ideal means in-situ programming solutions debug monitor communication. Moreover, association with peripheral data controller channels permits packet handling these tasks with processor time reduced minimum. Debug Unit also manages interrupt handling COMMTX COMMRX signals that come from that trace activity Debug Communication Channel.The Debug Unit allows blockage access system through interface. specific register, Debug Unit Chip Register, gives information about product version internal configuration. Table 12-2.
Chip Name AT91SAM7SE32 AT91SAM7SE256 AT91SAM7SE512
AT91SAM7SExx Chip
Chip 0x27280340 0x272A0940 0x272A0A40
further details Debug Unit, Debug Unit section. 12.5.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent device packaging technology.
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IEEE 1149.1 JTAG Boundary Scan enabled when JTAGSEL high. SAMPLE, EXTEST BYPASS functions implemented. debug mode, processor responds with non-JTAG chip that identifies processor system. This IEEE 1149.1 JTAG-compliant. possible switch directly between JTAG operations. chip reset must performed after JTAGSEL changed. Boundary-scan Descriptor Language (BSDL) file provided test. 12.5.4.1 JTAG Boundary-scan Register Boundary-scan Register (BSR) contains bits that correspond active pins associated control signals. Each AT91SAM7SExx input/output corresponds 3-bit register BSR. OUTPUT contains data that forced pad. INPUT facilitates observability data applied pad. CONTROL selects direction pad. more information, please refer BDSL files which available SAM7SE Series.
12.5.5 Code Register Access: Read-only
VERSION
PART NUMBER
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PART NUMBER
PART NUMBER
MANUFACTURER IDENTITY
MANUFACTURER IDENTITY
VERSION[31:28]: Product Version Number 0x0. PART NUMBER[27:12]: Product Part Number
Chip Name AT91SAM7SE32 AT91SAM7SE256 AT91SAM7SE512 Chip 0x5B1D 0x5B15 0x5B14
MANUFACTURER IDENTITY[11:1] 0x01F. Bit[0] Required IEEE Std. 1149.1. 0x1.
Chip Name AT91SAM7SE32 AT91SAM7SE256 AT91SAM7SE512 JTAG Code 05B1_D03F 05B1_503F 05B1_403F
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Reset Controller (RSTC)
Reset Controller (RSTC), based power-on reset cells, handles resets system without external components. reports which reset occurred last. Reset Controller also drives independently simultaneously external reset peripheral processor resets. brownout detection also available prevent processor from falling into unpredictable state.
13.1
Block Diagram
Figure 13-1. Reset Controller Block Diagram
Reset Controller
bod_rst_en brown_out Brownout Manager
bod_reset
Main Supply
Startup Counter
Reset State Manager
rstc_irq
proc_nreset
user_reset
NRST
nrst_out
NRST Manager
exter_nreset
periph_nreset
WDRPROC wd_fault
SLCK
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13.2
13.2.1
Functional Description
Reset Controller Overview Reset Controller made NRST Manager, Brownout Manager, Startup Counter Reset State Manager. runs Slow Clock generates following reset signals: proc_nreset: Processor reset line. also resets Watchdog Timer. periph_nreset: Affects whole embedded peripherals. nrst_out: Drives NRST pin. These reset signals asserted Reset Controller, either external events software action. Reset State Manager controls generation reset signals provides signal NRST Manager when assertion NRST required. NRST Manager shapes NRST assertion during programmable time, thus controlling external device resets. startup counter waits complete crystal oscillator startup. wait delay given crystal oscillator startup time maximum value that found section Crystal Oscillator Characteristics Electrical Characteristics section product documentation.
13.2.2
NRST Manager NRST Manager samples NRST input drives this when required Reset State Manager. Figure 13-2 shows block diagram NRST Manager. Figure 13-2. NRST Manager
RSTC_MR RSTC_SR
URSTIEN rstc_irq
RSTC_MR
URSTS NRSTL
Other interrupt sources user_reset
URSTEN
NRST
RSTC_MR
ERSTL nrst_out External Reset Timer exter_nreset
13.2.2.1
NRST Signal Interrupt NRST Manager samples NRST Slow Clock speed. When line detected low, User Reset reported Reset State Manager. However, NRST Manager programmed trigger reset when assertion NRST occurs. Writing URSTEN RSTC_MR disables User Reset trigger. level NRST read time NRSTL (NRST level) RSTC_SR. soon NRST asserted, URSTS RSTC_SR set. This clears only when RSTC_SR read.
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Reset Controller also programmed generate interrupt instead generating reset. URSTIEN RSTC_MR must written 13.2.2.2 NRST External Reset Control Reset State Manager asserts signal ext_nreset assert NRST pin. When this occurs, "nrst_out" signal driven NRST Manager time programmed field ERSTL RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives approximate duration assertion between seconds. Note that ERSTL defines two-cycle duration NRST pulse. This feature allows Reset Controller shape NRST level, thus guarantee that NRST line driven time compliant with potential external devices connected system reset.
13.2.3
Brownout Manager Brownout detection prevents processor from falling into unpredictable state power supply drops below certain level. When VDDCORE drops below brownout threshold, brownout manager requests brownout reset asserting bod_reset signal. programmer disable brownout reset setting bod_rst_en input signal, i.e.; locking corresponding general-purpose Flash. When brownout reset disabled, reset performed. Instead, brownout detection reported BODSTS RSTC_SR. BODSTS clears only when RSTC_SR read. BODSTS trigger interrupt BODIEN RSTC_MR. factory, brownout reset disabled. Figure 13-3. Brownout Manager
bod_rst_en bod_reset
RSTC_MR
BODIEN
RSTC_SR
brown_out
BODSTS
Other interrupt sources
rstc_irq
13.2.4
Reset States Reset State Manager handles different reset sources generates internal reset signals. reports reset status field RSTTYP Status Register (RSTC_SR). update field RSTTYP performed when processor reset released.
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13.2.4.1
Power-up Reset When VDDCORE powered Main Supply cell output filtered with start-up counter that operates Slow Clock. purpose this counter ensure that Slow Clock oscillator stable before starting device. startup time, shown Figure 13-4, hardcoded comply with Slow Clock Oscillator startup time. After startup time, reset signals released field RSTTYP RSTC_SR reports Power-up Reset. When VDDCORE detected Main Supply Cell, reset signals asserted immediately.
Figure 13-4. Power-up Reset
SLCK Main Supply output proc_nreset periph_nreset
Freq.
Startup Time
Processor Startup cycles
NRST (nrst_out)
EXTERNAL RESET LENGTH cycles
13.2.4.2
User Reset User Reset entered when level detected NRST URSTEN RSTC_MR NRST input signal resynchronized with SLCK insure proper behavior system. User Reset entered soon level detected NRST. Processor Reset Peripheral Reset asserted. User Reset left when NRST rises, after two-cycle resynchronization time threecycle processor startup. processor clock re-enabled soon NRST confirmed high. When processor reset signal released, RSTTYP field Status Register (RSTC_SR) loaded with value 0x4, indicating User Reset. NRST Manager guarantees that NRST line asserted EXTERNAL_RESET_LENGTH Slow Clock cycles, programmed field ERSTL. However, NRST does rise after EXTERNAL_RESET_LENGTH because driven externally, internal reset lines remain asserted until NRST actually rises.
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Figure 13-5. User Reset State
SLCK
Freq.
NRST
Resynch. cycles Resynch. cycles Processor Startup cycles
proc_nreset RSTTYP periph_nreset User Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH
13.2.4.3
Brownout Reset When brown_out/bod_reset signal asserted, Reset State Manager immediately enters Brownout Reset. this state, processor, peripheral external reset lines asserted. Brownout Reset left Slow Clock cycles after rising edge brown_out/bod_reset after two-cycle resynchronization. external reset also triggered. When processor reset released, field RSTTYP RSTC_SR loaded with value 0x5, thus indicating that last reset Brownout Reset.
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Figure 13-6. Brownout Reset State
SLCK brown_out bod_reset
Resynch. cycles Processor Startup cycles
Freq.
proc_nreset RSTTYP periph_nreset Brownout Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH cycles (ERSTL=2)
13.2.4.4
Software Reset Reset Controller offers several commands used assert different reset signals. These commands performed writing Control Register (RSTC_CR) with following bits PROCRST: Writing PROCRST resets processor watchdog timer. PERRST: Writing PERRST resets embedded peripherals, including memory system, and, particular, Remap Command. Peripheral Reset generally used debug purposes. EXTRST: Writing EXTRST asserts NRST during time defined field ERSTL Mode Register (RSTC_MR). software reset entered least these bits software. these commands performed independently simultaneously. software reset lasts Slow Clock cycles. internal reset signals asserted soon register write performed. This detected Master Clock (MCK). They released when software reset left, i.e.; synchronously SLCK. EXTRST set, nrst_out signal asserted depending programming field ERSTL. However, resulting falling edge NRST does lead User Reset. only PROCRST set, Reset Controller reports software status field RSTTYP Status Register (RSTC_SR). Other Software Resets reported RSTTYP.
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soon software operation detected, SRCMP (Software Reset Command Progress) Status Register (RSTC_SR). cleared soon software reset left. other software reset performed while SRCMP set, writing value RSTC_CR effect. Figure 13-7. Software Reset
SLCK
Freq.
Write RSTC_CR
Resynch. cycle Processor Startup cycles
proc_nreset PROCRST=1 RSTTYP periph_nreset PERRST=1 NRST (nrst_out) EXTRST=1
EXTERNAL RESET LENGTH cycles (ERSTL=2)
Software Reset
SRCMP RSTC_SR
13.2.4.5
Watchdog Reset Watchdog Reset entered when watchdog fault occurs. This state lasts Slow Clock cycles. When Watchdog Reset, assertion reset signals depends WDRPROC WDT_MR: WDRPROC Processor Reset Peripheral Reset asserted. NRST line also asserted, depending programming field ERSTL. However, resulting level NRST does result User Reset state. WDRPROC only processor reset asserted. Watchdog Timer reset proc_nreset signal. watchdog fault always causes processor reset WDRSTEN set, Watchdog Timer always reset after Watchdog Reset, Watchdog enabled default with period maximum. When WDRSTEN WDT_MR reset, watchdog fault impact reset controller.
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Figure 13-8. Watchdog Reset
SLCK
Freq.
wd_fault
Processor Startup cycles
proc_nreset RSTTYP periph_nreset Only WDRPROC Watchdog Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH cycles (ERSTL=2)
13.2.5
Reset State Priorities Reset State Manager manages following priorities between different reset sources, given descending order: Power-up Reset Brownout Reset Watchdog Reset Software Reset User Reset Particular cases listed below: When User Reset: watchdog event impossible because Watchdog Timer being reset proc_nreset signal. software reset impossible, since processor reset being activated. When Software Reset: watchdog event priority over current state. NRST effect. When Watchdog Reset: processor reset active Software Reset cannot programmed. User Reset cannot entered.
13.2.6
Reset Controller Status Register Reset Controller status register (RSTC_SR) provides several status fields:
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RSTTYP field: This field gives type last reset, explained previous sections. SRCMP bit: This field indicates that Software Reset Command progress that further software reset should performed until current one. This automatically cleared current software reset. NRSTL bit: NRSTL Status Register gives level NRST sampled each rising edge. URSTS bit: high-to-low transition NRST sets URSTS RSTC_SR register. This transition also detected Master Clock (MCK) rising edge (see Figure 13-9). User Reset disabled (URSTEN interruption enabled URSTIEN RSTC_MR register, URSTS triggers interrupt. Reading RSTC_SR status register resets URSTS clears interrupt. BODSTS bit: This indicates brownout detection when brownout reset disabled (bod_rst_en triggers interrupt BODIEN RSTC_MR register enables interrupt. Reading RSTC_SR register resets BODSTS clears interrupt. Figure 13-9. Reset Controller Status Interrupt
read RSTC_SR
Peripheral Access
cycle resynchronization NRST NRSTL
cycle resynchronization
URSTS rstc_irq (URSTEN (URSTIEN
13.3
Reset Controller (RSTC) User Interface
Reset Controller (RSTC) Register Mapping
Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0000 0x0000_0000
Table 13-1.
Offset 0x00 0x04 0x08
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13.3.1 Reset Controller Control Register Register Name: RSTC_CR Access Type:
Write-only
EXTRST
PERRST
PROCRST
PROCRST: Processor Reset effect. correct, resets processor. PERRST: Peripheral Reset effect. correct, resets peripherals. EXTRST: External Reset effect. correct, asserts NRST pin. KEY: Password Should written value 0xA5. Writing other value this field aborts write operation.
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13.3.2 Reset Controller Status Register Register Name: RSTC_SR Access Type:
Read-only
SRCMP RSTTYP BODSTS NRSTL
URSTS
URSTS: User Reset Status high-to-low edge NRST happened since last read RSTC_SR. least high-to-low transition NRST been detected since last read RSTC_SR. BODSTS: Brownout Detection Status brownout high-to-low transition happened since last read RSTC_SR. brownout high-to-low transition been detected since last read RSTC_SR. RSTTYP: Reset Type Reports cause last processor reset. Reading this RSTC_SR does reset this field.
RSTTYP Reset Type Power-up Reset Watchdog Reset Software Reset User Reset Brownout Reset Comments VDDCORE rising Watchdog fault occurred Processor reset required software NRST detected Brownout reset occurred
NRSTL: NRST Level Registers NRST Level Master Clock (MCK). SRCMP: Software Reset Command Progress software command being performed reset controller. reset controller ready software command. software reset command being performed reset controller. reset controller busy. 13.3.3 Reset Controller Mode Register Register Name: RSTC_MR
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Access Type:
Read/Write
URSTIEN
ERSTL
BODIEN
URSTEN
URSTEN: User Reset Enable detection level NRST does generate User Reset. detection level NRST triggers User Reset. URSTIEN: User Reset Interrupt Enable USRTS RSTC_SR effect rstc_irq. USRTS RSTC_SR asserts rstc_irq URSTEN BODIEN: Brownout Detection Interrupt Enable BODSTS RSTC_SR effect rstc_irq. BODSTS RSTC_SR asserts rstc_irq. ERSTL: External Reset Length This field defines external reset length. external reset asserted during time 2(ERSTL+1) Slow Clock cycles. This allows assertion duration programmed between seconds. KEY: Password Should written value 0xA5. Writing other value this field aborts write operation.
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Real-time Timer (RTT)
14.1 Overview
Real-time Timer built around 32-bit counter used count elapsed seconds. generates periodic interrupt or/and triggers alarm programmed value.
14.2
Block Diagram
Figure 14-1. Real-time Timer
RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST RTTINCIEN RTT_SR RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS RTT_AR ALMV rtt_alarm
14.3
Functional Description
Real-time Timer used count elapsed seconds. built around 32-bit counter Slow Clock divided programmable 16-bit value. value programmed field RTPRES Real-time Mode Register (RTT_MR). Programming RTPRES 0x00008000 corresponds feeding real-time counter with signal Slow Clock 32.768 Hz). 32-bit counter count seconds, corresponding more than years, then roll over Real-time Timer also used free-running timer with lower time-base. best accuracy achieved writing RTPRES Programming RTPRES possible, result losing status events because status register cleared Slow Clock cycles after read. Thus configured trigger interrupt, interrupt occurs during Slow Clock cycles after reading RTT_SR. prevent several executions interrupt handler, interrupt must disabled interrupt handler re-enabled when status register clear.
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Real-time Timer value (CRTV) read time register RTT_VR (Real-time Value Register). this value updated asynchronously from Master Clock, advisable read this register twice same value improve accuracy returned value. current value counter compared with value written alarm register RTT_AR (Real-time Alarm Register). counter value matches alarm, ALMS RTT_SR set. alarm register maximum value, corresponding 0xFFFF_FFFF, after reset. RTTINC RTT_SR each time Real-time Timer counter incremented. This used start periodic interrupt, period being second when RTPRES programmed with 0x8000 Slow Clock equal 32.768 Reading RTT_SR status register resets RTTINC ALMS fields. Writing RTTRST RTT_MR immediately reloads restarts clock divider with programmed value. This also resets 32-bit counter.
Note: Because asynchronism between Slow Clock (SCLK) System Clock (MCK): restart counter reset RTT_VR current value register effective only slow clock cycles after write RTTRST RTT_MR register. status register flags reset taken into account only slow clock cycles after read RTT_SR (Status Register).
Figure 14-2. Counting
cycle cycle
RTPRES Prescaler
ALMV-1
ALMV
ALMV+1
ALMV+2
ALMV+3
RTTINC (RTT_SR) ALMS (RTT_SR) Interface
read RTT_SR
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14.4 Real-time Timer (RTT) User Interface
Real-time Timer (RTT) Register Mapping
Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000
Table 14-1.
Offset 0x00 0x04 0x08 0x0C
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14.4.1 Real-time Timer Mode Register Register Name: RTT_MR Access Type:
Read/Write
RTPRES RTTRST RTTINCIEN ALMIEN
RTPRES
RTPRES: Real-time Timer Prescaler Value Defines number SLCK periods required increment real-time timer. RTPRES defined follows: RTPRES Prescaler Period equal RTPRES Prescaler Period equal RTPRES. ALMIEN: Alarm Interrupt Enable ALMS RTT_SR effect interrupt. ALMS RTT_SR asserts interrupt. RTTINCIEN: Real-time Timer Increment Interrupt Enable RTTINC RTT_SR effect interrupt. RTTINC RTT_SR asserts interrupt. RTTRST: Real-time Timer Restart Reloads restarts clock divider with programmed value. This also resets 32-bit counter.
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14.4.2 Real-time Timer Alarm Register Register Name: RTT_AR Access Type:
Read/Write
ALMV
ALMV
ALMV
ALMV
ALMV: Alarm Value Defines alarm value (ALMV+1) compared with Real-time Timer. 14.4.3 Real-time Timer Value Register Register Name: RTT_VR Access Type:
Read-only
CRTV
CRTV
CRTV
CRTV
CRTV: Current Real-time Value Returns current value Real-time Timer.
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14.4.4 Real-time Timer Status Register Register Name: RTT_SR Access Type:
Read-only
RTTINC ALMS
ALMS: Real-time Alarm Status Real-time Alarm occurred since last read RTT_SR. Real-time Alarm occurred since last read RTT_SR. RTTINC: Real-time Timer Increment Real-time Timer been incremented since last read RTT_SR. Real-time Timer been incremented since last read RTT_SR.
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Periodic Interval Timer (PIT)
15.1 Overview
Periodic Interval Timer (PIT) provides operating system's scheduler interrupt. designed offer maximum accuracy efficient management, even systems with long response time.
15.2
Block Diagram
Figure 15-1. Periodic Interval Timer
PIT_MR
PIT_MR
PITIEN
PIT_SR
PITS
reset
pit_irq
12-bit Adder
read PIT_PIVR
20-bit Counter
Prescaler
MCK/16
CPIV
PIT_PIVR
PICNT
CPIV
PIT_PIIR
PICNT
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15.3
Functional Description
Periodic Interval Timer aims providing periodic interrupts operating systems. provides programmable overflow counter reset-on-read feature. built around counters: 20-bit CPIV counter 12-bit PICNT counter. Both counters work Master Clock /16. first 20-bit CPIV counter increments from programmable overflow value field Mode Register (PIT_MR). When counter CPIV reaches this value, resets increments Periodic Interval Counter, PICNT. status PITS Status Register (PIT_SR) rises triggers interrupt, provided interrupt enabled (PITIEN PIT_MR). Writing value PIT_MR does reset/restart counters. When CPIV PICNT values obtained reading Periodic Interval Value Register (PIT_PIVR), overflow counter (PICNT) reset PITS cleared, thus acknowledging interrupt. value PICNT gives number periodic intervals elapsed since last read PIT_PIVR. When CPIV PICNT values obtained reading Periodic Interval Image Register (PIT_PIIR), there effect counters CPIV PICNT, PITS. example, profiler read PIT_PIIR without clearing pending interrupt, whereas timer interrupt clears interrupt reading PIT_PIVR. enabled/disabled using PITEN PIT_MR register (disabled reset). PITEN only becomes effective when CPIV value Figure 15-2 illustrates counting. After Enable reset (PITEN= CPIV goes counting until value reached, then reset. restarts counting, only PITEN again. stopped when core enters debug state.
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Figure 15-2. Enabling/Disabling with PITEN
cycle restarts Prescaler Prescaler PITEN cycle
CPIV PICNT PITS (PIT_SR) Interface
read PIT_PIVR
6222C-ATARM-21-Nov-07
15.4
Periodic Interval Timer (PIT) User Interface
Periodic Interval Timer (PIT) Register Mapping
Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000
Table 15-1.
Offset 0x00 0x04 0x08 0x0C
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15.4.1 Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type:
Read/Write
PITIEN PITEN
PIV: Periodic Interval Value Defines value compared with primary 20-bit counter Periodic Interval Timer (CPIV). period equal (PIV PITEN: Period Interval Timer Enabled Periodic Interval Timer disabled when value reached. Periodic Interval Timer enabled. PITIEN: Periodic Interval Timer Interrupt Enable PITS PIT_SR effect interrupt. PITS PIT_SR asserts interrupt. 15.4.2 Periodic Interval Timer Status Register Register Name: PIT_SR Access Type:
Read-only
PITS
PITS: Periodic Interval Timer Status Periodic Interval timer reached since last read PIT_PIVR. Periodic Interval timer reached since last read PIT_PIVR.
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15.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type:
Read-only
PICNT
PICNT
CPIV
CPIV
CPIV
Reading this register clears PITS PIT_SR. CPIV: Current Periodic Interval Value Returns current value periodic interval timer. PICNT: Periodic Interval Counter Returns number occurrences periodic intervals since last read PIT_PIVR.
15.4.4 Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type:
Read-only
PICNT
PICNT
CPIV
CPIV
CPIV
CPIV: Current Periodic Interval Value Returns current value periodic interval timer. PICNT: Periodic Interval Counter Returns number occurrences periodic intervals since last read PIT_PIVR.
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Watchdog Timer (WDT)
16.1 Overview
Watchdog Timer used prevent system lock-up software becomes trapped deadlock. features 12-bit down counter that allows watchdog period seconds (slow clock 32.768 kHz). generate general reset processor reset only. addition, stopped while processor debug mode idle mode.
16.2
Block Diagram
Figure 16-1. Watchdog Timer Block Diagram
write WDT_MR WDT_MR WDT_CR WDRSTT reload
12-bit Down Counter WDT_MR Current Value reload 1/128 SLCK
WDT_MR WDRSTEN wdt_fault Reset Controller) wdt_int
read WDT_SR reset WDERR reset WDUNF reset WDFIEN WDT_MR
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16.3
Functional Description
Watchdog Timer used prevent system lock-up software becomes trapped deadlock. supplied with VDDCORE. restarts with initial values processor reset. Watchdog built around 12-bit down counter, which loaded with value defined field Mode Register (WDT_MR). Watchdog Timer uses Slow Clock divided establish maximum Watchdog period seconds (with typical Slow Clock 32.768 kHz). After Processor Reset, value 0xFFF, corresponding maximum value counter with external reset generation enabled (field WDRSTEN after Backup Reset). This means that default Watchdog running reset, i.e., power-up. user must either disable setting WDDIS WDT_MR) does expect must reprogram meet maximum Watchdog period application requires. Watchdog Mode Register (WDT_MR) written only once. Only processor reset resets Writing WDT_MR register reloads timer with newly programmed mode parameters. normal operation, user reloads Watchdog regular intervals before timer underflow occurs, writing Control Register (WDT_CR) with WDRSTT Watchdog counter then immediately reloaded from WDT_MR restarted, Slow Clock divider reset restarted. WDT_CR register write-protected. result, writing WDT_CR without correct hard-coded effect. underflow does occur, "wdt_fault" signal Reset Controller asserted WDRSTEN Mode Register (WDT_MR). Moreover, WDUNF Watchdog Status Register (WDT_SR). prevent software deadlock that continuously triggers Watchdog, reload Watchdog must occur while Watchdog counter within window between WDD, defined WatchDog Mode Register WDT_MR. attempt restart Watchdog while Watchdog counter between results Watchdog error, even Watchdog disabled. WDERR updated WDT_SR "wdt_fault" signal Reset Controller asserted. Note that this feature disabled programming value greater than equal value. such configuration, restarting Watchdog Timer permitted whole range WDV] does generate error. This default configuration reset (the values equal). status bits WDUNF (Watchdog Underflow) WDERR (Watchdog Error) trigger interrupt, provided WDFIEN mode register. signal "wdt_fault" reset controller causes Watchdog reset WDRSTEN already explained reset controller programmer Datasheet. that case, processor Watchdog Timer reset, WDERR WDUNF flags reset. reset generated WDT_SR read, status bits reset, interrupt cleared, "wdt_fault" signal reset controller deasserted. Writing WDT_MR reloads restarts down counter. While processor debug state idle mode, counter stopped depending value programmed bits WDIDLEHLT WDDBGHLT WDT_MR.
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Figure 16-2. Watchdog Behavior
Watchdog Error Watchdog Underflow WDRSTEN Normal behavior Forbidden Window Permitted Window WDT_CR WDRSTT WDRSTEN
Watchdog Fault
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16.4
Watchdog Timer (WDT) User Interface
Watchdog Timer (WDT) Register Mapping
Register Control Register Mode Register Status Register Name WDT_CR WDT_MR WDT_SR Access Write-only Read/Write Once Read-only Reset Value 0x3FFF_2FFF 0x0000_0000
Table 16-1.
Offset 0x00 0x04 0x08
16.4.1 Watchdog Timer Control Register Register Name: WDT_CR Access Type:
Write-only
WDRSTT
WDRSTT: Watchdog Restart effect. Restarts Watchdog. KEY: Password Should written value 0xA5. Writing other value this field aborts write operation.
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16.4.2 Watchdog Timer Mode Register Register Name: WDT_MR Access Type:
Read/Write Once
WDIDLEHLT WDDBGHLT
WDDIS
WDRPROC
WDRSTEN
WDFIEN
WDV: Watchdog Counter Value Defines value loaded 12-bit Watchdog Counter. WDFIEN: Watchdog Fault Interrupt Enable Watchdog fault (underflow error) effect interrupt. Watchdog fault (underflow error) asserts interrupt. WDRSTEN: Watchdog Reset Enable Watchdog fault (underflow error) effect resets. Watchdog fault (underflow error) triggers Watchdog reset. WDRPROC: Watchdog Reset Processor WDRSTEN Watchdog fault (underflow error) activates resets. WDRSTEN Watchdog fault (underflow error) activates processor reset. WDD: Watchdog Delta Value Defines permitted range reloading Watchdog Timer. Watchdog Timer value less than equal WDD, writing WDT_CR with WDRSTT restarts timer. Watchdog Timer value greater than WDD, writing WDT_CR with WDRSTT causes Watchdog error. WDDBGHLT: Watchdog Debug Halt Watchdog runs when processor debug state. Watchdog stops when processor debug state. WDIDLEHLT: Watchdog Idle Halt Watchdog runs when system idle mode. Watchdog stops when system idle state.
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WDDIS: Watchdog Disable Enables Watchdog Timer. Disables Watchdog Timer.
16.4.3 Watchdog Timer Status Register Register Name: WDT_SR Access Type:
Read-only
WDERR WDUNF
WDUNF: Watchdog Underflow Watchdog underflow occurred since last read WDT_SR. least Watchdog underflow occurred since last read WDT_SR. WDERR: Watchdog Error Watchdog error occurred since last read WDT_SR. least Watchdog error occurred since last read WDT_SR.
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
Voltage Regulator Mode Controller (VREG)
17.1 Overview
Voltage Regulator Mode Controller contains Read/Write register, Voltage Regulator Mode Register. offset 0x60 with respect System Controller offset. This register controls Voltage Regulator Mode. Setting PSTDBY (bit puts Voltage Regulator Standby Mode Low-power Mode. reset, PSTDBY reset, wake Voltage Regulator Normal Mode.
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17.2
Voltage Regulator Power Controller (VREG) User Interface
Voltage Regulator Power Controller Register Mapping
Register Voltage Regulator Mode Register Name VREG_MR Access Read/Write Reset Value
Table 17-1.
Offset 0x60
17.2.1 Voltage Regulator Mode Register Register Name: VREG_MR Access Type:
Read/Write
PSTDBY
PSTDBY: Periodic Interval Value Voltage regulator normal mode. Voltage regulator standby mode (low-power mode).
AT91SAM7SE512/256/32 Preliminary
6222C-ATARM-21-Nov-07
AT91SAM7SE512/256/32 Preliminary
Memory Controller (MC)
18.1 Overview
Memory Controller (MC) manages controls accesses requested masters, typically ARM7TDMI processor Peripheral Controller. features simple arbiter, address decoder, abort status, misalignment detector Embedded Flash Controller. addition, contains Memory Protection Unit (MPU) consisting areas that protected against write and/or user accesses. Access peripherals protected same way.
18.2
Block Diagram
Figure 18-1. Memory Controller Block Diagram
Memory Controller ARM7TDMI Processor Embedded Flash Controller Abort Status Internal Internal Flash
Abort
Arbiter
Misalignment Detector
Address Decoder
Memory Protection Unit
External Interface
User Interface
Peripheral Controller Peripheral Peripheral
Bridge
From Master Slave
Peripheral
6222C-ATARM-21-Nov-07
18.3
Functional Description
Memory Controller handles internal arbitrates accesses both masters. made arbiter address decoder abort status misalignment detector memory protection unit Embedded Flash Controller handles only little-endian mode accesses. masters work little-endian mode only.
18.3.1
Arbiter Memory Controller simple, hard-wired priority arbiter that gives control masters. Peripheral Data Controller highest priority; processor lowest one.
18.3.2
Address Decoder Memory Controller features Address Decoder that first decodes four highest bits 32-bit address defines separate areas: 256-Mbyte address space internal memories Eight 256-Mbyte address spaces, each assigned eight chip select lines External Interface 256-Mbyte address space reserved embedded peripherals undefined address space 1536M bytes that returns Abort accessed
AT91SAM7SE512/256/32 Preliminary
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18.4 External Memory Areas
Figure 18-2 shows assignment 256-Mbyte memory areas. Figure 18-2. External Memory Areas
256M Bytes 256M Bytes 256M Bytes 256M Bytes 0x0000 0000
0x0FFF FFFF
Internal Memories Chip Select Chip Select Chip Select Chip Select Chip Select Chip Select Chip Select Chip Select External Interface
0x1000 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
0x3000 0000
0x3FFF FFFF
0x4000 0000 256M Bytes 256M Bytes 256M Bytes 256M Bytes 256M Bytes
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF 0x9000 0000
256M Bytes 1,536 bytes
0xEFFF FFFF
Undefined (Abort)
256M Bytes
0xF000 0000
0xFFFF FFFF
Peripherals
18.4.1
Internal Memory Mapping Within Internal Memory address space, Address Decoder Memory Controller decodes eight more address bits allocate 1-Mbyte address spaces embedded memories. allocated memories accessed along 1-Mbyte address space repeated times within this address space, equaling bytes divided size memory. When address access undefined within internal memory area, Address Decoder returns Abort master.
6222C-ATARM-21-Nov-07
Figure 18-3. Internal Memory Mapping
0x0000 0000
0x000F FFFF
Internal Memory Area
Bytes
0x0010 0000
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal Memory Area Internal Flash Internal Memory Area Internal SRAM Internal Memory Area Internal
Bytes
Bytes Bytes Bytes
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
18.4.2
Internal Memory Area first bytes Internal Memory Area contain processor exception vectors, particular, Reset Vector address 0x0. Before execution remap command, internal on-chip Flash mapped into Internal Memory Area that ARM7TDMI reaches executable instruction contained Flash. general purpose (GPNVM used boot either (default) from Flash. Setting GPNVM selects boot from Flash, clearing selects boot from ROM. Asserting ERASE clears GPNVM thus selects boot from default. After remap command, internal SRAM address 0x0020 0000 mapped into Internal Memory Area memory mapped into Internal Memory Area accessible both original location address 0x0.
18.4.3
Remap Command After execution, Remap Command causes Internal SRAM accessed through Internal Memory Area vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) mapped from address address 0x20, Remap Command allows user redefine dynamically these vectors under software control. Remap Command accessible through Memory Controller User Interface writing MC_RCR (Remap Control Register) field one. Remap Command cancelled writing MC_RCR field one, which acts toggling command. This allows easy debug user-defined boot sequence offering simple chip same configuration after reset.
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
18.4.4 Abort Status There three reasons abort occur: access undefined address access protected area without permitted state access misaligned address. When abort occurs, signal sent back masters, regardless which generated access. However, only ARM7TDMI take abort signal into account, only under condition that generating access. Peripheral Data Controller does handle abort input signal. Note that connection represented Figure 18-1. facilitate debug fault analysis operating system, Memory Controller integrates Abort Status register set. full 32-bit wide abort address saved MC_AASR. Parameters access saved MC_ASR include: size request (field ABTSZ) type access, whether data read write, code fetch (field ABTTYP) whether access accessing undefined address (bit UNDADD), misaligned address (bit MISADD) protection violation (bit MPU) source access leading last abort (bits MST0 MST1) whether abort occurred each master since last read register (bit SVMST0 SVMST1) unless this information loaded bits case Data Abort from processor, address data access stored. This useful, searching which address generated abort would require disassembling instructions full knowledge processor context. case Prefetch Abort, address have changed, prefetch abort pipelined processor. processor takes prefetch abort into account only read instruction executed probable that several aborts have occurred during this time. Thus, this case, preferable content Abort Link register processor. 18.4.5 Memory Protection Unit Memory Protection Unit allows definition memory spaces within internal memories. Note that external memories protected. After reset, Memory Protection Unit disabled. Enabling requires writing Protection Unit Enable Register (MC_PUER) with PUEB Programming memory spaces done registers MC_PUIA0 MC_PUIA15. size each memory spaces programmable power between bytes bytes. base address also programmable number bits according size. Memory Protection Unit also allows protection peripherals programming Protection Unit Peripheral Register (MC_PUP) with field PROT appropriate value. peripheral address space each internal memory area protected against write non-privileged access masters. When masters performs forbidden access, Abort generated Abort Status traces what happened.
6222C-ATARM-21-Nov-07
There priority protection memory spaces. case overlap between several memory spaces, strongest protection taken into account. access performed address which contained memory spaces, Memory Protection Unit generates abort. reset value MC_PUIAx registers which blocks access first memory starting address which prevents core from reading exception vectors. Therefore, regions must programmed allow read/write access first Bytes memory range during initialization. 18.4.6 Embedded Flash Controller Embedded Flash Controller added Memory Controller ensures interface flash block with 32-bit internal bus. allows increase performance Thumb Mode Code Fetch with system 32-bit buffers. also manages with programming, erasing, locking unlocking sequences thanks full commands. Misalignment Detector Memory Controller features Misalignment Detector that checks consistency accesses. each access, regardless master, size access bits address checked. type access word (32-bit) bits type access half-word (16-bit) abort returned master access cancelled. Note that accesses processor when fetching instructions checked. misalignments generally software bugs leading wrong pointer handling. These bugs particularly difficult detect debug phase. requested address saved Abort Status Register address instruction generating misalignment saved Abort Link Register processor, detection this kind software bugs simplified.
18.4.7
AT91SAM7SE512/256/32 Preliminary
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18.5 Memory Controller (MC) User Interface
Memory Controller (MC) Memory Mapping
Register Remap Control Register Abort Status Register Abort Address Status Register Reserved Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Area Protection Unit Peripherals Protection Unit Enable Register EFC0 Configuration Registers EFC1 Configuration Registers External Interface Registers Configuration Registers SDRAMC Configuration Registers Configuration Registers MC_PUIA0 MC_PUIA1 MC_PUIA2 MC_PUIA3 MC_PUIA4 MC_PUIA5 MC_PUIA6 MC_PUIA7 MC_PUIA8 MC_PUIA9 MC_PUIA10 MC_PUIA11 MC_PUIA12 MC_PUIA13 MC_PUIA14 MC_PUIA15 MC_PUP MC_PUER Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write EFC0 User Interface EFC1 User Interface User Interface User Interface SDRAMC User Interface User Interface Name MC_RCR MC_ASR MC_AASR Access Write-only Read-only Read-only Reset State
Base Address: 0xFFFFFF00 Table 18-1.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x60 0x70 0x80 0x90 0xB0 0xDC
6222C-ATARM-21-Nov-07
18.5.1 Remap Control Register Register Name: MC_RCR Access Type: Absolute Address:
Write-only 0xFFFF FF00
RCB: Remap Command effect. This Command acts toggle basis: writing alternatively cancels restores remapping page zero memory devices.
AT91SAM7SE512/256/32 Preliminary
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AT91SAM7SE512/256/32 Preliminary
18.5.2 Abort Status Register Register Name: MC_ASR Access Type: Reset Value: Absolute Address:
Read-only 0xFFFF FF04
ABTTYP MISADD SVMST1 MST1 ABTSZ UNDADD SVMST0 MST0
UNDADD: Undefined Address Abort Status last abort access undefined address address space. last abort access undefined address address space. MISADD: Misaligned Address Abort Status last aborted access address misalignment. last aborted access address misalignment. MPU: Memory Protection Unit Abort Status last aborted access Memory Protection Unit. last aborted access Memory Protection Unit. ABTSZ: Abort Size Status
ABTSZ Abort Size Byte Half-word Word Reserved
ABTTYP: Abort Type Status
ABTTYP Abort Type Data Read Data Write Code Fetch Reserved
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MST0: ARM7TDMI Abort Source last aborted access ARM7TDMI. last aborted access ARM7TDMI. MST1: Abort Source last aborted access PDC. last aborted access PDC. SVMST0: Saved ARM7TDMI Abort Source abort ARM7TDMI occurred since last read MC_ASR notified MST0. least abort ARM7TDMI occurred since last read MC_ASR. SVMST1: Saved Abort Source abort occurred since last read MC_ASR notified MST1. least abort occurred since last read MC_ASR.
AT91SAM7SE512/256/32 Preliminary
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18.5.3 Abort Addre
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