10-bit Gsps With DMUX AT84AS004 Summary Performances Full-po
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10-bit Resolution Gsps Sampling Rate Fully Compatible with AT84AS003 10-bit Gsps with DMUX Selectable Demultiplexed Output mVpp Differential Single-ended Analog Input Differential Single-ended Clock input LVDS Output Compatibility Functions: Gain Adjust Sampling Delay Adjust Demultiplexed Simultaneous Staggered Digital Outputs Data Ready Output with Asynchronous Reset Out-of-range Output (11th Bit) Power Consumption 6.5W Power Supplies: -5V, -2.2V, 3.3V VPLUSD Output Power Supply Package Cavity Down EBGA (Enhanced Ball Grid Array) Overall Dimensions
10-bit Gsps With DMUX AT84AS004 Summary
Performances
Full-power Analog Input Bandwidth ±0.2 Gain Flatness from Single-tone Performance Gsps, Full First Nyquist Zone ENOB Effective Bits, 1000 SFDR dBFS, 1000 Dual-tone Performance (IMD3) Gsps dBFS each tone) Fin1 MHz, Fin2 1005 MHz: IMD3 dBFS Fin1 1545 MHz, Fin2 1555 MHz: IMD3 dBFS
Screening
Temperature Range: 0°C; 90°C (Commercial Grade) -20°C; 110°C (Industrial Grade)
Applications
Direct Down Conversion Ultra Wide Band Satellite Receivers Radars Countermeasures High-speed Acquisition Systems High Energy Physics Automatic Test Equipment
5431AS-BDC-07/05
Note: This summary document. complete document available this time. more information, please contact your local Atmel sales office.
Description
AT84AS004 combines 10-bit Gsps analog-to-digital converter with DMUX, designed accurate digitization broadband signals. features Effective Number Bits (ENOB) dBFS Spurious Free Dynamic Range (SFDR) Gsps over full first Nyquist zone. demultiplexed digital outputs LVDS logic compatible, allowing easy interfacing with standard FPGAs DSPs .The AT84AS004 operates Gsps, without additional tuning synchronization between DMUX. AT84AS004 comes EBGA317 package. This package same boards, offering excellent reliability when subjected large thermal variations.
Figure Block Diagram
BIST ASYNRST PGEB DRRB
CLK/CLKN
Port AOR/AORN Port BOR/BORN Port COR/CORN Port DOR/DORN DR/DRN
LVDS Buffers
Logic Block
Quantizer
VINN
Demultiplexer
B/GB SLEEP STAGG DRTYPE
AT84AS004
5431AS-BDC-07/05
AT84AS004
Functional Description
AT84AS004 10-bit Gsps combined with high-speed demultiplexer (DMUX) used lower LVDS output stream (10-bit data out-of range bit) factor fully compatible with AT84AS003 10-bit Gsps ADC. works fully differential mode from analog input digital outputs. provides on-chip differential termination clock input. analog input mVpp differential input impedance. reverse terminations required analog input. They should placed close possible EBGA package input pins maximum). output clock output data LVDS compatible (100 differentially terminated). AT84AS004 features asynchronous resets: DRRB, which ensures that first digitized data corresponds first acquisition ASYNCRST, which initializes DMUX gain control used finely adjust gain unity gain. control B/GB provided select either binary gray data output format. Sampling Delay Adjust function (SDA, activated SDAEN signal) used finetune aperture delay approximately around nominal value. This function useful when interleaving multiple ADCs. control B/GB provided select either binary Gray data output format. tunable delay cell (controlled CLKDACTRL) integrated between DMUX clock path fine-tune data according clock alignment interface between DMUX. This delay tuned from -250 around default center value, featuring typical tuning range. tuning should necessary operating frequencies Gsps. extra stand-alone delay cell also provided. controlled analog DACTRL control input activated DAEN. tuning range typically pattern generator (PGEB) integrated block debugging purposes acquisition setup. Similarly, Built-in Self Test (BIST) provided quick debug DMUX block. demultiplexer ratio selected using (1:2 ratio). modes output clock (via DRTYPE) selectable: mode: only output clock's rising egde active, output clock rate same output data rate DR/2 mode: both output clock's rising falling edges active, output clock rate half output data rate AT84AS004's data output different modes: Staggered: even bits output with half data period delay Simultaneous: even bits output same time sleep mode provided lower power consumption DMUX block. junction temperature monitoring also provided facilitate management junction temperature, sensing voltage drop across diode implemented close chip's point.
5431AS-BDC-07/05
AT84AS004 delivered Enhanced Ball Grid Array (EBGA). TCE, which similar that material, makes highly suitable applications exposed large thermal variations. Table 2-1.
Name VCCA VCCD VMINUSD VPLUSD AGND DGND CLK, CLKN VIN, VINN DRRB ASYNCRST DR/DRN A0.A9 A0N.A9N AOR, AORN B0.B9 B0N.B9N BOR/ BORN/ DRB/DRBN C0.C9 C0N.C9N COR/CORN/ DRC/DRCN D0.D9 D0N.D9N
Description Functions
Function Analog 3.3V power supply Digital 3.3V power supply Analog power supply Digital -2.2V power supply Output power supply Analog ground Digital ground Input clock signals Analog input data reset DMUX asynchronous reset Output clock signals Output data port Additional output port Port output clock staggered mode Output data port Additional output port port output clock staggered mode Output data port Additional output port port output clock staggered mode Output data port Name DOR/ DORN/ DRD/DRDN CLKDACTRL DACTRL DAEN DAI, DAIN DAO, DAON SDAEN PGEB B/GB SLEEP Function Additional output port port output clock staggered mode DMUX ratio selection signal Control signal clock delay cell Control signal standalone delay cell Enable signal standalone delay cell Input signals standalone delay cell Output signals standalone delay cell gain adjust sampling delay adjust enable pattern generator Binary gray output code selection Sleep mode selection signal Staggered mode selection data outputs Input clock type selection signal
STAGG
CLKTYPE
DRTYPE
Output clock type selection signal
BIST
Built-in self test Diode junction temperature monitoring (ADC)
DIODE
AT84AS004
5431AS-BDC-07/05
AT84AS004
Figure 2-1. Device Pinout
VCCA VMINUSD VCCD VPLUSD
3.3V
-2.2V 3.3V 2.5V AT84AS004
VIN, VINN CLK, CLKN DRRB ASYNCRST SDAEN PGEB B/GB DACTRL CLKDACTRL DAI, DAIN SLEEP STAGG CLKTYPE DAEN BIST DRTYPE
[A0.A9] [A0N.A9N] AOR, AORN [B0.B9] [B0N.B9N] BOR, BORN [C0.C9] [C0N.C9N] COR, CORN [D0.D9] [D0N.D9N] DOR, DORN DAO, DAON DIODE
AGND
DGND
5431AS-BDC-07/05
Package Information
Figure EBGA Package Outline (Bottom View)
DIMENSIONAL REFERENCES NOM. MIN. 1.25 1.45 0.60 0.50 0.85 0.75
0.10
AT84AS004
MAX. 1.65 0.70 0.95 35.20 25.20 0.90 0.60
CORNER
34.80 24.80
PLATED DETAIL
VIEW BOTTOM VIEW
35.00 33.02 (BSC.) 25.00 22.86 (BSC.) 0.75 1.27 TYP.
0.25
REF.
0.25 0.20
DETAIL
NOTES: DIMENSIONS MILLIMETERS. REPRESENTS BASIC SOLDER BALL GRID PITCH. "MD" "ME" REPRESENTS BASIC SOLDER BALL MATRIX SIZE
PLACES)
DIRECTION RESPECTIVELY, SYMBOL MAXIMUM ALLOWABLE NUMBER BALLS AFTER DEPOPULATING. DIMENSION MEASURED MAXIMUM SOLDER BALL DIAMETER PARALLEL PRIMARY DATUM DIMENSION "ddd" MEASURED PARALLEL PRIMARY DATUM PRIMARY DATUM SEATING PLANE DEFINED SPHERICAL CROWNS SOLDER BALLS. PACKAGE SURFACE SHALL PLATED.
SIDE VIEW
0.30 0.15
DETAIL
BLACK SPOT IDENTIFICATION. ENCAPSULANT SIZE VARY WITH SIZE. "A4" MEASURED EDGE ENCAPSULANT INNER EDGE BALL PAD. DIMENSIONING TOLERANCING ASME Y14.5 1994 OUTLINE DIMENSION REFERENCE JEDEC MS034.
SEATING PLANE
QUALIFICATION PURPOSE ONLY.
DETAIL
MCM-EBGA 35.0x25.0
MARKETING OUTLINE DRAWING
BALL SIZE: 0.762 (before reflow) opening: 0.575
DRAWING
REV.
SHEET
MCM_ADC_DEMUX_sep_04
5431AS-BDC-07/05
AT84AS004
Ordering Information
Part Number AT84XAS004TP
Package EBGA
Temperature Range Ambient Commercial 0°C; 90°C Industrial -20°C; 110°C Ambient
Screening Prototype
Comments Prototype version Please contact your local Atmel sales office
AT84AS004CTP AT84AS004VTP AT84AS004TP-EB
EBGA EBGA EBGA
Standard Standard Prototype Evaluation
5431AS-BDC-07/05
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5431AS-BDC-07/05
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