10-bit Gsps AT84AS008 Performances Full Power Input Bandwidt

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10-bit Gsps AT84AS008 Performances Full Power Input Bandwidt

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10-bit Resolution Gsps Sampling Rate Seamless Ascending Compatibility with TS83102G0B 10-bit Gsps mVpp Full-scale Analog Input Range Differential Single-ended Analog input Clock Input Differential Outputs ECL/LVDS Output Compatibility Functions: Gain Adjust Sampling Delay Adjust Data Ready Output with Asynchronous Reset Out-of-range Output Power Consumption: 4.2W Power supplies: Analog: -5V, Digital: -2.2V 1.5V Radiation Tolerant Package: CBGA152 Cavity Down Hermetic Package Evaluation Board AT84AS008GL-EB Companion Device: DMUX 10-bit 1:2/1:4 LVDS Gsps AT84CS001
10-bit Gsps AT84AS008
Performances
Full Power Input Bandwidth Gain Flatness: ±0.2 (from GHz) Input VSWR: Maximum from Single Tone Performances dBFs): SFDR dBc; ENOB; Gsps, SFDR dBc; ENOB; Gsps, SFDR dBc, ENOB; Gsps, Dual Tone Performances (IMD3), Gps, (-7dBFS tone): (Fin1 MHz, Fin2 1005 MHz): IMD3 dBFS (Fin1 1545 MHz, Fin2 1555 MHz): IMD3 dBFS (Fin1 1945 MHz, Fin2 1955 MHz): IMD3 dBFS Error Rate (10-11) Gsps
Screening
Temperature Range Packaged Device: 90°C (Commercial Grade) -20°C 110°C (Industrial Grade)
Applications
Broadband Direct Down Conversion Wide Band Satellite Receivers Phased Array Antennas, Radars High-speed Instrumentation High-speed Acquisition Systems High Energy Physics Automatic Test Equipment
5404A-BDC-11/06
Description
AT84AS008 10-bit Gsps allows accurate digitization high frequency signals thanks analog input bandwidth. innovative design on-chip Track Hold (T/H) digitizing core lead unprecedented dynamic performance sampling rate (over full first Nyquist zone). ENOB achieved Gsps Nyquist conditions, using gray encoded digital outputs optimum performance. AT84AS008 features enhanced spectral purity very noise floor, independent frequency temperature. particularly well suited performance enhancement (i.e. dithering). AT84AS008 fully compatible with TS83102G0B 10-bit Gsps ADC, allowing zero-effort system improvement plug-and-play replacement with part. Figure 1-1. Block Diagram
PGEB B/GB
Track &Hold VINB Analog Quantizer
Logic block
CLKB
Clock generation
DECB/ DIODE
DRRB
Functional Description
AT84AS008 10-bit Gsps ADC. device includes front-end Track Hold stage (T/H), followed analog encoding stage (Analog Quantizer) which outputs analog residues resulting from analog quantization. Successive banks latches regenerate analog residues into logical levels before entering error correction circuitry resynchronization stage followed differential output buffers. AT84AS008 works fully differential mode from analog inputs digital outputs. differential Data Ready output (DR/DRB) available indicate when outputs valid Asynchronous Data Ready Reset ensures that first digitized data corresponds first acquisition. sampling rates exceeding Gsps, gray output encoding recommended optimum performance.
AT84AS008
5404A-BDC-11/06
AT84AS008
Control B/GB (A11 CBGA package) provided select either binary gray data output format. gain control CBGA package) provided adjust gain transfer function. Sampling Delay Adjust function (SDA) provided fine tune aperture delay, applications requesting interleaving multiple ADCs example. Pattern Generator integrated chip debug acquisition set-up. This function enabled through PGEB CBGA package). range (OR,ORB) indicates when input overrides full-scale range. selectable decimation function also available enhanced testability coverage (A10 CBGA package) along with junction temperature monitoring function. AT84AS008 uses only vertical isolated transistors together with oxide isolated polysilicon resistors, which allows enhanced radiation tolerance (over kRad (Si) expected total dose). AT84AS008 provides full ascending compatibility with TS83102G0B with enhanced performances.
Specifications
Absolute Maximum Ratings
Absolute Maximum Ratings
Symbol DVEE VPLUSD VPLUSD DVEE DVEE VINB VINB (VCLK VCLKB)/2 VCLK VCLKB SDAEN, DRRB, B/GB, PGEB, DECB Comments Value -5.7 -1.1 -5.5 -1.5 -1.5 -1.5 Unit
Table 3-1.
Parameter
Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage difference between digital voltages Maximum difference between negative supply voltages Analog input voltages Maximum difference between VINB Clock input common mode voltage Maximum difference between VCLK VCLKB Static input voltage Digital input voltage Digital output voltage Junction temperature Note:
VPLUSD operating -2.2 VPLUSD operating
Absolute maximum ratings limiting values (referenced 0V), applied individually, while other parameters within specified operating conditions. Long exposure maximum rating affect device reliability. integrated circuits have handled with appropriate care avoid damages ESD. Damage caused inappropriate handling storage could range from performance degradation complete failure.
5404A-BDC-11/06
Recommended Conditions
Recommended Conditions
Symbol VPLUSD Differential output compatibility LVDS output compatibility Comments 4.75 -0.9 1.375 Grounded Maximum operating VPLUSD -5.25 -5.25 Recommended save power when VPLUS above 1.4V(2) differential single-ended (Vinb grounded) single-ended clock input impedance differential input (recommended) Commercial grade Industrial grade Tstg -2.3 -5.0 -5.0 -2.2 -4.75 -4.75 -2.1 mVpp -0.8 1.45 5.25 -0.7 1.525 Unit
Table 3-2.
Parameter
Positive supply voltage
Positive digital supply voltage(1)
VPLUSD VPLUSD VPLUSD
Negative supply voltages Negative supply voltages Negative supply voltages Differential analog input voltage (full-scale) Clock input power level (ground common mode) Operating temperature Range Storage temperature Notes:
DVEE DVEE VINB
PCLK, PCLKB
90°C -20°C 110°C
performances independent VPLUSD common mode voltage performances guaranteed limits specified VPLUSD range (from -0.9V 1.7V). save power DVEE raised -2.2V long difference between VPLUSD DVEE remains greater than 3.5V.
AT84AS008
5404A-BDC-11/06
AT84AS008
Electrical Characteristics
DVEE (unless otherwise specified): performances independent VPLUSD DVEE common mode voltage performances guaranteed limit specified VPLUSD range (from -0.9V 1.7V) DVEE range (from -2.1V, long VPLUSD-VEE 3.5V) VINB mVpp (full-scale single-ended differential Input). Clock inputs differential driven; analog-input single-ended driven Table 3-3.
Parameter Resolution Power Requirements Power supply voltage analog digital (ECL) digital (LVDS) Power supply current analog digital LVDS (DVEE -2.2) LVDS (DVEE Negative supply voltage analog digital Negative supply current analog digital LVDS (DVEE -2.2) LVDS (DVEE Power dissipation LVDS (DVEE -2.2) LVDS (DVEE Analog Inputs Full-scale input voltage range (differential mode) common mode voltage) Full-scale input voltage range (single-ended input option other input grounded) Analog input power level single-ended) Analog input capacitance (die) Input leakage current Input resistance single-ended differential VIN, VINB VIN, VINB -125 -125 -250 VPLUSD VPLUSD IVCC IVPLUSD IVPLUSD IVPLUSD DVEE IVEE IDVEE IDVEE IDVEE -5.25 -5.25 4.75 -0.8 1.45 5.25
Electrical Operating Characteristics Ambient Temperatures Temperatures
Test Level Symbol Unit Bits
-4.75 -4.75
5404A-BDC-11/06
Table 3-3.
Parameter Clock Inputs
Electrical Operating Characteristics Ambient Temperatures Temperatures (Continued)
Test Level Symbol Unit
Logic common mode compatibility clock inputs Clock inputs common voltage range (VCLK VCLKB) coupled clock input) coupled LVDS compatibility (common mode 1.2V) Clock input power level (low-phase noise sinewave input) single-ended differential Clock input swing (single ended; with CLKB GND) Clock input swing (differential voltage) each clock input Clock input capacitance (die) Clock input resistance single-ended differential ended Digital Inputs (SDAEN, PGEB, DECB/Diode, B/GB) logic logic high Digital Inputs (DRRB Only) Logic Compatibility logic logic high Digital Outputs(1) Logic compatibility (depending VPLUSD value) Output levels transmission lines, differentially terminated logic logic high swing (each single-ended output) common mode Logic compatibility (depending VPLUSD value) Output levels transmission lines, differentially terminated logic logic high swing (each single-ended output) common mode(4) VPLUSD 1.525V VPLUSD 1.45V VPLUSD 1.375V
Differential LVDS
-1.2
PCLK
VCLK VCLK VCLKB CCLK RCLK RCLK
±200 ±141
±320 ±226
±500 ±354
Negative -1.810 -1.165 -1.625 -0.880
Differential (VPLUSD -0.8V typical)
-0.99
-1.24 -0.96 -1.1
-1.15 -1.15
LVDS (VPLUSD 1.45V typical) DVEE -2.2V
1250
1050 1280 1160
1100 1310
1010
AT84AS008
5404A-BDC-11/06
AT84AS008
Table 3-3.
Parameter Logic compatibility (depending VPLUSD value) Output levels transmission lines, differentially terminated logic logic high swing (each single-ended output) common mode(4) VPLUSD 1.525V VPLUSD 1.45V VPLUSD 1.375V Accuracy DNLrms Differential non-linearity Integral non-linearity(2) Integral non-linearity Gain central value Gain error drift Input offset voltage Notes:
Electrical Operating Characteristics Ambient Temperatures Temperatures (Continued)
Test Level Symbol Unit
LVDS (VPLUSD 1.45V typical) DVEE
1160
1220 1030
1180
DNLrms DNL+ INLINL+
-2.5
ppm/°C
Differential output buffers impedance differential single-ended). Histogram testing Msps MHz. Gain fine tuned thanks gain adjust function. output common mode only depends VPLUSD value thus adjusted accordingly.
Table 3-4.
Parameter
Electrical Characteristics Ambient Temperatures Temperatures Max)
Test Level Symbol Unit
Analog Inputs
Full power input bandwidth(1) Small signal input bandwidth (10% full-scale) Gain flatness
FPBW SSBW VSWR
±0.2 1.1:1 ±0.3 1.2:1
Input voltage standing wave ratio
Performance: Nominal Condition Ambient Temperature dBFS Single ended input mode (unless otherwise specified), clock duty cycle, 0dBm differential clock (CLK, CLKB), Binary output data format. Signal-to-noise Distortion Ratio Gsps Gsps Gsps Gsps
SINAD
5404A-BDC-11/06
Table 3-4.
Parameter
Electrical Characteristics Ambient Temperatures Temperatures Max) (Continued)
Test Level Symbol Unit
Effective Number Bits Gsps Gsps Gsps Gsps Signal Noise Ratio Gsps Gsps Gsps Gsps Total Harmonic Distortion harmonics) Gsps Gsps Gsps Gsps Spurious Free Dynamic Range Gsps Gsps Gsps Gsps Two-tone Third Order Inter-modulation Distortion Gsps dBFS each tone) Fin1 MHz; Fin2 1005 Fin1 1545 MHz; Fin2 1555 Fin1 1945 MHz; Fin2 1955 Notes:
ENOB
|THD|
|SFDR|
|IMD3|
dBFs
"Definition Terms" page From 1.5GHz Specified from input signal. Input VSWR measured soldered device. assumes external controlled impedance line, driving source impedance (S11 dB).
Table 3-5.
Parameter
Transient Switching Performances
Test Level Symbol Unit
Transient Performance
error rate(1) settling time (VIN-VINB mVpp) Overvoltage recovery time step response rise/fall time (10/90%) Overshoot Ringback
10-11
Error/ Sample
AT84AS008
5404A-BDC-11/06
AT84AS008
Table 3-5.
Parameter
Transient Switching Performances (Continued)
Test Level Symbol Unit
Switching Performance Characteristics Maximum clock frequency(2) Minimum clock frequency
Jitter TR/TF TR/TF |TOD-TDR| TRDR
0.22 0.22
Gsps Msps Clock Cycles
Minimum clock pulse width (high) Minimum clock pulse width (low) Aperture delay Aperture uncertainty
Output rise/fall time DATA (20%-80%)(3) Output rise/fall time DATA READY (20%80%)(3) Data Output Delay(4) Data Ready Output Delay(4) Output Data Data Ready propagation delay(5) Data Ready Output Data propagation delay Output data pipeline delay Data ready reset delay
Notes:
Output error amplitude lsb. 2.2Gsps "Definition Terms" page CLOAD termination (for each single-ended output). Termination load parasitic capacitance derating value: ps/pF (ECL). "Timing Information" page propagation times defined package input/outputs. They given reference only Values given Gsps external clock frequency (50% duty cycle). different sampling rates, apply following formula: +(|TOD-TDR|) +(|TOD-TDR|), where clock period. This places rising edge (True-False) differential Data Ready signal middle Output Data valid window. This gives maximum setup hold times external data acquisition.
Explanation Test Levels
Explanation Test Levels 100% production tested +25°C(1) (for temperature range(2)) 100% production tested +25°C(1), sample tested specified temperatures (for temperature ranges(2)) Sample tested only specified temperatures Parameter guaranteed design characterization testing (thermal steady-state conditions specified temperature) Parameter typical value only guaranteed design only
Table 3-6.
Only minimum maximum values guaranteed (typical values issuing from characterization results).
Notes: Unless otherwise specified. Refer "Ordering Information" page
5404A-BDC-11/06
Functions Description
Functions Description
Function
Table 3-7.
Name
VPLUSD DVEE VIN,VINB CLK,CLKB [D0:D9][D0B:D9B] DR,DRB DRRB PGEB SDAEN DECB/DIODE
Positive power supply: Positive power supply buffers:-0.8V ECL; 1.45V LVDS Negative power supply: Negative power supply buffers:-5V -2.2V LVDS output logic) Differential analog input Differential clock input Differential output data. Differential range Differential data ready Active data ready reset Active pattern generator enable Sampling delay adjust input Active sampling delay adjust enable
VEED VINB SDAEN DECB/DIODE B/GB PGEB DRRB CLKB VDIODE AT84AS008 D0.D9 D0B.D9B VPLUSD 1.45V
Gain adjust input Active decimator enable diode junction temperature monitoring
AT84AS008
5404A-BDC-11/06
AT84AS008
Timing Diagram
Timing Diagram
Analog input External clock Internal clock Latch Latch Regeneration Latches Latch Latch Latch Logic encoding Latch Latch Gray Binary decoding Data ready Pipeline Delay clock cycles Outputs
Figure 3-1.
Gray Binary decoding Output Latches Latch Latch
Detailed timing diagram provided Section page
Coding
Coding Table
Digital Output
Table 3-8.
Differential Analog Input 250.25 250.25 249.75 125.25 124.75 0.25 -0.25 -124.75 -124.25 -249.75 -250.25 -250.25
Voltage Level >Top full-scale full-scale full-scale full-scale full-scale Midscale Midscale full-scale full-scale Bottom full-scale Bottom full-scale Bottom full-scale
Binary (B/GB floating) MSB.LSB Out-of-Range 1111111111 1111111111 1111111110 1100000000 1011111111 1000000000 0111111111 0100000000 0011111111 0000000001 0000000000 0000000000
GRAY (B/GB VEE) MSB.LSB Out-of-Range 1000000000 1000000000 1000000001 1010000000 1110000000 1100000000 0100000000 0110000000 0010000000 0000000001 0000000000 0000000000
5404A-BDC-11/06
Characterization Results
Nominal Conditions
Unless Otherwise specified: -5V, VPLUSD 1.45V 80°C clock duty cycle, binary output data format dBFS analog Input
Full Power Input Bandwidth
Analog input level dBFS Gain flatness -0.5 from Figure 4-1. Full Power Input Bandwidth
-0,5 -1,0 -1,5 -2,0 dBFS -2,5 -3,0 -3,5 -4,0 -4,5 -5,0 -5,5 -6,0 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900
5404A-BDC-11/06
-0.5 Gain Flatness
Bandwidth
(MHz)
VSWR Versus Input Frequency
Figure 4-2. VSWR Curve Analog Input (VIN) Clock (CLK)
VSWR 1000 1500 2000 2500 3000 Frequency (MHz)
AT84AS008
AT84AS008
Step Response
measured sqrt(TrPulseGenerator2 TrADC2) TrPulseGenerator (estimated) Actual TrADC Figure 4-3. Step Response Rise Time Gsps, GHz)
1200 1100 1000 -100 -200 Time (ps) 1000 100%
Dynamic Performance Versus Sampling Frequency
Dynamic Parameters Versus Sampling Frequency Nyquist Conditions (Fin Fs/2)
SFDR (dBc) 1600 1800 (Msps) 2000 2200 1400 1600 SFDR without first Harmonics Dependent independent SFDR
Figure 4-4.
1400
ENOB (Bit)
1800 (Msps)
2000
2200
(dB)
(dB)
1400 1600 1800 (Msps) 2000 2200
1400
1600
1800 (Msps)
2000
2200
5404A-BDC-11/06
Dynamic Performance Versus Input Frequency
Dynamic Parameters Versus Input Frequency Gsps Gsps
Figure 4-5.
SFDR (dBFS)
ENOB (Bit)
1000 1200 1400 1600 1800 2000 2200 (MHz)
1000 1200 1400 1600 1800 2000 2200 (MHz)
(dBFS)
1000 1200 1400 1600 1800 2000 2200 (MHz)
(dBFS)
1000 1200 1400 1600 1800 2000 2200 (MHz)
Gsps, dBFS Analog Input Gsps, dBFS Analog Input
Gsps, dBFS Analog Input Gsps, dBFS Analog Input
Figure 4-6.
SFDR (Minus First Harmonics) Versus Input Frequency Gsps Gsps
SFDR (dBFS)
1000 1200 1400 1600 1800 2000 2200 (MHz) Gsps, dBFS Analog Input Gsps, dBFS Analog Input
AT84AS008
5404A-BDC-11/06
AT84AS008
Signal Spectrum
Gsps, MHz, 1698 MHz, dBFS analog input, kpoint
Fundamental (Fin MHz) Gsps SFDR (H5)
Figure 4-7.
-100 -120 -140 -160
Fundamental (1700 1698 MHz)
-100 -120 -140 -160
SFDR (H2)
Figure 4-8.
Gsps, 1899 MHz, dBFS Analog Input, kpoint
Fundamental (Fin MHz) Gsps SFDR (H2)
Fundamental (1900 1899 MHz)
SFDR (H2)
-100 -120 -140
-100 -120 -140 -160
Figure 4-9.
Gsps, 1098 1998 MHz, dBFS Analog Input, kpoint
Fundamental (Fin 1098 MHz) Gsps SFDR (H3)
Fundamental (2200 1998 MHz)
SFDR (H3)
-100 -120 -140 -160 1000 1100
-100 -120 -140 -160
1100 1050 1000
5404A-BDC-11/06
Dynamic Performance Sensitivity Versus Temperature Power Supply
Figure 4-10. Dynamic Parameters Versus Junction Temperature Gsps, MHz, dBFS Analog Input
(°C)
SFDR (dBc)
ENOB (Bit)
(°C)
(dB)
(dB)
(°C)
(°C)
Figure 4-11. Dynamic Parameters Min., Typ. Max. Power Supplies, dBFS Analog Input
ENOB (Bit)
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
SFDR (dBc)
(dB)
(dB)
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
Gsps
Gsps 1098
Note:
Min. power supplies: 4.75,V -4.75V, VPLUSD 1.375V
Typ. power supplies: -5V, VPLUSD 1.45V Max. power supplies: 5.25V, -5.25V, VPLUSD 1.525V
AT84AS008
5404A-BDC-11/06
AT84AS008
SFDR Performance with without Added Dither
dither profile defined according ADC's pattern well trade-off reached between increase SFDR loss SNR, described Figure 4-12 Please refer application note Dither more information. Figure 4-12. SFDR (dBc dBFS) with without Added Dither (-17 Band Dither) Versus Analog Input Power Gsps,
-100 -110 -120 Level (dB_FS)
Level (dB_FS)
SFDR (dBc dBFS)
SFDR without dither
SFDR with dither
dBFS)
without dither
with dither
4.10
Dual Tone Performance
Figure 4-13. Dual Tone Signal Spectrum Gsps, Fin1 MHz, Fin2 1005 dBFS), IMD3 dBFS.
IMD3 -100 -120 -140 (MHz) dBFS dBFS dBFS dBFS dBFS Fin2 dBFS Fin1 dBFS
dBFS
5404A-BDC-11/06
Figure 4-14. Dual Tone Signal Spectrum Gsps, Fin1=1545 MHz, Fin2 1555 dBFS), IMD3 dBFS.
Fin2 Fin1 dBFS dBFS dBFS IMD3 dBFS dBFS dBFS -100 -120 -140 (MHz)
dBFS
dBFS
Figure 4-15. Dual Tone Signal Spectrum Gsps, Fin1 1945 MHz, Fin2 1955 dBFS), IMD3 dBFS
-100 -120 -140 (MHz) Fin1 dBFS dBFS IMD3 dBFS dBFS dBFS dBFS dBFS Fin2 dBFS
Figure 4-16. Dual Tone Signal Spectrum Gsps, Fin1 1015 MHz, Fin2 1025 dBFS), IMD3 dBFS.
-100 -120 -140 dBFS dBFS dBFS dBFS IMD3 1005 1035 dBFS dBFS Fin2 Fin1 1015 1025 dBFS dBFS
dBFS
dBFS
dBFS
1000 1050 1100 (MHz)
AT84AS008
5404A-BDC-11/06
AT84AS008
Figure 4-17. Dual Tone Signal Spectrum Gsps, Fin1= 1545 MHz, Fin2 1555 dBFS), IMD3 dBFS.
Fin2 dBFS dBFS dBFS dBFS IMD3 dBFS dBFS dBFS Fin1 dBFS
dBFS
-100
-120
-140
100010501100 (MHz)
Figure 4-18. Dual Tone Signal Spectrum Gsps, Fin1=1945 MHz, Fin2 1955 dBFS), IMD3 dBFS.
IMD3 -100 -120 -140 100010501100 (MHz) dBFS dBFS dBFS dBFS dBFS dBFS Fin2 dBFS Fin1 dBFS
4.11
performance
Figure 4-19. Digitizing Broadband Pattern Gsps, Notch Centered Around MHz, dBFS Loading Factor.
0,22 Filter
dBFS
-100
-120 F(MHz)
5404A-BDC-11/06
Description
Table 5-1.
Symbol Power Supplies B10, B11, R11, P12, A14, B14, C14, G14, K14, P14, Q14, R14, B15, Q15, B16, C10, Q10, P10, C11, P11, Q11, A12, B12, C12, Q12, R12, D14, E14, F14, L14, M14, A13, B13, C13, P13, Q13, R13, H14, analog supply (connected same power supply plane)
Description (CBGA 152)
Number Function
Analog ground
analog supply (connected same power supply plane) Digital positive supply -2.2V digital power supply
VPLUSD DVEE Analog Inputs VINB Clock Inputs CLKB Digital Outputs D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B, D8B, Additional Functions
In-phase analog input signal differential sample hold preamplifier Inverted phase analog input signal differential sample hold preamplifier
In-phase clock input Inverted phase clock input
D16, E16, F16, G16, J16, K16, L16, M16, N16, D15, E15, F15, G15, J15, K15, L15, M15, N15,
In-phase digital outputs LSB, Inverted phase digital outputs In-phase out-of-range output Inverted phase out-of-range output In-phase data ready signal output Inverted phase data ready signal output
B/GB
Binary gray select output format control binary output format B/GB floating connected gray output format B/GB connected
AT84AS008
5404A-BDC-11/06
AT84AS008
Table 5-1.
Symbol
Description (CBGA 152) (Continued)
Number Function Decimation function enable junction temperature measurement: Decimation active when (die junction temperature monitoring then possible) Normal mode when high left floating junction temperature monitoring when current applied Active pattern generator enable Digitized input delivered outputs according B/GB PGEB floating connected Checker Board pattern delivered outputs PGEB connected Asynchronous data ready reset function (active level) Gain adjust Sampling delay adjust Sampling delay adjust enable inactive floating connected active connected
DECB DIODE
PGEB
DRRB SDAEN
5404A-BDC-11/06
Figure 5-1.
CBGA152 Pinout
DIODE DECB/ PGEB
AT84AS008 CBGA
BOTTOM VIEW
Notes:
required, balls electrically connected simplifying routing. pinout given with BOTTOM view. columns rows were defined different from JEDEC standard.
5.1.1
Package Description
Hermetic CBGA Outline Dimensions Ceramic body size: Ball pitch: 1.27 Cofired: Al2O3 Optional: discrete capacitor mounting lands side package extra decoupling.
AT84AS008
5404A-BDC-11/06
AT84AS008
Figure 5-2. Mechanical Description Bottom View
Chamfer
Metalic 9.27 9.27
21.00 ±0.20
21.00 0.20
Index ball)
0.80 0.10 0.20 (Position array columns/ref 0.15 (Position balls within array)
5.1.2
Mechanical View Figure 5-3. Isometric View
1.27 pitch
5404A-BDC-11/06
Figure 5-4.
Package View
21.00
2.50
4.335 9.085
4.335
7.20 9.00
10.685
2.50
These lands designed discrete capacitor device 0603 size (1.6
2.50
9.270
Marking Area
6.815 2.50
Marking Area
5.605
brazed metallization
connected
Index (0.50 Full Circle)
Figure 5-5.
Package View with Optional Discrete Capacitors
21.00
2.50
4.335 9.085 10.685
4.335
7.20 9.00
2.50
2.50
9.270
Capacitor discrete devices 0603 size (1.6 Thickness Weight each
Marking Area
2.50
6.815
5.605
Marking Area
brazed metalization
connected
Index (0.50 Full Circle)
Note:
additional decoupling power supplies, extra land capacitors have been foreseen shown this scheme. They needed evaluation board decoupling recommendations followed standard power supply used switched power supply). Performance results device have proven equivalent with without these capacitors.
AT84AS008
5404A-BDC-11/06
AT84AS008
5.1.3 Cross Section
CBGA 21x21 Cross Section bits/2.2 Gsps ADC. External heatsink required
0.25
Al2O3 ceramic
Solder balls Diam 0.76 1.27 grid
0.15
Combo soldered 9.27 0.254 thick Grounded
heatspreader brazed Al2O3 VEE=-5 Volt potential
Location external heatsink
1.25 0.12
0.65
0.50 0.05
1.27
0.80
5404A-BDC-11/06
5.1.4
CBGA Cavity, Wirebonding Resistor Pairs CBGA Cavity, Wirebonding Resistor Pairs
Figure 5-6.
termination resistors soldered into package cavity
5.2.1
Thermal Moisture Characteristics
Dissipation Conduction Convection thermal resistance from junction ambient RTHJA around 30°C/W. Therefore, lower RTHJA mandatory external heatsink improve dissipation convection conduction. heatsink should fixed contact with side package (CuW heatspreader over Al2O3) which -5V. heatsink needs electrically isolated; using adequate electrical isolation. Example: thermal resistance from case ambient RTHCA typically 4.0°C/W flow still air) with heatsink depicted figure dimensions 50mm 50mm 22mm (respectively Global junction ambient thermal resistance RTHJA 4.35°C/W RTHJC +2.0°C/W thermal grease resistance +4.0°C/W RTHCA (case ambient) 0.35°C/W total (RTHJA).
AT84AS008
5404A-BDC-11/06
AT84AS008
Assuming: Typical thermal resistance from junction bottom case RTHJC 4.35oC/Watt (Finite Element Method thermal simulation results).This value does include thermal contact resistance between package external heatsink (glue, paste, thermal foil interface example). example, 2.0°C/W value thickness thermal grease.
Note:
Example calculation ambient temperature ensure 110°C: Assuming RTHJA 10.35°C/W Power dissipation 4.6W, (RTHJA 4.6W) -(10.35 4.6) 62.39°C increased lowering RTHJA with adequate flow m/s, example).
Figure 5-7.
Black Anodized Aluminum Heatsink Glued Copper Base Screwed Board (All Dimensions mm).
Circular Base (diam. Heat Spreader Tied
Black Anodized Aluminium
Copper Base with Standoffs
AI203
Board
Holes Screw (diam.
Cooling system efficiency monitored using temperature sensing diodes, integrated device. 5.2.2 Thermal Dissipation Conduction Only When external heatsink cannot used relevant thermal resistance thermal resistance from junction bottom balls: J-Bottom-of-balls. Thermal path, this case, junction, then silicon, glue, heatspreader, Al2O3 package, balls (Sn63Pb37). Finite Element Method (FEM) with thermal simulator lead J-bottom balls 12.3°C/Watt. This value assume pure conduction from junction bottom balls.(that worst case, radiation convection applied). With such assumption Bottom-of-balls user independent. complete thermal analysis, user must thermal resistance from board which soldered device) ambient, which value user dependent (type board, thermal via, area covered copper each layer board, thickness, airflow cold plate parameters consider).
5404A-BDC-11/06
Equivalent Input/Output Schematics
Figure 6-1. Equivalent Analog Input Circuit Protection
Controlled Transmission Line (Bonding Package Ball)
Double
Pads
VINB Double Controlled Transmission Line (Bonding Package Ball)
Note:
termination point located inside package cavity coupled ground.
Figure 6-2.
Equivalent Analog Clock Input Circuit Protection
Double Double CLKB Double
5404A-BDC-11/06
Note:
termination point chip coupled ground through capacitor.
AT84AS008
1.5V
Package Pins
Terminati Resistors Soldered into Package Cavity
AT84AS008
Figure 6-3. Equivalent Data Output Buffer Circuit Protection
VPLUSD 10.5 VPLUSD VPLUSD OUTB
DVEE
Figure 6-4.
Gain Adjust Equivalent Input Circuits Protection
0.9V
Figure 6-5.
B/GB PGEB Equivalent Input Schematics Protection
B/GB -1.3V
5404A-BDC-11/06
Figure 6-6.
DRRB Equivalent Input Schematic Protection
DRRB
-2.6V
-1.3V
Figure 6-7.
DECB/DIODE Equivalent Input Schematic Protection
Tsense DECB/DIODE -1.3V
AT84AS008
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AT84AS008
Definition Terms
Table 7-1.
Term Maximum Sampling Frequency Minimum Sampling frequency
Definition Terms
Description Sampling frequency which ENOB bits Sampling frequency which Gain fallen 0.5dB with respect gain reference value. Performances guaranteed below this frequency Probability exceed specified error threshold sample maximum specified sampling rate. error code code that differs more than from correct code Analog input frequency which fundamental component digitally reconstructed output waveform fallen with respect frequency value (determined analysis) input full-scale dBFS) Analog input frequency which fundamental component digitally reconstructed output waveform fallen with respect frequency value (determined analysis) input full-scale dBFS) Ratio expressed signal amplitude, below fullscale dBFS), other spectral components, including harmonics except Ratio expressed signal amplitude, below fullscale, other spectral components excluding twenty five first harmonics Ratio expressed first twenty five harmonic components, input signal amplitude, below full-scale. reported (i.e, related converter full-scale), (i.e, related input signal level Ratio expressed signal amplitude, below fullscale, value highest spectral component (peak spurious spectral component). peak spurious component harmonic. reported (i.e., related converter full-scale), (i.e, related input signal level) SINAD ENOB Where actual input amplitude full-scale range under test
Error Rate
FPBW
Full Power Input Bandwidth
SSBW
Small Signal Input Bandwidth
SINAD
Signal-to-noise Distortion Ratio
Signal-to-noise Ratio
Total Harmonic Distortion
SFDR
Spurious Free Dynamic Range
ENOB
Effective Number Bits
Differential Non-Linearity
Differential non-linearity output code difference between measured step size code ideal step size. expressed LSBs. maximum value (i). error specification less than guarantees that there missing output codes that transfer function monotonic Integral non-linearity output code difference between measured input voltage which transition occurs ideal value this transition. expressed LSBs, maximum value Delay between rising edge differential clock inputs (CLK,CLKB) (zero crossing point), time which (VIN,VINB) sampled
Integral Non-Linearity
Aperture Delay
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Table 7-1.
Term JITTER
Definition Terms (Continued)
Description Aperture Uncertainty Settling Time Overvoltage Recovery Time Sample sample variation aperture delay. voltage error jitter depends slew rate signal sampling point Time delay achieve 0.2% accuracy converter output when full-scale step function applied differential analog input Time recover 0.2% accuracy output, after 150% full-scale step applied input reduced midscale Delay from rising edge differential clock inputs (CLK,CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load Delay from falling edge differential clock inputs (CLK,CLKB) (zero crossing point) next point change differential data ready output (zero crossing) with specified load General expression with encoding clock period General expression with encoding clock period Minimum clock pulse width (high) TC2TC2 Minimum clock pulse width (low) Number clock cycles between sampling edge input data associated output data being made available, (not taking account TOD) Delay between falling edge Data Ready output asynchronous Reset signal (DDRB) reset digital zero transition Data Ready output signal (DR) Time delay output DATA signals rise from delta between level high level Time delay output DATA signals fall from delta between level high level Ratio input offset variation change power supply voltage When input signal larger than upper bound input range, output code identical maximum code Range logic one. When input signal smaller than lower bound input range, output code identical minimum code, range logic one. assumed that input signal amplitude remains within absolute maximum ratings) tones Inter-modulation distortion (IMD) rejection ratio either input tone worst third order Inter-modulation products measured characterize performance response broad bandwidth signals. When applying notch-filtered broadband whitenoise signal input under test, Noise Power Ratio defined ratio average out-of-notch average in-notch power spectral density magnitudes spectrum output sample test VSWR corresponds input insertion loss input power reflection. example VSWR corresponds return loss (i.e. power transmitted reflected)
Digital Data Output Delay
Data Ready Output Delay Time Delay from Data Transition Data Ready Time Delay from Data Ready Data Encoding Clock period Pipeline Delay
TRDR
Data Ready Reset Delay
PSRR
Rise Time Fall Time Power Supply Rejection Ratio
Return Zero
Inter-Modulation Distortion
Noise Power Ratio
VSWR
Voltage Standing Wave Ratio
AT84AS008
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AT84AS008
AT84AS008 Application Information
8.1.1
Timing Information
Timing Value AT84AS008 Timing values defined Section 3.3. Timing values given package inputs/outputs, taking into account package transmission line, bond wire, protections capacitance, specified termination loads. Evaluation board propagation delays controlled impedance traces taken into account. Apply proper derating values corresponding termination topology.
8.1.2
Propagation Time Considerations Timing values given from package include additional propagation times between device pins input/output termination loads. evaluation board, propagation time delay ps/mm (155 ps/inch) corresponding dielectric constant 10GHz) RO4003 used board. different dielectric layer used (for instance Teflon), please appropriate propagation time values. depend propagation times because they differential data (See "Definition Terms" page 31.). also most straightforward data measure, because differential: measured directly onto termination loads, with matched oscilloscope probes.
8.1.3
TOD-TDR Variation over Temperature Values track each other over temperature percent variation degrees Celsius temperature variation). Therefore variation over temperature negligible. Moreover, internal chip) skews between each data TODs effect considered negligible. Consequently, minimum values never more than apart. same true maximum values. However, external values dictated total digital data skews between every TODs (each digital data) TDR: board, bonding wires output line length differences, output termination impedance mismatches. external board) skew effect been taken into account specification minimum maximum values TDR.
8.1.4
Principle Operation analog input sampled rising edge external clock input (CLK,CLKB) after (aperture delay). digitized data available after clock periods latency (pipeline delay (TPD)), clock rising edge, after typical propagation delay TOD. Data Ready differential output signal frequency (DR, DRB) half external clock frequency, switches same rate digital outputs. Data Ready output signal (DR, DRB) switches external clock falling edge after propagation delay TDR. TDR, rising edge (True-False) differential Data Ready signal placed middle output data valid window. This gives maximum setup hold times external data acquisition. Master asynchronous reset input command DRRB (ECL compatible single-ended input) available initializing differential Data Ready output signal (DR,DRB). This feature man-
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datory certain applications using interleaved ADCs using single with demultiplexed outputs. Without Data Ready signal initialization, impossible store output digital data defined order. When used with AT84CS001 1:2/1:4 DMUX, required initialize Data Ready, this device start either clock edge.
8.2.1
Principle Data Ready Signal Control DRRB Input Command
Data Ready Output Signal Reset Data Ready signal reset falling edge DRRB input command, logical level (-1.8V). DRRB also tied Data Ready output signal Master Reset. long DRRB remains logical level, tied -5V), Data Ready output remains logical zero independent external free running encoding clock. Data Ready output signal (DR,DRB) reset logical zero after TRDR. TRDR measured between -1.3V point falling edge DRRB input command zero crossing point differential Data Ready output signal (DR,DRB).The Data Ready Reset command pulse minimum time width.
8.2.2
Data Ready Output Signal Restart Data Ready output signal restarts DRRB command rising edge, logical high levels (-0.8V). DRRB also Grounded, allowed float, normal free running Data Ready output signal. Data Ready signal restart sequence depends logical level external encoding clock, DRRB rising edge instant: DRRB rising edge occurs when external encoding clock input (CLK,CLKB) low: Data Ready output first rising edge occurs after half clock period clock falling edge, after delay time already defined here above. DRRB rising edge occurs when external encoding clock input (CLK,CLKB) high: Data Ready output first rising edge occurs after clock period clock falling edge, delay Consequently, analog input sampled clock rising edge, first digitized data corresponding first acquisition after Data Ready signal restart (rising edge) always strobed third rising edge data ready signal. time delay (TD1) specified between last point change differential output data (zero crossing point) rising falling edge differential Data Ready signal (DR,DRB) (zero crossing point). Note: normal initialization Data Ready output signal, external encoding clock signal frequency level must controlled. reminded that minimum encoding clock sampling rate MSPS, internal droop rate. Consequently clock cannot stopped without corrupting current held data.
AT84AS008
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AT84AS008
8.2.3 Timing Diagram with Data Ready Reset Figure 8-1. AT84AS008 Timing Diagram Gsps Clock Rate) Data Ready Reset, Clock Held Level
VIN/VINB CLK/CLKB
Clock Period
Digital Outputs Data Ready DR/DRB Data Ready Reset
TRDR
Figure 8-2.
AT84AS008 Timing Diagram Gsps Clock Rate) Data Ready Reset, Clock Held High Level
VIN/VINB CLK/CLKB Digital Outputs
Clock Periods
Data Ready DR/DRB Data Ready Reset TRDR
8.3.1
Analog Inputs (VIN/VINB)
Static Issues: Differential Versus Single-ended (Full-scale Inputs) front-end Track Hold differential preamplifier been designed order entered either differential mode single-ended mode, maximum operating speed (2.2 Gsps), without affecting dynamic performances (does request single differential balun). single-ended input configuration, in-phase full-scale input amplitude 0.5V peak-to-peak, centered into 50).
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Figure 8-3.
Typical Single-ended Analog Input Configuration (Full-scale)
+250 +250 VINB
Full-scale Analog Input
-250
analog input full-scale range 0.5V peak peak (Vpp), into (100 differential) termination resistor. differential mode input configuration, that means 0.25V each input, ±125 around zero volt. input common mode ground. Figure 8-4. Differential Inputs Voltage Span (Full-scale)
+125 +250 -250 VINB
Full-scale Analog Input
-125
8.3.2
Dynamic Issues: Input Impedance VSWR AT84AS008 analog input features (±2%) differential input impedance pF): Each analog input (VIN,VINB) terminated single-ended (100 differential) resistors (±2% matching) soldered into package cavity. package Analog Inputs transmission lines feature controlled impedance. Each single-ended input capacitance (taking into account protection) This leads global input VSWR (including ball, package bounding) less than from GHz.
Clock Inputs (CLK/CLKB)
AT84AS008 clock inputs designed either single-ended differential operation. AT84AS008 clock inputs chip differentially terminated. Termination point coupled ground through chip capacitor. Therefore either ground different common modes could used (ECL, LVDS). However logic LVDS square wave clock generators recommended because poor jitter performances.
AT84AS008
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AT84AS008
Furthermore, propagation times biasing tees used offset common mode voltage LVDS levels match. very phase noise (low jitter) sinewave input signal should used enhanced performance, when digitizing high frequency analog inputs. Typically, using sinewave oscillator featuring -135 dBc/Hz phase noise, from carrier, global jitter value (including generator) less than been measured. clock signal frequency fixed rates, recommended narrow band filter signal improve jitter performance. Note: clock input buffer termination load chip, point coupled (40pF) chip ground plane, whereas analog input buffer termination soldered inside package cavity, point coupled package ground plane. Therefore, driving analog input single ended does perturb chip ground plane, (since termination point connected package ground plane). driving clock input single ended will perturb chip ground plane, (since termination point coupled chip ground plane). Therefore, required drive clock input differential, minimum chip ground plane perturbation operating recommended). Typical clock input power dBm. minimum operating clock input power (equivalent minimum swing amplitude), avoid performances degradations linked clock signal slew rate. single differential balun with sqrt ratio used (featuring input impedance with differential termination). instance: equivalent into into termination (secondary) equivalent 0.632 into 0.632 sqrt 0.894 into termination (secondary), ±0.226V each clock input Recommended clock inputs common mode ground. 8.4.1 Differential Clock Inputs Voltage Levels Typical) Figure 8-5. Differential Clock Inputs (Ground Common Mode): Recommended
+0.23 CLKB
-0.23
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8.4.2
Equivalent Single-ended Clock Inputs Voltage Levels Typical) Figure 8-6. Single-ended Clock Input (Ground Common Mode)
+0.32 CLKB
-0.32
Noise Immunity Information
Circuit noise immunity performance begins design level. Efforts have been made design order make device insensitive possible chip environment perturbations resulting from circuit itself induced external circuitry (cascode stages isolation, internal damping resistors, clamps, internal chip decoupling capacitors.) Furthermore, fully differential operation from analog input digital outputs provides enhanced noise immunity common mode noise rejection. Common mode noise voltage induced differential analog clock inputs will cancelled these balanced differential amplifiers. Moreover, proper active signals shielding been provided chip reduce amount coupled noise active inputs: analog inputs clock inputs TS83102G0B device have been surrounded ground pins, which must directly connected external ground plane.
Digital Outputs: Termination Logic Compatibility
Each single-ended output AT84AS008 differential output buffers internally terminated, feature differential output impedance. resistors connected VPLUSD digital power supply. AT84AS008 output buffers designed drive controlled impedance lines properly terminated resistor. 10.5 bias current flowing alternately into resistors when switching ensures 0.25V single-ended voltage drop across resistor (0.5V differential) Each single-ended output transmission line length must kept identical (keep mm). Mismatches differential line lengths cause output differential common mode variation. recommended bypass midpoint differential termination with capacitor avoid common mode perturbation case slight mismatch differential output line lengths. recommended-termination scenarios here below.
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AT84AS008
Note: Since output buffers feature differential output impedance, possible drive directly high input impedance storing registers, without terminating transmission lines. time domain, this means that incident wave will reflect transmission line output travel back data output buffer. Since buffer output impedance back reflection will occur output swing will doubled.
VPLUSD Digital Power Supply Settings: differential digital output levels: VPLUSD should supplied with -0.8V connect ground resistor ensure -0.8V voltage drop). LVDS digital output logic compatibility, VPLUSD should tied 1.45V (±75mV).
8.6.1
differential output termination configurations Figure 8-7. Terminated Differential Outputs (Recommended)
VPLUSD -0.8V
OUTB
-1.17V -0.94V Differential Output Swing: ±0.23V 0.46 Common Mode Level -1.05V
10.5
Figure 8-8.
Unterminated Differential Outputs (Optional)
VPLUSD -0.8V
OUTB
-1.4V -0.94V Differential Output Swing: ±0.46V 0.92 Common Mode Level -1.17V
10.5
5404A-BDC-11/06
8.6.2
LVDS Differential Output Loading Configurations Figure 8-9. Terminated Differential Outputs
VPLUSD 1.45V
OUTB
1.09V 1.31V Differential Output Swing: ±0.23 0.46 Common Mode Level 1.20V
10.5
Figure 8-10. Unterminated Differential Outputs (Optional)
VPLUSD 1.45V
Zc=50 OUTB Zc=50
0.85V 1.31V Differential Output Swing: ±0.46V 0.92 Common Mode Level -1.08V
10.5
8.6.3
LVDS Logic Compatibility LVDS FORMAT IEEE 1596.3- 1994): 1125mV< Common mode<1275mV 250mV< Output swing< 400mV.
Common Mode (Each Single-ended Output
Swing
1.575V
Swing Swing
1275 1125 False-True Output 0.825V True-False Output
Output Swing ±300 Output Swing ±200
1.575V
1.075V
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AT84AS008
8.7.1
Main Functions
Range (OR/ORB) goes logical high state when input exceeds positive full-scale falls below negative full-scale. When analog input exceeds positive full-scale, digital outputs remain high logical state, with (OR,ORB) logical one. When analog input falls below negative full-scale, digital outputs remain logical state, with (OR,ORB) logical again.
8.7.2
Error Rate (BER) AT84AS008 internal regeneration latches indecision (for inputs very close latches threshold) produce errors logic encoding circuitry leading large amplitude output errors. This fact that latches regenerating internal analog residues into logical states with finite voltage gain value (Av) within given positive amount time D(t): exp(D(t)/), with positive feedback regeneration time constant. AT84AS008 been designed reducing probability occurrence such errors 10-12. standard technique reducing amplitude such errors down consists setting digital output data gray code format. Though AT84AS008 been designed featuring Error Rate 10-12 with binary output format.
8.7.3
Gray Binary Output data format select possible user choose between binary gray output data format, order reduce amplitude such errors when occurring, storing gray output codes. Digital Data format selection: BINARY output format B/GB floating GND. GRAY output format B/GB connected VEE.
8.7.4
Pattern Generator Function Pattern Generator function (enabled connecting PGEB -5V) allows check rapidly operation thanks checker board pattern delivered internally ADC. Each output should toggle from successively, giving sequences such 0101010101 (strobed falling edge 1010101010 (strobed rising edge every clock cycles. DECB/DIODE: Junction Temperature Monitoring Output Decimation Enable DECB/DIODE provided both decimation function enable junction temperature monitoring. When -5V, runs decimation mode data output from ADC, thus reducing data rate 32). When DECB/DIODE left floating high, then said normal mode operation (output data decimated) used junction temperature monitoring only. user does intend junction temperature monitoring function, DECB/DIODE (A10) left either floating connected ground.
8.7.5
5404A-BDC-11/06
decimation function used debug initial stages. This function indeed allows reduce output rate thus allowing quick debug phase speed rate compatible with industrial testing environment. When active, this function makes output only data, thus resulting data rate which times slower than clock rate.
Note: decimation test mode different from pattern generator function, which used check outputs.
8.7.6
External Configurations Description Because internal diode-mounted transistor (used junction temperature monitoring), user implement external head-to-tail protection diodes avoid potential reverse currents flows which damage internal diode component. external configurations possible: Configuration allowing both junction temperature monitoring output data decimation. Configuration allowing junction temperature monitoring only. Configuration allowing both Junction temperature monitoring output data decimation. This external configuration allows apply requested levels activate output data decimation (ECL -5V) same time monitor junction temperature diode (this explains seven protection diodes needed other direction, described following figure). Figure 8-11. Recommended Diode Implementation allowing both junction temperature monitoring function Decimation mode. Figure 8-12. Diode Implementation Decimation Activation
Configuration junction temperature monitoring only this mode decimation cannot activated).
Note: preliminary specification recommended head-to-tail protection diodes. Final updated configuration described figure here below.
AT84AS008
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AT84AS008
Figure 8-13. Diode implementation Junction Temperature Monitoring Function Only
IGND Idiode Vdiode VGND
Figure 8-14. Junction Temperature Diode Transfer Function forward voltage drop, (VDIODE) across diode component, versus junction temperature, (including chip parasitic resistance), given below (IDIODE mA):
Diode voltage (mV)
Tamb avec radiateur
Jonction temperature (°C)
Note:
operating junction temperature must kept below 125°C, ensure long term device reliability.
5404A-BDC-11/06
8.7.7
Gain Control gain adjustable means CBGA package. gain adjust transfer function given below:
1.30 1.20 1.10 1.00 Gain 0.90 0.80 0.70 0.60 0.50 -0.5 -0.4 -0.3 -0.2 -0.1 Typical
Gain Adjust Voltage
8.7.8
Sampling Delay Adjust Sampling delay adjust (SDA pin) allows fine tune sampling aperture delay around nominal value (160 ps). This functionality enabled thanks SDAEN signal, which active when tied inactive when tied GND. This feature particularly interesting interleaving ADCs increase sampling rate. variation delay around nominal value function voltage shown following graph (simulation result):
Figure 8-15. Typical Tuning Range ±120 Applied Control Voltage Varying Between -0.5V 0.5V
Delay Variable Delay Cell
Delay(s)
-500 -400 -300 -200 -100 0.00
Note:
variation delay function temperature negligible.
AT84AS008
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AT84AS008
Ordering Information
Part Number AT84AS008CGL AT84AS008VGL Package CBGA152 CBGA152 Temperature Range Commercial grade 90°C Industrial grade -20°C 110°C Ambient Screening Level Standard Standard Evaluation board (delivered with heat sink) Comments
AT84AS008GL-EB
CBGA152
Prototype
Appendix
Datasheet Status
Status Objective specification Target specification Preliminary specification Alpha-site Preliminary specification Beta-site Product specification This datasheet contains target goal specifications discussion with client application validation This datasheet contains target goal specifications product development This datasheet contains preliminary data. Additional data published later date could include simulation results This datasheet also contains characterization results This datasheet contains final product specifications Limiting Values Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given characteristics sections specification implied. Exposure limiting values extended periods affect device reliability Application Information Where application information given, advisory does form part specification Validity Before design phase Valid during design phase Valid before characterization phase Valid before industrialization phase Valid production purposes
10.1
Life Support Applications
These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. customers using selling these products such applications their risk agree fully indemnify damages resulting from improper sale.
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AT84AS008
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AT84AS008
Description Functional Description Specifications
3.1Absolute Maximum Ratings 3.2Recommended Conditions 3.3Electrical Characteristics 3.4Explanation Test Levels 3.5Functions Description 3.6Timing Diagram 3.7Coding
Characterization Results
4.1Nominal Conditions 4.2Full Power Input Bandwidth 4.3VSWR Versus Input Frequency 4.4Step Response 4.5Dynamic Performance Versus Sampling Frequency 4.6Dynamic Performance Versus Input Frequency 4.7Signal Spectrum 4.8Dynamic Performance Sensitivity Versus Temperature Power Supply 4.9SFDR Performance with without Added Dither 4.10Dual Tone Performance 4.11NPR performance
Description
5.1Package Description 5.2Thermal Moisture Characteristics
Equivalent Input/Output Schematics Definition Terms AT84AS008 Application Information
8.1Timing Information 8.2Principle Data Ready Signal Control DRRB Input Command 8.3Analog Inputs (VIN/VINB) 8.4Clock Inputs (CLK/CLKB) 8.5Noise Immunity Information 8.6Digital Outputs: Termination Logic Compatibility
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8.7ADC Main Functions
Ordering Information
Appendix
10.1Life Support Applications
AT84AS008
5404A-BDC-11/06
Whilst technologies taken care ensure accuracy information contained herein accepts responsibility consequences thereof also reserves right change specification goods without notice. technologies accepts liability beyond that standard conditions sale respect infringement third party patents arising from tubes other devices accordance with information contained herein.
5404A-BDC-11/06

10-bit Gsps AT84AS008 Performances Full Power Input Bandwidt

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