10-bit Gsps With DMUX AT84AS003 Performances Full-power Anal

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10-bit Gsps With DMUX AT84AS003 Performances Full-power Anal

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10-bit Resolution Gsps Sampling Rate Selectable Demultiplexed Output mVpp Differential Single-ended Analog Input Differential Single-ended Clock Input LVDS Output Compatibility Functions: Gain Adjust Sampling Delay Adjust Demultiplexed Simultaneous Staggered Digital Outputs Data Ready Output with Asynchronous Reset Out-of-range Output (11th Bit) Power Consumption: 6.5W Power Supplies: -5V, -2.2V, 3.3V VPLUSD Output Power Supply Package Cavity Down EBGA (Enhanced Ball Grid Array) Overall Dimensions
10-bit Gsps With DMUX AT84AS003
Performances
Full-power Analog Input Bandwidth Gain Flatness from Single-tone Performance Gsps, Full First Nyquist Zone ENOB Bits, dBc, SFDR dBc, Dual-tone Performance (IMD3) Gsps dBFS Each Tone) Fin1 MHz, Fin2 MHz: IMD3 dBFS
Screening
Temperature Range: Tamb 0°C; 90°C (Commercial Grade) Tamb 40°C; 110°C (Industrial Grade)
Applications
Direct Down Conversion Broadband Digital Receivers Test Instrumentation High Speed Data Acquisition High Energy Physics
5403B-BDC-02/06
Description
AT84AS003 combines 10-bit Gsps analog-to-digital converter with DMUX, designed accurate digitization broadband signals. features Effective Number Bits (ENOB) Spurious Free Dynamic Range (SFDR) Gsps over full first Nyquist zone. demultiplexed digital outputs LVDS logic compatible, allowing easy interfacing with standard FPGAs DSPs. AT84AS003 operates Gsps. AT84AS003 comes EBGA package. This package same boards, offering excellent reliability when submitted large thermal shocks.
Block Diagram
Figure 2-1.
Block Diagram
BIST ASYNRST PGEB DRRB
CLK/CLKN
Port AOR/AORN Port BOR/BORN Port COR/CORN Port DOR/DORN DR/DRN
LVDS Buffers
Logic Block
Quantizer
VINN
Demultiplexer
B/GB SLEEP STAGG DRTYPE
AT84AS003
5403B-BDC-02/06
AT84AS003
Functional Description
AT84AS003 10-bit Gsps combined with demultiplexer (DMUX) allowing lower output Data stream (10-bit data Range bit) selectable factor works fully differential mode from analog input digital outputs. should reverse terminated, close possible EBGA package input maximum). clock input on-chip differentially terminated. output clock output data LVDS logic compatible, should differentially terminated. AT84AS003 features asynchronous resets: -DRRB, which ensures that first digitized data corresponds first acquisition. ASYNCRST, which ensures that first digitized data will output port DMUX. gain tuned unity gain means analog control input. Sampling Delay Adjust function (SDA analog control input, activated SDAEN signal) used fine-tune aperture delay around center value. function interest interleaving multiple ADCs.The control B/GB provided select either Binary Gray data output format. tunable delay cell (controlled CLKDACTRL) integrated between DMUX clock path fine tune data clock alignment interface between DMUX. This delay tuned from around default center value, featuring typical delay tuning range. extra standalone delay cell also provided, (controlled DACTRL analog control input activated DAEN). tuning range typically pattern generator (PGEB) integrated part debug acquisition setup Similarly, Built-in Self Test (BIST) provided quick debug DMUX part. output demultiplexing ratio selected means digital control input. modes output clock (via DRTYPE) selected: mode: only output clock rising edge active, output clock rate same output data rate DR/2 mode: both output clock rising falling edges active, output clock rate half output data rate data outputs available output AT84AS003 different modes: Staggered: even bits come with half data period delay Simultaneous: even bits come same time power reduction mode (SLEEP control input) provided reduce DMUX power consumption. junction temperature monitoring made possible through DIODE input sensing voltage drop across diode implemented close chip point. AT84AS003 delivered Enhanced Ball Grid Array (EBGA), very suitable applications subjected large thermal variations (thanks which similar material TCE).
5403B-BDC-02/06
Table 3-1.
Name VCCA VCCD VPLUSD VMINUSD AGND DGND CLK, CLKN VIN, VINN DRRB ASYNCRST DR/DRN A0.A9 A0N.A9N AOR/DRAN, AORN/DRA B0.B9 B0N.B9N BOR/DRBN, BORN/DRB C0.C9 C0N.C9N COR/DRCN, CORN/DRC D0.D9 D0N.D9N DOR/DRDN, DORN/DRD CLKDACTRL DACTRL DAEN
Functions Description
Function Analog 3.3V power supply Digital power supply Analog power supply
VCCA VMINUSD VCCDVPLUSD 3.3V -2.2V 3.3V 2.5V [A0.A9] [A0N.A9N] AOR/DRAN, AORN/DRA [B0.B9] [B0N.B9N] BOR/DRBN, BORN/DRB [C0.C9] [C0N.C9N] COR/DRCN, CORN/DRC [D0.D9] [D0N.D9N] DOR/DRDN, DORN/DRD DAO, DAON DIODE
Output power supply Output 2.2V power supply Analog ground Digital ground Input clock signals Analog input data reset DMUX asynchronous reset Output clock signals Output data port Additional output port output clock staggered mode port Output data port
VIN, VINN CLK, CLKN DRRB ASYNCRST SDAEN B/GB
AT84AS003
DACTRL, CLKDACTRL DAI, DAIN SLEEP STAGG CLKTYPE DAEN BIST DRTYPE
AGND
DGND
Name DAI, DAIN DAO, DAON SDAEN
Function Input signals standalone delay cell Output signals standalone delay cell gain adjust enable sampling delay adjust pattern generator Binary gray output code selection Sleep mode selection signal Staggered mode selection Data outputs Input clock type selection signal connected VCCD left floating) Output clock type selection signal Built-in Self Test Diode junction temperature monitoring (ADC)
Additional output port output clock staggered mode port
Output data port Additional output port Output clock staggered mode Port Output data port SLEEP Additional output port output clock staggered mode port DMUX ratio selection signal Control signal clock delay cell Control signal standalone delay cell Enable signal standalone delay cell STAGG CLKTYPE DRTYPE BIST DIODE PGEB B/GB
AT84AS003
5403B-BDC-02/06
AT84AS003
Specifications
Absolute Maximum Ratings
Absolute Maximum Ratings
Symbol VCCA VCCD VPLUSD VMINUSD VPLUSD VMINUSD VINN VINN VCLK VCLKN VCLK VCLKN SDAEN, B/GB, PGEB, DECB DRRB CLKTYPE, DRTYPE, SLEEP, STAGG, BIST, DAEN ASYNCRST DAI, DAIN CLKDACTRL, DACTRL DIODE DIODE Value -0.3 VCCA VCCD VCCD VCCD VCCD Unit
Table 4-1.
Parameter
Analog positive supply voltage Digital positive supply voltage Analog negative supply voltage Digital positive supply voltage Digital negative supply voltage Maximum difference between VPLUSD VMINUSD Analog input voltages Maximum difference between VINN Clock input voltage Maximum difference between VCLK VCLKN Control input voltage Digital input voltage reset voltage DMUX function input voltage DMUX asynchronous reset DMUX input voltage DMUX control voltage Maximum input voltage DIODE Maximum input current DIODE Junction temperature Notes:
Absolute maximum ratings short term limiting values (referenced applied individually, while other parameters within specified operating conditions. Long exposure maximum ratings affect device reliability. integrated circuits have handled with appropriate care avoid damage ESD. Damage caused inappropriate handling storage could range from performance degradation complete failure.
5403B-BDC-02/06
Table 4-2.
Parameter
Recommended Condition
Symbol VCCA VCCD VMINUSD VINN Vinclk single-ended (VINN grounded through single-ended clock input differential clok (recommended) Comments Recommended Value ±125 Unit mVpp mVpp
Positive supply voltage Positive supply voltage Negative supply voltage Positive negative supply voltage Differential analog input voltage Differential clock input level
Clock input power level (ground common mode)
PCLK PCLKN
control input voltage functions reset DMUX standalone delay cell inputs
SDAEN, B/GB, PGEB, DECB DRRB DAI, DAIN SLEEP, STAGG, ASYNCRST, BIST, DAEN, DRTYPE, CLKDACTRL, DACTRL Tstg Commercial grade industrial grade
3.3V 3.3V
DMUX control inputs
3.3V
Operating temperature range Storage temperature Maximum junction temperature
90°C 20°C 110°C
AT84AS003
5403B-BDC-02/06
AT84AS003
Electrical Operating Characteristics
VCCA VCCD 3.3V, VMINUSD 2.2V VINN VINN dBFS single-ended driven with VINN connected ground PCLK (differential driven)
Table 4-3.
Parameter Resolution
Electrical Characteristics Ambient Temperature Temperature Max)
Test Level Symbol Unit
Power Requirements Positive supply Voltages Positive Supply Current analog digital digital outputs -analog VCCA 3.3V -digital VCCD 3.3V (1:2 DMUX) -digital VCCD 3.3V (1:4 DMUX) -output VPLUSD 2.5V VCCA VCCD VPLUSD IVCCA IVCCD IVCCD IVPLUSD IVEE VMINUSD IVMINUSD 5.25 3.15 3.15 3.45 3.45 4.75
Negative supply voltage Negative supply current Negative supply voltage Negative supply current Power Dissipation (1:2 DMUX) Analog Inputs Full-scale input voltage range Differential mode common mode voltage Full-scale input voltage range Single-ended input option common mode voltage Analog input power level single-ended) Analog input capacitance (die) Input leakage current single-ended Input resistance differential
VINN
VIN, VINN
5403B-BDC-02/06
Table 4-3.
Parameter Clock Inputs
Electrical Characteristics Ambient Temperature Temperature Max) (Continued)
Test Level Symbol Unit
Logic common mode compatibility clock inputs Clock input common voltage range (VCLK VCLKN) common mode) Clock input power level (low-phase noise sinewave input) single-ended differential Clock input swing (single ended with CLKN GND) Clock input swing (differential voltage) each clock input Clock input capacitance (die) Clock input resistance Single-ended Differential ended Digital Data Outputs Logic compatibility LVDS transmission lines, differential termination) Logic Logic high Differential output Common mode Control Function Inputs DRRB ASYNCRST Logic Logic high DRTYPE, SLEEP, STAGG, BIST, DAEN Logic Logic high SDAEN, PGEB, B/GB logic logic high DAI, DAIN differential input common mode
Differential LVDS coupling)
PCLK
VCLK VCLK, VCLKN RCLK RCLK
VODIFF VOCM
1.25 1.125
1.075 1.425 1.25
1.25 1.375
VIDIFF VICM
1.25
Infinite
AT84AS003
5403B-BDC-02/06
AT84AS003
Table 4-3.
Parameter CLKDACTRL, DACTRL accuracy DNLrms Differential non-linearity Integral non-linearity Integral non-linearity Gain central value Gain error drift Input offset voltage Note:
Electrical Characteristics Ambient Temperature Temperature Max) (Continued)
Test Level Symbol VCCD VCCD Unit
DNLrms DNL+
0.95
1.05
ppm/°C
proper operation BIST mode, VCCD 3.3V. Histogram testing Gsps DNLrms component quantization noise. Histogram testing Msps MHz. This range gain thanks gain adjust function.
5403B-BDC-02/06
Table 4-4.
Parameter
Electrical Characteristics Ambient Temperature Temperature Max)
Test Level Symbol Unit
Analog Inputs Full power input bandwidth Small signal input bandwidth (10% full-scale) Gain flatness Input voltage standing wave ration
FPBW SSBW VSWR
1.1: 1.2:
Performance: Nominal Condition Ambient Temperature dBFS single-ended input mode (unless otherwise specified); clock duty cycle; differential clock (CLK, CLKN); binary output data format. Effective Number Bits Gsps Gsps Signal Noise Ratio Gsps Gsps ENOB
Total Harmonic Distortion Gsps Gsps |THD|
Spurious Free Dynamic Range Gsps Gsps |SFDR|
Two-tone Third Order Inter-modulation Distortion Gsps each tone)
Fin1 MHz; Fin2
Note: "Definition Terms" page
|IMD3|
dBFS
From GHz. Specified from input signal. Input VSWR measured soldered device. assumes external controlled impedance line, driving source impedance (S11 dB).
AT84AS003
5403B-BDC-02/06
AT84AS003
Table 4-5.
Parameter Transient Performance error rate setting time (VIN-VINN mVpp) Overvoltage recovery time step response rise/fall time -90%) Overshoot Ringback Switching Performance Characteristics Maximum clock frequency Minimum clock frequency
Transient Switching Performances
Test Level Symbol Unit
10-11
Error/ sample
Jitter
0.22 0.22
Gsps Msps
Maximum clock pulse width (high) Minimum clock pulse width (low) Aperture delay
Aperture uncertainty DRRB pulse width ASYNCRST pulse width Output Data Data Output Delay Data output delay Skew Data pipeline delay Synchronized ratio Synchronized ratio Staggered ratio Staggered ratio Data output rise/fall time (20% -80%) Output Clock Output clock delay Output clock rise/fall time (20% -80%) Output data output clock propagation delay
Tskew
4.5/5.5 4.5/5.5/6.5/7.5
Clock cycles
TR/TF
TR/TF TD2-TD1 TOD-TDR
5403B-BDC-02/06
Table 4-5.
Parameter
Transient Switching Performances (Continued)
Test Level Symbol Unit
Standalone Delay Cell (DACTRL) Tunable Delay cell (CLKDACTRL)(4) Input frequency Input duty cycle Propagation delay with CLKDACTRL DACTRL VCCD/3 Propagation delay with CLKDACTRL DACTRL VCCD/3 Note: DCYCSDA TSDAMIN TSDAMAX 1.70 2.00 2.50 2.30 2.90 FMSDA
Output error amplitude LSB. Gsps 110°C. "Definition Terms" page propagation times defined package input/outputs. They given reference only. "Definition Terms" page delay cell used both standalone delay cell input clock path (DR) characteristic that linear with junction temperature. largest tuning range obtained near ambient temperature.
Explanation Test Levels
Level Note:
Comments 100% production tested 25°C (for Temperature range 100% production tested 25°C, sample tested specified temperatures (for temperature ranges). Sample tested only specified temperatures Parameter guaranteed design characterization testing (thermal steady-state conditions specified temperature). Parameter typical value only guaranteed design only Unless otherwise specified. Only minimum maximum values guaranteed (typical values issued from characterization results).
AT84AS003
5403B-BDC-02/06
AT84AS003
Digital Coding
Differential Analog Input
Voltage Level
Digital Output Binary (B/GB floating) MSB.LSB out-of-range Gray (B/GB )MSB.LSB out-of-range 1000000000 1000000000 1000000001 1010000000 1110000000 1100000000 0100000000 0110000000 0010000000 0000000001 0000000000 0000000000
250.25 250.25 249.75 125.25 124.75 0.25 -0.25 124.75 124.25 249.75 250.25 250.25
>Top full scale full scale full scale full scale LSB3/4 full scale scale scale full scale full scale Bottom full scale Bottom full scale Bottom full scale
1111111111 1111111111 1111111110 1100000000 1011111111 1000000000 0100000000 0011111111 0000000001 0000000000 0000000000
5403B-BDC-02/06
Characterization Results
Nominal Conditions
Unless otherwise specified: VCCA 3.3V, VCCD 3.3V, -5V, VPLUSD 2.5V, VMINUSD 2.2V 80°C clock duty cycle, binary output data format dBFS analog input
Full Power Input Bandwidth
Analog input level dBFS Gain flatness from Full Power Input Bandwidth
-0,5 -1,0 -1,5 -2,0 dBFS -2,5 -3,0 -3,5 -4,0 -4,5 -5,0 -5,5 -6,0 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 3100 3300 -0.5 Gain Flatness Bandwidth
(MHz)
VSWR Versus Input Frequency
Figure 5-1. VSWR Curve Analog Input (VIN) Clock (CLK)
2,60 2,40 2,20 2,00
VSWR
1,80 1,60 1,40 1,20 1,00 1000 1500 2000 2500 3000 3500 Frequency (MHz)
AT84AS003
5403B-BDC-02/06
AT84AS003
Step Response
measured sqrt (TrPulseGenerator TrPulseGenerator (estimated) Actual TrADC 83.5 Figure 5-2. Step Response Rise Time Gsps, MHz)
1200 1100 1000 -100 -200 Time (ps)
100%
1000 1100 1200 1300 1400 1500
Dynamic Performance Versus Sampling Frequency
Dynamic Parameters Versus Sampling Frequency Nyquist Conditions (Fin Fs/2)
1000 1100 1200 1300 1400 1500
Figure 5-3.
SFDR (dBc Dependent independent 1000 1100 SFDR without first Harmo
ENOB (Bit
(Msps)
1200 1300 (Msps
1400
1500
(dB)
1000
1100 1200 1300 1400 1500
1000
1100
1200
1300
1400
1500
(Msps)
(Msps)
5403B-BDC-02/06
Dynamic Performance Versus Input Frequency
Dynamic Parameters Versus Input Frequency Gsps
SFDR (dBFS) ENOB (Bit) (MHz) (dBFS) (MHz) (MHz) (MHz)
Figure 5-4.
Signal Spectrum
Figure 5-5. Gsps, dBFS Analog Input, kpoint
Fundamental (Fin MHz) SFDR (H7) -100 -120 -140
AT84AS003
5403B-BDC-02/06
AT84AS003
Dynamic Performance Sensitivity Versus Temperature Power Supply
Dynamic Parameters Versus Junction Temperature Gsps, MHz, dBFS Analog Input
(dB) (dB) (°C) (°C) (°C) SFDR (dBc) ENOB (Bit) (°C)
Figure 5-6.
Figure 5-7.
Dynamic Parameters Min., Typ. Max. Power Supplies, Gsps, MHz, dBFS Analog Input
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
ENOB (Bit)
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
SFDR (dBc)
(dB)
(dB)
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
Note:
Minimum power supplies: 3.45,V 4.75V Typical power supplies: 3.3V, Maximum power supplies: 3.15V, 5.25V
5403B-BDC-02/06
Dual Tone Performance
Figure 5-8. Dual Tone Signal Spectrum Gsps, Fin1 MHz, Fin2 dBFS)
IMD3 2Fin1 Fin2 2Fin2 Fin1 Fin1 dBFS Fin2 dBFS
dBFS
-100 -120 -140 -160
5.10
Performance
Figure 5-9. Digitizing Broadband Pattern Gsps, Notch Centered Around MHz, dBFS Loading Factor
40.41
dBFS
-100
-120 F(MHz)
AT84AS003
5403B-BDC-02/06
Figure 6-1.
5403B-BDC-02/06
PGEB B/GB DIODE VMINUSD VMINUSD SLEEP STAGG AORN AGND AGND VMINUSD VMINUSD ASYNCRST DRAN AGND VPLUSD AGND VPLUSD VCCD VPLUSD VCCD VCCD VPLUSD VPLUSD VPLUSD VPLUSD VPLUSD VCCD DGND VPLUSD VPLUSD DGND VPLUSD AGND VPLUSD AGND VPLUSD VCCD VPLUSD VCCD VCCD VPLUSD VPLUSD VPLUSD VPLUSD VCCD VCCD VCCD DGND DGND AGND AGND VPLUSD VCCD VCCD VMINUSD VPLUSD AGND AGND VPLUSD VMINUSD DGND DGND VCCD VCCD DGND DGND BORN VPLUSD VPLUSD DRBN
VCCA
VCCA
VCCA
Description
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
AGND
AGND
VCCA
AGND
AGND
AGND
AGND
AGND
CLKN
AGND
AGND
EBGA Pinout Table (View from Bottom Package)
AGND
VCCD
VCCD
DRTYPE
VCCA
VCCA
VPLUSD
VPLUSD
VCCA
DGND
DGND
AGND
VPLUSD
VPLUSD
DRRB
SDAEN
AGND
DGND
DGND
AGND AGND
AGND
AGND
AGND
AGND VCCA VPLUSD
DGND VCCD
VPLUSD
VPLUSD
AGND AGND
AGND
AGND
AGND
AGND VCCA VPLUSD VPLUSD
DGND VCCD VCCD
VPLUSD
VPLUSD
VCCD
VPLUSD
VCCD
VPLUSD
VCCD
VPLUSD
VPLUSD
VCCD
VCCD
VCCD
AGND AGND AGND VCCA VMINUSD VMINUSDCLKDACTRL DGND DGND
AGND
AGND
AGND
VPLUSD
VPLUSD
VPLUSD
VCCD
VPLUSD
VCCD
VPLUSD
VCCD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VCCD
AGND AGND VINN DA1N CLKTYPE AGND DAON BIST
AGND
AGND
DRDN
DRCN
AGND VINN AGND DACTRL
AGND
AGND
DAEN
DORN
CORN
AT84AS003
Table 6-1.
Symbol
Description
Number Function
Power Supplies DGND C17, C18, D17, D18, R18, T18, U16, B21, B23, C21, C23, D21, D23, E21, E23, F21, F23, F26, F27, G25, G26, G27, H25, H26, J25, J26, K27, N25, P25, R22, R23, R24, R25, R26, R27, T22, t23, T24, T25, T26, T27, U22, U23, U24, U25, U26, U27, V21, V23, V24, V26, V27, W22, W25, W26, A24, A26, A27, B24, B26, B27, C24, C26, C27, D24, D26, D27, E24, E26, F25, L25, L26, M27, R21, T21, U21, A25, B22, B25, C20, C22, C25, D20, D22, D25, E20; E22, E25, F20, F22, F24, K25, K26, L27, M25, M26, N26, N27, R20, D14, D15, C11, C13, C14, C15, C16, C19, D11, D13, D19, E19, F19, R19, T11, T13, T14, T15, T19, U11, U13, U14, C10, C12, D10, D12, D16, E17, R16, T10, T12, T16, T17, U10, A19, A20, B19, B20, E18, F18, U19, Digital ground
AGND
Analog ground
VCCA
analog positive power supply
analog negative power supply Connect
VPLUSD
DMUX output power supply
VCCD
DMUX digital power supply
VMINUSD Inputs CLK, CLKN
digital negative power supply 2.2V)
H27,
clock differential Inputs ECL/PECL/LVDS compatible in-phase analog input (double pin: terminated ground) inverted-phase analog input (double pin: terminated ground)
V25,
VINN Outputs A0.A9 A0N.A9N AOR/DRAN, AORN/DRA
V22,
B16, B15, B14, B13, B12, B11, B10, A16, A15, A14, A13, A12, A11, A10,
In-phase digital outputs port LVDS compatible Inverted-phase digital outputs port LVDS compatible Port additional port output clock staggered mode
AT84AS003
5403B-BDC-02/06
AT84AS003
Table 6-1.
Symbol B0.B9 B0N.B9N BOR/DRBN, BORN/DRB C0.C9 C0N.C9N COR/DRCN, CORN/DRC D0.D9 D0N.D9N DOR/DRDN, DORN/DRD Control Functions Inputs DRRB data ready reset LVCMOS (3.3V) compatible DMUX asynchronous reset -leave floating connect VCCD normal mode -connect ground reset mode sampling delay adjust enable -SDA disabled when left floating connected ground -SDA enabled when connected sampling delay adjust 0.5V range) Pattern generator enable -leave floating connect ground normal mode -connect test mode Binary gray output coding selection -leave floating connect ground binary coding -connect gray coding gain adjust control 0.5V range) Connect VCCD
Description (Continued)
Number V10, V11, V12, V13, V14, W10, W11, W12, W13, W14, V16, Function In-phase digital outputs port LVDS compatible Inverted-phase digital outputs port LVDS compatible Port additional port output clock staggered mode In-phase digital outputs port LVDS compatible Inverted-phase digital outputs port LVDS compatible Port additional port output clock staggered mode In-phase digital outputs port LVDS compatible Inverted-phase digital outputs port LVDS compatible Port additional port output clock staggered mode Differential output clock LVDS compatible
ASYNCRST
SDAEN
PGEB
B/GB
CLKTYPE
5403B-BDC-02/06
Table 6-1.
Symbol
Description (Continued)
Number Function DMUX SLEEP mode enable -leave floating connect VCCD normal mode -connect ground SLEEP mode DMUX staggered mode enable -leave floating connect VCCD normal mode -connect ground STAGG mode DMUX output clock mode selection -connect ground DR/2 type -leave floating connect VCCD type DMUX ratio mode selection -connect ground ratio -leave floating connect VCCD ratio DMUX BIST mode -leave floating connect VCCD normal mode -connect ground BIST mode DMUX clock delay control (from VCCD VCCD) Standalone delay cell control (from VCCD VCCD) Standalone delay cell enable -delay cell disabled when left floating connected VCCD -delay cell enabled when connected ground Standalone delay cell differential inputs LVDS compatible
SLEEP
STAGG
DRTYPE
BIST
CLKDACTRL DACTRL
DAEN
DAI, DAIN Control Functions Inputs DAO, DAON DIODE
W19,
W20, B18,
Standalone delay cell differential outputs LVDS compatible junction temperature monitoring connect (leave this floating)
AT84AS003
5403B-BDC-02/06
AT84AS003
Main Reset
There reset signals available: DRRB ASYNCRST. DRRB active while ASYNCRST active high. These reset signals required start device properly. recommended apply both reset signals simultaneously. Please refer Application Section more information implement reset functions. case multiple channels, recommended hold input clock signal during reset described Figure 7-1) ensure synchronization channels. DRRB/ASYNCRST signal frequency should maximum. reset pulse should minimum. Figure 7-1. Asynchronous Reset Timing Diagram, Mode, Simultaneous Mode (Principle Operation)
Tamb
cycles cycle
Tskew
Tskew
5403B-BDC-02/06
Figure 7-2.
Asynchronous Reset Timing Diagram, Mode, Simultaneous Mode (Principle Operation)
Tamb
DRRB cycles ASYNCRST
Tskew
cycles
A0.A9 B0.B9 C0.C9 D0.D9
Tskew
Tskew
Tskew
mode)
(DR/2 mode)
Note:
time delay between first raising edge after reset signal before delay. This time number clock cycle. Definition TOD: time between falling edge next point change data Definition TDR: time between falling edge next point change data ready. always lower over temperature power supply clock cycles TDR. clock cycles With This delay long several delay lines DMUX.
Control Signal Settings
SLEEP, DAEN, STAGG, BIST DRTYPE control signals same static buffer. ASYNCRST activated logic high (tied/switched VCCD 3.3V, ground, left floating) deactivated logic (grounded). SLEEP, DAEN, STAGG, BIST activated logic grounded), deactivated logic high ground, tied VCCD 3.3V, left floating). This illustrated Figure 7-3.
AT84AS003
5403B-BDC-02/06
AT84AS003
Figure 7-3. Control Signal Setting
Control signal Control signal High level (`1') (`0') connected Control signal
level
Table 7-1.
Function
DMUX Mode Settings Summary
Logic Level Electrical Level ground ground Normal conversion ground ground ground ground Simultaneous mode ground ground Standalone delay adjust disabled ground ground ratio ground ground Reset ground ground mode DR/2 mode Normal conversion ratio Standalone delay adjust activated Staggered mode Normal conversion Power reduction mode (the outputs fixed arbitrary LVDS level) Description BIST
BIST
SLEEP
STAGG
DAEN
ASYNCRST
DRTYPE
5403B-BDC-02/06
Programmable DMUX Ratio
demultiplexer ratio programmable thanks ratio selection signal:
DMUX Ratio
Figure 7-4.
DMUX Ratio
Input Words: Output Words: Port Port Port Port Used Used
Figure 7-5.
DMUX Ratio
Input Words: Output Words: Port Port Port Port
Output Mode (STAGG)
output modes provided: Staggered: output data come DMUX after other Simultaneous: output data come DMUX same time staggered mode, output clock each port provided DRA, DRAN, DRB, DRBN, DRC, DRCN DRD, DRDN signals which corresponds respectively AORN, AOR, BRON, BOR, CORN, COR, DORN DOR. simultaneous mode default mode (STAGG left floating logic staggered mode activated means STAGG input (active low).
AT84AS003
5403B-BDC-02/06
AT84AS003
Figure 7-6. Simultaneous Mode Ratio (STAGG
mode) DR/2 mode) Data Port Data Port Data Port Data Port
Figure 7-7.
Staggered Mode Ratio (STAGG
Data Port Data Port
(AORN) mode (AORN) DR/2 mode mode (BORN) DR/2 mode mode) DR/2 mode)
5403B-BDC-02/06
Figure 7-8.
Staggered Mode Ratio (STAGG
Data Port (AORN) mode (AORN) DR/2 mode Data Port (BORN) mode (BORN) DR/2 mode Data Port (CORN mode) (CORN DR/2 mode)
Data Port (DORN) mode (DORN) DR/2 mode
mode DR/2 mode
Additional
simultaneous output mode: (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) (DOR/DRDN, DORN/DRD) signals used process Range from output data. ratio, (AOR, AORN) (BOR, BORN) will output this signal half initial speed. ratio, (AOR, AORN), (BOR, BORN), (COR, CORN) (DOR, DORN) will output this signal initial speed. Staggered output mode: (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) (DOR/DRDN, DORN/DRD) will output Data Ready signal each ports, centered corresponding data.
AT84AS003
5403B-BDC-02/06
AT84AS003
frequency (DRA, DRAN), (DRB, DRBN), (DRC, DRCN) (DRD, DRDN) depends DRTYPE mode (same data mode, half DR/2 mode). ratio, DR/DRN DRB/DRBN same. ratio, DR/DRN DRD/DRDN same.
Output Clock Type Selection
modes output clock type chosen: mode: only output clock rising edge active, output clock rate same output data rate DR/2 mode: both output clock rising falling edges active, output clock rate half output data rate This illustrated Figure Figure 7-10. Figure 7-9.
Data
Mode
Figure 7-10. DR/2 Mode
Data
Table 7-2.
DRTYPE
Table DMUX Output Clock Type Selection Settings
DMUX Output Clock Type DR/2
When DRTYPE left floating, default mode
Power Reduction Mode (SLEEP)
power reduction (SLEEP) mode allows user reduce power consumption device (demultiplexing part Sleep mode). this mode, device's consumption reduced Power reduction mode active when SLEEP low. device normal mode when SLEEP high.
Standalone Delay Cell
standalone delay cell provided allow user delay DAI/DAIN differential input signal. delay controlled DACTRL. tuning range about DACTRL varying from VCCD VCCD) This function results delayed output signal: DAO/DAON. DAI/DAIN DAO/DAON LVDS signals.
5403B-BDC-02/06
Figure 7-11. Standalone Delay Cell Block Diagram
DAI/DAIN DACTRL
Delay (550
DAO/DAO
Clock input Delay Cell
delay cell provided allow user tune delay between Clock Data DEMUX input. delay controlled CLKDACTRL. ranges from -275 CLKDACTRL varying from VCCD VCCD) This function results delayed internal clock signal. Figure 7-12. Standalone Delay Cell Block Diagram
CLK/CLK CLKDACTRL
Delay
Internal clock signal
7.10
Built-In Self Test
Built-in Self Test allows test rapidly DMUX block device. activated BIST (active low). When this signal left floating, BIST inactive. When BIST mode, clock must applied device, which mode. output clock mode DRTYPE either DR/2. BIST mode, bits either high level (even bits phase opposition) transition every cycle. proper operation Built-in-Self Test, VCCD should 3.3V minimum.
7.11
Junction Temperature Monitoring
junction temperature measurement setting available, maximum junction temperature monitoring (hot point measurement). measurement method consists forcing current into diode mounted transistor sensing voltage across DIODE closest available ground pin. measurement setup described Figure 7-13 page
AT84AS003
5403B-BDC-02/06
AT84AS003
Figure 7-13. Diode Junction Temperature Monitoring Setup parallel
DIODE
AGND
Protection Diodes
Caution: Respect current source polarity. cases, make sure that maximum voltage compliance current source limited maximum resistor mounted series with current source avoid damages, which occur transistor device (this occur instance current source connected reverse). diode forward voltage versus junction temperature steady state conditions) characteristic given Figure 7-14. forward voltage drop, (VDIODE) across diode component, versus junction temperature (including chip parasitic resistance) given below (IDIODE mA).
5403B-BDC-02/06
Figure 7-14. DIODE Characteristic
Junction temperature Versus Diode Voltage
Diode voltage (mV)
Jonction temperature (°C)
Note:
operating junction temperature must kept below 125°C, ensure long term device reliability.
7.12
Pattern Generator Function
Pattern Generator function (enabled connecting PGEB -5V) allows check rapidly operation thanks checker board pattern delivered internally ADC. Each output should toggle from successively. AT84AS004 output, bits each port transition every cycle.
7.13
Gain Control
gain adjustable means EBGA package. gain adjust transfer function given below:
1.30 1.20 1.10 1.00 Gain 0.90 0.80 0.70 0.60 0.50 -0.5 -0.4 -0.3 -0.2 -0.1 Typical
Gain Adjust Voltage
AT84AS003
5403B-BDC-02/06
AT84AS003
7.14 Sampling Delay Adjust
Sampling delay adjust (SDA pin) allows fine tune sampling aperture delay around nominal value (160ps). This functionality enabled thanks SDAEN signal, which active when tied inactive when tied GND. This feature particularly interesting interleaving ADCs increase sampling rate.The variation delay around nominal value function voltage shown following graph (simulation result): Figure 7-15. Typical Tuning Range Applied Control Voltage Varying Between pin.
Delay Variable Delay Cell
Delay(s)
-500 -400 -300 -200 -100 0.00
Voltage
Note:
variation delay function temperature negligible.Block Diagram
5403B-BDC-02/06
Equivalent Input/Output Schematics
Equivalent Analog Input Circuit Protection
Figure 8-1. AT8AS003 Analog Input Buffer Schematic (VIN/VINN)
Controlled Transmission Line Double (Bonding Package Ball) 260fF
120fF
Double Pads
1.5V
Package Pins
VINN
Controlled Transmission Line (Bonding Package Ball)
Double 260fF
120fF
Note:
External reverse termination required.
Equivalent Clock Input Circuit Protection
Figure 8-2.
Double 260fF Double 260fF CLKB Double 260fP 120fF 215fF 120fF 40pF
AT84AS003 Clock Input buffer schematic (CLK/CLKN)
5403B-BDC-02/06
Note:
termination point chip coupled ground through capacitor.
AT84AS003
AT84AS003
Equivalent Data/Clock Output Buffer Circuit Protection
Figure 8-3. AT84AS003 Data (Ai/AiN.Di/DiN), Clock (DR/DRN) DAO/DAON Output Buffer Schematic
VPLUSD (2.5V vccdiode ESD: vccdiode vccdiode ESD: vccdiode
outn
ESD: gnddiode gnddiode 50.0 1.1K 1.4K 1.4K
ESD: gnddiode gnddiode
DGND (0V)
SUBST (-5V)
Standalone Delay Cell Data Input (DAI/DAIN) Buffer Circuit Protection
Figure 8-4. AT84AS003 Standalone Delay Cell Input DAI/DAIN Buffer Schematic
VCCD (3.3V
2.00K
ESD: vccdiode ESD: vccdiode
2.00K
49.9 49.9
1.25V 0.175V
ESD: ESD: gnddiode gnddiode 272fF 272fF
1.25V 0.175V
5.00p
4.00k
DGND (0V)
SUBST (-5V)
5403B-BDC-02/06
Delay Cell (DACTRL/DACTRLN CLKCTRL/CLKCTRLN) Control Input Schematic Protection
Figure 8-5. AT84AS003 Delay Cell Control Input DACTRL/DACTRLN CLKCTRL/CLKCTRLN Buffer Schematic
VCCD (3.3V
2.00K ESD: vccdiode
2.00K
10.0K
2.00K
2.00K
ESD: gnddiode 10.0K 2.00K 2.00K
DGND (0V)
SUBST
DRRB Equivalent Input Schematic Protection
AT84AS003 DRRB Reset Input Buffer Schematic
3.3V
Figure 8-6.
1.4V 3.3V 3.3V
DRRB -2.6V
AT84AS003
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AT84AS003
ASYNCRST Equivalent Input Schematic Protection
Figure 8-7. AT84AS003 Asynchronous Reset ASYNCRST Buffer Schematic
VCCD (3.3V
4.00K ESD: vccdiode 12.7K
4.00K
25.0K
ESD: gnddiode 9.32K 4.00K 4.00K
DGND (0V)
SUBST (-5V)
Gain Adjust Equivalent Input Circuits Protection
Figure 8-8. AT84AS003 Gain Adjust Control Input Buffer Schematic (GA)
65fF 130fF 75fF
0.9V
5403B-BDC-02/06
B/GB PGEB Equivalent Input Schematics Protection
Figure 8-9. AT84AS003 B/GB PGEB Control Buffer Schematic
65fF B/GB 130fF 75fF -1.3V
8.10
Control Signals Input Buffers Protection
Figure 8-10. AT84AS003 Control Signals Buffer Schematic (RS, DRTYPE, BIST, SLEEP, STAGG, DAEN)
VCCD (3.3V
4.00K ESD: vccdiode
1.2K
1.2K
10.0K
16.00K ESD: gnddiode 10.0K
DGND (0V)
SUBST (-5V)
AT84AS003
5403B-BDC-02/06
AT84AS003
Definition Terms
Definition Terms
max) Maximum Sampling Frequency Minimum Sampling Frequency Sampling frequency which ENOB 6bits Sampling frequency which Gain fallen with respect gain reference value. Performances guaranteed below this frequency. Probability exceed specified error threshold sample maximum specified sampling rate. error code code that differs more than from correct code. Analog input frequency which fundamental component digitally reconstructed output waveform fallen with respect frequency value (determined analysis) input fullscale dBFS). Analog input frequency which fundamental component digitally reconstructed output waveform fallen with respect frequency value (determined analysis) input fullscale dBFS). Ratio expressed signal amplitude, below full-scale dBFS), other spectral components, including harmonics except Ratio expressed signal amplitude, below full-scale, other spectral components excluding twenty five first harmonics. Ratio expressed first twenty five harmonic components, input signal amplitude, below fullscale. reported (i.e., related converter fullscale), (i.e., related input signal level Ratio expressed signal amplitude, below full-scale, value highest spectral component (peak spurious spectral component). peak spurious component harmonic. reported (i.e., related converter full-scale), (i.e., related input signal level Where actual input SINAD -Fs/2 amplitude fullENOB -scale range under test. differential non-linearity output code difference between measured step size code ideal step size. expressed LSBs. maximum value (i). error specification less than guarantees that there missing output codes that transfer function monotonic. Integral non- linearity output code difference between measured input voltage which transition occurs ideal value this transition. expressed LSBs, maximum value (i). Delay between rising edge differential clock inputs (CLK,CLKB) (zero crossing point), time which (VIN,VINB) sampled.
min)
(BER)
Error Rate
(FPBW)
Full Power Input Bandwidth
(SSBW)
Small Signal Input Bandwidth
(SINAD)
Signal Noise Distortion Ratio
(SNR)
Signal Noise Ratio
(THD)
Total Harmonic Distortion
(SFDR)
Spurious Free Dynamic Range
(ENOB)
Effective Number Bits
(DNL)
Differential Non-Linearity
(INL)
Integral Non-Linearity
(TA)
Aperture Delay
5403B-BDC-02/06
Definition Terms (Continued)
(JITTER) (TS) (ORT) Aperture Uncertainty Settling Time Over Voltage Recovery Time Digital Data Output Delay Sample sample variation aperture delay. voltage error jitter depends slew rate signal sampling point. Time delay achieve accuracy converter output when full-scale step function applied differential analog input. Time recover accuracy output, after full-scale step applied input reduced midscale. Delay from rising edge differential clock inputs (CLK,CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load. Delay from falling edge differential clock inputs (CLK,CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load. General expression with encoding clock period. General expression with encoding clock period. minimum clock pulse width (high) minimum clock pulse width (low) Number clock cycles between sampling edge input data associated output data being made available, (not taking account TOD). Time delay output DATA signals rise from delta between level high level. Time delay output DATA signals fall from delta between level high level. Ratio input offset variation change power supply voltage. When input signal larger than upper bound input range, output code identical maximum code Range logic one. When input signal smaller than lower bound input range, output code identical minimum code, out-of-range logic one. assumed that input signal amplitude remains within absolute maximum ratings). tones inter-modulation distortion (IMD) rejection ratio either input tone worst third order intermediation products. measured characterize performance response broad bandwidth signals. When applying notch-filtered broadband white-noise signal input under test, noise power ratio defined ratio average out-of-notch average in-notch power spectral density magnitudes spectrum output sample test. VSWR corresponds input insertion loss input power reflection. example VSWR corresponds return loss (i.e. power transmitted reflected).
(TOD)
(TDR)
Data Ready Output Delay Time Delay from Data Transition Data Ready Time Delay from Data Ready Data Encoding Clock period
(TD1) (TD2) (TC)
(TPD)
Pipeline Delay
(TR) (TF) (PSRR)
Rise Time Fall Time Power Supply Rejection Ratio
(NRZ)
Return Zero
(IMD)
Inter-Modulation Distortion
(NPR)
Noise Power Ratio
(VSWR)
Voltage Standing Wave Ratio
AT84AS003
5403B-BDC-02/06
AT84AS003
Thermal Moisture Characteristics
there JEDEC standard definition thermal resistance applied multi-die device, only thermal resistance each (ADC block powered only DMUX block powered only) provided. easy understanding thermal behavior device, thermal data with both devices powered however provided. results were computed with ANSYS thermal simulation tool with following assumptions: Half geometry simulation heating zone heating air, pure conduction, radiation
10.1
Thermal Resistance from Junction Bottom Balls
When both blocks powered thermal simulation results Temperature center block 32.9°C Temperature center DMUX block 13.6°C When each block powered time, resulting thermal resistance from junction bottom balls junction-bottom balls (ADC block only) 7°C/W junction-bottom balls (DMUX block only) 3.9°C/W
10.2
Thermal Resistance from Junction Case
When both blocks powered resulting thermal resistance from junction case Temperature center block 18.5°C Temperature center DMUX block 4.1°C When each block powered time, resulting thermal resistance from junction case junction- case (ADC block only) 4.1°C/W junction- case (DMUX block only) 1.5°C/W
10.3
Thermal Resistance from Junction Board
When both blocks powered resulting thermal resistance from junction board Temperature center block 57.6°C Temperature center DMUX block 37.3°C When each block powered time, resulting thermal resistance from junction board junction- board (ADC block only) 8°C/W junction- board (DMUX block only) 4.9°C/W
Note: Assumed board size
5403B-BDC-02/06
10.4
Thermal Resistance from Junction Ambient
When both blocks powered resulting thermal resistance from junction ambient Temperature center block 106°C Temperature center DMUX block 85.3°C When each block powered time, resulting thermal resistance from junction ambient Junction- ambient (ADC block only) 17.1°C/W Junction- ambient (DMUX block only) 13.9°C/W
10.5
Thermal Management Recommendations
still 25°C ambient temperature conditions, maximum temperature 106°C 25°C 131°C reached block. consequently necessary manage heat from AT84AS003 very carefully avoid permanent damages device over temperature operation. cooling conditions, external heatsink must placed package. electrical isolation necessary package potential. advised external heatsink with intrinsic thermal resistance better than 4°C/Watt when using room temperature 20~25°C.At 60°C, external heatsink should have intrinsic thermal resistance better than 3°C/Watt. Figure 8-10 page provides outlines heat sink used AT84AS003-EB evaluation board. Figure 10-1. AT84AS003-EB Evaluation Board Heat Sink Outlines
50.4 50.7 16.5 heat sink
Note: units
AT84AS003
5403B-BDC-02/06
AT84AS003
10.6 Moisture Characteristics
This device sensitive moisture (MSL3 according JEDEC standard). Shelf life sealed bag: months 40°C relative humidity (RH). After this opened, devices that will subjected infrared reflow, vapor-phase reflow, equivalent processing (peak package body temp. 220°C) must mounted within hours factory conditions 30°C/60% stored Devices require baking, before mounting, Humidity Indicator when read 23°C 5°C. baking required, devices baked for: hours 40°C 5°C/-0°C temperature device containers, hours 125°C high-temperature device containers.
Applying AT84AS003
11.1 Bypassing, Decoupling Grounding
power supplies have decoupled ground close possible signal accesses board parallel
Figure 11-1. AT84AS003 Power supplies Decoupling grounding Scheme
External Power Supply Access VPLUSD MINUSD
Power Supply Plane
(VCCD
Ground
Note:
VCCD VCCA planes should separated power supplies reunited strap board.
Each group neighboring power supply pins attributed same value should bypassed with least pair parallel capacitors. These capacitors should placed close possible power supply package pins. minimum required pairs capacitors power supply type VCCA VCCD VPLUSD VMINUSD
5403B-BDC-02/06
Figure 11-2. AT84AS003 Power Supplies Bypassing Scheme
AT84AS003 (min) AGND
PLUS
(min)
DGND VMINUSD
(min)
(min)
AGND
(min)
11.2
Analog Input Implementation
pins available each positive (VIN) negative (VINN) inputs. necessary terminated each input pair ground close possible EBGA package pins.
Figure 11-3. AT84AS003 Analog Input Reverse Termination Scheme
AT84AS003 (V25) (W24) Differential single- ended signal VINN (V22) Lines VINN (W23)
analog input AT84AS003 device indifferently entered single-ended differential mode.
AT84AS003
5403B-BDC-02/06
AT84AS003
Figure 11-4. AT84AS003 Analog Input Termination Scheme (Single-ended)
Single ended signal Full-scale amplitude mVp-p Centered common mode
Line
AT84AS003 (V25)
(W24)
VINN
VINN (W23) VINN (V22)
Note:
terminations connected negative inputs (VINN) replaced resistor ground.
Figure 11-5. AT84AS003 Analog Input Termination Scheme (Differential)
AT84AS003
Differential signal Full-scale amplitude mVp-p Centered common mode
mVp-p mVp-p
(V25)
Line
(W24)
VINN
VINN (W23) VINN (V22)
11.3
Clock Input Implementation
AT84AS003 clock inputs (CLK/CLKN) designed either single-ended differential operation recommended drive clock differentially optimize device's performances high frequencies. external termination required clock inputs (CLK/CLKN) they already on-chip terminated resistors connected ground on-chip capacitor. AT84AS003 input clock used either coupled common mode) coupled (ECL, LVDS example) mode. recommended differential sinewave signal mVp-p differential) centered common mode drive clock signals. balun (with Sqrt(2) ratio) then necessary convert single-ended clock signal differential clock signal.
Note: clock frequency fixed, then recommended narrow-band filter clock signal order minimize jitter integrated noise aver band interest.
5403B-BDC-02/06
Figure 11-6. AT84AS003 Clock Input Termination Scheme (Single-ended)
AT84AS003
Single ended signal Full-scale amplitude mVp-p Centered common mode CLKN CLKN (J27) Line (H27)
Figure 11-7. AT84AS003 Clock Input Recommended Termination Scheme (Differential)
AT84AS003
Differential signal Full-scale amplitude Centered common mode Line CLKN
(H27)
11.4
LVDS Input Implementation
DAI/DAIN input data standalone delay cell LVDS compatible. differentially on-chip terminated described Figure 11-8. Figure 11-8. AT84AS003 LVDS Input (DAI/DAIN) Termination Scheme
AT84AS003
Line
Line
CLKN (J27)
Line
Line
Line
DAIN
AT84AS003
5403B-BDC-02/06
AT84AS003
11.5 LVDS Output Implementation
data (Ai/AiN.Di/DiN, AOR/AORN.DOR/DORN DAO/DAON) clock outputs (DR/DRN) LVDS compatible. They have differentially terminated described Figure 11-9. Figure 11-9. AT84AS003 LVDS Output Termination Scheme
AT84AS003 Line Positive Output Signal
Line Negative Output Signal
11.6
DRRB ASYNCRST Implementation
DRRB ASYNCRST required start device properly.DRRB active level while ASYNCRST active high level. recommended apply both reset signals simultaneously, possible solution differential driver that DRRB ASYNCRST generated signals differential pair. This would allow both simultaneous application signals device simple drive both signals. example provided below (principle operation). Figure 11-10. AT84AS003 DRRB ASYNCRST Driver Scheme
DRRB Pulse Source
ASYNCRST
Please refer AT84AS003 "Reset Implementation Application Note" more information.
5403B-BDC-02/06
Package Information
Figure 12-1. EBGA Package Outline
AT84AS003
5403B-BDC-02/06
AT84AS003
Ordering Information
Table 13-1.
Part Number AT84AS003CTP
Ordering Information
Package EBGA Temperature Range Commercial Tamb 90°C Industrial -40°C Tamb 110°C Ambient Screening Standard Comments
AT84AS003VTP
EBGA
Standard Prototype version please contact your local Atmel sales office Please contact your local Atmel sales office Please contact your local Atmel sales office Evaluation
AT84XAS003TPY
EBGA RoHS
Prototype
AT84AS003CTPY
EBGA RoHS EBGA RoHS EBGA
Commercial Tamb 90°C Industrial 40°C Tamb 110°C Ambient
Standard
AT84AS003VTPY AT84AS003TP-EB
Standard Prototype
5403B-BDC-02/06
AT84AS003
5403B-BDC-02/06
AT84AS003
Table Contents
Features Performances Screening. Applications Description Block Diagram Functional Description Specifications
Absolute Maximum Ratings Electrical Operating Characteristics Explanation Test Levels Digital Coding
Characterization Results
Nominal Conditions Full Power Input Bandwidth VSWR Versus Input Frequency Step Response Dynamic Performance Versus Sampling Frequency Dynamic Performance Versus Input Frequency Signal Spectrum Dynamic Performance Sensitivity Versus Temperature Power Supply Dual Tone Performance
5.10 Performance
Description Main Features
Reset Control Signal Settings Programmable DMUX Ratio Output Mode (STAGG) Additional Output Clock Type Selection
5403B-BDC-02/06
Power Reduction Mode (SLEEP) Standalone Delay Cell Clock input Delay Cell
7.10 Built-In Self Test 7.11 Junction Temperature Monitoring 7.12 Pattern Generator Function 7.13 Gain Control 7.14 Sampling Delay Adjust
Equivalent Input/Output Schematics
Equivalent Analog Input Circuit Protection Equivalent Clock Input Circuit Protection Equivalent Data/Clock Output Buffer Circuit Protection Standalone Delay Cell Data Input (DAI/DAIN) Buffer Circuit Protection
Delay Cell (DACTRL/DACTRLN CLKCTRL/CLKCTRLN) Control Input Schematic Protection DRRB Equivalent Input Schematic Protection ASYNCRST Equivalent Input Schematic Protection Gain Adjust Equivalent Input Circuits Protection B/GB PGEB Equivalent Input Schematics Protection
8.10 Control Signals Input Buffers Protection
Definition Terms
Thermal Moisture Characteristics
10.1 Thermal Resistance from Junction Bottom Balls 10.2 Thermal Resistance from Junction Case 10.3 Thermal Resistance from Junction Board 10.4 Thermal Resistance from Junction Ambient 10.5 Thermal Management Recommendations 10.6 Moisture Characteristics
Applying AT84AS003
11.1 Bypassing, Decoupling Grounding 11.2 Analog Input Implementation 11.3 Clock Input Implementation 11.4 LVDS Input Implementation 11.5 LVDS Output Implementation
AT84AS003
5403B-BDC-02/06
AT84AS003
11.6 DRRB ASYNCRST Implementation
Package Information Ordering Information Table Contents.
5403B-BDC-02/06
AT84AS003
5403B-BDC-02/06
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10-bit Gsps With DMUX AT84AS003 Performances Full-power Anal

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