Gate External Battery Reverse Protection NMOS 5V/3.3V Regulator C

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Gate External Battery Reverse Protection NMOS 5V/3.3V Regulator C

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Direction-controlled Driving Four Externally-powered NMOS Transistors Programmable Dead Time Included Avoid Peak Currents Within H-bridge Integrated Charge Pump Provide Gate Voltages High-side Drivers Supply
Gate External Battery Reverse Protection NMOS
5V/3.3V Regulator Current Limitation Function Reset Derived From 5V/3.3V Regulator Output Voltage Sleep Mode With Supply Current Typically Wake-up Signal Pins
Interface Programmable Window Watchdog Battery Overvoltage Protection Battery Undervoltage Management Overtemperature Warning Protection (Shutdown) Compliant 3.3V/5V Regulator with Trimmed Band QFN32 Package
H-bridge Motor Driver ATA6823 Preliminary
Description
ATA6823 designed several body powertrain applications. used drive continuous current motor full H-bridge configuration. external microcontroller controls driving function providing signal direction signal allows motor-control application. control performed low-side switch; high-side switch permanently driving phase. VMODE configuration 3.3V mode (for regulator interface high level). window watchdog programmable time, programmable choosing certain value external watchdog resistor RWD, internally trimmed accuracy 10%. communication transceiver integrated.
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Figure 1-1.
Block Diagram
VRES CPLO Charge Pump CPIH
RGATE
RGATE
RGATE
RGATE PGND
Driver
Driver
Driver
Driver VBAT timer
PBAT VBAT VINT
Regulator
Supervisor
Vint Regulator Oscillator
Logic Control
timer
VBAT VBATSW Regulator Bandgap VMODE /RESET
Battery
Microcontroller
ATA6823 [Preliminary]
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ATA6823 [Preliminary]
Configuration
Figure 2-1. Pinning QFN32
VBATSW VBAT PGND PBAT VMODE VINT /RESET Atmel ATA6823 ZZZZZ-AL CPLO CPHI VRES
Note:
ATA6823 ZZZZZ
Date code Year above 2000, week number) Product name Wafer number Assembly sub-lot number
Table 2-1.
Description
Symbol VMODE VINT /RESET VRES Function Selector interface logic voltage level Blocking capacitor nF/10V/X7R Resistor defining watchdog interval combination adjust cross conduction time Reset signal microcontroller Watchdog trigger signal Ground chip core LIN-bus terminal Transmit signal from microcontroller Defines rotation direction motor input controls motor speed Microcontroller output keep chip Active mode Receive signal from microcontroller Diagnostic output Diagnostic output Diagnostic output Source voltage H-bridge, high-side Gate voltage H-bridge, high-side Source voltage H-bridge, high-side Gate voltage H-bridge, high-side Gate voltage reverse protection NMOS, blocking capacitor nF/25V/X7R
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Table 2-1.
Description (Continued)
Symbol CPHI CPLO PBAT PGND VBAT VBATSW Function Charge pump capacitor nF/25V/X7R Blocking capacitor nF/25V/X7R Power supply (after reverse protection) charge pump H-bridge Gate voltage H-bridge, low-side Gate voltage H-bridge, low-side Power ground H-bridge charge pump 5V/100 supply microcontroller, blocking capacitor µF/10V/X7R Supply voltage core (after reverse protection) PMOS switch from VBAT Enable input
General Statement Conventions
Parameter values given without tolerances indicative only tested production Parameters given with tolerances without parameter number first column parameter table "guaranteed design" (mainly covered measurement other specified parameters). These parameters tested production. tolerances given knowledge parameter tolerances important application lowest power supply voltage named voltage specifications referred otherwise stated Sinking current means that current flowing into (value positive) Sourcing current means that current flowing (value negative)
Related Documents
Qualification integrated circuits according Atmel® procedure based AEC-Q100 AEC-Q100-004 JESD78 (Latch-up) S5.1-1998 801-2 (only information regarding requirements PCB)
ATA6823 [Preliminary]
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ATA6823 [Preliminary]
Application
General Remark
This chapter describes principal application which ATA6823 designed. Because Atmel cannot considered understand fully aspects system, application environment, warranties fitness particular purpose given.
Table 4-1.
Component CVINT CVCC CVRES RRWD CLIN
Typical External Components
Function Blocking capacitor VINT Blocking capacitor Cross conduction time definition capacitor Cross conduction time definition resistor Blocking capacitor Charge pump capacitor Reservoir capacitor Watchdog time definition resistor Filter capacitor Value 10V, 10V, Typical 100V, Typical 25V, 25V, 25V, Typical Typical 100V Tolerance
Functional Description
5.1.1
Power Supply Unit with Supervisor Functions
Power Supply supplied reverse-protected battery voltage. prevent from destruction, proper external protection circuitry added. recommended least capacitor combination storage caps behind reverse protection circuitry closed VBAT (see Figure page fully-internal low-power low-drop regulator, stabilized external blocking capacitor provides necessary low-voltage supply needed wake-up process. low-power band reference trimmed used bigger regulator, too. internal blocks supplied internal regulator.
Note: internal supply voltage VINT must used other supply purpose!
Nothing inside except logic interface microcontroller supplied 5V/3.3V regulator. power-good comparator checks output voltage VINT regulator keeps whole chip reset long voltage low. There high-voltage switch which brings battery voltage VBATSW measurement purposes. This switch switched HIGH stays case watchdog reset going sleep mode, VBATSW turns OFF. signal used switch external voltage regulators, etc.
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5.1.2
Voltage Supervisor This block intended protect external power transistors against overvoltage battery level manage undervoltage Function: case both overvoltage alarm (VTHOV) undervoltage alarm (VTHUV) external NMOS motor bridge transistors will switched off. failure state will flagged DG2. other actions will carried out. voltage supervision block connected VBAT filtered first-order pass with corner frequency typical kHz.
5.1.3
Temperature Supervisor There temperature sensor integrated on-chip prevent from overheating failure external circuitry protect external NMOSFET transistors. case detected overtemperature (150°C), diagnostic will switched signalize this event microcontroller. should undertake actions reduce power dissipation case detected overtemperature (165°C), regulator drivers including transceiver will switched immediately /RESET will LOW. Both temperature thresholds correlated. absolute tolerance ±10°C there built-in hysteresis about 10°C avoid fast oscillations. After cooling down below 155°C threshold; will into Active mode. interface separate thermal shutdown with disabled low-side driver typically 165°C.
Sleep Mode
able guarantee quiescent current inactive Sleep mode established. Sleep mode possible wake-up using pins LIN. Sleep mode, following blocks active: Band Internal regulator (VINT) with external blocking capacitor Input structure detecting pins threshold Wake-up block receive part
Wake-up Sleep Mode Strategy
modes: Sleep Active. change between modes described below. default state after power-on Active mode. wake-up procedure brings from standby mode (Sleep) active mode (Active). internal supply VINT, input structure certain part receiver permanently active ensure proper startup system. Active Sleep procedures implemented follows: Active activating input intended switch-on from external signal. input structure consists comparator with built-in hysteresis. ESD-protected diodes against VBAT; this reason input voltage level must positive higher than VBAT.
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ATA6823 [Preliminary]
Pulling VBAT level will drive into Active mode. debounced with time constant based clock. Active using interface second possibility wake-up performed using transceiver. Sleep mode, receiver partially active. wake-up requires steps: voltage below value V/DATwake (about VVBAT receive part interface active (not confused with Active mode whole IC). active receive part able detect valid pin. during filter time twakeLIN (typically will change Active mode. short change back HIGH during filter time will reset filter. This information stored latch after entering Active mode change Active mode caused LIN, pins remain without disturbing Active mode. Stay Active input intended keep Active Mode signal from microcontroller. input ESD-protected diodes against VCC. Therefore, input voltage must positive higher than VCC. cannot used switch from Sleep Active because regulator Sleep mode will zero. Sleep HIGH transition following permanent time gotosleep (typically switches Sleep mode. Figure illustrates wake-up LIN. status PREWAKE characterized activated receive block interface. After going Active mode, regulator starts working. Sleep possible with valid HIGH transition (permanent longer than tdb) valid HIGH state (HIGH longer than tdb) before.
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Figure 5-1.
VBAT
Wake-up
VBAT VBAT
VBAT 1.5V activating "PREWAKE"
twake twake
STATUS ACTIVE
SLEEP
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ATA6823 [Preliminary]
5V/3.3V Regulator
5V/3.3V regulator fully integrated on-chip. requires only ceramic capacitor stability current capability. Using VMODE pin, output voltage selected either 3.3V. Switching output voltage during operation intended supported. VMODE must hard-wired either VINT 3.3V. logic HIGH level microcontroller interface will adapted regulator voltage. output voltage accuracy general ±3%; mode with VVBAT limited prevent destruction current delivered regulator limited maximum delivered voltage will break down reset occur. Please note that this regulator main heat source chip. maximum output current maximum battery voltage high ambient temperature only guaranteed mounted efficient heat sink. power-good comparator checks output voltage regulator keeps external microcontroller reset long voltage low.
Reset Watchdog Management
timing basis watchdog provided trimmed internal oscillator. period TOSC adjustable external resistor RWD. watchdog expects triggering signal rising edge) from microcontroller input within period time window TWD. order save current consumption, watchdog switched during Sleep mode.
Figure 5-2.
Timing Diagram Watchdog Function
tres tresshort
/RESET
5.5.1
Timing Sequence example, with external resistor following typical parameters watchdog. TOSC 12.32 12.1 9.61 16.88 ±10% times tres fixed values with tolerance 10%.
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After ramp-up battery voltage (power-on reset), regulator switched reset output, /RESET, stays time tres (typically ms), then switches high. initial lead time (typically setups controller) watchdog waits rising edge start normal window watchdog sequence. rising edge detected, watchdog will reset microcontroller tres wait rising edge Times (close window) (open window) form window watchdog sequence. avoid receiving reset from watchdog, triggering signal from microcontroller must timeframe 9.61 trigger event will restart watchdog sequence. Figure 5-3. versus
(ms)
triggering fails, /RESET will pulled ground shortened reset time typically watchdog start sequence similar power-on reset. internal oscillator trimmed tolerance ±10%. This means that also vary ±10%. following calculation shows worst case calculation watchdog period which microcontroller provide. t1min 0.90 10.87 t1max 1.10 13.28 t2min 0.90 8.65ms, t2max 1.10 10.57 Twdmax t1min t2min 10.87 8.65 19.52 Twdmin t1max 13.28 16.42 ±3.15 (±19.1%) Figure above shows typical watchdog period depending value external resistor ROSC. reset will active VtHRESx; level VtHRESx realized with hysteresis (HYSRESth).
Transceiver
bi-directional interface implemented data transfer between local protocol controller. transceiver consists side driver (1.2V with slew rate control, wave shaping, current limitation, high-voltage comparator followed debouncing unit receiver.
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ATA6823 [Preliminary]
5.6.1 Transmit Mode During transmission, data will transferred driver generate signal LIN. minimize electromagnetic emission line, driver integrated slew rate control wave-shaping unit. Transmission will interrupted following cases: Thermal shutdown active overtemperature active Sleep mode Figure 5-4. Definition Timing Parameters
tBit
(input transmitting Node)
tBit
tBit
tBus_dom(max)
tBus_rec(min)
THRec(max)
(Transceiver supply transmitting node)
Thresholds receiving node Signal
THDom(max) Thresholds receiving node
THRec(min) THDom(min)
tBus_dom(min)
(output receiving Node
tBus_rec(max)
trx_pdf(1)
(output receiving Node
trx_pdr(1)
trx_pdr(2)
trx_pdf(2)
recessive level generated from integrated pull-up resistor series with active diode. This diode prevents reverse current VBUS during differential voltage between VSUP (VBUS VSUP). additional termination resistor necessary ATA6823 slave nodes. this used master nodes, necessary that terminated external resistor series with diode VBAT. 5.6.2 Dominant Time-out Function input internal pull-down resistor. internal timer prevents line from being driven permanently dominant state. forced longer than tdom 18.4 will switched recessive mode. reset this mode switch high before switching dominant again.
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5.7.1
Control Inputs EN1, EN2, DIR,
Pins EN1, enable pins used activate with HIGH. level input, withstand voltage 40V. Internal pull-down resistors included.
5.7.2
Logical input control direction external motor controlled internal pull-down resistor included.
5.7.3
Logical input information delivered external microcontroller. Duty cycle frequency this passed through H-bridge. internal pull-down resistor included.
Table 5-1.
Status Depending Control Inputs Detected Failures
Driver Stage External Power /PWM /PWM Standby mode Motor forward Motor reverse Comments
Control Inputs
internal signal high when least valid trigger been accepted (SYNC VBAT inside specified range charge pump reached minimum voltage (CPOK device overheated (OT2 case short circuit, appropriate transistor switched after debounce time about order avoid cross current through bridge, cross conduction timer implemented. time constant programmable means combination.
Table 5-2.
CPOK Note:
Status Diagnostic Outputs
Device Status Diagnostic Outputs Charge pump failure Overtemperature warning Overvoltage Undervoltage Short circuit Comments
represents: don't care effect) OT1: Overtemperature warning Overvoltage VBAT Undervoltage VBAT Short circuit CPOK: Charge pump
order able distinguish between wake-up from from EN2, source wake-up flagged until first valid trigger (LIN
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ATA6823 [Preliminary]
Regulator
regulator used generate gate voltage low-side driver. output voltage will used input charge pump, which generates gate voltage high-side driver. purpose regulator limit gate voltage external power transistors 12V. needs ceramic capacitor stability. output voltage reduced supply voltage VBAT falls below 12V.
Charge Pump
integrated charge pump needed supply gates external power transistors. needs shuffle capacitor reservoir capacitor Without load, output voltage reservoir capacitor VBAT plus charge pump clocked with dedicated internal oscillator KHz. charge pump designed reach good level.
5.10
Thermal Shutdown
There thermal shutdown block implemented. With rising junction temperature, first warning level will reached 150°C. this point stays fully functional warning will sent microcontroller. junction temperature 165°C regulator will switched reset occurs.
5.11
H-bridge Driver
includes push-pull drivers control external power NMOS used high-side drivers push-pull drivers control external power NMOS used low-side drivers. drivers able used with standard logic-level power NMOS. drivers high-side control charge pump voltage supply gates with voltage above battery voltage level. low-side drivers supplied directly. possible control external load (motor) forward reverse direction (see Table page 12). duty cycle controls speed. duty cycle 100% possible both directions.
5.11.1
Cross Conduction Time prevent high peak currents H-bridge, non-overlapping phase switching external power NMOS realized. external combination defines cross conduction time following way: (µs) 0.41 (nF) (tolerance: ±0.15 combination charged switching level internal comparator start level. resistor must greater than should close possible value capacitor material recommended. time measurement triggered signal crossing level.
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Figure 5-5.
Timing Drivers
tLxHL tLxf tLxLH tLxr
tHxLH tHxr tHxHL tHxf
delays tHxLH tLxLH include cross conduction time tCC.
5.12
Short Circuit Detection
detect short H-bridge circuitry, internal comparators detect voltage difference between source drain external power NMOS. transistors switched source-drain voltage difference higher than value with tolerances) time (typically signal (short circuit) will drivers will switched immediately. diagnostic will "H". With next transition PWM, will cleared corresponding drivers, depending pin, will switched again. There PBAT supervision block implemented detect possible voltage drop PBAT during short circuit. voltage PBAT falls under VSCPB (5.6V with tolerances) time drivers will switched immediately will "H". will cleared above.
ATA6823 [Preliminary]
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ATA6823 [Preliminary]
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Description Ground Power ground Reverse protected battery voltage Reverse protected battery voltage Digital output Digital output 4.9V output, external blocking capacitor Cross conduction time capacitor/resistor combination Digital input coming from microcontroller Watchdog timing resistor Digital input direction control Digital input control Test mode Digital input enable control Digital input enable control regulator output Digital input output, external blocking capacitor Digital output Digital input data Source external high-side NMOS Gates external low-side NMOS Gates external high-side NMOS Charge pump Charge pump Charge pump output Switched VBAT Power dissipation Storage temperature Soldering temperature (10s) Notes: VVBAT 13.5V additionally limited external thermal resistance Name PGND VBAT PBAT /RESET DG1, DG2, VINT VMODE CPLO CPHI VRES VBATSW Ptot STORE SOLDERING -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
+0.3 VVCC VVCC +5.5 VVINT VVINT VVCC VVCC VVCC VVCC VVBAT +5.5 VVINT VVCC VVCC VVBAT VPBAT VVRES VVBAT
Unit
VPGND -0.3 -0.3 -0.3 -0.3
+150
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Thermal Resistance
Parameters Thermal resistance junction heat slug Thermal resistance junction ambient when heat slug soldered Symbol Rthjc Rthja Value Unit
Operating Range
operating conditions define limits functional operation parametric characteristics device. Functionality outside these limits implied unless otherwise stated explicitly. Parameters Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Normal functionality Normal functionality, overtemperature warning Drivers switched OFF, regulator Note: Full functionality H-bridge drivers switched (undervoltage detection) H-bridge drivers switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly H-bridge drivers switched off, regulator working, RESET correct H-bridge drivers switched
Symbol VVBAT1 VVBAT2 VVBAT3 VVBAT4 VVBAT5
+125 +125
Unit
Operating supply voltage(2)
Ambient temperature range under bias
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ATA6823 [Preliminary]
Electrical Characteristics
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Parameters Test Conditions Symbol IVBAT1 IVBAT2 VINT Measured during qualification only Measured during qualification only VVBAT 13.5V VTHOV VTOVhys VTHUV VTUVhys RON_VBATSW 1.225 19.8 4.94 1.235 1.245 22.3 Unit Type* Power Supply Supervisor Functions Current consumption VBAT VVBAT 13.5V(1) Current consumption VBAT VVBAT =13.5V Standby mode Internal power supply Band voltage Overvoltage threshold VBAT Overvoltage threshold hysteresis VBAT Undervoltage threshold VBAT Undervoltage threshold hysteresis VBAT resistance VBAT switch 5V/3.3V Regulator Regulated output voltage Regulated output voltage Line regulation Load regulation Output current limitation Serial inductance CVCC including Serial resistance CVCC including Blocking
(2),
VVBAT Iload VVBAT Iload Iload Iload VVBAT
VCC1 VCC2 line regulation load regulation IOS1 CVCC
4.85 (3.2) 4.75 (3.2)
5.15 (3.4) 5.25 (3.4)
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, high material recommended higher values, stability zero load guaranteed Tested during qualification only Value depends TOSC; function tested with digital test pattern Tested during characterization only Supplied charge pump section "Cross Conduction Time" Voltage between source-drain external switching transistors active case short-circuit message will never generated switch-on time
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Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. 2.10 Parameters HIGH threshold VMODE threshold VMODE Reset Watchdog threshold voltage level /RESET threshold voltage level /RESET Hysteresis /RESET level Length pulse /RESET Length short pulse /RESET Wait first trigger Time VtHRESL before activating /RESET Resistor defining internal bias currents watchdog oscillator Watchdog oscillator period Watchdog oscillator period with internal resistor Watchdog input low-voltage threshold Watchdog input high-voltage threshold Hysteresis watchdog input voltage threshold Close window
Test Conditions
Symbol VMODE VMODE
Unit
Type*
VMODE (VMODE "L") VMODE (VMODE "L")
VtHRESH VtHRESL HYSRESth tres tresshort tdelayRESL RRWD TOSC TOSC_start (2.7) 6800 6800
(3.05)
T100 T100 T100
RRWD
11.09
13.55
3.10
VVCC
3.11 3.12 3.13 3.14
VILWD VIHWD VhysWD VVCC TOSC
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, high material recommended higher values, stability zero load guaranteed Tested during qualification only Value depends TOSC; function tested with digital test pattern Tested during characterization only Supplied charge pump section "Cross Conduction Time" Voltage between source-drain external switching transistors active case short-circuit message will never generated switch-on time
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ATA6823 [Preliminary]
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. 3.15 3.16 3.17 Parameters Open window Output low-voltage /RESET Internal pull-up resistor /RESET Transceiver Low-level output current Normal mode; VLIN 0.4V Normal mode; VLIN VBAT 0.4V VTXD ILIN VVAT 7.3V Rload VVAT Rload VVAT 7.3V Rload 1000 VVAT Rload 1000 serial diode mandatory VBUS VBAT_max Input leakage current driver VBUS VBAT Driver VBAT VBUS VBUS VBAT ILRX IHRX VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k_ RLIN IBUS_LIM IBUS_PAS_dom Test Conditions
Symbol
TOSC
Unit
Type*
IOLRES
VOLRES RPURES
High-level output current Driver recessive output voltage Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Pull resistor Current limitation Input leakage current receiver including pull-up resistor specified Leakage current recessive
VBAT
4.10
4.11
IBUS_PAS_rec
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, high material recommended higher values, stability zero load guaranteed Tested during qualification only Value depends TOSC; function tested with digital test pattern Tested during characterization only Supplied charge pump section "Cross Conduction Time" Voltage between source-drain external switching transistors active case short-circuit message will never generated switch-on time
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Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Parameters Test Conditions Symbol Unit Type* Leakage current ground loss Control unit disconnected GNDDevice from ground VBAT =12V Loss local ground must VBUS affect communication residual network Node sustain current that flow VBAT disconnected under this condition. VSUP_Device must remain operational VBUS under this condition Center receiver threshold Receiver dominant state Receiver recessive state Dominant time wake-up LIN-bus Input low-voltage threshold Input high-voltage threshold Hysteresis Pull-down resistor Pull-up resistor Rise/fall time Debounce time Charge Pump Charge pump voltage Charge pump voltage Load Load VVBAT VVBAT
4.12
IBUS_NO_gnd
4.13
IBUS
4.14 4.15 4.16 4.17 4.18
VBUS_CNT (Vth_dom Vth_rec)/2
VBUS_CNT VBUSdom VBUSrec VBUShys TBUS
0.475
0.525
0.175
Receiver input hysteresis VHYS Vth_rec Vth_dom VLIN
Control Inputs EN1, DIR, PWM, T100 VVCC T100 VVCC
EN1, DIR, PWN,
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, high material recommended higher values, stability zero load guaranteed Tested during qualification only Value depends TOSC; function tested with digital test pattern Tested during characterization only Supplied charge pump section "Cross Conduction Time" Voltage between source-drain external switching transistors active case short-circuit message will never generated switch-on time
ATA6823 [Preliminary]
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ATA6823 [Preliminary]
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Parameters Period charge pump oscillator load current without load load current with load H-bridge Driver Low-side driver HIGH output voltage ON-resistance sink stage pins ON-resistance source stage pins Output peak current pins switched Output peak current pins switched HIGH Pull-down resistance pins ON-resistance sink stage pins ON-resistance source stage pins VVBAT VLxH RDSON_LxL, RDSON_LxH, ILxL, ILxH, RPDLx RDSON_HxL, RDSON_HxH, IHxL, IHxH, VHxL, Load Load Test Conditions Symbol T100 IVGCPz IVGCP Unit Type*
-100
VVBAT 13.5V Output peak current VVBAT pins switched VVBAT Output peak current pins switched HIGH Static high-side switch output low-voltage pins VVBAT 13.5V VVBAT VVBAT
7.10
-100
7.11
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, high material recommended higher values, stability zero load guaranteed Tested during qualification only Value depends TOSC; function tested with digital test pattern Tested during characterization only Supplied charge pump section "Cross Conduction Time" Voltage between source-drain external switching transistors active case short-circuit message will never generated switch-on time
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Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. 7.12 Parameters Static high-side switch output high-voltage pins Sink resistance between ground Sleep mode Dynamic Parameters 7.14 Dynamic high-side switch output high-voltage pins fPWM Propagation delay time, low-side driver from high Propagation delay time, low-side driver from high Fall time low-side driver Rise time low-side driver Propagation delay time, Figure page high-side driver from high VVBAT 13.5V Propagation delay time, high-side driver from high Fall time high-side driver Rise time high-side driver Cross conduction time External resistor External capacitor switching transistor
Test Conditions (PWM static)
Symbol VHxHstat1(7)
VVBAT
VVBAT
Unit
Type*
7.13
RHxsleep
VHxHdyn1
VVBAT
VVBAT
7.15
Figure page VVBAT 13.5V
tLxHL
7.16
tLxLH VVBAT 13.5V CGx=5 tLxf tLxr tHxHL
7.17 7.18 7.19
7.20
tHxLH VVBAT 13.5V, tHxf tHxr RONCC
7.21 7.22 7.23 7.24 7.25 7.26
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, high material recommended higher values, stability zero load guaranteed Tested during qualification only Value depends TOSC; function tested with digital test pattern Tested during characterization only Supplied charge pump section "Cross Conduction Time" Voltage between source-drain external switching transistors active case short-circuit message will never generated switch-on time
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ATA6823 [Preliminary]
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. 7.27 7.28 7.29 Parameters Switching level comparator Short circuit detection voltage Short circuit detection time Input Input low-voltage threshold Input high-voltage threshold Hysteresis Pull-down resistor Rise/fall time Debounce time level output current High level output current
Test Conditions
Symbol Vswtcc
0.653 VVCC
0.667 VVCC
0.68 VVCC
Unit
Type*
(10)
0.47 T100
T100
Diagnostic Outputs DG1, DG2, 0.4V(6) 0.4V(6)
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, high material recommended higher values, stability zero load guaranteed Tested during qualification only Value depends TOSC; function tested with digital test pattern Tested during characterization only Supplied charge pump section "Cross Conduction Time" Voltage between source-drain external switching transistors active case short-circuit message will never generated switch-on time
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Schaffner Electromagnetic Compatibility
10.1 Transients Power-supply Rail (Battery)
application (including external protection circuitry, Figure page withstand test pulses Table 10-1.
Table 10-1.
Test Pulse
Test Pulses
Test Level -100V 150V -200V 200V 4V/5.5V Duration Number Pulses ms/2s pulses, minute recurrence period Specs 0.01 0.5, Acceptance level
Figure 10-1. Pulse
-100V
Figure 10-2. Pulse
150V
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ATA6823 [Preliminary]
Figure 10-3. Pulse
-200V
Figure 10-4. Pulse
200V
Figure 10-5. Pulse 0.01)
5.5V
4.0V
2000
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10.2
Transients
Transients these pins coupled capacitively valid application with external circuitry concerning figure Values: Pulse Pulse (see Figure 10-3 Figure 10-4 page coupled LIN, Acceptance level
10.3
Conducted Emissions, Radiated Emissions Susceptibility
application using described this specification fulfill demands following specifications: GMW3100 (2001-08) TL82166 (1998-02) TL82366 (2002-03) TL965 (1999-10) responsibility both deliverer user described meet mentioned specifications.
Latch-up Requirements
device withstands pulses when tested according S5.1-1998: Constant voltage pulse polarity samples, failures Electrical post stress testing room temperature Static latch-up tested according AEC-Q100-004 JESD78. samples, failures Electrical post stress testing room temperature test, voltage pins VBAT, LIN, VBATSW, must exceed when able drive specified current.
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ATA6823 [Preliminary]
Ordering Information
Extended Type Number ATA6823-PHQY Package QFN32 Remarks Pb-free
Package Information
Package: Exposed Dimensions indicated tolerances 0.05 0.9±0.1
0.05-0.05
technical drawings according specifications
0.65 nom. 4.55
Drawing-No.: 6.543-5097.01-4 Issue: 24.02.03
Revision History
Please note that following page numbers referred this section refer specific revision mentioned, this document. Revision 4856E-AUTO-07/07 History datasheet template
4856E-AUTO-07/07
Headquarters
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4856E-AUTO-07/07

Gate External Battery Reverse Protection NMOS 5V/3.3V Regulator C

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