Rad. Tolerant 8-bit ROMless Microcontroller 80C32E Description

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Rad. Tolerant 8-bit ROMless Microcontroller 80C32E Description

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8032 Instruction Compatible Four 8-bit Ports Three 16-bit Timer/Counters bytes Full-duplex UART Asynchronous Port Reset Sources, Level Interrupt Structure Kbytes Program Memory Space Kbytes Data Memory Space Power Control Modes Idle Mode Power-down Mode On-chip Oscillator Operating Frequency: Power Supply: 4.5V 5.5V Temperature Range: Military (-55oC 125oC) Single Event Latch-up below Threshold MeV/mg/cm2 Tested Total Dose krads (Si) according Method 1019 Packages: Side Brazed 40-pin, MQFPJ 44-pin Quality grades: with 5962-00518 ESCC with Specification 9521002
Rad. Tolerant 8-bit ROMless Microcontroller 80C32E
Description
80C32E radiation tolerant ROMless version 80C52 single chip 8-bit microcontroller. 80C32E retains features 80C32 with bytes internal RAM, 6source, 2-level interrupt system, on-chip oscillator three 16-bit timer/counters. fully static design 80C32E reduces system power consumption bringing clock frequency down value, even without loss data. 80C32E software-selectable modes reduced activity further reduction power consumption. idle mode frozen while timers, serial port interrupt system still operating. power-down mode saved other functions inoperative.
Rev. 4149N-AERO-04/07
Block Diagram
T2EX
XTAL1 XTAL2 PSEN Ctrl
Timer Timer Timer
UART
256x8
CORE
Parallel Ports Ext. Port Port Port Port IB-bus
INT0
Configuration
P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 P0.1/A1 P0.2/A2 P0.3/A3 P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA/VPP PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P1.5 P1.6 P1.7 P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.2/AD2 P0.3/AD3 P0.0/AD0 P0.1/AD1 P0.0/A0 NIC* P1.4 P1.3 P1.2 P1.1 P1.0
INT1
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 NIC* PSEN P2.7/A15 P2.6/A14 P2.5/A13
SB40
MQFPJ44
P3.6/WR P2.2/A10 P2.3/A11 P2.4/A12 4149N-AERO-04/07 P3.7/RD NIC* P2.0/A8 P2.1/A9 XTAL2 XTAL1
Note:
NIC: Internal Connection
80C32E
80C32E
Description
Mnemonic Type Name Function Ground: reference Power Supply: This power supply voltage normal, idle power-down operation Port Port open-drain, bidirectional port. Port pins that have written them float used high impedance inputs. Port pins must polarized order prevent parasitic current consumption. Port also multiplexed low-order address data during access external program data memory. this application, uses strong internal pull-up when emitting Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, Port pins that externally pulled will source current because internal pull-ups. Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, Port pins that externally pulled will source current because internal pull-ups. Port emits high-order address byte during fetches from external program memory during accesses external data memory that 16-bit addresses (MOVX @DPTR).In this application, uses strong internal pull-ups emitting During accesses external data memory that 8-bit addresses (MOVX @Ri), port emits contents SFR. Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, Port pins that externally pulled will source current because internal pull-ups. Port also serves special features 80C51 family, listed below. (P3.0): Serial input port (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt (P3.4): Timer external input (P3.5): Timer external input (P3.6): External data memory write strobe (P3.7): External data memory read strobe Reset: high this machine cycles while oscillator running, resets device. internal diffused resistor permits power-on reset using only external capacitor VCC.
P0.0-P0.7
P1.0-P1.7
P2.0-P2.7
P3.0-P3.7
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Mnemonic
Type
Name Function Address Latch Enable: Output pulse latching byte address during access external memory. normal operation, emitted constant rate oscillator frequency, used external timing clocking. Note that pulse skipped during each access external data memory. Program Store ENable: read strobe external program memory. When executing code from external program memory, PSEN activated twice each machine cycle, except that PSEN activations skipped during each access external data memory. PSEN activated during fetches from internal program memory. External Access Enable: must externally held enable device fetch code from external program memory locations. Crystal Input inverting oscillator amplifier input internal clock generator circuits. Crystal Output from inverting oscillator amplifier
PSEN
XTAL1 XTAL2
80C32E
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80C32E
Idle Power-down Operation
Idle mode allows interrupt, serial port timer blocks continue operate while clock gated off. Power-down mode stops oscillator. Table PCON Register PCON Power Control Register
SMOD Number Mnemonic SMOD
Description Double Baud Rate select double baud rate mode Reserved value read from this indeterminate. this bit. Reserved value read from this indeterminate. this bit. Reserved value read from this indeterminate. this bit. General-purpose Flag Cleared user General-purpose usage. user General-purpose usage. General-purpose Flag Cleared user General-purpose usage. user General-purpose usage. Power-down mode Cleared hardware when reset occurs. enter power-down mode. Idle mode Clear hardware when interrupt reset occurs. enter idle mode.
Reset Value 000X 0000 addressable
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Idle Mode
instruction that sets PCON.0 causes that last instruction executed before going into Idle mode. Idle mode, internal clock signal gated CPU, interrupt, Timer, Serial Port functions. status preserved entirety: Stack Pointer, Program Counter, Program Status Word, Accumulator, other registers maintain their data during Idle. port pins hold logical states they time Idle activated. PSEN hold logic high levels. There ways terminate Idle. Activation enabled interrupt will cause PCON.0 cleared hardware, terminating Idle mode. interrupt will serviced, following RETI next instruction executed will following instruction that device into idle. flag bits used give indication interrupt occurred during normal operation during Idle. example, instruction that activates Idle also both flag bits. When Idle terminated interrupt, interrupt service routine examine flag bits. other terminating Idle mode with hardware reset. Since clock oscillator still running, hardware reset needs held active only machine cycles oscillator periods) complete reset.
Power-down Mode
save maximum power, power-down mode invoked software. power-down mode, oscillator stopped instruction that invoked powerdown mode last instruction executed. internal SFRs retain their value until power-down mode terminated. lowered save further power. Either hardware reset external interrupt cause exit from powerdown. properly terminate power-down, reset external interrupt should executed before restored normal operating level must held active long enough oscillator restart stabilize. Only external interrupts INT0 INT1 useful exit from power-down. that, interrupt must enabled configured level edge sensitive interrupt input. Holding restarts oscillator bringing high completes exit detailed Figure When both interrupts enabled, oscillator restarts soon inputs held Power-down exit will completed when first input will released. this case higher priority interrupt service routine executed Once interrupt serviced, next instruction executed after RETI will following instruction that 80C32E into power-down mode.
Figure Power-down Exit Waveform
INT0 INT1
XTAL1
Active phase
Power-down phase
Oscillator restart phase
Active phase
Exit from power-down reset redefines SFRs, exit from power-down external interrupt does affect SFRs.
80C32E
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80C32E
Exit from power-down either reset external interrupt does affect internal content.
Note: idle mode activated with power-down mode (IDL bits set), exit sequence unchanged, when execution vectored interrupt, bits cleared idle mode entered.
Table State Ports During Idle Power-down Modes
Mode Idle Powerdown Program Memory External External PSEN PORT0 Floating Floating PORT1 Port Data Port Data PORT2 Address Port Data PORT3 Port Data Port Data
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Hardware Description
Electrical Characteristics
Refer 8-bit Microcontroller Hardware description manual details 80C32E functionality.
Absolute Maximum Ratings(2)
Ambient Temperature Under Bias. Military-55°C 125°C Storage Temperature -65°C 150°C Voltage .-0.5V Voltage .-0.5V 0.5V Power Dissipation W(2) Notes: Stresses above those listed under Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability. This value based maximum allowable temperature thermal resistance package.
80C32E
4149N-AERO-04/07
80C32E
Parameters
Table Parameters Standard VoltageTA -55°C +125°C; 10%; MHz.
Symbol VIH1 VOL1 Parameter Input Voltage Input High Voltage except XTAL1, Input High Voltage, XTAL1, Output Voltage, ports
Min. -0.5
0.45 0.45
Unit
Test Conditions
mA(4) mA(4) -400 -150
Output Voltage, port ALE, PSEN(5) Output High Voltage, ports 0.75 0.75
VOH1 RRST
Output High Voltage, port ALE, PSEN Pull-down Resistor Logical Input Current ports Input Leakage Current Logical Transition Current, ports Capacitance Buffer Power-down Current Power Supply Current Freq Freq Idle Freq Freq Idle Freq Freq Idle
(1)(2)(6)
-750 1.25F 0.36F
0.45V 0.45 2.0V 25°C 2.0V 5.5V 5.5V
Notes:
under reset measured with output pins disconnected; XTAL1 driven with TCLCH, TCHCL (see Figure 0.5V, 0.5V; XTAL2 N.C.; Port VCC. would slightly higher crystal oscillator used. Idle measured with output pins disconnected; XTAL1 driven with TCLCH, TCHCL 0.5V, 0.5V; XTAL2 N.C; Port VCC; (see Figure Power-down measured with output pins disconnected; VSS, PORT VCC; XTAL2 NC.; (see Figure Capacitance loading Ports cause spurious noise pulses superimposed VOLs Ports noise external capacitance discharging into Port Port pins when these pins make transitions during operation. worst cases (capacitive loading pF), noise pulse line exceed 0.45V with maxi peak 0.6V. Schmitt Trigger necessary. Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin: Maximum 8-bit port: Port Ports Maximum total output pins:
4149N-AERO-04/07
exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. Operating measured with output pins disconnected; XTAL1 driven with TCLCH, TCHCL 0.5V, 0.5V; XTAL2 N.C.; Port VCC; VSS. internal runs code (label: SJMP label). would slightly higher crystal oscillator used. Measurements made with products when possible, which worst case.
Figure Test Condition, Under Reset
(NC) CLOCK SIGNAL XTAL2 XTAL1 other pins disconnected.
Figure Operating Test Condition
Reset after high pulse during least clock cycles (NC) CLOCK SIGNAL XTAL2 XTAL1
other pins disconnected.
Figure Test Condition, Idle Mode
Reset after high pulse during least clock cycles (NC) CLOCK SIGNAL XTAL2 XTAL1
other pins disconnected.
80C32E
4149N-AERO-04/07
80C32E
Figure Test Condition, Power-down Mode
Reset after high pulse during least clock cycles (NC) XTAL2 XTAL1 other pins disconnected.
Figure Clock Signal Waveform Tests Active Idle Modes
VCC-0.5V 0.45V TCLCH TCHCL TCLCH TCHCL 5ns. 0.7VCC 0.2VCC-0.1
4149N-AERO-04/07
Parameters
Each timing symbol characters. first character always (stands time). other characters, depending their positions, stand name signal logical status that signal. following list characters what they stand for. Example: TAVLL Time Address Valid Low. TLLPL Time PSEN Low. -55°C +125°C (Military temperature range); 10%; Load capacitance Port PSEN Load capacitance other outputs Table External Program Memory Characteristics (ns)
Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ Parameter Pulse Width Address Valid Address Hold After Valid Instruction PSEN PSEN Pulse Width PSEN Valid Instruction Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN Address Valid Address Valid Instruction PSEN Address Float
Figure External Program Memory Read Cycle
TCLCL TLHLL TLLIV TLLPL TPLPH PSEN TLLAX TAVLL INSTR A0-A7 TAVIV PORT ADDRESS SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXAV TPXIZ A0-A7 INSTR
TPXIX INSTR
PORT
80C32E
4149N-AERO-04/07
80C32E
Table External Data Memory Characteristics (ns)
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter Pulse Width Pulse Width Valid Data Data Hold After Data Float After Valid Data Address Valid Data Address Data Valid Transition Data set-up High Data Hold After Address Float High high
Figure External Data Memory Write Cycle
TLLDV TWHLH
PSEN
TLLWL TRLDV
TRLRH TRHDZ TRHDX DATA TRLAZ ADDRESS A8-A15
TLLAX PORT A0-A7 TAVWL PORT ADDRESS SFR-P2 TAVDV
4149N-AERO-04/07
Figure External Data Memory Read Cycle
TWHLH
PSEN
TLLWL
TWLWH
TLLAX PORT A0-A7 TAVWL PORT ADDRESS SFR-P2 ADDRESS A8-A15 TQVWX TQVWH DATA TWHQX
Table Serial Port Timing Shift Register Mode (ns)
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge input data valid
Figure Shift Register Timing Waveforms
INSTRUCTION TXLXL CLOCK TQVXH OUTPUT DATA WRITE SBUF INPUT DATA CLEAR TXHDV
VALID VALID
TXHQX TXHDX
VALID VALID
VALID
VALID
VALID
VALID
80C32E
4149N-AERO-04/07
80C32E
Table External Clock Drive Characteristics (XTAL1)
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Period High Time Time Rise Time Fall Time
33.33 Unit
Figure External Clock Drive Waveforms
VCC-0.5 0.45
0.7VCC 0.2VCC-0.1V TCHCL
TCLCX TCLCL
TCHCX TCLCH
Figure Testing Input/Output Waveforms VCC-0.5V INPUT/OUTPUT 0.45V 0.2VCC+0.9 0.2VCC-0.1
inputs during testing driven logic 0.45V logic "0". Timing measurement made logic logic "0". Figure Float Waveforms FLOAT VOH-0.1V VOL+0.1V VLOAD VLOAD+0.1V VLOAD-0.1V
timing purposes port longer floating when change from load voltage occurs begins float when change from loaded VOH/VOL level occurs. IOL/IOH
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Figure Clock Waveforms
INTERNAL CLOCK XTAL2 EXTERNAL PROGRAM MEMORY FETCH PSEN DATA SAMPLED FLOAT DATA SAMPLED FLOAT DATA SAMPLED FLOAT THESE SIGNALS ACTIVATED DURING EXECUTION MOVX INSTRUCTION STATE4 P1P2 STATE5 P1P2 STATE6 P1P2 STATE1 P1P2 STATE2 P1P2 STATE3 P1P2 STATE4 P1P2 STATE5 P1P2
(EXT) READ CYCLE
INDICATES ADDRESS TRANSITIONS
PROGRAM MEMORY EXTERNAL) FLOAT WRITE CYCLE DATA PORT OPERATION DATA PINS SAMPLED DEST DEST PORT (P1, (INCLUDES INT0, INT1, SERIAL PORT SHIFT CLOCK (MODE PINS SAMPLED PINS SAMPLED DATA PINS SAMPLED INDICATES TRANSITION PROGRAM MEMORY EXTERNAL) (EVEN MEMORY INTERNAL) INDICATES TRANSITION
SAMPLED
SAMPLED
This diagram indicates when signals clocked internally. time takes signals propagate pins, however, ranges from This propagation delay dependent variables such temperature loading. Propagation also varies from output output component. Typically though (TA=25°C fully loaded) propagation delays approximately other signals typically Propagation delays incorporated specifications.
80C32E
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80C32E
Ordering Information
Table Possible Order Entries
Part Number MC-80C32E-30-E MJ-80C32E-30-E 5962-0051801QQC 5962-0051801QXC 5962-0051801VQC 5962-0051801VXC 952100201 952100202 MM0-80C32E-30-E(1) MM0-80C32E-30-SV Note: Speed (MHz) Temperature Range 25°C 25°C Package Side Brazed 40-pin (.6) MQFPJ 44-pin Quality Flow Engineering samples Engineering samples QML-Q QML-Q QML-V QML-V ESCC ESCC Engineering samples QML-V
-55° +125° Side Brazed (.6) -55° +125° MQFPJ 44-pin -55° +125° Side Brazed (.6) -55° +125° MQFPJ 44-pin -55° +125° Side Brazed (.6) -55° +125° MQFPJ 44-pin -55° +125° -55° +125°
Please contact Atmel availability.
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Package Drawings
40-pin Side Braze (600 mils)
80C32E
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80C32E
44-pin Multilayer Quad Flat Pack
4149N-AERO-04/07
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4149N-AERO-04/07

Rad. Tolerant 8-bit ROMless Microcontroller 80C32E Description

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