Table Contents Section Introduction Description .1-1 Features .1-

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Evaluation Board TSC695
Table Contents Section Introduction
Description .1-1 Features .1-1
Section Processor.
Processor Package .2-5 Data Buffers Control.2-7 Processor Socket Part Number.2-8 Emulation Capability .2-8 Debug Jumper .2-8 PROM8 Jumper .2-8
Section Flash) 3-11
Flash 8-bit .3-11 Flash 40-bit .3-11 Flash Expansion SIMM .3-13 Example Flash Expansion SIMM .3-14
Section 4-15
Bank 0.4-15 Bank 1.4-15 Expansion SIMM .4-16 Example Expansion SIMM.4-17
Section FPGA 5-19
FPGA Part Number .5-19 FPGA Socket Part Number .5-19 FPGA Pin-out .5-20 FPGA Clocks.5-22 FPGA Downloading.5-23
Section DMA. 6-25 Section TSC695 Power Clock 7-27
TSC695 Power.7-27 TSC695 Clocks .7-27
Evaulation Board TSC695
4139G-AERO-11/05
Table Contents
Section Reset, HALT, EWDINT Status LED's 8-29
RESET .8-29 HALT .8-30 EWDINT .8-31 Status LED's .8-31
Section Test Points 9-33 Section Logic Analizer POD's 10-35
10.1 .10-35 10.2 .10-36
Section Serial Links 11-39
11.1 11.2 11.3 11.4 Serial .11-39 Serial .11-39 Connection .11-40 Connection .11-41
Section Connector 12-43 Section Expansion Connectors. 13-45
13.1 points connector .13-45 13.2 points connector .13-46 13.3 points connector .13-47
Section Board Implementation. 14-49 Section Deviations 15-51
15.1 CB[6:0] DPAR FPGA .15-51 15.2 Reset HALT Driven JTAG Connector.15-51 15.3 TSC695 Signals FPGA .15-51
Section Schematics 16-53 Section Document History 17-73
Evaulation Board TSC695
4139G-AERO-11/05
Section Introduction
Description
eVAB-695 board used evaluate demonstrate TSC695 32-bit RISC embedded processor implementing SPARC architecture specification. TSC695 includes chip Integer Unit (IU), Floating Point Unit (FPU), Memory Controller Arbiter. Real Time applications, TSC695 offers high security Watch Dog, Timer's, Interrupt Controller, Parallel Serial interfaces. Fault tolerance supported using specific parity internal/external buses EDAC external data bus. design highly testable with support OnChip Debugger (OCD), internal boundary scan through JTAG interface. This board based TSC695, space, SRAM space DPRAM space. Several extension connectors large range memory mapping produces high flexibility evaluation demonstration. Free user interfaces also proposed customize application.
Features
eVAB-695 board designed standard VME. board format (23.3 inches). rear front 96-pin connectors only respect power lines bus. TSC695 includes major features (except co-processor implementation master/checker mode) ERC32 chip-set. component divided blocks: based SPARC V7.0 architecture compliant ANSI/IEEE standard specific memory controller slave arbiter seven peripherals:
watchdog NMI) timers interrupt controller UART's JTAG controller with
1.2.1
Processor
1.2.2
eVAB-695 have either 8-bit boot-Flash Kbytes code either 40-bit boot-Flash Mbytes code. bytes code using SIMM module mounted expansion. eVAB-695 equipped with RDBmon remote debugger.
Evaluation Board TSC695
Rev. 4139G-AERO-11/05
Introduction
1.2.3
eVAB-695 have banks 40-bit SRAM Mbytes data/code each. bytes data/code using SIMM modules mounted expansion.
1.2.4
FPGA
board provided without FPGA. capability given mount ALTERA 10K50 FPGA board. Note: FPGA interface been used Atmel internal prototyping needs. only been partially validated. FPGA area receives signals TSC695 except address data buses. FPGA receives address data buffered buses. Some other FPGA I/O's connected expansion connectors. FPGA downloaded either serial PROM (not provided), either BitBlaster connector.
1.2.5 1.2.6
Expansion Connectors Debugging
expansion connectors provided. reserved system expansion (processor emulation, DMA, exchange RAM, dedicated expansion.
connector TAP-JTAG hardware debugging 34-bit pods logic analysis couples signal/Gnd test points system halt input input EWDINT)
1.2.7
Power
eVAB-695 powered (Vcc board) volts with proper choice components. Each TSC695 core (VccI) TSC695 buffers (VccO) powered separately from board.
4139G-AERO-11/05
Evaluation Board TSC695
Introduction
Board Block Diagram
Figure 1-1. Board Block Diagram
Expansion Connector
Expansion Connector
695E
Memory Interface
RASI.
Ctrl Ctrl
MDMAREQ/MDMAGNT
FPGA
34-bit pods
BRA[31:0]
BD[39:0]
RA[31:0]
D[39:0]
SYSCLK
Boot
Boot
SIMM
Bank[1,0]
Internal Peripherals SIMM SIMM Serial PROM
Bank[m,n] Bank[r,
Reset
FPGA Area
Connector
BitBlaster
processor TSC695 placed centre board compatible with test equipment. serial connectors, RESET HALT switches LED's board status placed left front side. placed rear side.
Evaluation Board TSC695
4139G-AERO-11/05
Section Processor
Processor Package
processor TSC695. package used package provided customers, 256-pin MQFP-F package. This component mounted special support, with chip-carrier. component placed bottom support. hole made board, under component, access when removed (SEU tests).
Figure 2-1. TSC695 View
INST FLUSH VSSO VCCO INULL DEBUG TMODE[0] TMODE[1] EWDINT IWDE WDCLK MHOLD DDIR VSSO VCCO DDIR BUFFEN MEMWR VSSO VCCO VSSI VCCI MEMCS[0] MEMCS[1] MEMCS[2] VSSO VCCO MEMCS[3] MEMCS[4] MEMCS[5] MEMCS[6] MEMCS[7] MEMCS[8] VSSO VCCO MEMCS[9] ROMCS PROM8 VSSI VCCI CB[0] VSSO VCCO CB[1] CB[2] CB[3] CB[4] VSSO VCCO CB[5] CB[6] BA[0] BA[1] SYSRESET RESET VSSO VCCO MEXC DXFER
GPINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] D[20] D[19] D[18] VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2] VCCO VSSO D[1]
TSC695
(top view)
RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31] RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] RA[18] VCCO VSSO RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO VSSO RA[2] RA[1]
Evaluation Board TSC695
LOCK RLDSTO VSSO VCCO IOSEL[0] IOSEL[1] IOSEL[2] VSSO VCCO IOSEL[3] IOWR CPAR VSSO VCCO IUERR EXTINTACK VSSI VCCI EXTINT[0] EXTINT[1] EXTINT[2] EXTINT[3] EXTINT[4] SYSAV SYSERR VSSO VCCO CPUHALT SYSHALT NOPAR ROMWRT BUSRDY BUSERR DMAREQ VSSI VCCI EXMCS DMAGNT VSSO VCCO DMAAS DRDY CLK2 TRST SYSCLK VSSO VCCO DPAR RASPAR RAPAR VSSO VCCO RA[0]
Rev. 4139G-AERO-11/05
Processor
Processor PinOut
Table 2-1. TSC695 Pin-out
Signal
GPIINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] D[20] D[19] D[18] VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2]
Signal
D[0] RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31] RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] RA[18] VCCO VSSO RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO
Signal
RA[0] VCCO VSSO RAPAR RASPAR DPAR VCCO VSSO SYSCLK TRST CLK2 DRDY DMAAS VCCO VSSO DMAGNT EXMCS VCCI VSSI DMAREQ BUSERR BUSRDY ROMWRT NOPAR SYSHALT CPUHALT VCCO VSSO SYSERR SYSAV EXTINT[4] EXTINT[3] EXTINT[2] EXTINT[1] EXTINT[0] VCCI VSSI EXTINTACK IUERR VCCO VSSO CPAR IOWR IOSEL[3] VCCO VSSO IOSEL[2] IOSEL[1] IOSEL[0] VCCO VSSO
Signal
DXFER MEXC VCCO VSSO RESET SYSRESET BA[1] BA[0] CB[6] CB[5] VCCO VSSO CB[4] CB[3] CB[2] CB[1] VCCO VSSO CB[0] VCCI VSSI PROM8 ROMCS MEMCS[9] VCCO VSSO MEMCS[8] MEMCS[7] MEMCS[6] MEMCS[5] MEMCS[4] MEMCS[3] VCCO VSSO MEMCS[2] MEMCS[1] MEMCS[0] VCCI VSSI VCCO VSSO MEMWR BUFFEN DDIR VCCO VSSO DDIR MHOLD WDCLK IWDE EWDINT TMODE[1] TMODE[0] DEBUG INULL VCCO VSSO
4139G-AERO-11/05
Evaluation Board TSC695
Processor
Table 2-1. TSC695 Pin-out (Continued)
Signal
VCCO VSSO D[1]
Signal
VSSO RA[2] RA[1]
Signal
RLDSTO LOCK
Signal
FLUSH INST
Data Buffers Control
Figure 2-2. Data Buffers Control Schematic [31:0] [6:0] BDPAR
xx245
xx245
xx245
xx245
xx245
[31:0]
[6:0] DPAR
FPGA
EXT_D_BUFFEN
EXT_C_BUFFEN
FPGA
BUFFEN
TSC695 POD3 pin26
BUFFEN
FPGA
Figure 2-3. Data Buffers Control Configuration
EXT_D_BUFFEN DATA_BUFFEN BUFFEN EXT_C_BUFFEN CB_BUFFEN BUFFEN
Data Controled Controled FPGA
Check
Evaluation Board TSC695
4139G-AERO-11/05
Processor
Processor Socket Part Number
socket used TSC695 device made ENPLAS (www.enplas.com). socket reference FPQ-256-0.508-01. chip carrier reference CA-256-0.508-01.
Emulation Capability
Excepted TMODE[1,0], DEBUG, ROMWRT NOPAR JTAG port, TSC695 signals available connectors. this way, emulation processor (support empty) done through (ex: ERC32 chip-set).
Debug Jumper
debug jumper drives directly TSC695 input "DEBUG" Gnd. Figure 2-4. Processor Debug Jumper J28J20 DEBUG Debug Debug
PROM8 Jumper
PROM8 jumper drives directly TSC695 input "PROM8" Gnd. Figure 2-5. Processor PROM8 jumper
PROM8
PROM8 PROM40
4139G-AERO-11/05
Evaluation Board TSC695
Processor
Parity Jumper
PARity jumper drives directly TSC695 input "NOPAR" Gnd.
Figure 2-6. Processor Parity jumper
PARity
Parity Parity
Evaluation Board TSC695
4139G-AERO-11/05
Section Flash)
128K 512K components used. PROM's, EPROM's Flash devices available. capacity must correctly programmed Memory Configuration Register (field psiz) TSC695. capacity will total board capacity included expansion SIMM module. on-board ROM's placed sockets.
Flash 8-bit
possible 8-bit mode. device 32-pin PLCC located U12. Table 3-1. Flash 8-bit Configuration
Capacity (8-bit Mode) 128K using Flash 29F010 512K using Flash 29F040 128K bytes code 512K bytes code
Flash 40-bit
possible 40-bit mode. devices used 32-pin PLCC located byte D[24:31], byte D[16:23], byte D[8:15],
D[0:7]byte Parity (MSB), [0:6] U13.
Table 3-2. Flash 40-bit Configuration
Capacity (40-bit Mode) 128K using Flash 29F010 512K using Flash 29F040 512K bytes code bytes code
Evaluation Board TSC695
3-11
Rev. 4139G-AERO-11/05
Flash)
Flash 8-bit/ Flash 40-bit Selection
Schematic
FPGA implemented, Flash 8-bit Flash 40-bit cannot present same time. Only decoding made FPGA allow presence both Flash 8-bit Flash 40-bit.
3.3.1
Figure 3-1. Flash 8-bit Flash 40-bit Selection Schematic
Other conditions
PROM8
TSC695
BOOTROM1_40_CS
PROM8
BOOTROM1_8_CS
Flash_8_CS Flash_40_CS
FPGA
ROMCS
FlashCS
3.3.2
FlashCS Jumper
Figure 3-2. FlashCS Jumper Configuration
BOOTROM1_8_CS Flash_8_CS ROMCS BOOTROM1_40_CS Flash_40_CS ROMCS
FPGA configured FPGA
3-12
4139G-AERO-11/05
Evaluation Board TSC695
Flash)
3.3.3
Flash 8-bit Write
ROM8-bit mode, input write signal Flash (U12) powered either MEMWR either
Figure 3-3. Flash 8-bit Write Jumper Configuration
MEMWR WR_U12
WR_U12 MEMWR WR_U12
3.4.1
Flash Expansion SIMM
Flash Expansion SIMM selection
bytes code using 72-pin SIMM proprietary module connector mounted Flash (ROM) expansion connector. operating mode mode selected boot space (ROM_8 ROM_40). FPGA implemented, Flash 8-bit Flash 40-bit cannot present same time SIMM expansion. on-SIMM Flash's selection made ROMCS signal using connector. FPGA implemented, on-SIMM Flash selected either BOOTROM2_8_CS (FPGA BOOTROM2_40_CS (FPGA signals coming from FPGA. connector used selection. Only decoding made FPGA allow presence SIMM both Flash 8-bit Flash 40bit.
3.4.2
Schematic
Figure 3-4. Flash Expansion SIMM Selection Schematic
TSC695 PROM8 FPGA ROMCS BOOTROM2_8_CS SIMM_40_CS SIMM_8_CS Other conditions BOOTROM2_40_CS
PROM8
On-SIMM FlashCS
Evaluation Board TSC695
3-13
4139G-AERO-11/05
Flash)
Figure 3-5. Flash Expansion SIMM Selection
BOOTROM2_8_CS SIMM_8_CS ROMCS BOOTROM2_40_CS SIMM_40_CS ROMCS
FPGA configured FPGA
3.4.3
Flash Expansion SIMM pin-out
This pin-out compatible SIMM module SRAM expansion. Bottom view:
MEMWR
SIMM_8_CS +VCC
BRA13
BRA14
BRA15
BRA16
BRA17
BRA18
BRA19
BRA20
BRA21
BCB00
BCB01
BCB02 (512K
BD04 BD05
BD06
BRA02 BRA03 BRA04 BRA05 BRA06 BD07 BD12 BD13 BD14 BD15 BD20 BD21
SIMM_40_CS BRA07 BRA08 BRA09 BRA10 +VCC BRA11 BRA12 BCB04 BCB05 BCB06 BCB07 BD22 BD23 BD28 BD29 BD30 BD31
view:
Example Flash This module expand Flash capacity from 512K bytes code 8-bit mode bytes code 40-bit mode. Expansion SIMM
Figure 3-6. Example Flash Expansion SIMM module
BD[7:0] BD[15:8] BD[23:16] BD[31:24] BCB[7:0]
(512K
(512K
(512K
(512K
FLASH
FLASH
FLASH
FLASH
FLASH
(512K
BA[1:0] BRA[18:2]
BRA[20:2]
MEMWR
SIMM_8_CS
SIMM_40_CS
3-14
4139G-AERO-11/05
BRA[19] BRA[20]
BRA[21]
Evaluation Board TSC695
FLASH
BCB03
BD00
BD01
BD02
BD03
BD08
BD09
BD10
BD11
BD16
BD17
BD18
BD19
BD24
BD25
BD26
BD27
BA00
BA01
Section
space 40-bit mode) built banks bytes code/data. first banks implemented board, other ones implemented 72-pin SIMM modules expansion. on-board RAM's soldered.
Bank
first bank (Bank composed five 512K SRAM's selected MEMCS[0] TSC695. total capacity bytes code/data. devices used located check byte parity, byte (D[0.7]), byte (D[8.15], byte (D[16.23]) byte (D[24.31]). First word address: 0x02000000 Last word address: 0x021FFFFC
Bank
second bank (Bank composed five 512K SRAM's selected MEMCS[1] TSC695. total capacity bytes code/data. devices used located check byte parity, byte (D[0.7]), byte (D[8.15], byte (D[16.23]) byte (D[24.31]). First word address: 0x02200000 Last word address: 0x023FFFFC
Evaluation Board TSC695
4-15
Rev. 4139G-AERO-11/05
Expansion banks using 72-pin SIMM module connector mounted expansion connector. SIMM
This space selected jumper (from MEMCS[2] MEMCS[9]). Expansion SIMM selection
4.3.1
Figure 4-1. Expansion SIMM Selection
CS2A MEMCS[2] MEMCS[3] MEMCS[4] MEMCS[5]
MEMCS[6] MEMCS[7] MEMCS[8] MEMCS[9] CS1A
4.3.2
Expansion SIMM pin-out
+VCC +VCC
This pin-out compatible with SIMM module Flash expansion. Bottom view:
MEMWR
CS1A
RA13
RA14
RA15
RA16
RA17
RA18
RA19
RA20
RA21
CB00
CB01
CB02
RA02 RA03 RA04 RA05 RA06
+VCC CS2A RA07 RA08 RA09 RA10 RA11 RA12 CB04 CB05 CB06 CB07
view:
Expansion banks using 72-pin SIMM module connector mounted expansion connector. SIMM
This space selected jumpers board (from MEMCS[2] MEMCS[9]). Expansion SIMM selection Figure 4-2. Expansion SIMM selection
4.4.1
CS2B
MEMCS[2] MEMCS[3] MEMCS[4] MEMCS[5]
MEMCS[6] MEMCS[7] MEMCS[8] MEMCS[9] CS1B
4-16
4139G-AERO-11/05
Evaluation Board TSC695
CB03
4.4.2
Expansion SIMM pin-out
+VCC +VCC
This pin-out compatible SIMM module Flash expansion. Bottom view:
MEMWR
CS1B
RA13
RA14
RA15
RA16
RA17
RA18
RA19
RA20
RA21
CB00
CB01
CB02
RA02 RA03 RA04 RA05 RA06
+VCC CS2B RA07 RA08 RA09 RA10 RA11 RA12 CB04 CB05 CB06 CB07
view:
Example Expansion SIMM
module expand capacity from bank banks.
Figure 4-3. Example Expansion SIMM module
D[7:0] D[15:8] D[23:16] D[31:24] CB[7:0]
RA[20:2] (512K (512K (512K (512K
SRAM
SRAM
SRAM
SRAM
Evaluation Board TSC695
SRAM
MEMWR
(512K
CB03
4-17
4139G-AERO-11/05
Section FPGA
internal prototyping needs, Atmel developed FPGA area TSC695 board. This interface only been partially validated (not signals have been execrised). following section gives points integration additional FPGA board. Atmel does intend fully validate FPGA interface. support will provided Atmel case integration such FPGA on-board reserved location. FPGA useful some functions board. dedicated area been reserved on-board this expansion mode requirement.
FPGA Part Number
eVAB-695 board designed ease integration ALTERA EPF-10K50 board. FPGA (BGA-356 package) should placed socket. Depending board powering 3.3V FPGA shall used. Volts:ALTERA EPF-10K50BC356-3 volts:ALTERA EPF-10K50VBC356-3
FPGA Socket Part Number
socket used FPGA device made E-Tec (www.e-tec.ch). socket reference BPW356-1270-26AA01.
Evaluation Board TSC695
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Rev. 4139G-AERO-11/05
FPGA
FPGA Pin-out
Figure 5-1. FPGA Pin-out
181716 151413 121110
Indicates location
EPF-10K50BC356-3 EPF-10K50VBC356-3 BGA-356 View
EPF-10K50BC356-3 EPF-10K50VBC356-3 BGA-356 Bottom View
5-20
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Evaluation Board TSC695
FPGA
Table 5-1. FPGA Pin-out with Inter-connections
Signal
(power) (power) BRA[0} BRA[1] BRA[2] BRA[3] (power) BRA[4] BRA[5] (power) BRA[6] BRA[7] (input) SYSCLK BRA[8] BRA[9] BRA[10] BRA[11] BRA[12] (power) BRA[13] BRA[14] (power) BRA[15] BRA[16] (power) (power) BRA[17] BRA[18] (power) BRA[19] BRA[20] BRA[21] BRA[22] BRA[23] BRA[24] BRA[25] BRA[26] (power) (input) BRA[27] BRA[28] BRA[29] BRA[30] BRA[31] RSIZE[0] RSIZE[1] (power) RASI[0] RASI[1] (power) (power) RASI[2] (power) RASI[3] ROMCS PROM8 P2-C24 P2-C23 P2-C22
Signal
P3-A29 nCONFIG (MSEL1) (MSEL0) (power) (TMS) (TRST) nSTATUS (power) P3-A30 P3-A31 P3-A32 BD[0] BD[1] BD[2] BD[3] BD[4] BD[5] BD[6] BD[7] (power) BD[8] BD[9] (power) BD[10] BD[11] BD[12] BD[13] BD[14] BD[15] BD[16] BD[17] BD[18] BD[19] BD[20] BD[21] BD[22] BD[23] BD[24] BD[25] BD[26] BD[27] BD[28] BD[29] BD[30] (power) (power) (power) BD[31] BOOTROM1_40_CS (power) BOOTROM1_8_ BOOTROM2_40 BOOTROM2_8_ DMAAS DMAREQ BUSERR
Signal
P3-B10 P3-B11 P3-B14 P3-B15 P3-B16 P3-B17 P3-B18 P3-B19 P3-B20 P3-B21 (power) P3-A17 P3-A18 P3-A19 P3-A20 P3-A21 (power) P3-A22 P3-A23 (power) (power) P3-A24 P3-A25 P3-A26 P3-A27 P3-A28 P3-B23 P3-B24 P3-B25 (power)
Signal
P3-C19 P3-C20 P3-C21 P3-C22 (power) (RDYnBSY P3-C23 P3-C24 P3-C25 (power) P3-C26 (power) P3-C27 P3-C28 P3-C29 P3-C30 P3-C31 P3-C32 IOSEL[0] IOSEL[1] (power) IOSEL[2] IOSEL[3] IOWR FLUSH (power) INST INULL IUERR SYSERR CPUHALT SYSAV GPIINT EXTINTACK RESET EWDINT IWDE WDCLK (power) LOCK DXFER RLDSTO (CLKUSR) (power) SYSHALT EXTINT[0] FPGA-RA26 EXTINT[1] EXTINT[2] EXTINT[3]
AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26
Signal
GPI[5] (power) Data0 BUFFEN (Data2 "open") (Data4 "open") GPI[6] (Data6 "open") GPI[7] CB[0] (DEV_CLRn) (power) CB[1] CB[2] CB[3] (power) CB[4] (power) CB[5] CB[6] (CS) (nCS) (TCK) (power) (power) (power) DPAR CPAR (Data5 "open") RAPAR (power) RASPAR TCK(of 695E) TMS(of 695E) TRST ](of 695E) TDI(of 695E) (input) (DEV_OE) TDO(of 695E) RESET_HALT[0] RESET_HALT[1] MEMCS[0] MEMCS[1] MEMCS[2] MEMCS[3] MEMCS[4] (nRS) (nWS) (power) (power) (power) (Data3 "open") (power) (Data7 "open") MEMCS[5] MEMCS[6] (power) MEMCS[7]
P3-B26 (power) P3-B27 P3-B28 P3-B29 P3-B30 P3-C1 P3-C2 P3-C3 P3-C4 (power) P3-C5 P3-C6 P3-C7 P3-C8 P3-C9 P3-C10
AA22 AA23 AA24 AA25 AA26 AB22 AB23
Evaluation Board TSC695
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FPGA
Table 5-1. FPGA Pin-out with Inter-connections (Continued)
Signal
(power) P2-C21 P2-C20 P2-C19 (power) (power) (power) P2-C18 P2-C17 P2-C16 master_DMARE master_DMAGN master_DMAAS master_DRDY P3-A15 P3-A16 (power) (power)
Signal
BUSRDY DMAGNT (power) (power) DRDY P3-B3 P3-B4 (power) P3-B5 P3-B6 P3-B7 P3-B8 P3-B9
Signal
P3-C11 P3-C12 (power) (power) P3-C13 P3-C14 P3-C15 P3-C16 P3-C17 P3-C18 INIT_DONE (power) (power)
AB24 AB25 AB26 AC22 AC23 AC24 AC25 AC26
Signal
EXTINT[4] GPI[0] GPI[1] GPI[2] (nCE) (TDI) GPI[3] DCLK (nCEO "open") (TDO "open") CONF_DONE (power) GPI[4]
AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Signal
MEMCS[8] MEMCS[9] (power) MEXC GCLK_1 (input) MHOLD (power) DDIR (power) EXMCS MEMWR BA[0] BA[1] (power) (power)
5.4.1
FPGA Clocks
FPGA Clocks Schematic
separate clocks must provided FPGA. Figure 5-2. FPGA Clocks Schematic CLK2
TSC695
AF13
GCLK_1
GCLK_0 FPGA
SYSCLK
TSC695
ECLK
connector
GCLK1 connector
5.4.2
FPGA Clocks Jumper
Figure 5-3. FPGA Clocks Selection
CLK2 GCLK_1 ECLK
GCLK_1 CLK2 GCLK_1 ECLK
5-22
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Evaluation Board TSC695
FPGA
5.4.3
FPGA External Clock
Figure 5-4. FPGA External Clock Location
ECLK connector
5.5.1
FPGA Downloading
Serial PROM
ways available downloading FPGA. serial PROM provided with board. serial PROM (EPC1) method possible bit-blaster mounted. serial PROM shall mounted 8-pin socket (not provided with board) powered Volts. Figure 5-5. FPGA Serial PROM location
5.5.2
Bit-Blaster
bit-blaster method available serial PROM mounted. Figure 5-6. Bit-Blaster Connector
nCTAT
view
bit-blaster must always powered Volts (J12-4). DC/DC converter (MAX682) used. This converter provides Volts, named Vbb, from source Volts
Evaluation Board TSC695
5-23
4139G-AERO-11/05
FPGA
Volts. powers pull-up resistors INIT_DONE, nCONFIG, CONF_DONE nSTATUS signals. Figure 5-7. Bit-Blaster DC/DC Converter
C144 (2.7 5.5V) (5V)
4.7K 4.7K
MAX682
J12-7
SKIP SHDN
390K PGnd C146 2.2uF C145 47uF tantale
5-24
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Evaluation Board TSC695
4.7K
4.7K
Section
special feature proposed build master with FPGA. Then another eVAB-695, seen target, accessed slave. able communicate between eVAB-695's address line RA26 driven FPGA (pin AB4). Only with inversion this line during master session, extended space master (address 0x04000000 0x0FFFFFFF) mapped boot-PROM, extended PROM, exchange Memory areas slave. same part extended space master (address 0x14000000 0x17FFFFFF) mapped areas slave. Figure 6-1. Address Configuration
FPGA-RA26 P1-RA26 695E-RA26
Evaluation Board TSC695
6-25
Rev. 4139G-AERO-11/05
Section TSC695 Power Clock
board powered (Vcc board) connector or/and also powered J28, allowing separate core TSC695.
TSC695 Power
Figure 7-1. TSC695 Power Configuration
(TSC695 core)
VccI
(board)
VccO
(TSC695 I/O)
from
Default Connections
P1P2P3(PCB)
from
P1P2P3(PCB)
TSC695 Clocks
CLK2 clock provided either oscillator format format) connector.
Evaluation Board TSC695
7-27
Rev. 4139G-AERO-11/05
TSC695 Power Clock
Figure 7-2. TSC695 clocks 74LV04-U34 74LV04-U34 ECLK-J15 GCLK1-J14 74LV04-U34 WDCLK TSC695-pin WDCLK P2-pin WDCLK FPGA-pin Figure 7-3. Clocks Location
CLK2-J25 oscillator
W-R36 W-R37
CLK2 TSC695-pin CLK2 P1-pin GCLK_1 FPGA-pin AF13
74LV04-U34 W-R38
oscillator
7-28
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Evaluation Board TSC695
Section Reset, HALT, EWDINT Status LED's
dedicated push buttons four status LED's available front side. connectors used input HALT EWDINT. RESET HALT provided connector. other sources RESET HALT managed into FPGA.
8.1.1
RESET
Schematic
Figure 8-1. RESET Schematic
4.7KW
4.7KW
SYSRESET TSC695
RESET 4.7KW
"On-Mom" 4.7mF RESET_HALT[1]
Other RESET sources
AE17 FPGA
Evaluation Board TSC695
8-29
Rev. 4139G-AERO-11/05
Reset, HALT, EWDINT Status LED's
8.1.2
Push Button Location
Figure 8-2. Reset Push Button Location
8.2.1
HALT
Schematic Figure 8-3. HALT schematic
4.7KW 4.7KW HALT 4.7KW "On-On" RESET_HALT[0] Other HALT sources SYSHALT connector
SYSHALT TSC695
AE16 FPGA
8.2.2
Push Button Location
Figure 8-4. HALT Push Button Location
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Reset, HALT, EWDINT Status LED's
8.2.3
Connector Location
Figure 8-5. HALT Connector Location
EWDINT
EWDINT used NMI. connector provided input this external signal. Figure 8-6. EWDINT Connector Location
8.4.1
Status LED's
Schematic
Figure 8-7. LED' Schematic TSC695 SYSAV TSC695 CPUHALT TSC695 green green
4.7KW
"RUN"
4.7KW
"SYSTEM AVAILABLE" "HALT"
4.7KW
8-31
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Evaluation Board TSC695
Reset, HALT, EWDINT Status LED's
8.4.2
LED's Location
Figure 8-8. LED's Location
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Evaluation Board TSC695
Section Test Points
Table 9-1. Test Points Table
Signal Signal EWDINT SYSCLK RESET SYSRESET SYSERR CPUHALT ROMCS MEMCS IOSEL MEMWR IOWR BUFFEN DDIR MHOLD INST
Evaluation Board TSC695
9-33
Rev. 4139G-AERO-11/05
Test Points
Figure 9-1. Test Points Location
9-34
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Evaluation Board TSC695
Section Logic Analyzer POD's
Four pod's logic analyzer available board. They provide inputs dis-assembler.
10.1
Logic Analyzer Logic Analyses
Table 10-1. Table
Even (red)
A2/A3 (brown)
Signal
Signal SYSCLK [15] [14] [13] [12] [11] [10]
A0/A1 (orange)
(brown)
clock E2:15 E2:14 E2:13 E2:12 E2:11 E2:10 E2:9 E2:8 E2:7 E2:6 E2:5 E2:4 E2:3 E2:2 E2:1 E2:0
A3:7 A3:6 A3:5 A3:4 A3:3 A3:2 A3:1 A3:0 A2:7 A2:6 A2:5 A2:4 A2:3 A2:2 A2:1 A2:0
DMAGNT [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]
A1:7 A1:6 A1:5 A1:4 A1:3 A1:2 A1:1 A1:0 A0:7 A0:6 A0:5 A0:4 A0:3 A0:2 A0:1 A0:0
clock E1:15 E1:14 E1:13 E1:12 E1:11 E1:10 E1:9 E1:8 E1:7 E1:6 E1:5 E1:4 E1:3 E1:2 E1:1 E1:0
Evaluation Board TSC695
10-35
Rev. 4139G-AERO-11/05
Logic Analyzer POD's
10.2
Logic Analyzer Logic Analyzer
Table 10-2. Table
Even (yellow) D2/D3 (blue) Signal clock E4:15 E4:14 E4:13 E4:12 E4:11 E4:10 E4:9 E4:8 E4:7 E4:6 E4:5 E4:4 E4:3 E4:2 E4:1 E4:0 D3:7 D3:6 D3:5 D3:4 D3:3 D3:2 D3:1 D3:0 D2:7 D2:6 D2:5 D2:4 D2:3 D2:2 D2:1 D2:0 EXMCS [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] Signal [15] [14] [13] [12] [11] [10] D1:7 D1:6 D1:5 D1:4 D1:3 D1:2 D1:1 D1:0 D0:7 D0:6 D0:5 D0:4 D0:3 D0:2 D0:1 D0:0 clock E3:15 E3:14 E3:13 E3:12 E3:11 E3:10 E3:9 E3:8 E3:7 E3:6 E3:5 E3:4 E3:3 E3:2 E3:1 E3:0 D0/D1 (yellow) (orange)
10-36
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Evaluation Board TSC695
Logic Analyzer POD's
10.3
Logic Analyzer Logic Analyzer
Table 10-3. Table
Even (blue) C2/C3 (white) Signal clock E6:15 E6:14 E6:13 E6:12 E6:11 E6:10 E6:9 E6:8 E6:7 E6:6 E6:5 E6:4 E6:3 E6:2 E6:1 E6:0 C3:7 C3:6 C3:5 C3:4 C3:3 C3:2 C3:1 C3:0 C2:7 C2:6 C2:5 C2:4 C2:3 C2:2 C2:1 C2:0 RESET LOCK RLDSTO MEMCS DXFER FLUSH INULL INST ROMCS MEXC MHOLD Signal IOSEL CPUHALT SYSERR DDIR RASI DMAREQ DMAAS DRDY RASI BUFFEN RIZE RASI MEMWR IOWR RIZE RASI C1:7 C1:6 C1:5 C1:4 C1:3 C1:2 C1:1 C1:0 C0:7 C0:6 C0:5 C0:4 C0:3 C0:2 C0:1 C0:0 clock E5:15 E5:14 E5:13 E5:12 E5:11 E5:10 E5:9 E5:8 E5:7 E5:6 E5:5 E5:4 E5:3 E5:2 E5:1 E5:0 C0/C1 (grey) (green)
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Evaluation Board TSC695
Logic Analyzer POD's
10.4
Logic Analyzer Logic Analyzer
Table 10-4. Table
Even (grey) E2/E3 (violet) Signal clock E8:15 E8:14 E8:13 E8:12 E8:11 E8:10 E8:9 E8:8 E8:7 E8:6 E8:5 E8:4 E8:3 E8:2 E8:1 E8:0 E3:7 E3:6 E3:5 E3:4 E3:3 E3:2 E3:1 E3:0 E2:7 E2:6 E2:5 E2:4 E2:3 E2:2 E2:1 E2:0 EXTINTACK EXTINT EXTINT EXTINT EXTINT EXTINT RAPAR RASPAR CPAR DPAR Signal BUSERR BUSRDY EWDINT GPIINT IOSEL IOSEL IOSEL MEMCS MEMCS MEMCS E1:7 E1:6 E1:5 E1:4 E1:3 E1:2 E1:1 E1:0 E0:7 E0:6 E0:5 E0:4 E0:3 E0:2 E0:1 E0:0 clock E7:15 E7:14 E7:13 E7:12 E7:11 E7:10 E7:9 E7:8 E7:7 E7:6 E7:5 E7:4 E7:3 E7:2 E7:1 E7:0 E0/E1 (green) (violet)
10-38
4139G-AERO-11/05
Evaluation Board TSC695
Section Serial Links
11.1
Serial
Figure 11-1. Serial link Configuration
front view
TSC695 TSC695
11.2
Serial
Figure 11-2. Serial Link Configuration
front view
TSC695 TSC695
Evaluation Board TSC695
11-39
Rev. 4139G-AERO-11/05
Serial Links
11.3
Connection
Figure 11-3. Connection Lay-out
serial port Function
eVAB-695E serial port
Function
TSC695 TSC695 TSC695
serial port (both Function
eVAB-695E serial port
Function
TSC695 TSC695 TSC695
eVAB-695E serial port
Function
TSC695 TSC695 TSC695
11-40
4139G-AERO-11/05
Evaluation Board TSC695
Serial Links
11.4
Connection
Figure 11-4. Connection Lay-out
serial port (COM1 COM2) Function
eVAB-695E serial port
Function
TSC695 TSC695 TSC695
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4139G-AERO-11/05
Evaluation Board TSC695
Section Connector
connector connector used JTAG. male type connector leads. Figure 12-1. Connector Lay-out
SY.c TDO(T
view
J13-11
TSC695-pin
received pull-up and/or pull-down resistor. default configuration resistor. TMS, TDI, TRST pads TSC695 internal pull-up resistor.
Evaluation Board TSC695
C146 C144 C145
C129
Bottom View
12-43
Rev. 4139G-AERO-11/05
Section Expansion Connectors
13.1 points connector
Table 13-1. Connector Definition
Signal
[13] [12] [11] [10] [09] [08] [07] [06] [05] [04] [03] SYSCLK [02] [01] [00] CLK2 DPAR [06] [05] [03] [02] [01] [00]
Signal
-RAPAR [31] [30] [29] [28] [27] [26] *8RSIZE RSIZE RASPAR [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14]
Signal
[25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [09] [08] [07] [06] [05] [04] [03] [02] [01] [00] [01] [00] CPAR
Evaluation Board TSC695
13-45
Rev. 4139G-AERO-11/05
Expansion Connectors
13.2
points connector
Table 13-2. Connector Definition
Signal
EXTINTACK EXTINT[4] EXTINT[3] EXTINT[2] EXTINT[1] EXTINT[0] MEXC EWDINT IWDE WDCLK MHOLD INULL FLUSH INST DXFER GPIINT
Signal
BUFFEN DDIR DDIR* EXMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS ROMCS IOSEL IOSEL IOSEL IOSEL IOWR MEMWR -Gnd
Signal
slave_DMAREQ DMAREQ slave_DMAGNT DMAGNT slave_DMAAS DMAAS slave_DRDY DRDY master_DMAREQ FPGA [pin C19] master_DMAGNT FPGA [pin C20] master_DMAAS FPGA [pin C21] master_DRDY FPGA [pin C22] EXT_D_BUFFEN FPGA [pin EXT_C_BUFFEN FPGA [pin FPGA [pin FPGA [pin C10] FPGA [pin C11] FPGA [pin C12] FPGA [pin C16] FPGA [pin C17] FPGA [pin C18] RESET SYSRESET CPUHALT SYSHALT BUSRDY SYSAV BUSERR SYSERR IUERR LOCK RLDSTO RASI RASI RASI RASI
13-46
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Evaluation Board TSC695
Expansion Connectors
13.3
points connector
Table 13-3. Connector Definition
Signal
FPGA [pin FPGA [pin FPGA [pin D26] FPGA [pin FPGA [pin N22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin M25] FPGA [pin M24] FPGA [pin M22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin C24] FPGA [pin C23] IWDE EWDINT SYSCLK RESET GPIINT
Signal
FPGA [pin P22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin N25] FPGA [pin N24] FPGA [pin N23] FPGA [pin L26] FPGA [pin L25] FPGA [pin L24] FPGA [pin L23] FPGA [pin L22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin K26] FPGA [pin K25] FPGA [pin K24] FPGA [pin K23] FPGA [pin K22] FPGA [pin FPGA [pin
Signal
FPGA [pin V24] FPGA [pin V23] FPGA [pin V22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin U25] FPGA [pin U24] FPGA [pin U23] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin T22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin R25] FPGA [pin R24] FPGA [pin R23] FPGA [pin R22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin P26] FPGA [pin P25] FPGA [pin P24] FPGA [pin P23]
13-47
4139G-AERO-11/05
Evaluation Board TSC695
Expansion Connectors
slave_DMAREQ* DMAREQ* from TSC695 slave_DMAGNT* DMAGNT* from TSC695 slave_DMAAS DMAAS from TSC695 slave_DRDY* DRDY* from TSC695
13-48
4139G-AERO-11/05
Evaluation Board TSC695
Section Board Implementation
Figure 14-1. Board Implementation Lay-out
Power
Debug RA26
BUFFEN
SIMM
SIMM
PROM
PROM8/40 GCLK1 WRROM
SRAM Bank
SRAM Bank
Simm SRAM Simm SRAM
Par/NoPar
PROM EPC1
FlashCS SIMMCS
Test Points
FPGA 10K50
Halt
CLK2 ECLK
Syshalt
Oscillators
WDCLK CLK2
EWDINT
BitBlaster
Reset
Evaluation Board TSC695
Simm PROM
14-49
Rev. 4139G-AERO-11/05
Board Implementation
Figure 14-2. Board Implementation References
eVAB-695E-Rev.D
14-50
4139G-AERO-11/05
Evaluation Board TSC695
Section Deviations
15.1
CB[6:0] DPAR FPGA
signals CB[7:0] DPAR connected FPGA those TSC695 those buffered other space than SRAM. Note that data connected FPGA are, effectively, those coming from data buffers. Disable enable buffer CB[7 DPAR (U26 xx245) using EXT_C_BUFFEN FPGA (pin drive directly CB[7:0] DPAR.
15.2
Reset HALT Driven JTAG Connector
"Reset "HALT (from JTAG FPGA CPU) possible. these functions needed, pins JTAG connector connect them FPGA, pins ("open").
15.3
TSC695 Signals FPGA
Note that following signals missing: TMODE[1,0] (not useful) DDIR* (but DDIR exits) ROMWRT* board pulldown) DEBUG MDS* NOPAR* Note: This shall taken into account FPGA implementation.
Evaluation Board TSC695
15-51
Rev. 4139G-AERO-11/05
Section Schematics
following section illustrates schematic diagrams TSC695 Evaluation Board.
Evaluation Board TSC695
16-53
Rev. 4139G-AERO-11/05
Schematics
16-54
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-55
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-56
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-57
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-58
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-59
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-60
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-61
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-62
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
16-63
4139G-AERO-11/05
Evaluation Board TSC695
Schematics
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4139G-AERO-11/05
Evaluation Board TSC695
Schematics
Evaluation Board TSC695
16-65
4139G-AERO-11/05
Schematics
16-66
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Evaluation Board TSC695
Schematics
Evaluation Board TSC695
16-67
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Schematics
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Evaluation Board TSC695
Schematics
Evaluation Board TSC695
16-69
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Schematics
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4139G-AERO-11/05
Evaluation Board TSC695
Schematics
Evaluation Board TSC695
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4139G-AERO-11/05
Section Revision History
17.1
Changes from Revision 08/99 Revision 01/00
Changed logic analizer pod's signals. Added WDCLK board. Flash SIMM selection. Placed DC/DC convertor FPGA. Buffering clock signals.
17.2
Changes from Revision 01/00 Revision 04/00
Updating Connector. Schematic R34/R35 (TAP).
17.3
Changes from Revision 04/00 Revision 03/01
Permutation names. Permutation VccO VccI. Addition board schematics.
17.4
Changes from Revision 03/01 Revision 08/03
Changing TSC695E TSC695. Changing eVAB-695E eVAB-695. Addition BUFFEN* controls on-board data buffers.
17.5
Changes from Revision 08/03 Revision 11/05
Changing +VCC (board documentation applicable boards) Precision memory mount process (socket versus soldering) Precision given FPGA area
Evaluation Board TSC695
17-73
Rev. 4139G-AERO-11/05
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Rev. 4139F-AERO-11/05

Table Contents Section Introduction Description .1-1 Features .1-

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