Tolerant 350K Used Gates CMOS Gates MG2RT Description M

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Tolerant 350K Used Gates CMOS Gates MG2RT Description M

Datasheet Thumbnail

Top Searches for this datasheet

Full Range Matrices with 480K Gates Drawn CMOS, Metal Layers, Gates DPRAM Compilers Library Optimized Synthesis, Floor Plan Automatic Test Generation (ATG) Volts Operation; Single Dual Supply Mode High Speed Performances: NAND2 Propagation Delay 4.5V, 2.7V Toggle Frequency 4.5V, 2.7V Programmable Available upon Request High System Frequency Skew Control through Clock Tree Synthesis Software Power Consumption: 1.96 µW/Gate/MHz µW/Gate/MHz Integrated Power Reset Matrices with Fully Programmable Pads Standard I/Os Versatile Cell: Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface Latch-up Protected High Noise Immunity: with Slew Rate Control Internal Decoupling Signal Filtering between Periphery Core Application Dependent Supply Routing Several Independant Supply Sources Wide Selection MQFPs MCGA Packages Pins Delivery Form with 94.6 Pitch Advanced Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence®, Mentor®, Vital® Synopsys® Reference Platforms EDIF VHDL Reference Formats Available Military Space Quality Grades (SCC, MIL-PRF-38535) Single Event Latch-up below threshold 80MeV/mg/cm2 Tested Total Dose Krad (Si) according Method 1019 with 5962-00B02
Tolerant 350K Used Gates CMOS Gates
MG2RT
Description
MG2RT series micron, array based, CMOS product family. Several arrays 480K gates cover most system integration needs. MG2RT manufactured using micron drawn, metal layer CMOS process, called SCMOS 3/2RT. base cell architecture MG2RT series provides high routability logic with extremely dense compiled memories: DPRAM. generated using synthesis tools. Accurate control clock distribution achieved hardware (Clock Tree Synthesis) software. noise prevention techniques applied array periphery: three more independent supplies, internal decoupling, customiszation dependent supply routing, noise filtering, skew controlled I/Os, swing differential I/Os, contribute improve noise immunity reduce emission level. MG2RT supported advanced software environment based industry standards linking proprietary commercial tools. Verilog, Modelsym Design Compiler reference front-end tools. Floor planning associated with timingdriven layout provides short back-end cycle.
MG2RT library allows straight forward migration from MG1RT Gates. netlist based this library simulated either MG2RT MG2RTP. also simulated provided there hardened cells. Table List Available MG2RT Matrices
Type MG2044E MG2091E MG2194E
Total Gates 44616 91464 193800 264375 361680 481143
Typical Usable Gates 31200 64000 135600 185000 253100 336800
Total Pads
Maximum Programmable
MG2265E MG2360E
MG2480E
Note:
available designs.
Libraries
MG2RT cell library been designed take full advantage features offered both logic test synthesis tools. Design testability assured full support SCAN, JTAG (IEEE 1149) BIST methodologies. More complex macro functions available VHDL, such Two-wire Interface (TWI), UART, Timer.
Block Generators
Block generators used create customer specific simulation model metallisation pattern regular functions like DPRAM. basic cell architecture allows cell DPRAM. main characteristics these generators summarised below.
Maximum Size (bits) Typical Characteristics Kbits) Bits/Word 1-36 1-36 Access Time (ns) Used Cells
Function DPRAM
MG2RT
4115L-AERO-06/05
MG2RT
Buffer Interfacing
Flexibility Inputs
buffers configured input, output, bi-directional, oscillator supply. level translator located close each buffer. Input buffers with CMOS thresholds non-inverting feature versions with without hysteresis. CMOS input buffers incorporate pull-up pull down terminators. special purposes, buffer allowing direct input matrix core available. Several kinds CMOS output drivers offered: fast buffers with drive noise buffers with drive
Outputs
Clock Generation
Clock Generation
Atmel offers different types oscillators: high frequency crystal oscillators oscillators. devices, mark-space ratio better than 40/60 start-up time less than
Frequency (MHz) Oscillators Xtal Xtal Xtal Xtal 100M Typical Consumption (mA)
Contact factory.
4115L-AERO-06/05
Power Supply Noise Protection
speed density SCMOS3/2RT technology cause large switching current spikes example when: either high current output buffers switch simultaneously, 480,000 gates switching within window
Sharp edges high currents cause some parisitic elements packaging become significant. this frequency range, package inductance series resistance should taken into account. known that inductor slows down settling time current causes voltage drops power supply lines. These drops affect behavior circuit itself disturb external application (ground bounce). order improve noise immunity core matrix, several mechanisms have been implemented inside arrays. kinds protection have been added: limit buffer switching noise other protect buffers against switching noise coming from matrix.
Buffers Switching Protection
Three features implemented limit noise generated switching current: power supplies input output buffers separated. rise fall times output buffers controlled internal regulator. design rule concerning number buffers connected same power supply line been imposed.
Matrix Switching This noise disturbance caused large number gates switching simultaneously. allow Current Protection this without impacting functionality circuit, three features have been added:
Decoupling capacitors integrated directly silicon reduce power supply drop. power supply network been implemented matrix. This solution reduces number parasitic elements such inductance resistance constitutes artificial Ground plane. mesh network supplies approximately cells. pass filter been added between matrix input output buffer. This limits transmission noise coming from ground supply matrix external world output buffers.
MG2RT
4115L-AERO-06/05
MG2RT
Packaging
Atmel offers wide range packaging options which listed below:
Pins Package Type(1) min/max Lead Spacing (mils)
MQFP
Note:
Contact Atmel local design centers check availability matrix/package combination.
4115L-AERO-06/05
Design Flows Tools
Design Flows Modes
generic design flow MG2RT array illustrated below. down design methodology proposed which starts with high level system description refined successive design steps. each step, structural verification performed which includes following tasks: Gate level logic simulation comparison with high level simulation results. Design test rules check. Power consumption analysis. Timing analysis (only after floor plan). System specification, preferably VHDL form. Functional description level. Logic synthesis. Floor planning bonding diagram generation. Test/Scan insertion, and/or fault simulation. Physical cell placement, JTAG insertion clock tree synthesis. Routing.
main design stages are:
meet various requirements designers, several interface levels between customer Atmel possible. each possible design modes review meeting required data transfer from user Atmel. cases final routing verifications performed Atmel. design acceptance formalized design review which authorizes Atmel proceed with sample manufacturing.
MG2RT
4115L-AERO-06/05
MG2RT
Figure MG2RT Design Flow
System Specifications
Simulation
Logic synthesis
Floor Plan Bonding diagram Gate Level Simulation
Scan insertion Fault Simulation
Placement
JTAG insertion Clock Tree Synthesis
Routing Extract
Backannotated Simulation
Sign-off Samples Manufacturing Test
4115L-AERO-06/05
Design Tool Design Kits (DK)
basic content design described table below. interface formats from Atmel rely IEEE industry standard: VHDL functional descriptions VHDL EDIF netlists Tabular, .VCD simulation results (VITAL format) back annotation physical floor plan information
design kits supported several commercial tools listed below. Design Support Cadence/Verilog (RTL gate), Logic Design Planner Mentor/Modelsim (RTL gate), Velocity, Architect, Flex Test Synopsys, Design Compiler, PrimeTime Vital
Table Design Description
Design Tool library Design manual libraries Synthesis library Gate level simulation library Design rules analyser Power consumption analyser Floor plan library Timing analyser library Package bonding software Scan path JTAG insertion fault simulation library
Atmel Software Name
Third Party Tools
STAR COMET
Note:
Refer "Design kits cross reference tables" ATD-TS-WF-R0181
MG2RT
4115L-AERO-06/05
MG2RT
Electrical Characteristics
Absolute Maximum Ratings
Ambient temperature under bias (TA) Military +125°C Junction temperature. 175°C Storage temperature. +150°C TTL/CMOS: Supply voltage -0.5V voltage .-0.5V 0.5V
Note: Stresses above those listed cause permanent damage device. Exposure absolute maximum rating conditions extended period affect device reliability.
Characteristics
Table Characteristics Specified
Symbol Parameter Input voltage CMOS input input Input HIGH voltage(3) CMOS input input Output voltage Output HIGH voltage Schmitt trigger positive threshold CMOS input input Schmitt trigger negative threshold CMOS input input CMOS hysteresis 25°C/5V hysteresis 25°C/5V Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP ICCSB ICCOP Leakage current cell Operating current cell 0.39 Unit Conditions
=24, mA(1) =-24, -12, mA(1)
-120
Delta
BOUT3 BOUT6 BOUT12 BOUT24 µA/MHz/gate
10.0 0.58
Notes:
According buffer: Bout24, Bout12, Bout6, Bout3. Supplied design limit guaranteed tested. more than output time shorted maximum duration seconds. Without Schmitt trigger.
4115L-AERO-06/05
Table Characteristics Specified 0.3V
Symbol Parameter Input voltage(3) LVCMOS input LVTTL input Input HIGH voltage(3) LVCMOS input LVTTL input Output voltage LVTTL Output high voltage LVTTL Schmitt trigger positive threshold LVCMOS input LVTTL input Schmitt trigger negative threshold LVCMOS input LVTTL input CMOS hysteresis 25°C/3V hysteresis 25°C/3V Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP ICCSB ICCOP Leakage current cell Operating current cell Unit Conditions
IOL=12, mA(1)
IOH= mA(1)
Delta
BOUT3 BOUT6 BOUT12 BOUT24 µA/MHz/gate
0.25
Notes:
According buffer: Bout24, Bout12, Bout6, Bout3. Supplied design limit guaranteed tested. more than output time shorted maximum duration seconds. Without Schmitt trigger.
MG2RT
4115L-AERO-06/05
MG2RT
Characteristics
Table Characteristics 25°C, Process typical (all values
Buffer BOUT12 Description Output buffer with drive Load Tphl Tplh BOUT3 Output buffer with drive Tphl Tplh BOUTQ noise output buffer with drive Tphl Tplh B3STA3 3-state output buffer with drive Tphl Tplh B3STA12 3-state output buffer with drive Tphl Tplh B3STAQ noise 3-state output buffer with drive Tphl 4.42 6.34 2.79 3.01 3.72 4.61 4.89 2.64 6.44 4.07 4.36 4.73 6.24 7.35 4.86 2.97 6.36 4.48 2.76 4.63 3.64 7.22 Transition Tplh 2.53 3.91
4115L-AERO-06/05
Table Characteristics 25°C, Process typical (all values
Cell BINCMOS Description CMOS input buffer Load Tphl Tplh BINTTL input buffer Tphl Tplh Inverter Tphl Tplh NAND2 input NAND Tphl Tplh Tphl FDFF flip-flop, Tplh BUF4X High drive internal buffer Tphl Tplh NOR2 2-Input gate Tphl Tplh OAI22 4-input INVERT gate Tphl Tplh Tphl OSFF flip-flop with scan input, 0.56 -0.34 -0.6 0.42 0.83 1.00 0.54 1.23 1.38 0.37 0.68 0.45 1.14 0.58 0.65 0.81 1.08 0.33 -0.12 0.76 0.44 -0.24 0.66 0.68 1.21 1.02 0.42 0.73 0.53 1.11 0.52 0.75 1.06 1.31 Transition Tplh 0.77 1.14
MG2RT
4115L-AERO-06/05
Atmel Corporation
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906, Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route Arsenaux Case Postale CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Chantrerie 70602 44306 Nantes Cedex France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue Rochepleine 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906, Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: information this document provided connection with Atmel products. license, express implied, estoppel otherwise, intellectual property right granted this document connection with sale Atmel products. EXCEPT FORTH ATMEL'S TERMS CONDITIONS SALE LOCATED ATMEL'S SITE, ATMEL ASSUMES LIABILITY WHATSOEVER DISCLAIMS EXPRESS, IMPLIED STATUTORY WARRANTY RELATING PRODUCTS INCLUDING, LIMITED IMPLIED WARRANTY MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, NON-INFRINGEMENT. EVENT SHALL ATMEL LIABLE DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES LOSS PROFITS, BUSINESS INTERRUPTION, LOSS INFORMATION) ARISING INABILITY THIS DOCUMENT, EVEN ATMEL BEEN ADVISED POSSIBILITY SUCH DAMAGES. Atmel makes representations warranties with respect accuracy completeness contents this document reserves right make changes specifications product descriptions time without notice. Atmel does make commitment update information contained herein. Unless specifically provided otherwise, Atmel products suitable for, shall used automotive applications. Atmel's products intended, authorized, warranted components applications intended support sustain life.
Atmel Corporation 2005. rights reserved. Atmel logo combinations thereof, registered trademarks, Everywhere trademarks Atmel Corporation subsidiaries. Other terms product names trademarks others.
Printed recycled paper.
4115L-AERO-06/05

Tolerant 350K Used Gates CMOS Gates MG2RT Description M

Top Searches for this datasheet

Other recent searches