The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

8-bit GSPS TS8388B Applications Digital Sampling Oscilloscop


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



8-bit Resolution Gain Adjust Full Power Input Bandwidth GSPS (min) Sampling Rate SINAD 44.3 (7.2 Effective Bits), SFDR dBc, GSPS, SINAD 42.9 (7.0 Effective Bits), SFDR dBc, GSPS, SINAD 40.3 (6.8 Effective Bits), SFDR dBc, GSPS, 1000 2-tone IMD: (489 MHz, MHz) GSPS lsb, Error Rate (10-13) GSPS Very Input Capacitance: mVpp Differential Single-ended Analog Inputs Differential Single-ended Compatible Clock Inputs LVDS/HSTL Output Compatibility Data Ready Output with Asynchronous Reset Gray Binary Selectable Output Data; Output Mode Power Consumption: 3.4W 70°C Typical Radiation Tolerance Oriented Design (150 Krad (Si) measured) Package Versions Evaluation board: TSEV8388B Demultiplexer TS81102G0: Companion Device Available
8-bit GSPS TS8388B
Applications
Digital Sampling Oscilloscopes Satellite Receiver Electronic Countermeasures/Electronic Warfare Direct Down-conversion
Description
TS8388B monolithic 8-bit analog-to-digital converter, designed digitizing wide bandwidth analog signals very high sampling rates GSPS. TS8388B uses innovative architecture, including on-chip Sample Hold (S/H), fabricated with advanced high speed bipolar process. on-chip full power input bandwidth, providing excellent dynamic performance undersampling applications (High digitizing).
2144D-BDC-03/05
Functional Description
Block Diagram
following figure shows simplified block diagram. Figure 2-1. Simplified Block Diagram
GAIN
MASTER/SLAVE TRACK HOLD AMPLIFIER VIN, VINB RESISTOR CHAIN ANALOG ENCODING BLOCK INTERPOLATION STAGES
REGENERATION LATCHES ERROR CORRECTION DECODE LOGIC CLOCK BUFFER OUTPUT LATCHES BUFFERS DRRB GORB DATA, DATAB
CLK, CLKB
Functional Description
TS8388B 8-bit GSPS based advanced high-speed bipolar technology featuring cutoff frequency GHz. TS8388B includes front-end master/slave Track Hold stage (S/H), followed analog encoding stage interpolation circuitry. Successive banks latches regenerate analog residues into logical data before entering error correction circuitry resynchronization stage followed differential output buffers. TS8388B works fully differential mode from analog inputs digital outputs. TS8388B features full-power input bandwidth GHz. control GORB provided select either Gray Binary data output format. gain control provided order adjust gain. Data Ready output asynchronous reset (DRRB) available TS8388B. TS8388B uses only vertical isolated transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation tolerance performance drift measured kRad total dose).
TS8388B
2144D-BDC-03/05
TS8388B
Specifications
Absolute Maximum Ratings
Absolute Maximum Ratings
Symbol DVEE VPLUSD DVEE VINB VINB VCLK VCLKB VCLK VCLKB Tstg GORB DRRB Comments Value -5.7 -0.3 -0.3 +0.3 -0.3 +0.9 VPLUSD VPLUSD -0.5 +1.5 +135 +150 Unit
Table 3-1.
Parameter
Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltage Analog input voltages Maximum difference between VINB Digital input voltage Digital input voltage Digital output voltage Clock input voltage Maximum difference between VCLK VCLKB Maximum junction temperature Storage temperature
+300 Lead temperature (soldering 10s) Tleads Note: Absolute maximum ratings limiting values (referenced 0V), applied individually, while other parameters within specified operating conditions. Long exposure maximum rating affect device reliability. thermal heat sink mandatory. "The board comes fully assembled tested, with TS8388B installed." page
Recommended Operating Conditions
Recommended Operating Conditions
Recommended Value
Table 3-2.
Parameter Positive supply voltage Positive digital supply voltage Positive digital supply voltage Negative supply voltage Differential analog input voltage (Full Scale) Clock input power level Operating temperature range
Symbol VPLUSD VPLUSD VEE, DVEE VIN, VINB VINB PCLK, PCLKB
Comments
+2.4 ±125 +125
5.25 +2.6 -4.75 ±137
Unit mVpp
output compatibility LVDS output compatibility
+1.4 -5.25
differential single-ended single-ended clock input Commercial grade: Industrial grade: Military grade:
±113
2144D-BDC-03/05
Electrical Operating Characteristics
DVEE -5V; +5V; -VINB mVpp Full Scale differential input; Digital outputs differentially terminated; (typical) 70°C. Full Temperature Range: -55°C +125°C, depending device grade.
Table 3-3.
Electrical Specifications
Test Level Value Unit Note
Parameter Power Requirements (CBGA68 package) Positive supply voltage Analog Digital (ECL) Digital (LVDS) Positive supply current Analog Digital Negative supply voltage Negative supply current Analog Digital Nominal power dissipation Power supply rejection ratio Power Requirements Power Requirements (CQFP68 packaged device) Positive supply voltage Analog Digital (ECL) Digital (LVDS) Positive supply current Analog Digital Negative supply voltage Negative supply current Analog Digital Nominal power dissipation Power supply rejection ratio
Symbol
VPLUSD VPLUSD IPLUSD AIEE DIEE PSRR
-5.5
-4.5
mV/V
VPLUSD VPLUSD IPLUSD AIEE DIEE
-5.3
-4.7
mV/V
PSRR
TS8388B
2144D-BDC-03/05
TS8388B
Table 3-3. Electrical Specifications (Continued)
Test Level Value Unit bits Note
Parameter Resolution Analog Inputs Full Scale Input Voltage range (differential mode) common mode voltage) Full Scale Input Voltage range (single-ended input option) (See Application Notes) Analog input capacitance Input bias current Input Resistance Full Power input Bandwidth (-3dB) CBGA68 package CQFP68 package Small signal input Bandwidth (10% full scale) Clock Inputs Logic compatibility clock inputs (See Application Notes) Clock inputs voltages (VCLK VCLKB): Logic voltage Logic voltage Logic current Logic current Clock input power level into termination Clock input power level Clock input capacitance
Symbol
VINB VINB FPBW SSBW
-125 -125 -250
CCLK
specified clock input power level -1.1 into -1.5
(10)
Digital Outputs Single-ended differential input mode, clock duty cycle (CLK, CLKB), Binary output data format, (typical) 70°C. Logic compatibility digital outputs (Depending value VPLUSD) (See Application Notes) Differential output voltage swings (assuming VPLUSD 0V): open transmission lines (ECL levels) differentially terminated differentially terminated Output levels (assuming VPLUSD open transmission lines: Logic voltage LVDS
(1)(6)
0.70 0.54
1.620 0.825 0.660 -1.62
-1.54
2144D-BDC-03/05
Table 3-3.
Electrical Specifications (Continued)
Test Level Value -0.88 -1.07 -1.16 -1.25 -0.8 -1.41 -1.40 -1.40 -1.10 -1.10 -1.34 -1.32 -1.25 Unit mV/°C
Parameter Logic voltage Output levels (assuming VPLUSD differentially terminated: Logic voltage Logic voltage Output levels (assuming VPLUSD differentially terminated: Logic voltage Logic voltage Differential Output Swing Output level drift with temperature
Symbol
Note
Accuracy (CBGA68 package) Single-ended differential input mode, clock duty cycle (CLK, CLKB), Binary output data format (typical) 70°C. Differential linearity Differential linearity Integral linearity Integral linearity missing codes Gain Input offset voltage Gain error drift Offset error drift DNLDNL+ INLINL+ -0.6 -1.2 -0.4 -0.7
(2)(3) (2)(3)
Guaranteed over specified temperature range ppm/°C ppm/°C
Accuracy (CQFP68 package) Single-ended differential input mode, clock duty cycle (CLK, CLKB), Binary output data format (typical) 70°C. Differential linearity Differential linearity Integral linearity Integral linearity missing code DNLDNL+ INLINL+ -0.5 -0.6 -1.0 -1.2 -0.25 -0.35
(2)(3) (2)(3)
Guaranteed over specified temperature range
TS8388B
2144D-BDC-03/05
TS8388B
Table 3-3. Electrical Specifications (Continued)
Test Level Value Unit ppm/°C ppm/°C Note
Parameter Gain error Input offset voltage Gain error drift Offset error drift Transient Performance Error Rate GSPS 62.5 settling time -VINB mVpp Overvoltage recovery time
Symbol
1E-12
Error/ sample
(2)(4)
Performance Single-ended differential input clock mode, clock duty cycle (CLK, CLKB), Binary output data format, 70°C, unless otherwise specified. Signal Noise Distortion ratio GSPS, GSPS, GSPS, 1000 dBFs) MSPS, Effective Number Bits GSPS, GSPS, GSPS, 1000 dBFs) MSPS, Signal Noise Ratio GSPS, GSPS, GSPS, 1000 dBFs) MSPS, Total Harmonic Distortion GSPS, GSPS, GSPS, 1000 dBFs) MSPS, ENOB SINAD Bits Bits Bits Bits
2144D-BDC-03/05
Table 3-3.
Electrical Specifications (Continued)
Test Level SFDR
Value Unit Note
Parameter Spurious Free Dynamic Range GSPS, GSPS, GSPS, 1000 dBFs) GSPS, 1000 dBFs) MSPS, Two-tone Inter-modulation Distortion FIN1 GSPS, FIN2 GSPS
Symbol
Switching Performance Characteristics Figure Figure page Maximum clock frequency Minimum clock frequency Minimum Clock pulse width (high) Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay Output rise/fall time DATA (20% 80%) Output rise/fall time DATA READY (20% 80%) Data ready output delay Data ready reset delay Data data ready Clock pulse width (See "Timing Diagrams" page Data data ready output delay (50% duty cycle) GSPS (See "Timing Diagrams" page Data pipeline delay Notes: Jitter TR/TF TR/TF TRDR TOD-TDR 0.280 0.350 1150 1110 0.500 0.500 +250 1360 1320 1660 1620 1000 GSPS MSPS (rms)
(9)(13) (2)(5) (2)(10) (11)(12) (11) (11) (2)(10) (11)(12) (14) (15)
clock cycles
(14)
(2)(15)
Differential output buffers internally loaded resistors. Buffer bias current "Definition Terms" page Histogram testing based sampling sinewave MSPS. Output error amplitude around correct code (including gain offset error). Maximum jitter value obtained single-ended clock input JTS8388B (chip board): (500 expected TS8388BG) Digital output back termination options depicted Application Notes. With typical value GSPS, timing safety margin data storing using ECLinPS 10E452 output registers from Freescale® equally shared before after rising edge Data Ready signals (DR, DRB). clock inputs indifferently entered differential single-ended, using levels typical power level into termination resistor inphase clock input. into clock input correspond power level clock generator.)
TS8388B
2144D-BDC-03/05
TS8388B
GSPS, 50/50 clock duty cycle, (TC1). -100 (typ) does depend sampling rate. Specified loading conditions digital outputs: controlled impedance traces properly 50/75 terminated, unterminated controlled impedance traces. Controlled impedance traces loaded standard ECLinPS register from Freescale. (i.e.: 10E452) (Typical input parasitic capacitance including package protections.) Termination load parasitic capacitance derating values: controlled impedance traces properly 50/75 terminated: ps/pF additionnal ECLinPS load. Unterminated (source terminated) controlled impedance lines: ps/pF additionnal ECLinPS termination load. Apply proper 50/75 impedance traces propagation time derating values: ps/mm (155 ps/inch) TSEV8388B Evaluation Board. Values track each other over temperature, variation TOD-TDR 100°C temperature variation). Therefore TOD-TDR variation over temperature negligible. Moreover, internal (on-chip) package skews between each Data TODs effect considered negligible. Consequently, minimum values never more than apart. same true maximum values (see Advanced Application Notes about "TOD-TDR Variation Over Temperature" page 26). value guarantees performance. value guarantees functionality. value guarantees functionality. value guarantees performance.
Timing Diagrams
TS8388B Timing Diagram GSPS Clock Rate), Data Ready Reset, Clock Held Level
Figure 3-1.
(VIN, VINB)
1000
(CLK, CLKB)
1360 TPD: Clock periods 1360
DIGITAL OUTPUTS
1000
DATA
DATA
1320
DATA
DATA
DATA
DATA
1320
TC1+TDR-TOD TC1-40
Data Ready (DR, DRB)
TC2+TOD-TDR TC2+40
TRDR
DRRB
(min)
2144D-BDC-03/05
Figure 3-2.
TS8388B Timing Diagram GSPS Clock Rate), Data Ready Reset, Clock Held HIGH Level
(VIN, VINB)
XN-1
1000
(CLK, CLKB)
1360 TPD: Clock periods 1360
DIGITAL OUTPUTS
1000
DATA
DATA
1320
DATA
DATA
DATA
DATA
DATA
1320
TC1+TDR-TOD TC1-40
Data Ready (DR, DRB)
TC2+TOD-TDR TC2+40
TRDR
DRRB
(min)
Explanation Test Levels
Table 3-4.
Notes:
Explanation Test Levels
Characteristics 100% production tested +25°C(1) (for Temperature range(2)). 100% production tested +25°C(1), sample tested specified temperatures (for Temperature range(2)). Sample tested only specified temperatures. Parameter guaranteed design characterization testing (thermal steady-state conditions specified temperature). Parameter typical value only. 100% production tested over specified temperature range (for "B/Q" Temperature range(2)).
Unless otherwise specified, tests pulsed tests: therefore where junction, case ambient temperature respectively. Refer "Ordering Information" page Only values guaranteed (typical values issuing from characterization results).
TS8388B
2144D-BDC-03/05
TS8388B
Functions Description
Functions Description
Function Positive power supply Analog negative power supply
VPLUSD (ECL) VPLUSD +2.4V (LVDS)
Table 3-5.
Name VPLUSD VIN, VINB CLK, CLKB <D0:D7> <D0B:D7B> GAIN GORB DIOD/DRRB
Digital positive power supply Ground Differential analog inputs Differential clock inputs Differential output data port Differential data ready outputs range outputs gain adjust Gray Binary digital output select junction temperature measurement/ asynchronous data ready reset
DVEE VINB CLKB GAIN GORG DIOD/ DRRB TS8388B
Digital Output Coding
(Non Return Zero) mode, ideal coding: does include gain, offset, linearity voltage errors.
Table 3-6.
Digital Output Coding
Digital Output
Differential Analog Input +251 +251 +249 +126 +124 -124 -126 -249 -251 -251
Voltage Level Positive full scale Positive full scale Positive full scale Positive scale Positive scale Bipolar zero Bipolar zero Negative scale Negative scale Negative full scale Negative full scale Negative full scale
Binary GORB Floating 11111111 11111111 11111110 11000000 10111111 10000000 01111111 01000000 00111111 00000001 00000000 00000000
Gray GORB 10000000 10000000 10000001 10100000 11100000 11000000 01000000 01100000 00100000 00000001 00000000 00000000
Range
2144D-BDC-03/05
Package Description
Description
TS8388BGL Description (CBGA68 package)
number B10, E11, G11, K10, F10, A10, D10, H11, J11, C11, G10, H10, L10, Function Ground pins. connected external ground plane. positive supply. analog negative supply. digital negative supply. phase analog input signal Sample Hold differential preamplifier. Inverted phase clock input signal (CLK). phase clock input signal. analog input sampled held rising edge signal. Inverted phase clock input signal (CLK). phase digital outputs. LSB. MSB. Inverted phase digital outputs. inverted LSB. inverted MSB. phase Range Bit. Range high leading edge code code 256. Inverted phase Range (OR). phase output Data Ready Signal. Inverted phase output Data Ready Signal (DR). Gray Binary select output format control pin. Binary output format GORB floating VCC. Gray output format GORB connected ground (0V). gain adjust pin. gain default grounded, gain transfer fuction nominally close one. function temperature measurement asynchronous data ready reset active low, single-ended input. +2.4V LVDS output levels otherwise GND(2).
Table 4-1.
Symbol DVEE VINB CLKB
B0B, B1B, B2B, B3B, B4B, B5B, B6B, GORB
GAIN
DIOD/DRRB VPLUSD Note:
B11, C10, J10,
A11, connected. common mode level output buffers 1.2V below positive digital supply. compatibility positive digital supply must (ground). LVDS compatibility (output common mode +1.2V) positive digital supply must 2.4V. subsequent LVDS circuitry withstand lower level input common mode, recommended lower positive digital supply level same proportion order spare power dissipation.
TS8388B
2144D-BDC-03/05
TS8388B
TS8388BGL Pinout
TS8388BGL Pinout CBGA Package
Figure 4-1.
VPLUSD
DVEE
VPLUSD
VPLUSD
DVEE
VPLUSD
Gorb
GAIN
VINB
Ball Index other side
CLKB
Diode
BOTTOM VIEW
2144D-BDC-03/05
Table 4-2.
Symbol VPLUSD DVEE VINB CLKB
TS8388BF/TS8388BFS Description (CQFP68 package)
number 54(1), 57(1) 37(1), 40(1) Function Ground pins. connected external ground plane. Digital positive supply compatibility, 2.4V LVDS compatibility).(2) positive supply. analog negative supply. digital negative supply. phase analog input signal Sample Hold differential preamplifier. Inverted phase analog input signal (VIN). phase clock input signal. analog input sampled held rising edge signal. Inverted phase clock input signal (CLK). phase digital outputs. LSB. MSB. Inverted phase digital outputs. inverted LSB. inverted MSB. phase Range Bit. Range high leading edge code code 256. Inverted phase Range (OR). phase output Data Ready Signal. Inverted phase output Data Ready Signal (DR). Gray Binary select output format control pin. Binary output format GORB floating VCC. Gray output format GORB connected ground (0V). gain adjust pin.
D0B, D1B, D2B, D3B, D4B, D5B, D6B, GORB GAIN
This double function (can left open grounded used): DIOD/DRRB DIOD: junction temperature monitoring pin. DRRB: asynchronous data ready reset function. Notes: Following numbers (CLK), (CLKB), (VIN) (VINB) have connected through resistor close possible package termination preferred option). common mode level output buffers 1.2V below positive digital supply. compatibility positive digital supply must (ground). LVDS compatibility (output common mode +1.2V) positive digital supply must 2.4V. subsequent LVDS circuitry withstand lower level input common mode, recommended lower positive digital supply level same proportion order spare power dissipation.
TS8388B
2144D-BDC-03/05
TS8388B
TS8388BF/TS8388BFS Pinout
TS8388BF/TS8388BFS Pinout CQFP68 package
VIEW VPLUSD VPLUSD DVEE DVEE DVEE VPLUSD VPLUSD
Figure 4-2.
index
VPLUSD GORB TS8388BF/TS8388BFS
VPLUSD Gain VINb VINb
Diode
CLKb
CLKb
2144D-BDC-03/05
Typical Characterization Results
Static Linearity
MSPS/FIN Figure 5-1. Integral Linearity
Note:
Clock Frequency MSPS; Signal Frequency MHz; Positive peak: 0.78 lsb; Negative peak: -0.73
Figure 5-2.
Differential Linearity
Note:
Clock Frequency MSPS; Signal Frequency MHz; Positive peak: lsb; Negative peak: -0.39
TS8388B
2144D-BDC-03/05
TS8388B
Effective Number Bits Versus Power Supplies Variation
Figure 5-3.
ENOB (bits) -6.5 -5.5 VEEA -4.5
Effective Number Bits (VEEA); MSPS;
Figure 5-4.
ENOB (bits)
Effective Number Bits (VCC); MSPS;
Figure 5-5.
ENOB (bits)
Effective Number Bits (VEED); MSPS;
-5.5
-4.5 VEED
-3.5
2144D-BDC-03/05
Typical Results
GSPS;
Figure 5-6.
Figure 5-7.
GSPS;
Figure 5-8.
GSPS; Full Scale Input)
TS8388B
2144D-BDC-03/05
TS8388B
Spurious Free Dynamic Range Versus Input Amplitude
Sampling Frequency: GSPS; Input Frequency MHz; Full Scale; ENOB 6.4; SINAD dBc; SFDR dBc; Gray Binary Output Coding
Figure 5-9.
Figure 5-10. Sampling Frequency: GSPS; Input Frequency MHz; Full Scale; ENOB 6.6; SINAD 40.8 dBc; SFDR dBc; Gray Binary Output Coding
2144D-BDC-03/05
Dynamic Performance Versus Analog Input Frequency
GSPS, 1600 MHz, Full Scale input (FS), Clock duty cycle 50/50, Binary/Gray output coding, fully differential single-ended analog clock inputs.
Figure 5-11. ENOB (dB)
ENOB (dB)
1000
1200
1400
1600
1800
Input frequency (MHz)
Figure 5-12. (dB)
(dB) 1000 Input frequency (MHz) 1200 1400 1600 1800
Figure 5-13. SFDR (dBc)
SFDR (dBc) 1000 1200 1400 1600 1800 Input frequency (MHz)
TS8388B
2144D-BDC-03/05
TS8388B
Effective Number Bits (ENOB) Versus Sampling Frequency
Analog Input Frequency: Nyquist conditions (FIN FS/2) Clock duty cycle 50/50, Binary output coding Figure 5-14. ENOB (dB)
FS/2 ENOB (dB)
1000 1200 1400 1600 Sampling frequency (MSPS)
SFDR Versus Sampling Frequency
Analog Input Frequency: Nyquist conditions (FIN FS/2) Clock duty cycle 50/50, Binary output coding
Figure 5-15. SFDR (dBc)
SFDR (dBc) FS/2 1000 1200 1400 1600 Sampling frequency (MSPS)
2144D-BDC-03/05
TS8388B Performances Versus Junction Temperature
Figure 5-16. Effective Number Bits Versus Junction Temperature GSPS; MHz; Duty Cycle
ENOB (bits)
Temperature (°C)
Figure 5-17. Signal Noise Ratio Versus Junction Temperature GSPS; MHz; Differential Clock; Single-ended Analog Input (VIN dBFs)
(dB)
Temperature (°C)
Figure 5-18. Total Harmonic Distorsion Versus Junction Temperature GSPS; MHz; Differential Clock; Single-ended Analog Input (VIN dBFs)
(dB)
Temperature (°C)
TS8388B
2144D-BDC-03/05
TS8388B
Figure 5-19. Power Consumption Versus Junction Temperature GSPS; MHz; Duty Cycle
Power consumption
Temperature (°C)
Typical Full Power Input Bandwidth
Figure 5-20. Full Power Input) CBGA68 package
Frequency (MHz) 1000 1200 1400 1600 1800 2000
Magnitude (dB)
2144D-BDC-03/05
Figure 5-21. Full Power Input) CQFP68 package
Frequency (MHz) 1100 1300 1500 1700
Magnitude (dB)
5.10
Step Response
Test pulse input characteristics: input full scale rise time
Note: This step response obtained with TSEV8388B chip on-board (device form).
Figure 5-22. Test Pulse Digitized with
mV/div ps/div
Time (ns)
TS8388B
2144D-BDC-03/05
TS8388B
Figure 5-23. Same Test Pulse Digitized with TS8388B
code
codes/div (Vpp ps/div
calculated rise time: between
Time (ns)
Note:
Ripples test setup (they present both measurements).
2144D-BDC-03/05
TS8388B Main
6.1.1
Timing Information
Timing Value TS8388B Timing values defined Table page advanced data, issued from electric simulations first characterizations results fitted with measurements. Timing values given package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, gullwing model, specified termination loads. Propagation delays 50/75 impedance traces taken into account TDR. Apply proper derating values corresponding termination topology. min/max timing values valid over full temperature range following conditions: Specified Termination Load (Differential output Data Data Ready): resistor parallel with standard ECLinPS register from Freescale (i.e.: 10E452) Typical ECLinPS inputs shows typical input capacitance (including package protections). addressing output Dmux, take care some Digital outputs have same termination load apply corresponding derating value given below. Output Termination Load derating values TDR: ps/pF additional ECLinPS load. Propagation time delay derating values have also applied TDR: ps/mm (155 ps/inch) TSEV8388B Evaluation Board. Apply proper time delay derating value different dielectric layer used.
6.1.2
Propagation Time Considerations Timing values given from include additional propagation times between device pins input/output termination loads. TSEV8388B Evaluation Board, propagation time delay ps/mm (155 ps/inch) corresponding GHz) dielectric constant RO4003 used Board. different dielectric layer used (for instance Teflon), please appropriate propagation time values. does depend propagation times because differential data time difference between Data Ready output delay digital Data output delay). also most straightforward data measure, again because differential: measured directly onto termination loads, with matched Oscilloscopes probes.
6.1.3
TOD-TDR Variation Over Temperature Values track each other over temperature variation TOD-TDR 100°C temperature variation). Therefore TOD-TDR variation over temperature negligible. Moreover, internal (on-chip) package skews between each Data TODs effect considered negligible.
TS8388B
2144D-BDC-03/05
TS8388B
Consequently, minimum values never more than apart. same true maximum values. other terms 1150 will 1620 (maximum time delay TDR). 1660 will 1110 (minimum time delay TDR). However, external TOD-TDR values dictated total digital datas skews between every TODs (each digital data) TDR: Board, bonding wires output lines lengths differences, output termination impedance mismatches. external board) skew effect been taken into account specification minimum maximum values TOD-TDR.
6.1.4
Principle Operation Analog input sampled rising edge external clock input (CLK, CLKB) after (aperture delay) typically digitized data available after clock periods latency (pipeline delay (TPD)), clock rising edge, after 1360 typical propagation delay TOD. Data Ready differential output signal frequency (DR, DRB) half external clock frequency, that switches same rate digital outputs. Data Ready output signal (DR, DRB) switches external clock falling edge after propagation delay typically 1320 Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) available initializing differential Data Ready output signal (DR, DRB). This feature mandatory certain applications using interleaved ADCs using single with demultiplexed outputs. Actually, without Data Ready signal initialization, impossible store output digital datas defined order.
6.2.1
Principle Data Ready Signal Control DRRB Input Command
Data Ready Output Signal Reset Data Ready signal reset falling edge DRRB input command, logical level (-1.8V). DRRB also tied Data Ready output signal Master Reset. long DRRB remains logical level, tied -5V), Data Ready output remains logical zero independant external free running encoding clock. Data Ready output signal (DR, DRB) reset logical zero after TRDR typical. TRDR measured between -1.3V point falling edge DRRB input command zero crossing point differential Data Ready output signal (DR, DRB). Data Ready Reset command pulse minimum time width.
2144D-BDC-03/05
6.2.2
Data Ready Output Signal Restart Data Ready output signal restarts DRRB command rising edge, logical high levels (0.8V). DRRB also Grounded, allowed float, normal free running Data Ready output signal. Data Ready signal restart sequence depends logical level external encoding clock, DRRB rising edge instant: DRRB rising edge occurs when external encoding clock input (CLK, CLKB) LOW: Data Ready output first rising edge occurs after half clock period clock falling edge, after delay time 1320 already defined hereabove. DRRB rising edge occurs when external encoding clock input (CLK, CLKB) HIGH: Data Ready output first rising edge occurs after clock period clock falling edge, delay 1320 Consequently, analog input sampled clock rising edge, first digitized data corresponding first acquisition after Data Ready signal restart (rising edge) always strobed third rising edge data ready signal. time delay (TD1) specified between last point change differential output data (zero crossing point) rising falling edge differential Data Ready signal (DR, DRB) (zero crossing point). normal initialization Data Ready output signal, external encoding clock signal frequency level must controlled. reminded that minimum encoding clock sampling rate MSPS consequently clock cannot stopped. single used both DRRB input command junction temperature monitoring. denomination will DRRB/DIOD. former version denomination DIOD. Temperature monitoring Data Ready control DRRB possible simultaneously.
Analog Inputs (VIN) (VINB)
analog input Full Scale range 0.5V peak peak (Vpp), into termination resistor. differential mode input configuration, that means 0.25V each input, ±125 around input common mode GROUND. typical input capacitance TS8388B CQFP CBGA packages. input capacitance mainly package.
6.3.1
Differential Inputs Voltage Span Figure 6-1. Differential Inputs Voltage Span
[mV] Full Scale analog input VINB
-250
-125
(VIN, VINB) ±250 diff
TS8388B
2144D-BDC-03/05
TS8388B
6.3.2 Differential Versus Single-ended Analog Input Operation TS8388B operate full speed either differential single-ended configuration. This explained fact uses high input impedance differential preamplifier stage, (preceeding Sample hold stage), which been designed order entered either differential mode single-ended mode. This true long out-of-phase analog input VINB terminated very closely neighboring shield ground pins (52, which constitute local ground reference inphase analog input (VIN). Thus differential analog input preamplifier will fully reject local ground noise (and capacitively inductively coupled noise) common mode effects. typical single-ended configuration, enter (VIN) input pin, with inverted phase input (VINB) grounded through termination resistor. single-ended input configuration, in-phase input amplitude 0.5V peak peak, centered into 50). inverted phase input ground potential through termination resistor. However, dynamic performances somewhat improved entering either analog clock inputs differential mode. 6.3.3 Typical Single-ended Analog Input Configuration Typical Single-ended Analog Input Configuration
[mV] Full Scale analog input VINB ±250 diff reverse termination VINB double (pins VINB
Figure 6-2.
VINB
(external package)
-250
Note:
Since VINB have double architecture, reverse termination needed. CBGA package, this reverse termination already package.
Clock Inputs (CLK) (CLKB)
TS8388B clocked full speed without noticeable performance degradation either differential single-ended configuration. This explained fact uses differential preamplifier stage clock buffer, which been designed order entered either differential single-ended mode. Recommended sinewave generator characteristics typically -120 dBc/Hz phase noise floor spectral density, from carrier, assuming single tone input clock signal.
6.4.1
Single-ended Clock Input (Ground Common Mode) Although clock inputs were intended driven differentially with nominal -0.8V/-1.8V levels, TS8388B clock buffer manage single-ended sinewave clock signal centered around This most convenient clock input configuration does require power splitter.
2144D-BDC-03/05
performance degradation (i.e.: timing jitter) observed this particular single-ended configuration GSPS Nyquist conditions (FIN MHz). This true long inverted phase clock input terminated very closely neighboring shield ground pins, which constitutes local Ground reference inphase clock input. Thus TS8388B differential clock input buffer will fully reject local ground noise (and capacitively inductively coupled noise) common mode effects. Moreover, very phase noise sinewave generator must used enhanced jitter performance. typical inphase clock input amplitude peak peak, centered (ground) common mode. This corresponds typical clock input power level into termination resistor. exceed avoid saturation preamplifier input transistors. inverted phase clock input grounded through termination resistor. Figure 6-3. Single-ended Clock Input (Ground common mode): VCLK Common Mode VCLKB Typical Clock Input Power Level (into termination resistor)
+0.5V VCLK CLKB double (pins CLKB
VCLK VCLK -0.5V
(external package)
reverse termination
Note:
exceed into termination resistor single clock input power level.
6.4.2
Differential Clock Input clock inputs driven differentially with nominal -0.8V/-1.8V levels. this mode, phase noise sinewave generator used drive clock inputs, followed power splitter (hybrid junction) order obtain degrees phase sinewave signals. Biasing tees used offseting common mode voltage levels. Note: biasing tees propagation times matching, tunable delay line required order ensure signals degrees phase especially fast clock rates GSPS range.
Figure 6-4.
-0.8V
Differential Clock Inputs (ECL Levels)
CLKB double (pins VCLK VCLKB CLKB
[mV]
Common mode -1.3V
(external package)
reverse termination
-1.8V
TS8388B
2144D-BDC-03/05
TS8388B
6.4.3 Single-ended Clock Input single-ended configuration enter (resp. CLKB) pin, with inverted phase Clock input CLKB (respectively CLK) connected -1.3V through termination resistor. inphase input amplitude peak peak, centered -1.3V common mode. Figure 6-5. Single-ended Clocl Input (ECL): VCLK Common Mode -1.3V; VCLKB -1.3V
-0.8V VCLK
VCLKB -1.3V
-1.8V
Noise Immunity Information
Circuit noise immunity performance begins design level. Efforts have been made design order make device insensitive possible chip environment perturbations resulting from circuit itself induced external circuitry (Cascode stages isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors). Furthermore, fully differential operation from analog input digital outputs provides enhanced noise immunity common mode noise rejection. Common mode noise voltage induced differential analog clock inputs will canceled these balanced differential amplifiers. Moreover, proper active signals shielding been provided chip reduce amount coupled noise active inputs. analog inputs clock inputs TS8388B device have been surrounded ground pins, which must directly connected external ground plane.
Digital Outputs
TS8388B differential output buffers internally loaded. resistors connected digital ground pins through -0.8V level shift diode (see Figure 6-6, Figure 6-7, Figure page 34). TS8388B output buffers designed driving (default) properly terminated impedance lines coaxial cables. bias current flowing alternately into resistors when switching ensures 0.825V voltage drop across resistor (unterminated outputs). VPLUSD positive supply voltage allows adjustment output common mode level from -1.2V PLUSD output compatibility) +1.2V PLUSD 2.4V LVDS output compatibility). Therefore, single-ended output voltages vary approximately between -0.8V -1.625V, (outputs unterminated), around -1.2V common mode voltage.
2144D-BDC-03/05
Three possible line driving back-termination scenarios proposed (assuming VPLUSD 0V): impedance transmission lines, differentially terminated (Figure 6-6): Each output voltage varies between -1.42V (respectively +1.4V +1V), leading ±0.41V 0.825V differential, around -1.21V (respectively +1.21V) common mode VPLUSD (respectively 2.4V). impedance transmission lines, differentially termination (Figure 6-7): Each output voltage varies between -1.02V -1.35V (respectively +1.38V +1.05V), leading ±0.33V differential, around -1.18V (respectively +1.21V) common mode VPLUSD (respectively 2.4V). impedance open transmission lines (Figure 6-8): Each output voltage varies between -1.6V -0.8V (respectively +0.8V +1.6V), which true levels, leading ±0.8V 1.6V differential, around -1.2V (respectively +1.2V) common mode VPLUSD (respectively 2.4V). Therefore, possible drive directly high input impedance storing registers, without terminating transmission lines. time domain, that means that incident wave will reflect transmission line output travel back generator (i.e.: data output buffer). buffer output impedance back reflection will occur.
Note: This longer true transmission line used, latter matching buffer output impedance.
Each differential output termination length must kept identical. recommended decouple midpoint differential termination with capacitor avoid common mode perturbation case slight mismatch differential output line lengths. large mismatches (keep differential line lengths will lead switching currents flowing into decoupling capacitor leading switching ground noise. differential output voltage levels termination) standard voltage levels, however possible drive standard logic circuitry like ECLinPS logic line from Freescale®. sampling rates exceeding GSPS, difficult trigger Acquisition System with digital outputs. becomes necessary regenerate digital data Data Ready means external amplifiers, order able test TS8388B optimum performance conditions.
TS8388B
2144D-BDC-03/05
TS8388B
6.6.1 Differential Output Loading Configurations (Levels Compatibility) Differential Output: Terminated
VPLUSD -0.8V -1V/-1.41V
Figure 6-6.
Differential output: +0.41V 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
-1.41V/-1V
Figure 6-7.
Differential Output: Terminated
VPLUSD -0.8V -1.02V/-1.35V
Differential output: +0.33V 0.660V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
-1.35V/-1.02V
2144D-BDC-03/05
Figure 6-8.
Differential Output: Open Loaded
VPLUSD -0.8V -0.8V/-1.6V
Differential output: +0.8V 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
-1.6V/-0.8V
6.6.2
Differential Output Loading Configurations (Levels LVDS Compatibility) Differential Output: Terminated
VPLUSD 2.4V 1.6V 1.4V/0.99V
Figure 6-9.
Differential output: +0.41V 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
0.99V/1.4V
Figure 6-10. Differential Output: Terminated
VPLUSD 2.4V 1.6V 1.38V/1.05V
Differential output: +0.33V 0.660V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
1.05V/1.38V
TS8388B
2144D-BDC-03/05
TS8388B
Figure 6-11. Differential Output: Open Loaded
VPLUSD 2.4V 1.6V 1.6V/0.8V
Differential output: +0.8V 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
0.8V/1.6V
Range
Range (OR, ORB) provided that goes logical high state when input exceeds positive full scale falls below negative full scale. When analog input exceeds positive full scale, digital output datas remain high logical state, with (OR, ORB) logical one. When analog input falls below negative full scale, digital outputs remain logical state, with (OR, ORB) logical again.
Gray Binary Output Data Format Select
TS8388B internal regeneration latches indecision (for inputs very close latches threshold) produce errors logic encoding circuitry leading large amplitude output errors. This fact that latches regenerating internal analog residues into logical states with finite voltage gain value (Av) within given positive amount time (t): exp((t)/), with positive feedback regeneration time constant. TS8388B been designed reducing probability occurrence such errors approximately 10-13 (targeted TS8388B GSPS). standard technique reducing amplitude such errors down consists outputting digital datas Gray code format. Though TS8388B been designed featuring Error Rate 10-13 with binary output format, possible user select between Binary Gray output data format, order reduce amplitude such errors when occurring, storing Gray output codes. Digital Datas format selection: BINARY output format GORB floating VCC. GRAY output format GORB connected ground (0V).
2144D-BDC-03/05
Diode
single used both DRRB input command junction monitoring. denomination DRRB/DIOD. Temperature monitoring Data Ready control DRRB possible simultaneously. (See "Principle Data Ready Signal Control DRRB Input Command" page Data Ready Reset input command). operating junction temperature must kept below 145°C, therefore adequate cooling system diode mounted transistor measured value versus junction temperature given below. Figure 6-12. Diode
1000 (mV) Junction temperature (°C)
TS8388B
2144D-BDC-03/05
TS8388B
6.10 Gain Control
gain adjustable means (input impedance parallel with pF). gain adjust transfer function given below. Figure 6-13. Gain Control
1.20 1.15 1.10 Gain 1.05 1.00 0.95 0.90 0.85 0.80 -500
-400
-300
-200
-100
Vgain (command voltage) (mV)
Note:
more information, please refer document "DEMUX ADCs Application Notes".
2144D-BDC-03/05
Equivalent Input/Output Schematics
Figure 7-1. Equivalent Analog Input Circuit Protections
VCLAMP +2.4V
-0.8V -0.8V
-5.8V -5.8V
+1.65V
E21V E21V
VINB
capacitance 5.8V
capacitance
-1.55V
5.8V
0.8V
0.8V
E21G
E21G
Note:
protection equivalent capacitance
Figure 7-2.
Equivalent Analog Clock Input Circuit Protections
+0.8V
-5.8V -0.8V
-5.8V
-5.8V
-5.8V -5.8V E31V
capacitance
E31V
CLKB
capacitance
5.8V
5.8V
0.8V 0.8V
E21G
E21G
Note:
protection equivalent capacitance
TS8388B
2144D-BDC-03/05
TS8388B
Figure 7-3. Equivalent Data Output Buffer Circuit Protections
VPLUSD 2.4V
-5.8V
-5.8V
E01V
E01V
OUTB
5.8V capacitance 0.8V
5.8V capacitance 0.8V
0.8V
0.8V
E21GA
DVEE
Note:
protection equivalent capacitance
Figure 7-4.
Gain Adjust Equivalent Analog Input Circuit Protections
-0.8V
+0.8V
NP1032C2
-5.8V
E22V
capacitance
0.8V
0.8V
5.8V
E22GA
Note:
protection equivalent capacitance
2144D-BDC-03/05
Figure 7-5.
GORB Equivalent Input Schematic Protections GORB: Gray Binary Select Input; Floating Tied Binary
-0.8V -0.8V -5.8V
E21VA
GORB
capacitance
5.8V
5.8V 5.8V
E31G
Note:
protection equivalent capacitance
Figure 7-6.
DRRB Equivalent Input Schematic Protections Actual Protection Range: 6.6V above VEE, fact stress above clipped diode used monitoring
GND=0V
NP1032C2
DRRB
-1.3V capacitance
-2.6V 5.8V
0.8V
E21G
Note:
protection equivalent capacitance
TS8388B
2144D-BDC-03/05
TS8388B
TSEV8388B: Device Evaluation Board
complete specification, separate TSEV8388B document.
General Description
TSEV8388B Evaluation Board (EB) board which been designed order facilitate evaluation characterization TS8388B device full power bandwidth GSPS military temperature range. high speed TS8388B requires careful attention circuit design layout achieve optimal performance. This four metal layer board with internal ground plane adequate functions order allow quick simple evaluation TS8388B performances over temperature range. TSEV8388B Evaluation Board very straightforward only implements TS8388B ADC, connectors input/output accesses 2.54 pitch connector compatible with high speed acquisition system probes. board also implements de-embedding fixture order facilitate evaluation high frequency insertion loss input microstrip lines, junction temperature measurement setting. board constituted sandwich dielectric layers, featuring insertion loss enhanced thermal characteristics operation high frequency domain extended temperature range. board dimensions board comes fully assembled tested, with TS8388B installed.
2144D-BDC-03/05
8.2.1
CBGA68 Thermal Moisture Characteristics
Thermal Resistance from Junction Ambient: RTHJA following table lists converter thermal performance parameters device itself, with external heatsink added. Table 8-1. Thermal Resitance
flow (m/s) Estimated thermal resistance (°C/W) 35.8 30.8 27.4 24.9 21.5 19.3 17.7
Figure 8-1.
Thermal Resistance from Junction Ambient: RTHJA
RTHJA (°C/W)
flow (m/s)
8.2.2
Thermal Resistance from Junction Case: RTHJC Typical value Rthjc given 6.7°C/W (8°C/W max). This value does include thermal contact resistance between package external component (heatsink PCBoard). example, 2.0°C/W taken thermal grease.
TS8388B
2144D-BDC-03/05
TS8388B
8.2.3 CBGA68 Board Assembly with External Heasink recommended external heatsink PCBoard special design. Cooling system efficiency monitored using Temperature Sensing Diode, integrated device. Figure 8-2. CBGA68 Board Assembly
50.5
24.2
20.2 32.5
Board
8.2.4
Moisture Characteristics This device sensitive moisture (MSL3 according JEDEC standard): Shelf life sealed bag: months <40°C <90% relative humidity (RH). After this opened, devices that will subjected infrared reflow, vapor-phase reflow, equivalent processing (peak package body temperature 220°C) must mounted within hours factory conditions 30°C/60% stored Devices require baking, before mounting, Humidity Indicator Card >20% when read 23°C ±5°C. baking required, devices baked for: hours 40°C +5°C/-0°C low-temperature device containers, hours 125°C ±5°C high temperature device containers.
2144D-BDC-03/05
Nominal CQFP68 Thermal Characteristics
Although power dissipation this performance, heat sink mandatory. user will find some advice this topics below.
8.3.1
Thermal Resistance from Junction Ambient: RTHJA following table lists converter thermal performance parameters, with without heatsink. following measurements, heatsink been used (see Figure page 45). Table 8-2. Thermal Resitance
Thermal Resistance (°C/W) CQFP68 Board Estimated Without Heatsink Targeted With Heatsink(1)
Flow (m/s) Note:
23.5 Heatsink glued backside package screwed pressed with thermal grease.
Figure 8-3.
Thermal Resistance from Junction Ambient: Rthja
RTHJA (°C/W) With heatsink
Without heatsink
flow (m/s)
TS8388B
2144D-BDC-03/05
TS8388B
8.3.2 Thermal Resistance from Junction Case: RTHJC Typical value Rthjc given 4.75°C/W. CQFP68 Board Assembly CQFP68 Board Assembly with External Heatsink
28.96 24.13 Printed circuit Aluminum heatsink 15.0 Interface: Af-filled epoxy thermal conductive grease max.
8.3.3
Figure 8-4.
16.0
50.0
2144D-BDC-03/05
8.4.1
Enhanced CQFP68 Thermal Characteristics
Enhanced CQFP68 CQFP68 been modified, order improve thermal characteristics: heatspreader been added bottom package. been electrically isolated with substrate.
8.4.2
Thermal Resistance from Junction Case: RTHJC Typical value Rthjc given 1.56°C/W. This value does include thermal contact resistance between package external component (heatsink PCBoard). example, 2.0°C/W taken thermal grease.
8.4.3
Heatsink recommended external heatsink, PCBoard special design. stand been calculated permit simultaneous soldering leads heatspreader with solder paste. Figure 8-5. Enhanced CQFP68 Suggested Assembly
28.78 24.13 Printed circuit board
heatspreader
Thermal
Solid ground plane
Cooling system efficiency monitored using Temperature Sensing Diode, integrated device.
TS8388B
2144D-BDC-03/05
TS8388B
8.5.1 8.5.1.1
Definitions
Definition Terms (BER) Error Rate Probability exceed specified error threshold sample. error code code that differs more than from correct code. (FPBW) Full Power Input Bandwidth Analog input frequency which fundamental component digitally reconstructed output fallen with respect frequency value (determined analysis) input Full Scale. (SINAD) Signal Noise Distortion Ratio Ratio expressed signal amplitude, below Full Scale, other spectral components, including harmonics except (SNR) Signal Noise Ratio Ratio expressed signal amplitude, below Full Scale, other spectral components excluding five first harmonics. (THD) Total Harmonic Distorsion Ratio expressed first five harmonic components, value measured fundamental spectral component. (SFDR) Spurious Free Dynamic Range Ratio expressed signal amplitude, below Full Scale, value next highest spectral component (peak spurious spectral component). SFDR parameter selecting converter used frequency domain application (Radar systems, digital receiver, network analyzer, etc.). reported (i.e.: degrades signal levels lowered), dBFS (i.e.: always related back converter full scale). (ENOB) Effective Number Bits
8.5.1.2
8.5.1.3
8.5.1.4
8.5.1.5
8.5.1.6
8.5.1.7
ENOB
SINAD 1.76 (A/V/2) 6.02
Where actual input amplitude full scale range under test. 8.5.1.8 (DNL) Differential Linearity Differential Linearity output code difference between measured step size code ideal step size. expressed LSBs. maximum value (i). error specification less than guarantees that there missing output codes that transfer function monotonic. (INL) Integral Linearity Integral Linearity output code difference between measured input voltage which transition occurs ideal value this transition. expressed LSBs, maximum value |INL (i)|.
8.5.1.9
2144D-BDC-03/05
8.5.1.10
(DG) Differential Gain peak gain variation percent) five different levels signal Full Scale peak peak amplitude. (TBC). (DP) Differential Phase Peak Phase variation degrees) five different levels signal Full Scale peak peak amplitude. (TBC). (TA) Aperture Delay Delay between rising edge differential clock inputs (CLK, CLKB) (zero crossing point), time which (VIN, VINB) sampled. (JITTER) Aperture Uncertainty Sample sample variation aperture delay. voltage error jitter depends slew rate signal sampling point. (TS) Settling Time Time delay achieve 0.2% accuracy converter output when Full Scale step function applied differential analog input. (ORT) Overvoltage Recovery Time Time recover 0.2% accuracy output, after 150% full scale step applied input reduced midscale. (TOD) Digital Data Output Delay Delay from falling edge differential clock inputs (CLK, CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load. (TD1) Time Delay from Data Data Ready Time delay from Data transition Data ready. (TD2) Time Delay from Data Ready Data General expression with encoding clock period. (TC) Encoding Clock Period Minimum clock pulse width (high) Minimum clock pulse width (low)
8.5.1.11
8.5.1.12
8.5.1.13
8.5.1.14
8.5.1.15
8.5.1.16
8.5.1.17
8.5.1.18
8.5.1.19
8.5.1.20
(TPD) Pipeline Delay Number clock cycles between sampling edge input data associated output data being made available, (not taking account TOD). TS8388B clock periods. (TRDR) Data Ready Reset Delay Delay between falling edge Data Ready output asynchronous Reset signal (DDRB) reset digital zero transition Data Ready output signal (DR).
8.5.1.21
TS8388B
2144D-BDC-03/05
TS8388B
8.5.1.22 (TR) Rise Time Time delay output DATA signals rize from delta between level high level. (TF) Fall Time Time delay output DATA signals fall from delta between level high level. (PSRR) Power Supply Rejection Ratio Ratio input offset variation change power supply voltage. (NRZ) Return Zero When input signal larger than upper bound input range, output code identical maximum code Range logic one. When input signal smaller than lower bound input range, output code identical minimum code, range logic one. assumed that input signal amplitude remains within absolute maximum ratings). (IMD) InterModulation Distortion tones intermodulation distortion (IMD) rejection ratio either input tone worst third order intermodulation products. input tones levels Full Scale. (NPR) Noise Power Ratio measured characterize performance response broad bandwidth signals. When using notch-filtered broadband white-noise generator input under test, Noise Power Ratio defined ratio average out-of-notch average in-notch power spectral density magnitudes spectrum output sample test.
8.5.1.23
8.5.1.24
8.5.1.25
8.5.1.26
8.5.1.27
2144D-BDC-03/05
Ordering Information
Table 9-1.
Part Number JTS8388B-1V1B JTS8388B-1V2B TS8388BCF TS8388BVF TS8388BMF TS8388BMF TS8388BMF TS8388BCFS TS8388BVFS TS8388BMFS TS8388BMFS TS8388BMFS
Ordering Information
Package CQFP CQFP CQFP CQFP CQFP CQFP with heatspreader CQFP with heatspreader CQFP with heatspreader CQFP with heatspreader CQFP with heatspreader Temperature Range Ambient Ambient High temperature 125°C) grade 90°C grade -40°C 110°C grade -55°C 125°C grade -55°C 125°C grade -55°C 125°C grade 90°C grade -40°C 110°C grade -55°C 125°C grade -55°C 125°C grade -55°C 125°C Screening Visual inspection Visual inspection Standard Standard Standard Mil-PRF-38535, level Standard temperatures test (min, ambient, max) Standard Standard Standard Mil-PRF-38535, level Standard temperatures test (min, ambient, max) ESA/SCC9000 Screening ESA/SCC qualified Level selection Acceptance Test ESA/SCC9000 Screening ESA/SCC qualified Level selection Acceptance Test ESA/SCC9000 Screening ESA/SCC qualified Level selection Acceptance Test ESA/SCC9000 Screening ESA/SCC qualified Level selection Acceptance Test DSCC 5962-0050401QXC DSCC 5962-0050401QYC Comments REQUEST ONLY (Please contact Marketing) REQUEST ONLY (Please contact Marketing)
TS8388BMFS9NB2
CQFP with heatspreader
grade -55°C 125°C
TS8388BMFS9NB3
CQFP with heatspreader
grade -55°C 125°C
TS8388BMFS9NC2
CQFP with heatspreader
grade -55°C 125°C
TS8388BMFS9NC3
CQFP with heatspreader
grade -55°C 125°C
TS8388B
2144D-BDC-03/05
TS8388B
Table 9-1.
Part Number TS8388BCGL TS8388BVGL TSEV8388BF
Ordering Information (Continued)
Package CBGA CBGA CQFP Temperature Range grade 90°C grade -40°C 110°C Ambient Screening Standard Standard Prototype Evaluation board (delivered with heatsink) Evaluation board with digital receivers (delivered with heatsink) Evaluation board (delivered with heatsink) Evaluation board with digital receivers (delivered with heatsink) Comments
TSEV8388BFZA2
CQFP
Ambient
Prototype
TSEV8388BGL
CBGA
Ambient
Prototype
TSEV8388BGLZA2
CBGA
Ambient
Prototype
2144D-BDC-03/05
CBGA68 Capacitors Resistors Implant
TS8388BGL Capacitors Resistors Implant
Figure 9-1.
DVEE
GAIN
VINB
CLKB
Only on-package marking Electrically isolated
Note:
discrete components 0603 size (1.6 mm).
TS8388B
2144D-BDC-03/05
GORB
TS8388B
Outline Descriptions
Package Dimension Pins CBGA
Figure 9-2.
CBGA package. AL203 substrate. Package design. Corner balls (x4) connected (mechanical ball). Balls 1.27 pitch 11x11 grid.
0.20
side with soldered devices
(using solder Sn/Pb 63/37)
0.95 Balls side
View balls side
1.27
15.00 0.15 7.84
Balls Sn/Pb 63/37 AI203 substrate
7.84
AI203 Ceramic Cap. Glued embedded substrate
Ball Index other side 1.00
1.45 0.12 15.00 0.15
0.80 0.10
0.40 (Position array balls edges 0.15 (Position balls within array)
1.27
Detail ball
0.63 0.10 units
0.15
2144D-BDC-03/05
Outline Dimensions
Figure 9-3. Package Dimension 68-lead Ceramic Quad Flat Pack (CQFP)
VIEW
20.32 index 0.050 1.27
0.005
0.58 0.05 0.023 0.002
24.13 0.152 0.950 0.006 0.005 0.010 0.13 0.25 0.20 0.075 0.008
CQFP
0.950 0.006 24.13 0.152 1.133 1.147 28.78 29.13
0.004
3.43 0.135
0.46 0.88 0.018 0.035
0.027 0.037 0.70 0.95
TS8388B
2144D-BDC-03/05
28.78 29.13 1.133 1.147
TS8388B
Figure 9-4. Package Dimension 68-lead Enhanced CQFP with Heatspreder
VIEW
20.32 index 0.050 1.27
0.005
0.58 0.05 0.023 0.002
24.13 0.152 0.950 0.006 0.978 0.0385 0.005 0.010 0.13 0.25 0.787 0.0310
CQFP
0.950 0.006 24.13 0.152 1.133 1.147 28.78 29.13 0.18 0.13 0.007 0.005
0.51 0.13 0.020 0.005
0.027 0.037 0.70 0.95
28.78 29.13 1.133 1.147
2144D-BDC-03/05
Datasheet Status Description
Table 10-1.
Datasheet Status
Validity This datasheet contains target goal specifications discussion with customer application validation. This datasheet contains target goal specifications product development. This datasheet contains preliminary data. Additional data published later; could include simulation results. This datasheet contains also characterization results. This datasheet contains final product specification. Before design phase
Datasheet Status Objective specification
Target specification
Valid during design phase
Preliminary specification -site Preliminary specification -site Product specification Limiting Values
Valid before characterization phase Valid before industrialization phase Valid production purposes
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application Information Where application information given, advisory does form part specification.
10.1
Life Support Applications
These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Atmel customers using selling these products such applications their risk agree fully indemnify Atmel damages resulting from such improper sale.
TS8388B
2144D-BDC-03/05
Atmel Corporation
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906, Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route Arsenaux Case Postale CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Chantrerie 70602 44306 Nantes Cedex France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue Rochepleine 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906, Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: information this document provided connection with Atmel products. license, express implied, estoppel otherwise, intellectual property right granted this document connection with sale Atmel products. EXCEPT FORTH ATMEL'S TERMS CONDITIONS SALE LOCATED ATMEL'S SITE, ATMEL ASSUMES LIABILITY WHATSOEVER DISCLAIMS EXPRESS, IMPLIED STATUTORY WARRANTY RELATING PRODUCTS INCLUDING, LIMITED IMPLIED WARRANTY MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, NON-INFRINGEMENT. EVENT SHALL ATMEL LIABLE DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES LOSS PROFITS, BUSINESS INTERRUPTION, LOSS INFORMATION) ARISING INABILITY THIS DOCUMENT, EVEN ATMEL BEEN ADVISED POSSIBILITY SUCH DAMAGES. Atmel makes representations warranties with respect accuracy completeness contents this document reserves right make changes specifications product descriptions time without notice. Atmel does make commitment update information contained herein. Atmel's products intended, authorized, warranted components applications intended support sustain life.
Atmel Corporation 2005. rights reserved. Atmel logo combinations thereof registered trademarks Atmel Corporation subsidiaries. Freescale® registered trademark Freescale Company. Other terms product names trademarks others.
Printed recycled paper.
2144D-BDC-03/05

Other recent searches


SPS-93160MWG - SPS-93160MWG   SPS-93160MWG Datasheet
SPS-2340-CXX0G - SPS-2340-CXX0G   SPS-2340-CXX0G Datasheet
RF551011b - RF551011b   RF551011b Datasheet
PALCE20RA10 - PALCE20RA10   PALCE20RA10 Datasheet
HDSP-4820 - HDSP-4820   HDSP-4820 Datasheet
-4830 - -4830   -4830 Datasheet
-4840 - -4840   -4840 Datasheet
2SK3081 - 2SK3081   2SK3081 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive