Section ATL35 Series Description .1-1 Design .1-3 Design Flow Too

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ATL35 Series
Section ATL35 Series
Description .1-1 Design .1-3 Design Flow Tools.1-3 Definition Requirements.1-5 Design Options .1-5 Logic Synthesis .1-5 AVR® 8-bit RISC Microcontroller Core .1-6 ARM7TDMI® 32-bit RISC Microprocessor Core .1-7 OakDSPCore® Digital Signal Processing Core .1-8 Teak® PalmDSPCore® Digital Signal Processing Cores .1-8 Macro Cores.1-6
1.5.1 1.6.1 1.6.2 1.6.3 1.6.4
ATL35 Series Cell Library .1-9 Testability Techniques .1-19 Advanced Packaging .1-20
Section Design.
Design Overview .2-1 Design Flow .2-2 Kickoff Meeting: First Milestone.2-4 Underlayer Acceptance: Second Milestone.2-4 Database Acceptance: Third Milestone.2-4 Final Design Review (FDR): Fourth Milestone .2-5 Prototype Delivery: Fifth Milestone.2-5 Logic Synthesis .2-6 ASIC Design Translation .2-6 Preroute Clock Tree Estimation.2-7 Clock Tree Synthesis.2-7 Clock Tree Verification .2-7
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.3.1 2.3.2 2.4.1 2.4.2 2.4.3
Design, Translation Conversion Approaches.2-6
Clock Trees .2-6
Design Testability (DFT) .2-8 Using Synopsys Compiler TetraMax.2-10 Test Generation.2-10
2.6.1
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2.6.2 2.6.3 2.6.4 2.7.1
Techniques .2-10 Structured Scan Techniques .2-11 Boundary Scan .2-12 Test Access Port (TAP) Architecture.2-13
JTAG/IEEE® 1149.1.2-13
Section Test.
ASIC Verification .3-1 Methodology .3-1 Vector Limits.3-3 Internal Serial Scan Vectors .3-3 Parametric Test Vector.3-3 Delay Path Test Vector (optional).3-3 JTAG Test Vectors .3-3 Test Vector Requirements.3-4 Parametric Testing .3-6 Test Methodology Options.3-7 Delay Path Measurement .3-8 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.2.1 3.3.1 3.4.1 3.4.2
Functional Test Vectors .3-4 ASIC Testers.3-5 Static Path Analysis .3-7
Conclusion .3-8
Section Packaging
Introduction .4-1
Section Quality Reliability Assurance
Executive Decision .5-1 Continuous Improvement Quality System.5-1 Atmel's Quality System .5-3 Reliability Assurance.5-4 Failure Rates .5-4 Bathtub Curve .5-4 Atmel Reliability Program .5-5 Design Quality Reliability.5-5
5.4.1 5.4.2 5.4.3 5.4.4
Failure Analysis Capability .5-6 CMOS Reliability Data .5-7 Gate Oxide Integrity.5-7
5.6.1
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5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9
Electromigration.5-7 Carriers .5-7 CMOS Latch-up Immunity .5-7 Construction Analysis .5-7 Sensitivity .5-7 CMOS Reliability .5-7 Statistical Process Control (SPC).5-7 Statistical Design Experiments (DOE) .5-8
5.6.10 Payoff .5-8
Section Military Aerospace
Designing High Reliability .6-1 Gate Array .6-2 CLASS .6-3 6.1.1 6.1.2
Section Cell Library.
Cell Library .7-1 Cell Parameters.7-1 Fanout .7-1 Timing Estimation .7-1 7.1.1 7.1.2 7.1.3
Gate Count Estimation .7-1
Section ATL35 Buffer Cell Library
Buffer Naming Convention .8-1 Site: Subsections.8-1 Input Buffers .8-2 Output Buffers .8-2 Bidirectional Buffers.8-2 Pullup, Pulldown Terminators.8-3 Keeper Terminator.8-3 Pullup, Pulldown Keeper Terminators .8-3 Oscillator Buffers .8-4 PX#L, PX#R Buffers .8-4 Buffer Characterization Data .8-5 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.2.1
Buffer Description.8-5 (Universal Serial Bus) .8-6 Phase-Locked Loops .8-6 Overview .8-6
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8.5.1 8.6.1 8.6.2
Functional Description.8-8 Clock Frequency Synthesis .8-8 Zero Delay Buffer .8-9
Applications .8-8
Design Requirements Recommendations .8-9 Choosing .8-10 Testability .8-10 Bypassing Clock .8-10 Testing Charge Pump .8-11 CP/PFD Test .8-11 CP/PFD Test .8-12 Testing .8-12 ATL35 Specified Phase-Locked Loops .8-12 Characteristics (Hspice Results) .8-13 Charge Pump Characteristics.8-14
8.8.1 8.8.2 8.8.3 8.8.4 8.8.5 8.8.6 8.8.7 8.8.8 8.8.9
Section Memory SRAMs.
Compiled Gate-level SRAMs .9-1 PRAM48X4.9-4 PRAM64X4.9-5 Compiled Personalization SRAMs.9-6 Conditions.9-6 Read Timing*.9-6 Compiled Personalization SRAMs.9-7 Write Cycle Propagation Delay* .9-7 Compiled Personalization SRAMs.9-8 Compiled Personalization PRAMR1W1 .9-9 Write Cycle Timing .9-9 Write Cycle Propagation Delay* .9-9 Compiled Personalization PRAMR1W1 .9-10 Write Cycle Propagation Delay* .9-10 Compiled Personalization PRAMR1W1 .9-11 9.1.1 9.1.2 9.2.1 9.2.2 9.2.3 9.3.1 9.3.2 9.4.1 9.5.1 9.5.2 9.5.3 9.6.1 9.6.2 9.7.1
Single-port Operation 0.35m Best Case Process .9-6
Single-port Operation 0.35m Typical Case Process .9-7
Single-port Operation 0.35m Worst Case Process .9-8 Two-port Operation 0.35m Best Case Process .9-9
Two-port Operation 0.35m Typical Case Process .9-10
Two-port Operation 0.35m Worst Case Process .9-11
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9.7.2 9.7.3
Write Cycle Timing .9-11 Write Cycle Propagation Delay .9-11
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Section ATL35 Series
Description
ATL35 Series ASIC family fabricated 0.35µ CMOS process with four levels metal. This family features arrays with million routable gates pins. high density high count capabilities ATL35 family, coupled with ability embedded microprocessor cores, engines memory same silicon, make ATL35 series ASICs ideal choice system-level integration. Figure 1-1. ATL35 Gate Array ASIC
Figure 1-2. ATL35 Embedded Array ASIC
Standard Gate Array Architecture
Analog
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Table 1-1. ATL35 Array Organization
Device Number ATL35/44 ATL35/68 ATL35/84 ATL35/100 ATL35/120 ATL35/132 ATL35/144 ATL35/160 ATL35/184 ATL35/208 ATL35/228 ATL35/256 ATL35/304 ATL35/352 ATL35/388 ATL35/432 ATL35/484 ATL35/540 ATL35/600 ATL35/700 ATL35/800 ATL35/900 ATL35/976 Notes: Routable Gates(1) 4,195 13,230 22,200 33,480 47,839 59,185 71,737 90,514 121,877 150,085 182,880 233,774 334,044 425,958 520,695 652,421 768,033 964,078 1,196,371 1,642,242 1,999,526 2,542,995 2,767,931 Routable Gates(1) 3,729 11,760 19,734 29,760 42,211 52,222 63,298 79,866 107,538 131,324 160,020 204,552 292,288 369,164 451,269 565,431 658,314 826,353 1,025,460 1,407,636 1,691,906 2,151,765 2,306,609 Available Routing Sites(2) 6,216 19,600 32,890 49,600 75,042 92,840 112,530 141,984 191,180 250,142 304,800 389,624 556,740 757,260 925,680 1,159,860 1,462,920 1,836,340 2,278,802 3,128,080 4,101,592 5,216,400 6,150,958 Count Count Gate Speed(3)
gate NAND2 Routing site transistors Nominal 2-input NAND gate 3.3V
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Design
Atmel supports several major software systems design with complete cell libraries, well utilities netlist verification, test vector verification accurate delay simulations. Table 1-2. Design Systems Supported
System Cadence® Design Systems, Inc. Tools Opus Schematic Layout NC-Verilog® Verilog Simulator Pearl® Static Path Verilog-XL® Verilog Simulator BuildGates Synthesis (Ambit) ModelSim® Verilog VHDL (VITAL) Simulator Leonardo® Spectrum® Logic Synthesis Design Compiler® Synthesis Compiler 1-Pass Test Synthesis Compiler Boundary Scan Synthesis TetraMax® Automatic Test Pattern Generation PrimeTime® Static Path VCS® Verilog Simulator Floorplan ManagerDebussy® First Encounter® Version 4.46 3.3-s008 4.3-s095 3.3-s006 4.0-p003 5.5e 2001.1d 01.01-SP1 01.08-SP1 01.08-SP1 01.08 01.08-SP1 01.08-SP1 v2001.2.3
Mentor Graphics® Synopsys®
NovasSoftware, Inc. Silicon Perspective®
Design Flow Tools
Atmel's ASIC design flow structured allow designer consolidate greatest number system components onto same silicon chip, using widely available thirdparty design tools. Atmel's cell library reflects silicon performance over extremes temperature, voltage process, includes effects metal loading, interlevel capacitance, edge rise fall times. design flow includes clock tree synthesis customer-specified skew latency goals. extraction performed final design database incorporated into timing analysis. ASIC Design Flow, shown page provides pictorial description typical interaction between Atmel's design staff customer. Atmel will deliver design kits support customer's synthesis, verification, floorplanning scan insertion activities. Leading-edge tools from vendors such Synopsys Cadence fully supported design flow. case embedded array design, Atmel will conduct design review with customer define partition embedded array ASIC define location memory blocks and/or cores underlayer layout model created. Following database acceptance, automated test pattern generation (ATPG) performed, required, scan paths using Synopsys tools; design routed; postroute data extracted. After post-route verification final design review, design taped fabrication.
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Table 1-3. Design Flow
Deliver Design
Kickoff Meeting
Embedded Array
Define Underlayer
Synthesis/ Design Entry
Scan/JTAG
Simulation/ Static Path
Floorplan
Embedded Array (Preliminary Netlist)
Create Underlayer
Database Handoff
Tape Underlayer
Database Acceptance
Fabricate Underlayer
Place Route/ Clock Tree
Verification/ Resimulation
Final Design Review Standard Cell Embedded/Gate Array
Tape Full Mask
Tape Metal Masks
Fabricate
Fabricate Personality
Customer Atmel Joint
Proto Assembly Test Rev. 2.2-03/02
Proto Shipment
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Definition Requirements
corner pads reserved Power Ground only. other pads fully programmable Input, Output, Bidirectional, Power Ground. When implementing design with compliant buffers, appropriate number sites must reserved VDD5 pins, which used distribute power compliant buffers.
1.5.1
Design Options
Logic Synthesis Atmel accept designs Verilog VHDL formats. Atmel fully supports Synopsys Verilog VHDL simulation well synthesis. formats, Verilog VHDL, Atmel's preferred format ASIC design Verilog.
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1.6.1
Macro Cores
AVR® 8-bit RISC RISC microcontroller true 8-bit RISC architecture, ideally suited Microcontroller Core embedded control applications. offered gate level, synthesizable macro core ATL35 family. supports powerful instructions. prefetches instruction during prior instruction execution, enabling execution instruction clock cycle. Fast Access RISC register file consists general purpose working registers. These registers eliminate data transfer delay traditional program code intensive accumulator architectures. incorporate program memory (ROM) data memory (SRAM). Among peripheral options offered are: UART, 8-bit timer/counter, 16-bit timer/counter, programmable watchdog timer SPI. Figure 1-3. 8-bit RISC Microcontroller Core
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8-BIT DATA
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1.6.2
ARM7TDMI® 32-bit RISC Microprocessor Core
ARM7TDMI powerful 32-bit processor offered hard macro core ATL35 family. ARM7TDMI member Advanced RISC Machines (ARM®) family general purpose 32-bit microprocessors, which offer high performance with very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers (CISC). This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective chip. Pipelining employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. memory interface been designed allow performance potential realized without incurring high costs memory system. Speed-critical control signals pipelined allow system control functions implemented standard lowpower logic, these control signals facilitate exploitation fast local access modes offered industry standard SRAMs. ARM7TDMI core interfaces several optional peripheral macros. Among peripheral options offered real-time clock, peripheral data controller, USART, external interface, interrupt controller, timer counter watchdog timer. Figure 1-4. ARM7TDMI 32-bit RISC Microprocessor Core
Address Incrementor
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1.6.3
OakDSPCore® Digital Signal Processing Core
Atmel's hard macro OakDSPCore 16-bit, general-purpose, low-power, low-voltage high-speed Digital Signal Processor (DSP). designed mid-to-high-end telecommunications consumer electronics applications, where low-power portability major requirements. Among applications supported digital cellular telephones, fast modems, advanced facsimile machines hard disk drives. available core Atmel's ASIC cell library, utilized engine DSP-based ASIC. specified with several levels modularity SRAM, blocks, allowing efficient DSP-based ASIC development. aimed achieving best cost-performance factor given (small) silicon area. element system-on-chip, takes into account such requirements program size, data memory size, glue logic power management. core consists three main execution units operating parallel: Computation/Bit-Manipulation Unit (CBU), Data Addressing Arithmetic Unit (DAAU) Program Control Unit (PCU). core also contains SRAM addressing units, Program Control Logic (PCL). other peripheral blocks that application specific defined part user-specific logic implemented around core same silicon die. enhanced general microprocessor functions meet most application requirements. programming model instruction aimed straightforward generation efficient compact code.
1.6.4
Teak® PalmDSPCore® Digital Signal Processing Cores
Teak Palm synthesizable dual-MAC cores from Group, Inc. Teak fixed-point 16-bit DSP, whereas Palm configured 16-bit, 20-bit 24-bit fixed-point math. Both cores optimized high MIPs with performance targeted handling filtering, voice compression/decompression modem functions portable wireless applications such digital cellular. Hardware support also provided implementing Viterbi forward error correction. Teak Palm cores both have comprehensive suite development tools that easy learn intended support rapid code development. compiler that supports in-line assembly language provides language extensions enhance code optimization provided. assembler linker also provided. Both emulation (using test silicon) source-level simulation assembly language enhance software verification.
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ATL35 Series Cell Library
Atmel's ATL35 Series ASICs make extensive library cell structures, including logic cells, buffers inverters, multiplexers, decoders options. Soft macros also available. ATL35 Series Phase Locked Loop (PLL) operates frequencies with minimal phase error jitter, making ideal frequency synthesis highspeed, on-chip clocks chip-to-chip synchronization. Output buffers programmable meet voltage current requirements @3.3V. These cells characterized SPICE modeling transistor level, with performance verified manufactured test silicon. Characterization performed over rated temperature voltage ranges ensure that simulation accurately predicts performance finished product.
Table 1-4. Cell Index
Cell Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI222 AOI2223 AOI2223H AOI222H AOI22H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF4T BUF8 BUF8T BUF12 Description 1-bit Full Adder with Buffered Outputs 2-input 2-input High Drive 3-input 3-input High Drive 4-input 4-input High Drive 5-input 2-input into 2-input 2-input ANDs into 2-input Three 2-input ANDs into 3-input Three 2-input ANDs into 3-input High Drive 2-input ANDs into 2-input High Drive 2-input into 2-input High Drive 2-input into 3-input Buffer Buffer Tristate Driver with Active-high Enable Tristate Driver with Active-low Enable Buffer Buffer Tristate Driver with Active-high Enable Buffer Tristate Driver with Active-high Enable Buffer Gate Count
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Table 1-4. Cell Index (Continued)
Cell Name BUF16 CLA7X DEC4 DEC4N DEC8N DFFH DFFBCPX DFFBSRX DFFC DFFCH DFFR DFFRQ DFFS DFFSR DLY1 DLY2 DLY3 DLY4 DSSC DSSBCPY DSSBR DSSBS DSSCH DSSR DSSS DSSSR HLD1 INV1 INV1D INV1Q INV1TQ INV2 INV2T Description Buffer 7-input Carry Lookahead Decoder Decoder with Active-low Enable Decoder with Active-low Enable Flip-flop Flip-flop High Drive Flip-flop with Asynchronous Clear Preset with Complementary Outputs Flip-flop with Asynchronous Reset with Complementary Outputs Flip-flop with Asynchronous Clear Flip-flop with Asynchronous Clear High Drive Flip-flop with Asynchronous Reset Quad Flip-flop with Asynchronous Reset Flip-flop with Asynchronous Flip-flop with Asynchronous Reset Delay Buffer Delay Buffer Delay Buffer Delay Buffer Scan Flip-flop Scan Flip-flop with Asynchronous Clear High Drive Scan Flip-flop with Clear Preset Scan Flip-flop with Reset Scan Flip-flop with Scan Flip-flop with Asynchronous Clear High Drive Scan Flip-flop with Reset Scan Flip-flop with Scan Flip-flop with Reset Hold Cell Inverter Dual Inverter Quad Inverter Quad Tristate Inverter with Active-high Enable Inverter Tristate Inverter with Active-high Enable Gate Count
1-10
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Table 1-4. Cell Index (Continued)
Cell Name INV3 INV4 INV8 JKFBCPX JKFC LATB LATBG LATBH LATIQ LATR LATS LATSR MUX2 MUX2H MUX2I MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H NAN4 Description Inverter Inverter Inverter Flip-flop Clear Preset Flip-flop with Asynchronous Clear Preset Complementary Outputs Flip-flop with Asynchronous Clear LATCH LATCH with Complementary Outputs LATCH with Complementary Outputs Inverted Gate Signal LATCH with High-drive Complementary Outputs Quad LATCH with Inverted Output LATCH with Reset LATCH with LATCH with Reset High Drive with Inverted Output with Inverted Output High Drive with Active-low Enable Quad with Active-low Enable Quad with Inverted Output with Inverted Output High Drive with Transmission Gate Data Inputs with Transmission Gate Data Inputs High Drive High Drive with Active-low Enable with Transmission Gate Data Inputs High Drive 2-input NAND Dual 2-input NAND 2-input NAND High Drive 3-input NAND 3-input NAND High Drive 4-input NAND Gate Count
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Table 1-4. Cell Index (Continued)
Cell Name NAN4H NAN5 NAN5H NAN5S NAN6 NAN6H NAN8 NAN8H NOR2 NOR2D NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR5S NOR8 OAI22 OAI222 OAI22224 OAI222H OAI22H OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H Description 4-input NAND High Drive 5-input NAND 5-input NAND High Drive 5-input NAND with 6-input NAND 6-input NAND High Drive 8-input NAND 8-input NAND High Drive 2-input Dual 2-input 2-input High Drive 3-input 3-input High Drive 4-input 4-input High Drive 5-input 5-input with 8-input 2-input into 2-input NAND 2-input into 2-input NAND Four 2-input into 4-input NAND 2-input into 2-input NAND High Drive 2-input into 2-input NAND High Drive 2-input into 3-input NAND 2-input 2-input High Drive 3-input 3-input High Drive 4-input 4-input High Drive 5-input 2-input Exclusive 2-input Exclusive High Drive 2-input Exclusive 2-input Exclusive High Drive Gate Count
1-12
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Table 1-5. 3.3V Buffer Cell Index
Cell Name PBATA100 PFDNOL PFDNOZ##L PFIPCI PFGTL PFGTLA PFICLK PFILVDSL PFILVDSLXR PFIVCOMPA PFIVREF PFOLVDS PFOLVDSH PFOZ## PFPECLL PFVSSCLEARA PFVSSCLEARC PFVSSCLEARD PICH PICI PICS PICSI PICK PLL5_100 PLL5_400 PLL4_80N PO## PO##F PO##S PUSB PVDDREG PX1L Description Bidirectional Buffer High-speed, Low-voltage Differential Output Pair Impedance Controlled, High-speed, Low-voltage Differential Output Pair Input Gunning Transceiver Logic Buffer Fast Output, Gunning Transceiver Logic Buffer Clock Amplifier Input Buffer Low-voltage, Differential Input Pair Low-voltage, Differential Input Pair, External Resistor Low-speed, Low-power Comparator Voltage Reference Low-voltage, Differential Output Pair Low-voltage, Differential Output Pair, High Drive Impedance Controlled Output, ohms Positive Output Pair Power-on Reset Power-on Reset, Higher Trip Point Power-on Reset, Lower Trip Point CMOS Input CMOS Input, High Drive Inverting CMOS Input CMOS Input with Schmitt Trigger Inverting CMOS Input with Schmitt Trigger CMOS Input Buffer with Selectable Hold Differential Input Optimized 20-100 Output, External Bias Optimized 100-400 Output, External Bias Optimized Output, Internal Bias Tristate Output Buffer; Fast Tristate Output Buffer, Slow Tristate Output Buffer, Universal Serial Interface Buffer Voltage Regulator Oscillator Frequency
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Table 1-5. 3.3V Buffer Cell Index (Continued)
Cell Name PX2L PX3L PX4L Description Oscillator Frequency Oscillator Frequency Oscillator Frequency
Table 1-6. 5.0V Tolerant Buffer Cell Index
Cell Name PBATA100 PFIPCIV PFGTL PFGTLA PFIVREF PFVSSCLEARB PFVSSCLEARC PFVSSCLEARD PICV PICSV PLL5_100 PLL5_400 PLL4_80N PO##V PO##FV PO##SV PX1L PX2L PX3L PX4L Description Tolerant Bidirectional Buffer Tolerant Input Gunning Transceiver Logic Buffer Fast Output, Gunning Transceiver Logic Buffer Voltage Reference Power-on Reset Power-on Reset, Higher Trip Point Power-on Reset, Lower Trip Point Tolerant CMOS Input Buffer Tolerant CMOS Input with Schmitt Trigger Optimized 20-100 Output; External Bias Optimized 100-400 Output; External Bias Optimized Output; Internal Bias Tolerant Tristate Output Buffer; Tolerant Fast Tristate Output Buffer; Tolerant Slow Tristate Output Buffer; Oscillator Frequency Oscillator Frequency Oscillator Frequency Oscillator Frequency
1-14
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Table 1-7. 5.0V Compliant Buffer Cell Index
Cell Name PFIPCIV5 PFGTL PFGTLA PFIVCOMPLS PFIVREF PFVSSCLEARB PFVSSCLEARC PFVSSCLEARD PICV5 PICSV5 PICKV5 PICSKV5 PLL5_100 PLL5_400 PLL4_80N PO##V5 PVDDREG PX1L PX2L PX3L PX4L Description Compliant Input Gunning Transceiver Logic Buffer Fast Output, Gunning Transceiver Logic Buffer Compliant Low-speed, Low-power Comparator Voltage Reference Power-on Reset Power-on Reset, Higher Trip Point Power-on Reset, Lower Trip Point Compliant CMOS Input Buffer Compliant CMOS Input with Schmitt Trigger Compliant CMOS Input Buffer with Selectable Hold Compliant CMOS Input Buffer with Schmitt Trigger Selectable Hold Optimized 20-100 Output; External Bias Optimized 100-400 Output; External Bias Optimized Output; Internal Bias Tolerant Tristate Output Buffer; Voltage Regulator Oscillator Frequency Oscillator Frequency Oscillator Frequency Oscillator Frequency
Table 1-8. Absolute Maximum Ratings1
Parameter Operating Ambient Temperature Storage Temperature Maximum Input Voltage: Inputs Tolerant/Compliant Maximum Operating Voltage (VDD) Maximum Operating Voltage (VDD5) Note: Rating -55°C +125°C -65°C +150°C 0.5V VDD5 0.5V 3.6V 5.5V
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
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Table 1-9. 2.5V Characteristics Applicable over recommended operating temperature voltage range unless otherwise noted.
Symbol Parameter Operating Temperature Supply Voltage High-level Input Current Buffer CMOS CMOS PO11 PO11 CMOS High-level Input Voltage CMOS Schmitt CMOS VHYS Low-level Input Voltage CMOS Schmitt Hysteresis High-level Output Voltage CMOS Schmitt PO11 PO11 (min) -500 (min) 0.7VDD 0.9VDD 0.1VDD VSS, (max), pull-up VOUT VDD, (max) VOUT VSS, (max) 0.7VDD 0.475VDD 0.7VDD 0.3VDD 0.325VDD 0.3VDD VSS, (max) VDD, (max) Test Condition Units
Low-level Input Current High-impedance State Output Current Output Short-circuit Current
Low-level Output Voltage
1-16
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Table 1-10. 3.3V Characteristics Applicable over recommended operating temperature voltage range unless otherwise noted.
Symbol Parameter Operating Temperature Supply Voltage High-level Input Current Buffer CMOS CMOS PO11 PO11 CMOS, LVTTL High-level Input Voltage CMOS/TTL-level Schmitt CMOS Low-level Input Voltage CMOS/TTL-level Schmitt VHYS Hysteresis High-level Output Voltage TTL-level Schmitt PO11 PO11 (min) -500 (min) 0.7VDD 0.9VDD 0.1VDD VSS, (max), pull-up VOUT VDD, (max) VOUT VSS, (max) 0.475VDD 0.325VDD VSS, (max) VDD, (max) Test Condition Units
Low-level Input Current High-impedance State Output Current Output Short-circuit Current
Low-level Output Voltage
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Table 1-11. 5.0V Characteristics Applicable over recommended operating temperature voltage range unless otherwise noted.
Symbol VDD5 Parameter Operating Temperature Supply Voltage Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current Buffer Tolerant Compliant CMOS CMOS PO11V PO11V PICV, PICV5 High-level Input Voltage CMOS/TTL-level Schmitt PICV, PICV5 Low-level Input Voltage CMOS/TTL-level Schmitt Hysteresis High-level Output Voltage Low-level Output Voltage CMOS/TTL-level Schmitt PO11V PO11V5 PO11V, PO11V5 -1.7 -1.7 0.7VDD 0.7VDD5 VDD, (max) VSS, (max) VSS, (max), pull VOUT VDD, (max) VOUT VSS, (max) 0.475VDD 0.5VDD 0.325VDD Test Condition Units
VHYS
Table 1-12. Buffer Characteristics
Symbol COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bidirectional Test Condition 3.3V 3.3V 3.3V Typical Units
1-18
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Testability Techniques
complex designs involving blocks memory and/or cores, careful attention must given design-for-test techniques. sheer size complex designs requires more efficient testability techniques. Combinations SCAN paths, multiplexed access memory and/or core blocks, built-in self-test logic addition functional test patterns) must employed provide both user Atmel with ability test finished product. example highly complex design could include clock management synthesis, microprocessor engine both, SRAM support microprocessor engine, glue logic support interconnectivity each these blocks. design each these blocks must take into consideration fact that manufactured device will tested high-performance digital tester. Combinations parametric, functional structural tests, defined digital testers, should employed create suite manufacturing tests. type block dictates type testability technique employed. will, construction, provide access nodes that functional and/or parametric testing performed. Since digital tester must control clocks during testing ASIC, provisions must made bypassed. Atmel's PLLs include multiplexing capability just this purpose. addition pins will allow other portions isolated test without impinging upon normal functionality. similar vein, access microprocessor, SRAM blocks must provided that controllability observability inputs outputs blocks achieved with minimum amount preconditioning. microprocessor, microcontroller digital signal processors support SCAN testing. SRAM blocks need provide access both address data ports that comprehensive memory tests performed. Multiplexing pins method providing this accessibility. glue logic designed using full SCAN techniques enhance testability. should noted that almost these cases, purpose testability technique give Atmel means assess structural integrity ASIC, i.e., sort devices with manufacturing-induced defects. techniques described above should considered supplemental patterns that exercise functionality design anticipated operating modes.
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Advanced Packaging
ATL35 Series ASICs offered wide variety standard packages, including plastic ceramic quad flatpacks, thin quad flatpacks, ceramic grid arrays ball grid arrays. High-volume onshore offshore contractors provide assembly test commercial product, with prototype capability Colorado Springs. Custom package designs also available required meet customer's specific needs, supported through Atmel's package design center. standard package cannot meet customer's needs, package designed precisely customer-specific application maintain performance obtained silicon. Atmel delivered custom-designed packages wide variety configurations.
Table 1-13. Package Options (Partial List)
Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super Low-profile Mini Chip-scale Flex-tape FCBGA Note:
Count 100, 120, 128, 132, 144, 160, 184, 208, 240, 144, 160, 208, 240, 100, 120, 128, 144, 160, 176, 100, 124, 144, 155, 180, 223, 224, 299, 100, 120, 132, 144, 160, 224, 121, 169, 208, 217, 225, 240, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 168, 204, 240, 256, 304, 352, 432, 560, 100, 108, 128, 132, 144, 160, 176, 192, 208, 224, 100, 108, 121, 128, 144, 160, 169, 176, 192, 208, 224, 256, 288, 100, 112, 132, 144, 156, 160, 180, 192, 196, 204, 208, 220, 225, 228, 256, 416, 480, 564, 672, 788, 896, 960, 1032, 1152, 1157, 1292, 1357, 1413, 1500, 1517, 1557, 1677, 1728, 1932
These packages require custom design substrate.
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Section Design
Design Overview Atmel's flexible design approach enables customer develop database compatible with Atmel's design flow through number different methodologies: logic synthesis, netlist translation FPGA/PLD conversion. Atmel provides comprehensive cell, IP/core functional timing libraries characterized commercial, industrial military conditions. Supported software versions platforms major systems shown Table page addition libraries, Atmel provides several proprietary software packages. Atmel test vector checker, VectorCheck, ensures that vectors acceptable format, pins functionally exercised, waveform timing relationships implemented tester hardware. Atmel netlist checker, DoubleCheck, identifies common design errors potential logic timing problems. also incorporates nonlinear delay calculator that accounts both preroute wireload estimation postroute back annotation when generating files supported simulators. logic synthesis approach generates gate-level netlist targeted Atmel cells Hardware Description Language (HDL) netlist. Benefits include more structured design, better adherence design rules, easier testability insertion, which lead shorter overall design cycle. Either Atmel customer perform synthesis. netlist translation approach converts existing gate array standard cell design into Atmel ASIC. Given netlist, vectors postroute timing information, Atmel translates design provides Verilog, EDIF VHDL netlist Atmel cells simulation verification customer's facility. Using this approach, Atmel deliver pin-for-pin compatible drop-in replacement, ASIC with improved performance, ASIC that combines several designs into one. should emphasized that this approach still requires customer review approve performance resultant Atmel ASIC. FPGA/PLD conversion approach creates ASIC from more FPGA/PLD designs should only used when netlist design unavailable logic synthesis. Prototype designs verified with programmable device then converted into ASIC production. with cell-based design translation, Atmel deliver pin-for-pin compatible drop-in replacement, ASIC with improved performance, single ASIC that combines several FPGA/PLDs. Like cell-based translation, this approach requires customer review approve performance resultant Atmel ASIC.
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Table 2-1. Atmel Gate Array/Embedded Array Design Tools
System Cadence Design Systems, Inc. Tools Opus Schematic Layout NC-Verilog Verilog Simulator Pearl Static Path Verilog-XL Verilog Simulator BuildGates Synthesis (Ambit) ModelSim® Verilog VHDL (VITAL) Simulator Leonardo Spectrum Logic Synthesis Design Compiler Synthesis Compiler 1-Pass Test Synthesis Compiler Boundary Scan Synthesis TetraMax Automatic Test Pattern Generation PrimeTime Static Path Verilog Simulator Floorplan Manager Debussy First Encounter Version 4.46 3.3-s008 4.3-s095 3.3-s006 4.0-p003 5.5e 2001.1d 01.01-SP1 01.08-SP1 01.08-SP1 01.08 01.08-SP1 01.08-SP1 v2001.2.3
Mentor Graphics Synopsys
Novas Software, Inc. Silicon Perspective
Design Flow
Regardless approach chosen, Atmel ISO9001/QS9000 certified design flow specifies four/five major milestones: Kickoff Meeting Underlayer Tapeout (UL), required Database Acceptance (DA) Final Design Review (FDR) Prototype Delivery Atmel defined specific requirements that must accomplished each step before proceeding next milestone.
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Figure 2-1. Simplified Design Flow
Customer
Kickoff Meeting
Atmel
Customer
Synthesis, Translation Conversion
Atmel
Customer
Database Submission Underlayer
Atmel
Customer
Underlayer Acceptance Tapeout
Atmel
Customer
Final Database Submission
Atmel
Customer
Database Acceptance
Atmel
Physical Design Verification
Atmel
Customer
Final Design Review
Atmel
Customer
Prototype Delivery
Notes:
Performed customer optionally Atmel ISO9001/QS9000 Milestone
Rev.2.3-04/02
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2.2.1
Kickoff Meeting: First Milestone
kickoff meeting, Atmel engineers will interfacing with customer introduced; design flow, milestones checklists presented detail; Deliverable Definition List (DDL) initial design schedules reviewed agreed upon. establishes what work Atmel will perform customer when that work will completed. Electrical performance power specifications, critical path timing requirements, testability requirements, custom cells, RAMs IP/cores discussed. meeting documented Kickoff Meeting Checklist. additional Statement Work (SOW) that further defines tasks, responsibilities schedules required certain complex designs with IP/cores design that requires Atmel Design Services.
2.2.1.1
Design Services
Synthesis, translation conversion steps typically occur between kickoff meeting Database Acceptance (DA). These steps performed either Atmel customer specified result netlist Atmel cells. needed, testability insertion, preroute functional timing verification, floorplanning performed customer before optionally, Atmel after design work done Atmel prior specified documented Checklist customer approval. Additional design work performed Atmel after documented Final Design Review Checklist. Underlayer Acceptance (UA) joint review between Atmel customer which customer formally accepts timing fixed placement macro cells custom underlayer that Atmel creating. assist evaluation underlayer, customer must provide design netlist Atmel cells that closely approximates final design size architecture, proposed floorplan final pinlist. customer's responsibility establish verify target timing requirements when Atmel performing place route. Database Acceptance (DA), joint review between Atmel customer, most important milestone smooth design process. Prior Atmel verifies that design passed netlist test vector checks. During meeting, Atmel reviews updated formally accepts finalized design database test vectors. Items covered Checklist include limited following: flat hierarchical netlist Atmel cells, test vectors, system loading input transition time file(s), package assignment file, netlist checker report, test vector checker reports, clock critical path timing specifications, testability requirements. Successful completion marks start physical design work Atmel. During physical design phase, each cell placed array routed (connected together) specified netlist. needed, more clock trees added design. resulting physical database analyzed with parasitic extraction tool, which generates back annotation files that include effects networks. functional timing verification, design simulated best, nominal worst case operating conditions using back annotation information, customer-supplied system loading Automatic Test Equipment (ATE) loading. this point netlist Standard Delay Format (SDF) file provided customer additional simulations customer site. Because estimated wire capacitance used preroute simulations, performance changes between preroute postroute simulations should minimal. specified, critical path timing verified with static path analysis tool. After functional timing verification complete, physical verification performed routed design. Design Rule Checking (DRC) confirms that design meets detailed CMOS process design rules fabrication process. Layout Versus Schematic (LVS) guarantees that routed design matches final simulation netlist. These checks ensure that prototype parts will meet customer specifications.
2.2.2
Underlayer Acceptance: Second Milestone
2.2.3
Database Acceptance: Third Milestone
2.2.3.1
Physical Design
2.2.3.2
Physical Design Verification
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Minor physical design corrections accommodated with Engineering Change Order (ECO) while major corrections usually require reroute. 2.2.4 Final Design Review (FDR): Fourth Milestone Final Design Review last joint review between Atmel customer before committing prototypes. Items that reviewed Checklist include limited following: changes, postroute netlist changes, DRC/LVS results, netlist test vector checker reports, buffer listing bonding diagram, electrical specifications, testability report, clock tree latency skew, postroute timing simulation static path results, power ground bounce analysis, package information. Before design taped masks made, customer must sign submit Approval Form. After been successfully completed customer signed Approval Form, tape released mask shop. Atmel tests prototype units room temperature verify functional electrical performance, then delivers packaged prototypes customer. Receipt customer-signed ASIC Prototype Approval Form completes design flow process releases Atmel start preproduction production manufacturing.
2.2.5
Prototype Delivery: Fifth Milestone
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Design, Translation Conversion Approaches
Logic Synthesis
Statement Work (SOW) contains list requirements specific each approach should completed Atmel contracted perform these design functions.
2.3.1
Logic synthesis performed Atmel customer. Atmel accepts design netlists Verilog VHDL formats incorporating behavioral, data flow structural language constructs. Alternatively, Atmel provide synthesis libraries commercial, industrial military operating conditions customers synthesize their designs. Regardless performs synthesis, resulting gate-level netlist functionally verified using customer testbenches, performance further optimized using combination timing analysis synthesis tools. When Atmel performs synthesis, results reviewed with customer during ensure that design functionality performance goals achieved. result synthesis gate-level netlist Atmel cells test vectors that suitable Translation process converting existing design from different cell library Atmel's ASIC cell library. Taking functionality timing into account, each cell original design mapped equivalent cell Atmel library. order avoid race conditions, delay cells added match speed slower technology. performance improvement needed, small functional blocks implemented hard macros, drive strength selected cells increased. there buffers Atmel cell library that adequately match performance existing part, buffers designed SPICE simulations match switching characteristics. This cell mapping approach minimizes need customer engineering resources time-consuming design modifications netlist level. verify proper operation performance, netlist translated vectors used functional timing simulations best, nominal worst case conditions temperature, voltage process. direct comparison, performance original device determined simulation actual characterization sample part. Under customer direction approval, signals paths with greater than desired timing difference accelerated delayed meet specifications, improve performance create greater design margin. Given proper timing specifications, static path analysis tool used verify critical paths (input register, register register, register output), setup hold, clock latency skew. Although static path analysis tool identifies potential timing problems paths design independent test vectors, vectors still required functional verification. design verification work performed Atmel prior covered Checklist.
2.3.2
ASIC Design Translation
Clock Trees
Atmel provides special clock buffers cell library preroute simulation. Customers directed these special buffers instead attempting generate clock distribution network from buffers, inverters other cells. Atmel replaces each special clock buffer cell with clock tree verifies latency skew times during physical design. Here some guidelines achieving better clock tree results: high-drive input buffer each clock signal. Provide actual input transition times each clock signal. Specify timing requirements between different clock domains. Identify groups registers that share common clock communicate with each other. They placed near each other minimize skew.
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2.4.1
Preroute Clock Tree Estimation
logic designer instantiates special Atmel clock tree buffer cell netlist placeholder each clock tree clock subtree. This cell used create reasonable signal transition times preroute simulations, does predict clock latency skew taken into account. gated clock distribution networks, clock tree buffer cells must used before after gating logic, timing each clock subtree determined separately. Contact Atmel engineer obtain clock buffer cell estimated latency delays that inserted file preroute timing simulation specified logic synthesis tool. Atmel builds clock trees using flat net-level approach which same feeds leaf pins given tree. Multiple clock trees easily constructed grouping clock pins unique nets, each driven separate clock buffer cell. necessary that each clock tree have chip input buffer. example, inverted noninverted clock originate from same port, slower clock generated from faster clock. geometry synthesized tree determined allowable transition time, insertion delay (also called latency), skew number leaf pins. Array size floorplanning will also contribute significantly Atmel's ability meet customer clock requirements, which specified build clock tree which leaf pins exclusively clock pins, customer must provide list nonclock leaf pins. clock tree includes gating logic generated clocks, Atmel needs know desired timing relationships between subtrees.
2.4.2
Clock Tree Synthesis
2.4.3
Clock Tree Verification
Back annotation data that includes time-of-flight effects networks extracted from route used static path analysis tool verify latency skew times each generated clock tree.
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Design Testability (DFT)
complexity ASIC designs increases, ability adequately test circuit using only functional pins severely limited. Atmel gate arrays range from well over input/output (I/O) pins. 60-pin array inputs sequential logic, exhaustively tested clock cycles, about seconds clock rate. Increasing input count inputs increases test time over years. Adding sequential logic (registers) increases test time exponentially with number clocked elements between input output (pipeline length). Obviously, designs must have some degree testability built into them order useful, reliable circuits that reach marketplace timely manner. Performing functional tests general functions corner cases device enough screen defective parts. Manufacturing defects such shorted ground shorted power translate functional defects that detected through functional tests. performing manufacturing tests, these physical faults detected through fault models such stuck-at-faults, which help translate physical defects detectable functional faults. Atmel provides multiplexed flip-flop type internal scan synthesis automatic test pattern generation means performing manufacturing tests. this process, Synopsys' test tools Compiler TetraMax used synthesize scan generate automatic test patterns. When using structured technique such mutiplexed flip-flop type scan synthesis, specific requirements imposed such flow must followed. Multiplexed flip-flop type scan procedure converts nonscan sequential elements that part scan architecture into their scan equivalent counterparts. scan equivalent flip-flops then formed into more serial shift registers. Serial shift registers partition combinational blocks, providing pseudo primary input (PI) pseudo primary output (PO) access combinational blocks that controllable observable through primary inputs primary outputs. ideal scenario, such conversion provides controllability observability access nodes design, leading 100% coverage stuck-at-fault type defects. metric used define such test coverage number detected faults test coverage number faults number undetectable faults Rules that govern controllability observability scan design known test design rules. avoid test design rule violations following recommended guidelines when synthesizing scan designs. Here some guidelines that, followed, will prevent test design rule violations. drive ports clock. Make sure registers that will part scan architecture controllable directly from clock. design generated gated clocks, provide test clocks muxed from bypass generated gated clocks test mode. bidirectional ports test clocks. Make sure asynchronous pins registers part scan architecture controllable directly from asynchronous control ports. design asynchronous registers part scan architecture that controllable directly from asynchronous port, provide muxed-in level asynchronous port test mode.
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make data inputs registers sensitive clocks. gate clocked register output generate another clock. Make sure design feedback loops. does they cannot removed from design, provide suitable location break loop test mode. clock signals drive multiple pins registers. make data inputs depend other clocks. multiple clocks capture data into registers latches. Make latches transparent test mode. attempt form latches combining available combinational primitive gates technology library. scan equivalent registers functional registers unless design synthesized scan ready. address testability issues designs with embedded memory blocks, additional measures such BIST shadow registers around memory blocks should considered. designs contain analog blocks IPs, they should considered other means manufacturing testing individual basis.
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2.6.1
Using Synopsys Compiler TetraMax
Test Generation following guidelines allow designs efficiently enhanced using Synopsys Compiler/TetraMax software. SCAN design rules followed, these tools scan chains design generate test vectors automatically achieve high fault coverage. When design rule followed, fault coverage reduced, sometimes dramatically, unless design modified comply with rules. This approach will require least additional Test Enable (TE) least pins muxing required Test mode. Three popular types techniques have been shown improve circuit's testability. These techniques partitioning, memory array isolation, test points. these techniques practical very large scale integration (VLSI) chip designs. Partitioning: Since cost test pattern generation approximately proportionate number gates cubed, task test pattern generation greatly simplified partitioning circuitry into smaller pieces. Partitioning accomplished providing internal access through multiplexers scan register.
2.6.2
Techniques
Table 2-2. Synopsys Test Compiler/Test Generation Guidelines
Testability Rule Synchronous design cross coupled gates unregistered feedback Single edge clocking clock gating latches Single external reset asynchronous resets presets generated chip combinational logic reset path internal tristate buses direct connections Reduced fault coverage; possible tristate contention during scan test Dynamic hazard MUXs gates; insert gating controls prevent contention. Clocked device allowed scan chain; reduced fault coverage Clocked device allowed scan chain; reduced fault coverage allowed scan chain; reduced fault coverage allowed scan chain; reduced fault coverage test mode, create single edge clocking with inverters multiplexers. data disable flip-flops instead clock enables; disable gating test mode. alternate test methods; force latches transparent mode with test mode. Reset ORed with test mode. Effects Infraction Associated logic untestable Workaround Break feedback path with test mode.
Memory Array Isolation: Whenever memory arrays embedded within combinational logic, problems arise attempting sort faults within memory array combinational logic. including ability isolate these arrays from surrounding combinational logic, tests devised individually test array combinational logic. Test Points: Test points another method improving functional test pattern fault coverage. Test points essentially enhance controllability observability circuit providing direct access internal nodes. Specialized test equipment, such bedof-nails tester, used test circuit boards. case large scale ICs, test points pads become impractical because size package costs func-
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tion number pads. However, scan registers viewed means inserting electrical test points into VLSI design. addition techniques described above, disciplined design rules greatly improve testability circuit design avoiding creation untestable circuits. Some examples given below. Redundant logic: Faults within redundant logic detectable. redundant logic required, test circuitry separate redundant paths test each these paths individually. Asynchronous logic: This creates potential race conditions within circuit. registered logic only. Initialization: Design circuits easy initialization allow easy stabilization sequential circuits prior test. 2.6.3 Structured Scan Techniques testability sequential circuits simplified providing means access internal registers. gain access these internal registers, standard registers within design replaced with special registers that configured normal parallel registers serial shift registers. Figure 2-2. Scan Register Design
With access provided registers through serial scan path, problem sequential logic test pattern generation transformed into simpler problem combinational logic test pattern generation. Scan Register Design: Several variations scannable register designs have been around years, actual implementation scan design vary great deal. basic Atmel scan register design, test enable allows selection parallel data input serial data input. Atmel's macrocell library contains several cells that used basic building blocks scan register design. These cells cells. Information about these cells available from your Atmel sales representative. judicious selection these cells, designer easily build scannable register meet needs. Scan Path Formation: Scannable registers formed into scan paths connecting serial output signal register serial input signal next register. register control clock signals connected registers within scan path.
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2.6.4
Boundary Scan
Boundary scan used simplify board system testing nothing more than adaptation serial scan technique. Boundary scan involves inclusion shift-register stage (contained boundary-scan cell) adjacent each component such that signals component boundaries controlled observed using scan testing principles. boundary-scan cells connected such that they form shift-register chain around periphery design. This path provided with serial input output connections appropriate clock control signals. This allows system board designed with incorporating boundary-scan form single data path through board design. Alternatively, system boards contain several independent boundary-scan paths. This formation boundary-scan paths system level greatly level system's testability. utilizing boundary-scan registers each board (assuming each boundary-scan register), board design partitioned. setting each IC's boundary-scan register external test mode, interconnections board level tested opens shorts. Alternatively, setting each IC's boundary-scan register internal test mode, each individual isolated independently tested. Combined, these features allow original equipment manufacturers (OEMs) simplify their board level test, eventually eliminating need bed-of-nails testers. Figure 2-3. Boundary-scannable Board Design
Serial Data
Serial Data
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JTAG/IEEE® 1149.1
effort standardize boundary-scan design resulted proposed Institute Electrical Electronics Engineers, Inc. (IEEE) standard 1149.1, "Standard Test Access Port Boundary-scan Architecture." This standard evolved from work Joint Test Action Group (JTAG), informal, international group semiconductor manufacturers OEMs. Standard 1149.1 approved full IEEE standard February 1990 become industry standard system design with boundary-scan. This standardization important that allows common approach boundary-scan design from different semiconductor manufacturers. Standard 1149.1 calls each incorporate this into design. shown following figure, 1149.1 consists four pins: test clock (TCK), test data (TDI), test data (TDO), test mode select (TMS). addition, controller, Instruction register test-data registers bypass boundaryscan included. Optionally, user-defined test-data registers, test reset (TRST) pin, device identification register, parallel STATUS included. selects appropriate data path through based contents Instruction register. Together, combine control controller, which turn generates clocks controls Instruction registers test-data registers. discussed above, boundary-scan register allows system's board interconnections IC's circuitry separately tested. addition, SAMPLE mode allows IC's normal operation data flow sampled through boundary-scan register. bypass register allows individual IC's boundary-scan register bypassed "short-circuited" when test data required flow through another system's board boundary-scan path. device identification register will contain IC's manufacturer's code name, IC's part number part variation (design revision). OEMs poll this register determine which tests apply user-defined test-data registers used other purpose such internal scan path further partition IC's logic. Atmel supports boundary scan logic synthesis through Synopsys' Compiler. cost overhead designing with 1149.1 minimal. most notable impact will reduction available external pins application purposes. further information regarding design 1149.1 your application, please contact design center your area. Benefits obtained through 1149.1-compatible ICs. available 1149.1-compatible used partially partition system design, thereby simplifying overall test system. addition, each 1149.1-compatible thought building block system level used many different times different designs design revisions. Once test been developed building block, need changed when block used again. Hence, 1149.1compatible reduce overall system level test development effort reduce time-to-market product. Please note that Atmel boundary-scan synthesis flow mandates test reset pin. Therefore, total number dedicated ports required boundary-scan logic synthesis five.
2.7.1
Test Access Port (TAP) Architecture
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Figure 2-4. JTAG Architecture1
TMS: Test Mode Select TCK: Test Clock TDI: Test Data TDO: Test Data TRST: Test Reset
Boundary-scan register
Device identification register
Optional
User test data registers
Optional
Bypass register
Decoding logic
INST
Instruction register
clocks controls
Output buffer
controller
Enable
clocks controls
Select STATUS OPTIONAL TRST
Notes: JTAG must five-port.
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Section Test
ASIC Verification This chapter describes design verification process used Atmel ensure that your
ASIC first-pass silicon success. subdivided into topics discussing functional test vectors, parametric testing, static path analysis, internal serial boundary scan, ASIC verification methodologies. also includes list deliverables expected from customer each topic. Database Acceptance (DA) design milestone Atmel's ASIC flow. occurs after Design Handoff, which operation transmitting design netlist(s), specifications, vector data Atmel. design passes when Atmel design engineer verifies records Checklist that information necessary complete design been properly received Atmel netlist test vector checks have passed. customer's responsibility hand design that meets requirements Checklist. beginning design process, customer should obtain latest version Checklist from Atmel engineering representative. Checklist customer's gateway creating successful ASIC with Atmel.
3.1.1
Methodology
While much Atmel ASIC Design Overview discusses design implementation, important understand verification process that ASIC goes through data from customer enhance level design verification. flow diagram Figure details verification process from customer specification through silicon evaluation.
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Figure 3-1. Gate Array/Embedded Array Design Verification
Deliver Design
Kickoff Meeting
Embedded Array
Define Underlayer
Synthesis/ Design Entry
Scan/JTAG
Simulation/ Static Path
Floorplan
Embedded Array (Preliminary Netlist)
Create Underlayer
Database Handoff
Tape Underlayer
Database Acceptance
Fabricate Underlayer
Place Route/ Clock Tree
Verification/ Resimulation
Final Design Review Standard Cell Embedded/Gate Array
Tape Full Mask
Tape Metal Masks
Fabricate
Fabricate Personality
Customer Atmel Joint
Proto Assembly Test Rev. 2.2-03/02
Proto Shipment
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Test
critical note that functional test vectors static path analysis performed design based entirely customer data submitted time Also, quality inserted scan function designing testability. Atmel only test verify customer's component level data that been provided. 3.1.2 Vector Limits Atmel uses number different test vector types verify ASIC. These listed below with summary limitations recommendations. later section will describe types greater detail. vectors listed here should provided Atmel customer, with possible exception Internal Serial Scan JTAG vectors, which Atmel contracted insert create. 3.1.2.1 Functional Test Vectors least test vector pattern speeds must within tester limits. total cycle count must less than three times design's gate count. Must pass VectorCheck test vector checking tool 3.1.3 Internal Serial Scan Vectors Total vector count must meet Automatic Test Equipment (ATE) memory size limit. Cycle Count (tester cycle limit) (total functional cycle count) Scan chain length should less than 1,000 flip-flops. Must pass VectorCheck test vector checking tool 3.1.4 Parametric Test Vector test vector input pins must toggle both high low. output pins must stable high low, each least consecutive cycles. Bidirectional pins must stable input output mode, each least consecutive cycles. Must pass VectorCheck test vector checking tool 3.1.5 Delay Path Test Vector (optional) test vector set, with five paths Input timing applied customer Output sample time pass worst-case simulation results Tester accuracy must accounted for. same cycle paths tested. Must pass VectorCheck test vector checking tool 3.1.6 JTAG Test Vectors Test vectors verify JTAG design components: controller, reset mechanism, boundary scan register, test data register Must pass VectorCheck test vector checking tool
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Functional Test Vectors
Functional test vectors ensure that customer's ASIC performs designed. functional test vector defined cycle-based procedure where input values applied device, producing changes output. test cycle defined, input application output sampling done relative that cycle length. Regardless operating conditions, same inputs applied output data compared same expected output. Each test vector should begin with known reset procedure. Before delivery Atmel, customer expected have test vector sets across specified environmental conditions. Atmel will simulate functional test vector sets with both preroute postroute delay information. same test vector sets then used evaluate customer's prototype units eventually production components. Atmel provides tool called VectorCheck ensure that test vectors conform tester standards. VectorCheck reads vectors variety formats provides pass/fail indication tester acceptability. Reports assist engineer correcting vector formatting problems. full details tester limitations, test vector strategies, data formats suggestions creating functional test vectors, please refer VectorCheck manual distributed with VectorCheck software. Once customer provided test vector data Atmel Database Acceptance, data VectorCheck results used create Verilog test decks that emulate tester environment. Atmel runs each test vector using best, nominal, worst case voltage, temperature, process conditions under tester loading. requested, vector also simulated using system loading. These simulations must pass order device proceed through design process. Functional test vector sets foundation verifying customer's design. using same test vector sets from customer development design review through production components, constant standard applied evaluate design. providing VectorCheck, Atmel encourages customer create test vectors that both verify design executable automated test equipment. noted "Vector Limits" section, there many kinds functional test vectors. these must pass VectorCheck well meet restrictions shown section "Test Vector Requirements" (see below).
3.2.1
Test Vector Requirements
Each vector must (BC) (WC) variation junction temperature, voltage, process corners. Running under nominal conditions also recommended. Each vector must with tester loading. Running with system loading also recommended. vector should have expected output, regardless operating condition. Vector sets must independent, with dependence other vector sets. There repeatable "power-up" state ASIC; each vector must start with reset initialization cycle(s). Simultaneous switching should limited cycle. Each vector should contain external signals internal bidirectional/tristate enables single file. Vectors should data following formats: Generic Tabular: Timestamp, data (print-on-change [POC]) (OVI Compliant) (POC)
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Synopsys ".vec" format
vectors must pass VectorCheck. following data should delivered Atmel each functional test vector set: Worst case data each simulation, acceptable format VectorCheck input, output, files
ASIC Testers
order useful manufacturing process, functional test vectors must executable Automated Test Equipment (ATE). Unlike digital simulators, testers constrained physical limitations such number pins, strobe resolution, test rate, etc. Compatibility with tester limitations most critical standard test vector sets, because Atmel cannot test devices that exceed hardware constraints. These testers used Colorado Springs, Colorado, prototype verification characterization. These also same type testers used production testing. Table details basic specifications used Atmel. Table 3-1. Basic Specifications
Capability Digital Pins Data Rate Pattern Depth Timesets Pulse Width Mixed Signal Frequency Arbitrary Waveform Generator Bandwidth Data Rate Output Range Frequency Analog Capture Port Sample Rate Input Range High Frequency Arbitrary Waveform Generator Sampling Frequency Output Range High Frequency Analog Capture Port Bandwidth Sample Rate (one channel) Vp-p (50) bits Msample 41.8 Vp-p (Differential); 20.9 Vp-p (Single Ended) bits MSample Vp-p (Differential; Vp-p (Single Ended) Credence® VistaTMLogic Credence Quartet One
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Digital Capture Port Frequency Pulse Width Sample Rate MSamples/s
Once customer's design been produced approved design verification samples have been delivered, Atmel will characterize customer's component, varying voltage from best nominal worst each three temperature values. Inputs will applied outputs compared expected results. This will ensure Atmel's ability manufacture this component prior production release. Once device entered production, test vectors room temperature three voltage corners. Additionally, sample from each tested under conditions. results from these functional test vector sets used determine which units shipped. 3.3.1 Parametric Testing Part standard design flow parametric analysis design I/O. measurement parameters including VOH, VOL, VIH, VIL, IIH, completed parallel functional test vectors. This testing done insure that device performs Atmel specifications. Atmel does perform characterization testing, including path delay testing, input setup, hold measurement, unless specifically negotiated. During characterization prototype units, input threshold parametric tests done each pin. performing these tests, thresholds established verified production test. During production testing, threshold test performed type. addition parametric testing, static device measured. device placed into number arbitrary states, taken from functional test vector set, power plane current measured. Characterization successful components used threshold production testing. During production testing, violation that threshold failure condition. parametric testing done with parametric test vector that customer provided Atmel. order Atmel perform parametric tests, test vector must meet following conditions. 3.3.1.1 3.3.1.2 Each output bidirectional output state must maintain ("0") high ("1") state consecutive test cycles. Each input bidirectional input state must transition once from ("0") high ("1") also once from high ("1") ("0"). resulting state must held least cycle. bidirectional tristate should placed high-impedance state from both low- high-output state least cycle. VectorCheck includes checks each these requirements. summary reports inform user when conditions met. Failure meet these conditions will limit level parametric testing. Atmel strongly recommends that conditions met, since that will guarantee best component evaluation. more details these conditions rules used check them, please refer online documentation that ships with VectorCheck.
3.3.1.3
Tristate
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Static Path Analysis
feature sizes grow smaller gate counts increase, becomes increasingly apparent that functional vectors longer completely verify design. Static Path Analysis also required more complete verification, especially critical paths. Atmel will perform point-to-point static path analysis that required design. Atmel currently uses Synopsys PrimeTime perform these tasks. This analysis duplicated actual silicon. should noted that even small designs, static path analysis produce large amount data result "false" paths. These false paths appear violate limits actually insignificant design could masking real data. Atmel design engineers will provide customer with postroute static path results expect that customer will able distinguish between false paths critical paths. Once false paths eliminated, analysis rerun such that they ignored. customer should deliver static path requests following format: Table 3-2. Static Path Request Format
Limit (ns) Best Case Limit (ns) Worst Case
Begin Point Instance/Pin Name Notes:
Point Instance/Pin Name
Instance/pin names internal external. There need specify both max, allowed. Wildcarding names allowed, e.g., Flop pins Flop Pins.
3.4.1
Test Methodology Options
have discussed functional test vectors, parametric silicon tests, static path analysis. While each these useful verifying design, implementing full scan test methodology even better. Well-implemented scan designs achieve very high fault coverage, ensuring parts shipped Atmel defect-free. Internal serial scan inserted either customer Atmel order increase fault coverage design. This technique does replace rather supplements functional test vectors provides higher fault coverage than typically possible with functional vectors alone. While functional test vectors indicate whether customer's design functions designed, internal serial scan vectors identify process faults. Internal serial scan should used part well-rounded test methodology. number test vectors limited tester memory ATE. cycle count combined functional ATPG test vector sets must less than memory limit ATE. Often, test counts reduced scan chains kept reasonable length less than 1,000 flip-flops. Please refer Atmel Test Capability Table your Atmel design representative determine your tester. Atmel supports full multiplexed registers purpose internal serial scan chains, using Synopsys Compiler full insertion. Customers planning using scan should aware that Synopsys rule-based compiler, which means designs that follow design rules often limited terms maximum achievable fault coverage. Items such gated uncontrollable clocks uncontrollable asynchronous pins will limit fault coverage test patterns generated design. enhance logic cell fault coverage, Atmel provides Synopsys Tetramax models embedded memories. These models allow more rigorous testing logic surrounding memory. discussed following sections, memories themselves tested with BIST wrapper provided Atmel.
3.4.1.1
Internal Serial Scan ATPG
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Test
more details serial scan insertion, please Design Testability, located Design section this overview. 3.4.2 Delay Path Measurement Atmel support single long path (>12 test vector set, where five paths measured. This test vector that tests that timing placement output sample point. This characterization rather pass/fail limit tester threshold. output strobe point must placed meet worst case simulation timing plus tester accuracy. Same-cycle critical paths measured. Generally, noncritical path outputs masked compared during this test vector set. path measurement test vector must meet same requirements standard functional test vector set, well pass VectorCheck. 3.4.2.1 JTAG Boundary Scan (IEEE 1149.1) JTAG boundary scan inserted either customer Atmel. JTAG boundary scan used facilitate board-level test device. Atmel uses Synopsys Compiler implement JTAG, utilizing standard controller provided Synopsys. Standard JTAG instructions supported, custom JTAG instructions possible. test validation analog cell features should discussed with Atmel representative well advance Database Acceptance. Test vectors embedded cores (e.g., ARM7TDMI, ARM946E-STM, OakDSPCore PINETM) provided Atmel. These test vectors specific core only designed test chip logic that created interface with core. designers such chips should thoroughly discuss testing these embedded cores with design engineers Atmel.
3.4.2.2 3.4.2.3
Analog Cells (PLL, POR, etc.) Embedded Cores
Conclusion
Atmel ASIC differentiates itself being very flexible organization. Atmel supports functional vectors that automated test equipment. Atmel supports parametric evaluation device I/O. Atmel supports encourages static path analysis. There provisions Internal Serial Scan, JTAG, Embedded SRAMS Cores, well analog features.
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Section Packaging
Introduction
Atmel pairs high-performance silicon with high-performance packages, custom designed company's gate arrays. Atmel offers gate arrays ceramic plastic packages. through hole surface mount ceramic packages designed meet Military specifications. Atmel's plastic through hole surface mount packages come variety lead configurations standard footprints. Atmel's Packaging Center provide complete custom package design services. Atmel's facility been designing custom packages several years developed network specifically package design. Atmel maintains close relationships with world's leading suppliers assembly packaging services, leverages these relationships provide innovative packaging solutions variety applications. access package drawings line, http://www.atmel.com/atmel/ quality/quality13.htm. Atmel also offers unique capability provide prototypes plastic TQFP packages. These design verification sample (DVS) packages assembled Colorado Springs facility shipped within hours receipt prototype dice. Table partial list Atmel package options; other package options available. Contact your local Atmel sales office. list Atmel sales offices,
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Table 4-1. Package Options (Partial List)
Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super Low-profile Mini Chip-scale Flex-tape FCBGA Note:
Count 100, 120, 128, 132, 144, 160, 184, 208, 240, 144, 160, 208, 240, 100, 120, 128, 144, 160, 176, 100, 124, 144, 155, 180, 223, 224, 299, 100, 120, 132, 144, 160, 224, 121, 169, 208, 217, 225, 240, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 168, 204, 240, 256, 304, 352, 432, 560, 100, 108, 128, 132, 144, 160, 176, 192, 208, 224, 100, 108, 121, 128, 144, 160, 169, 176, 192, 208, 224, 256, 288, 100, 112, 132, 144, 156, 160, 180, 192, 196, 204, 208, 220, 225, 228, 256, 416, 480, 564, 672, 788, 896, 960, 1032, 1152, 1157, 1292, 1357, 1413, 1500, 1517, 1557, 1677, 1728, 1932
These packages require custom design substrate.
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Section Quality Reliability Assurance
Executive Decision
Atmel's corporate goal only meet customers' requirements provide them with competitive advantage through innovation, service quality. Atmel works achieve this goal developing methods building quality reliability into products, processes services. Because responsibility Atmel employees, concern quality begins with initial product inception remains constant through product completion.
Continuous Improvement Quality System
recipients Malcolm Baldrige National Quality Award stated: realize that race without finish line. [Our goal improve constantly forever system production service, improve quality productivity, thus constantly decrease costs." Atmel this continuous improvement journey well. goal ongoing improvement only products services quality assurance process itself. work improve this process benchmarking, listening customer feedback, conducting self-assessments. journey continuous improvement involves various techniques such statistical process control (SPC), statistical design experiments (DOE), maverick control statistical limits (SBL), failure mode effect analysis (FMEA), measurement system analysis (MSA) many others. Just important tools commitment employ these tools effectively support requirements continuous improvement system. responsibility every Atmel employee develop maintain this commitment. these techniques throughout corporation, just manufacturing, proof Atmel's commitment continuous improvement. Throughout entire company whether order entry, wafer fabrication, review customer specifications, government compliance testing, simply returning customer's call Atmel striving "zero defects." Atmel employees have undergone extensive training through years order implement techniques systems continuous improvement. This training included Crosby 14-step Program; Alamo Problem Solving, Decision Making Planning; SPC; DOE; FMEA; MSA; Problem Solving; various in-house programs managerial supervisory skills. Teams have been established throughout Atmel identify problems, implement solutions initiate preventative action. These teams include Corrective Action Teams
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(CATs), Preventative Action Teams (PATs), Work Area Teams (WATs) task teams. These teams work enhance Atmel's total quality program. Figure 5-1. Continuous Improvement Process History
ellen
CUSTOMER QS-9000 ISO-14001 Pb-Free
NEXT STEPS Enhanced 6-Sigma SSQA ISO-9000: 2000
INITIATIVES
SYSTEMS ISO-9000
FMEA Maverick Control
lvin
PROCESS SPC, Sigma Impact
PREVENTION
FASTER BETTER Empower QIT's Effective Problem Solving Effective Planning
FASTER
Steering Committee CONTINUE Quality Improvement Teams (QITs) Hassle Systems
Better Defined Networks Standards Initiate
START Pilot Groups
1985
2002
Atmel improved quality assurance process giving customers more input setting direction. increase response meeting needs customers, conduct quality reviews, implement special requirements system enhancements, actively drive improvements from customer surveys. Atmel's management team integrating these quality management principles into continuous improvement system.
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Quality Reliability Assurance
Atmel's Quality System
Atmel's quality system based compliance 9001, QS9000 MIL-PRF38535 standards. Atmel achieved 9001 certification through Underwriter's Laboratories. Atmel dedicated continual training educational programs employees. employees trained, certified audited compliance specified requirements. addition, Atmel offers education programs conjunction with University Colorado other institutions.
Figure 5-2. Quality System Flow
Corporate Quality Manual (MIL- PRF38535, 9001, 9000)
Corporate Policy Specifications
General Quality Specifications
Quality Management System
Product Realization
Measurement, Analysis Improvement
Management Responsibility
Resource Management
Document Control Records Archives
Quality Planning Process Controls Design Control Purchasing Product Identification Traceability Materials Control Flowdown Customer Rqmts Product Configuration Mgmt Change Control Calibration Preventive Maint. Technology Release Product Qualification
Process Controls Control Nonconforming Product Audits Preventive Correction Action
Customer Satisfaction Management Review Site Management
Process Controls Resources Training Environmental Controls Management
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Quality Reliability Assurance
5.4.1
Reliability Assurance
Failure Rates reliability integrated circuit will vary over lifespan; therefore, failure rate units operating after specific number hours best describes product reliability. This failure rate defined Instantaneous Failure Rate (IFR). Other measures include Average Failure Rate average over period time Cumulative Failure Rate total number failures occurring during operation. Because device failures hour small, failure rates usually measured billions device hours defined Failure Units FITs. hundred failures billion device hours FITs 1000 hours. traditional "bathtub" curve used describe failure rate associated with product actually combination exponential failure rate models. first model starts with large failure rate that rapidly decays low, almost constant failure rate. This model used describe early-life reliability failures associated with this stage (Phase are, most part, process anomalies screened during Atmel's in-process final acceptance testing. second model starts with low, relatively constant failure rate climbs exponentially after some period time. This wearout stage (Phase device, where mechanisms such electromigration oxide breakdown predominate. combining these models, bathtub-shaped curve representing lifetime product formed. nearly flat portion bathtub curve result summing tails models represents Phase low, stable failure rate characteristic this stage. Failures observed during this stage random nature mixture randomly occurring process defects wearout type mechanisms. Devices shipped customer stable portion their lifetimes. Atmel's production tests, incoming material inspections, process specifications have been developed screen remove potential Phase failures before product shipped customer. test screening limits have been established through characterization qualification series gate arrays processes used fabrication. Statistical Design Experiments (DOE) Statistical Process Control (SPC) used maintain process stability repeatability through development production.
5.4.2
Bathtub Curve
Figure 5-3. Bathtub Failure Curve
Phase Infant Mortality
Phase Random
Phase Wearout
Failure Rate
Time
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Quality Reliability Assurance
Through analysis Phase failures induced during accelerated life tests, Atmel developed techniques extend material life. effect this extend Phase time period, forestall Phase 5.4.3 Atmel Reliability Program part continuous improvement system, Atmel initiated reliability program designed measure, monitor improve product reliability while reducing cost associated with reliability testing. This program includes production data, early life failures, qualification data reliability evaluations. minimum, Atmel subjects product standard qualification tests. results these tests serve foundation reliability database. During qualification, Atmel performs failure analysis failed unit regardless impact qualification status. addition qualification activities, Atmel evaluates specific failure mechanisms such electromigration, time-dependent dielectric breakdown, ESD, latch-up, carriers stress-induced voiding. addition qualification processes, product lines packaging, Atmel performs quarterly reliability monitor testing processes. 5.4.4 Design Quality Reliability Many quality reliability concerns minimized with proper design techniques. example, Electrostatic Discharge (ESD), which contributes production yield loss latent reliability problem, reduced eliminated through establishment adequate design rules. Atmel's quality reliability assurance systems insure that data taken from actual product testing back design groups verification models design rule updates. This commitment reliability quality during design cycle resulted cell library that fully verified.
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Quality Reliability Assurance
Failure Analysis Capability
Cross Sectioning Interconnects Diffusions Photoresist Angle Metallurgical (packaging) Packaging Failure Analysis Package X-ray Delid/Decap Leak Testing Penetrant Moisture Content Plastic Impurity Content Corrosion Analysis Electrical Failure Analysis Failure Verification/Benchtesting Liquid Crystal Analysis Mechanical Microprobing Focused Beam (FIB)
Deprocessing Chemical Chemical (plasma) Focused Beam Step Coverage Metal Polysilicon Oxide/Nitride Photoresist Outside Services Requests SIMS Auger Spreading Resistance Acoustic Microscopy Electron Beam Induced Current (EBIC) Optical Microscopy Metallurgical Microscopes Linewidth Measurement Low-power Stereoscopes 3x5, 8x10 photos available Scanning Electron Microscopy/Energy Dispersive X-ray Spectroscopy Feature Identification Elemental Identification Process Characterizations Yield Enhancement
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Quality Reliability Assurance
5.6.1
CMOS Reliability Data
Gate Oxide Integrity Expected lifetime exceeds worst-case system requirements based following assumptions: Activation Energy, 0.27 Junction Temperature, 175°C. Voltage
5.6.2
Electromigration
Atmel verified design rules maximum current density through electromigration testing straight line, contact structures. Typical operating lifetimes 600+ years have been calculated from data current density 2E5A/cm2 110°C. Atmel's gate array carrier data shows that product reliability carriers concern. Accelerated tests Idsat decrease conditions showed derated operating life years. latch-up occur CMOS logic device, sustained impedance path between circuit's internal supply buses must created. This path usually induced when current pulse "turns more parasitic SCRs result over-voltage transient supply, input output pin. Atmel's epitaxial layer with substrate significantly inhibits latch-up. This combined with protection diodes gives Atmel gate arrays complete latch-up immunity.
5.6.3
Carriers
5.6.4
CMOS Latch-up Immunity
5.6.5
Construction Analysis
cross-sections routinely performed Atmel's CMOS processes. This data serves quality monitor provides early detection order affect correction process variations that could possibly have detrimental effect reliability Atmel's CMOS Gate Array/Embedded Array products. Exposure result variety problems ranging from immediate, catastrophic failure latent defects that surface field. sensitivity (ESDS) levels depend definition failure. Atmel tests categorizes product procedures specified Method 3015 MIL-STD-883D. This method requires that three devices pass both functional tests after each level exposure. This test extremely stringent: even marginal parametric failures still functional devices must defined failures. ESDS highly dependent circuit layout, every personalization characteristic ESDS level. Consequently, Atmel characterizes every product ESDS with goal 2,000V minimum ESDS sensitivity.
5.6.6
Sensitivity
5.6.7
CMOS Reliability
Semiconductor reliability measured either failure rate, usually reported FITs. Failure Unit defined number failures billion device hours operation. corresponds MTBF million device hours. This corresponds better than years operation between failures 100-piece sample size. Atmel 0.35 CMOS process, calculated confidence estimate 50°C operation activation energy. Inherent quality system define monitor critical process steps. used only monitor control parametric limits also evaluate, establish control equipment settings capabilities. Process yield monitors extensively utilized with every wafer along with periodic reliability monitoring test structures.
5.6.8
Statistical Process Control (SPC)
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involves mathematical portrayal data graphical form allow determination whether process step control control. Through experimentation evaluation, upper lower control limits established each parametric value given process step. parametric values charted continual basis. result easy-to-read graph that operators technicians monitor. Atmel monitors over charts throughout wafer fabrication, test packaging operations. 5.6.9 Statistical Design Experiments (DOE) greatly reduce time required process qualification optimization. This especially useful wafer fabrication, where quality depends interaction hundreds different process steps materials. When coupled with computer-aided design process models, used predict relationships outcomes before running actual experiments. Actual experiments only those processes that show most promise. This turn reduces time cost designing products processes improving existing ones. 5.6.10 Payoff focus Atmel's quality reliability efforts customer their system. Through strict attention customers' component system requirements, Atmel achieved preferred supplier status. Atmel been successful establishing dock-tostock programs with several computer military customers. dock-to-stock programs, Atmel ships kitted product directly customer's production line, exact required. This reduces customers' inventory levels well incoming inspection costs. Over percent Atmel's Gate Array/Embedded Array products shipped dock-to-stock.
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Section Military Aerospace
Designing High Reliability
Atmel committed supplying highest reliability ASIC military aerospace applications. Atmel's quality management system provides design manufacturing discipline Atmel's ASIC products well standard memory products. quality management system continuously improved based feedback from frequent customer audits regular audits conducted self-audit team, well system internal monitoring management review. design manufacturing capability utilized ASIC products, Columbia Design Center, Colorado Springs Operation, approved subcontractors vendors, permits Atmel supply Commercial Shelf (COTS) products using MIL-PRF-38535, appendix Quality System. that necessary develop ASIC military Follow good design practices make sure entire circuit testable, controllable, observable documented. proper derating factors process, voltage temperature when performing timing functional simulations. Develop complete functional test vectors grade coverage accordance with MIL-STD-883 Method 5012. Atmel's cell libraries design tools help achieve extremely high levels fault coverage. Atmel's facility Colorado Springs supports in-process burn-in, temperature testing, periodic Group Quality Conformance Inspection (QCI), majority tests required periodic Group QCI. Figures outline product flow military ASICs Quality Conformance Inspections.
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6.1.1
Gate Array
Figure 6-1. MIL-STD-883 Class Product Flow
SPC, Monitors Wafer Fabrication
SPC, Monitors
Wafer Sort Electrical Test
SPC, Monitors
Saw, Attach Wire Bond
SPC, Monitors
Internal Visual Method 2010, Condition
Monitors
Seal Topside Mark
Monitors
Environmental Preconditioning; Temperature Cycling Method 1010, Condition Constant Acceleration Method 2001, Condition Fine Gross Leak Method 1014
Monitors
Pre-burn-in Electrical Screening
Monitors
Burn-in, Method 1015
100% Final Electrical Screening +25°C, -55°C, +125°C
Monitors
100% External Visual, Method 2009
Group Inspection, Method 5005 Review Groups Quality Conformance Inspection Documentation
Pre-ship Inspection
Shipment
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Military Aerospace
6.1.2
CLASS
Figure 6-2. MIL-STD-883 Quality Conformance Inspection Method 5005
Standard Production Screen
D-1: Physical Dimensions Meth. 2016 B-2: Resistance Solvants Meth. 2015 D-2: Lead Integrity Meth. 2004, 2028 Seal1 Meth. 1014 B-5: Bond Strength Meth. 2011 D-5: Salt Atmosphere Meth. 1009, Seal Meth. 1014 B-3: Solderability Meth. 2003/2022 D-6: Internal Water Vapor Meth. 1018
Seal Test Meth. 1014
Baseline Electrical Parameters
C-1: Lifetest Meth. 1005 Endpt. Electrical
D-7: Adhesion Lead Finish Meth. 2025
Mechanical Series: Meth. 2002, Meth. 2007, Meth. 2001, Seal Meth. 1014 Meth. 1010/1011 Endpt. Electrical
D-3: Environmental/ Thermal Series Meth. 1011, cycles Meth. 1010, cycles Meth. 1004 Meth. 1004/1010 Seal Meth. 1014 Endpt. Electrical
D-8: Torque2 Meth. 2024
Sensitivity3: Meth. 2015 Endpt. Electrical 25°C
Notes: Required when package leads exit through glass-frit-seal. Required whenever glass seal used establish integrity hermeticity. ESDS characterization only.
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Section Cell Library
access cell data sheets ATL35 Series ASIC, click here.
Cell Library
Cell Parameters
Cell data sheets show logic symbol, truth table, schematic, timing information. data included cell timing information explained detail below. This cell data sheet format used Atmel ASIC libraries. Gates: Lists number gates cell occupies. This used designer determine what size array required design. gate four transistors. Loads: Lists capacitive load input represents. load used determine propagation delay driving cell. This covered timing section.
7.1.1
7.1.2
Fanout
output rise fall times approximated multiplying output drive slope with logic load. Rise fall times should kept below (nominal) regular nets. Clock nets should have (worst) faster input transition. DoubleCheck, Atmel's netlist checker, detects overloaded nets. timing tables give designer information needed estimate propagation delay based number loads cell driving. delay calculated using Delay Intercept (Slope Loads) where: Delay total propagation delay. Intercept base (zero loads) delay. Slope additional delay load. Load capacitance cell driving. Path "A->O" denotes delay from input output Path Timechk "D+CLK" denotes setup/hold requirement between inputs CLK.
7.1.3
Timing Estimation
Gate Count Estimation
most common method used estimate size gate array number gates. gate defined two-input NAND Atmel's library, NAN2. NAN2 uses four transistors. each Atmel gate array, there specified capacity that expressed number used gates. number used gates relationship total number available gates referred percent utilization. While this method size estimation widely used, inherently inaccurate. internally developed tool,
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Cell Library
size estimator, place calculate estimated size designs containing gates, cores, memories.
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Section Buffer Cell Library
Buffer Naming Convention
corner pads each reserved power ground only. other pads fully programmable input, output, bidirectional buffers, pads. Pullup, pulldown keeper terminators included input buffers. Output drive available stages, ATL25 buffers start with prefix. standard buffer naming convention detailed description each type follows. ATL25 Series CMOS gate arrays have been designed offer improved flexibility designer. Each site divided into subsections: output input with resistor. connected both subsections.
8.1.1
Site: Sub-Sections Input with Resistor Output sites configurable input, output, three-state output bidirectional buffers, each with pullup pulldown capability, required, utilizing their corresponding subsection. Bidirectional buffers result input output buffer placed adjacent subsections same site. Special buffers require multiple sites. Oscillators require sites; each power ground utilizes site. Refer specific buffer descriptions details.
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Buffer Cell Library
8.1.2
Input Buffers
{ClD} [V[5]]
Inversion Tolerant Input Option; Combine with Compliant Outputs Schmitt Trigger CMOS; Differential
Pinlist: External Output Signal into Array
Note:
names capitalized alphanumeric. required optional integer value
ATL25 CMOS input buffers available with pullup, pulldown keeper functions electrically programmable from control pins buffer. 8.1.3 Output Buffers
{1-C {1-C [V[5]] [FlS[#]] (1-9) Slew Index Scale Fast, Slow Slew Inversion Tolerant Option, Compliant Output Option Value: convert decimal n-channel output drive Value: convert decimal channel output drive
Current Multiplier Pinlist: Standard Tolerant datasheet datasheet Compliant
External Output Data from Array 3-state Enable
Note:
names capitalized alphanumeric. required optional integer value
output buffers drive current range from increments. standard output buffers have three-state capability combined with input pullup, pulldown keeper terminator. addition, slow fast slew configurations available low-noise high-performance applications, respectively. outputs 3-volt tolerant operated volts.
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ATL25 Series
Buffer Cell Library
8.1.4
Transmission Line/Impedance Matching Outputs
[VlLS]
Inversion Higher External Voltage Tolerance Level Shift Higher External Voltage Compliance Value Series Resistor
Pinlist: External Output Data from Array Three-state Enable
Note: names capitalized alphanumeric. required optional integer value
8.1.5
Bidirectional Buffers Bidirectional buffers combination input output buffers placed same site. bidirectional buffer requires separate instances input output buffers design netlist physically only utilizes site.
Phase-Locked Loops
Atmel offers several phase-locked loops (PLLs) designed compatible with ATL25 library. These PLLs generate digital clocks that aligned phase frequency with input reference clocks. Typical applications include frequency synthesis zero-delay clock buffers. Most requirements with only metal personalization (thus, there additional mask requirements when adding most PLLs ASIC). loop filter (capacitors resistor) have off-chip gate array implementation on-chip, using embedded array. Therefore, custom masks required when adding most PLLs ASIC. (PLLs with on-chip bias capacity will require custom mask.) following diagram shows phase-locked loop configured clock synthesis. block composed three main functions: phase frequency detector (PFD), charge pump-based loop filter, voltage-controlled oscillator (VCO). MUX1 included testability will discussed later. PLL's function generate oscillator clock (Oscclk') such that phase frequency alignment with input reference clock (Refclk'). Note that Oscclk' Oscclk/N Refclk' Refclk/M.
8.2.1
Overview
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Buffer Cell Library
Figure 8-1. In-Clock Frequency Synthesis Configuration
Oscclk Refclk
Oscclk MUX1
Refclk
Oscclk Down
Refclk
Down Charge Pump Bias Bias RVCO Loop Fltr
Bias
Bias
Note:
Capacitor noise suppression usually smaller than CL1. Phase alignment based positive edges Oscclk' Refclk'. Negative edge alignment available upon request.
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Buffer Cell Library
8.2.2
Functional Description
maintains phase frequency alignment between Refclk' Oscclk'. This process starts comparing clocks input PFD. digital block that will send DOWN signals charge pump depending phase difference between clocks. charge pump will then either remove charge from capacitor CL11, adjusting voltage input VCO. frequency will then either increase decrease lock onto reference clock (XN). This cycle continues until Refclk' Oscclk' have matching phase frequency. When Refclk' Oscclk' aligned, will stop sending DOWN signals charge pump. charge pump will longer charge discharge will maintain previously frequency.
8.2.3 8.2.3.1
Applications Clock Frequency Synthesis
common applications discussed here. commonly used generate clock signals given frequency from stable clock reference. example, using crystal oscillator reference, additional clock generated through PLL. Figure page shows this would implemented. reference clock from crystal oscillator (Refclk) MHz, Refclk' could divided setting will align Oscclk' with Refclk' MHz. order achieve Oscclk, working backwards, should From above example seen that Oscclk (N/M)*Refclk. Thus, used generate clock different (usually higher) frequency than input reference clock.
8.2.3.2
Zero Delay Buffer
Figure page shows application zero delay buffer. this application, Clock' incoming clock signal that drives clock tree gate array/embedded array. used eliminate delay from node Clock' output clock tree buffering Bufclk. Again, Clock' incoming clock signal that been buffered CMOS-level input buffer. This signal into reference clock (Refclk). output feeds through clock tree buffering flip-flops ends clock tree. will generate Bufclk such that phase frequency alignment with Clock'. feeding clock tree into PLL, Bufclk will phase frequency aligned with Clock'. Thus there zero delay from Clock' Bufclk. important limitation this circuit that Clock/Clock' must always running. Clock/Clock' stops running, will continue generate Bufclk unknown frequency. Figure 8-2. Zero Delay Buffer
Clock Tree Buffering Clock
CMOS
Refclk
Clock' PLLOUT Bufclk Oscclk
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Buffer Cell Library
8.2.3.3
Design Requirements Recommendations
requires five adjacent pins. These pins VDD, VSS, VCOBIAS, CPBIAS LOOPFLTR. Figure page Rvco required generate reference currents inside charge pump. required create second-order loop filter. pins that isolated from digital pins required. Bypass capacitor recommended reduce supply noise PLL. clean power supply important reduce jitter Oscclk.
8.2.3.4
Choosing
There several parameters PLL. These parameters include lock time, natural frequency (also known bandwidth), damping factor, Atmel engineer will involved selecting design suit your needs. minimum, following information required when requesting PLL.
Parameter Junction temperature range Supply voltage (including tolerance) Refclk frequency Oscclk frequency (clock divider value) (clock divider value) Required lock time Application Requirements -40°C 125°C 2.5V kHz-100 MHz-600 300µs Frequency synthesis, delay cancellation, synchronization
8.2.3.5
Testability
PLLs implemented Atmel's gate array technology will tested digital test equipment. following recommended methods testing PLL. output must bypassed during digital test. digital test equipment must have direct control clocks order properly test ASIC. this reason, MUX1 been added allow component bypassed controlled directly digital test equipment. CPBIAS signal controls select line MUX1. With CPBIAS (RCP connected between CPBIAS GND), output passed through Oscclkout. During production test, CPBIAS forced high (logical) allow REFCLK pass through Oscclkout.
8.2.3.5.1 Bypassing Clock
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ATL25 Series
Buffer Cell Library
Figure 8-3. Clock Synthesis Configuration Modified Testability
Oscclkout
8.2.4
Testing Charge Pump
charge pump portions tested through additional PLL(Phase-Locked Loop Test Mode). PLLcan either additional gate array/embedded array internal programmable register bit. PLLis forced logic during this test, connected from CPBIAS (thus selecting MUX1). this configuration, digital test equipment control Oscclk' Refclk' pins PLL. Note that TSTCLK created feeding functional input (that have some other purpose when test mode) into input MUX2. Figure 8-4, CP/PFD Test Waveforms, shows waveforms that must applied Oscclk' Refclk' Test purpose this test charge from VDD/2 some known period time. doing this, Charge Pump will verified proper functionality. Test works follows. Oscclk' Refclk' held low. digital test equipment will also force LOOPFLTR GND, thus discharging CL1. digital test equipment will release LOOPFLTR. Refclk' starts toggling. This will trigger charge pump start forcing current into LOOPFLTR. voltage LOOPFLTR will increase linearly from this point time digital test equipment will measure voltage LOOPFLTR ensure achieved VDD/2. clock period Refclk' time design specific will provided Atmel design engineer. Figure 8-4. CP/PFD Test Waveforms
8.2.4.1
CPPFD Test
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Buffer Cell Library
8.2.4.2
CP/PFD Test
Figure 8-5, CP/PFD Test Waveforms, shows waveforms that must applied Oscclk' Refclk' Test purpose this test discharge from VDD/2 some known period time. This test works same Test except that charge pump will sink current from LOOPFLTR instead sourcing Figure 8-5. CP/PFD Test Waveforms
8.2.5
Testing
Figure page shows additional circuit that used testing frequency VCO. counter used determine much time required have positive transitions. Knowing time number transitions, frequency determined. test works following way. VDD/2 volts forced into LOOPFLTR PLLis forced low. will start oscillating center frequency. known time (t1), PLLwill transition from high. From this point digital test equipment will observe TERMCNT until transitions from high time frequency will t1)/Y. Note that TERMCNT does have dedicated gate array/embedded array. PLLsignal used multiplex TERMCNT with functional output pin. Also, recommended value will provided Atmel design engineer.
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ATL25 Series
Buffer Cell Library
Table 8-1. Volt Buffer Cell Index
Cell Name PICI PICS PICSI PO11 PO11 PO22 PO22 PO33 PO33 PO44 PO44 PO55 PO55 PO66 PO66 PO77 PO77 PO88 PO88 PO99 PO99 POAA POAA POBB POBB POCC POCC Timing Description Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
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Buffer Cell Library
8-10
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ATL25 Series
Section Compiled Gate Level SRAMs
Overview
Atmel offers variety compiled personalization RAMs ATL25 series gate arrays. These static asynchronous SRAMs utilize personalization layers occupy standard gate array sites. SRAMs come either two-port single-port architectures. two-port SRAMs have sets address inputs: read address write address. output SRAM word that pointed read address. When Write Enable (WE) input goes low, word written address specified write address. single-port SRAMs have address inputs that controls both write read operations. output SRAM always word that pointed address inputs. When input goes low, word written address specified address input. Both single-port two-port SRAMs have enables their outputs. outputs stay high while output enable signal high. SRAMs compiled depths ranging from words. following tables give size information some common SRAM sizes. Note that site count listed tables includes unusable sites immediately around SRAM. Contact Atmel exact size SRAM listed.
9.1.1
SRAM Loading
Single-port SRAM Inputs LOADS (unit loads): 4.0; 4.0; 4.0; 4.0; 4.0; 4.0; 4.0; Two-port SRAM Inputs LOADS (unit loads): 4.0; 4.0; 4.0; 4.0; 4.0; 4.0; 4.0; 4.0; 4.0; 4.0; 4.0; 4.0;
ATL25 Series
2041B-ASIC-03/06
Compiled Gate Level SRAMs
Table 9-1. Common Single-Port SRAM Sizes
SRAM Width (bits) sites PRAM4X8 sites PRAM8X8 Depth (words) sites PRAM12X8 sites PRAM16X8 1316 sites PRAM24X8 1708 sites PRAM32X8 PRAM32X12 PRAM32X16 PRAM32X24 PRAM32X32 PRAM24X12 2196 sites PRAM24X16 2684 sites PRAM24X24 3660 sites PRAM24X32 4636 sites PRAM16X12 1692 sites PRAM16X16 2068 sites PRAM16X24 2820 sites PRAM16X32 3572 sites PRAM12X12 1188 sites PRAM12X16 1452 sites PRAM12X24 1980 sites PRAM12X32 2508 sites PRAM8X12 sites PRAM8X16 1144 sites PRAM8X24 1560 sites PRAM8X32 1976 sites PRAM4X12 sites PRAM4X16 sites PRAM4X24 1140 sites PRAM4X32 1444 sites sites sites sites sites
Table 9-2. Common Two-Port SRAM Sizes
SRAM Width (bits) DEPTH (words) sites PRAM4X8R1W1 sites PRAM8X8R1W1 sites PRAM12X8R1W1 1035 sites PRAM16X8R1W1 1455 sites PRAM24X8R1W1 1875 sites PRAM32X8R1W1 sites PRAM4X12R1W1 sites PRAM8X12R1W1 1045 sites PRAM12X12R1W1 1311 sites PRAM16X12R1W1 1843 sites PRAM24X12R1W1 2375 sites PRAM32X12R1W1 sites PRAM4X16R1W1 sites PRAM8X16R1W1 1265 sites PRAM12X16R1W1 1587 sites PRAM16X16R1W1 2231 sites PRAM24X16R1W1 2875 sites PRAM32X16R1W1 sites PRAM4X24R1W1 1271 sites PRAM8X24R1W1 1705 sites PRAM12X24R1W1 2139 sites PRAM16X24R1W1 3007 sites PRAM24X24R1W1 3875 sites PRAM32X24R1W1 1053 sites PRAM4X32R1W1 1599 sites PRAM8X32R1W1 2145 sites PRAM12X32R1W1 2691 sites PRAM16X32R1W1 3783 sites PRAM24X32R1W1 4875 sites PRAM32X32R1W1
example, shown below symbols single- two-port SRAMs (PRAM4X4 PRAM4X4R1W1). Important note: unused address inputs must tied SRAM will function properly (i.e., ADDR4 tied SRAMs words smaller, ADDR3 SRAMs words smaller, ADDR2 SRAMs words smaller, ADDR1 2word SRAM). This also true two-port memories.
2041B-ASIC-03/06
ATL25 Series
Compiled Gate Level SRAMs
Figure 9-1. Example Megacell Block Pinout
PRAM4X4SUB32
DIN0 DIN1 DIN2 DIN3 DOUT0 DOUT1 DOUT2 DOUT3
PRAM4X4DSUB32
BDIN0 BDIN1 BDIN2 BDIN3 ADOUT0 ADOUT1 ADOUT2 ADOUT3
Note:
must tied VSS, since this block depth
9.1.2
PRAM48X4
SRAMs multiplexed create deeper SRAM. example build single-port SRAM shown below.
A5BAR DIN0 DIN1 DIN2 DIN3 DIN0 DIN1 DIN2 DIN3 DOUT0 DOUT1 DOUT2 DOUT3 NAN2H DOUT0 NAN2H DOUT1 NAN2H DOUT2 NAN2H
BUF2
BUF2 BUF2 BUF2
A5BAR INV2
BUF2
PRAM32x4
DOUT3
INV2
DIN0 DIN1 DIN2 DIN3
INV2 INV2 INV2 INV2
VSS!
DOUT0 DOUT1 DOUT2 DOUT3
PRAM16x4
A5BAR
ORR2
ORR2
following pages contain SRAM write read timi

Section ATL35 Series Description .1-1 Design .1-3 Design Flow Too

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