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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface

XAPP349 (v1.3) March 25, 2005

Application Note: CoolRunner CPLD
CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
XAPP349 (v1.3) March 25, 2005
Summary
Introduction
An interface to the 8051 microcontroller has been implemented in a CoolRunner XPLA3 CPLD. This design consists of a state machine that interprets the 8051 bus cycles to read and write data to a set of registers called a register file. A high-level block diagram is shown in Figure 1. Communication between the 8051 microcontroller and the application logic is accomplished through a register file. The 8051 microcontroller writes data to the register file to configure and control the application logic. The application logic writes status information and service requests to the microcontroller through the register file. Data transfer is also done through registers. Flags can be designed that denote when registers are empty and / or full depending on the application. The number of registers and their bit definitions are defined in general terms and should be customized for the application.
CoolRunner CPLD
Address Microcontroller Data Control Microcontroller Interface Register File Application Logic
Figure 1: CoolRunner CPLD 8051 Microcontroller Interface
8051 Microcontroller Bus Protocol
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Microcontroller
Address the Device
Peripheral
Decode the Address
1. Latch the address 2. Decode the address and determine if the CPLD is being addressed
Transfer Data
Terminate Transfer
Terminate the Cycle
Start Next Cycle
Figure 2: 8051 Bus Protocol for External Memory Accesses
Bus Cycle Timing Diagrams
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TLLDV TRLRH
TRLAZ
TRLDV
TRHDZ DATA IN
TWLWH
TQVWX DATA OUT
TWHDX
Figure 4: 8051 Microcontroller External Data Memory Write Cycle
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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
CoolRunner CPLD 8051 Microcontroller Interface Signals
Input
Input Input Output
CLK RESET
Input Input
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XAPP349 (v1.3) March 25, 2005
CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
CoolRunner CPLD Block Diagram
The block diagram of the CoolRunner CPLD 8051 Interface consists of address decode logic, a bus interface state machine, interrupt logic, user definable registers, and a data out multiplexor to supply the requested data during a read cycle as shown in Figure 5.
Data from Application Logic
Address / Decode Logic
Register 0
Bus Interface State Machine
Register 0
Interrupt Logic
Register N
Data Out Mux / Register
Figure 5: CoolRunner CPLD 8051 Microcontroller Interface Block Diagram
Address Decode Logic
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Bus Interface State Machine
The 8051 µC bus protocol is implemented in the state machine shown in Figure 6.
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Register File
Example Status Register
This register is an example status register containing the status of a typical application. This status register is read-only with the exception of certain bits which are software clearable as described in Table 4. Note that for software testability, it may be determined that all bits of the
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Read Software Clearable
Unused
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XAPP349 (v1.3) March 25, 2005
CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
Example Control Register
Read / Write
Example Data Input Register
Example Data Output Register
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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
Application Logic
The CoolRunner CPLD 8051 Microcontroller Interface is intended to be used as a front end to additional application logic. The preceding paragraphs have described the code available to implement this interface however, modifications to the address decode logic, device and register addresses, and register definitions will be required to suit the application.
VHDL Testbench and Functional Simulation
CoolRunner XPLA3 CPLD Implementation
The CoolRunner 8051 Microcontroller Interface utilizes only 57 macrocells and has been targeted to a XPLA3 64 macrocell device. The speed grade chosen is dependent on the system clock frequencies and should be analyzed by the designer to determine which speed grade is required. Once application logic has been added to the design, the user should target a CoolRunner CPLD with enough macrocells to accommodate the 8051 Microcontroller Interface described in this application note and the required application logic.
Post-fit Timing Simulation
VHDL Code Download and Disclaimer
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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. THIRD PARTIES MAY HAVE PATENTS ON THE 8051 MICROCONTROLLER BUS. BY PROVIDING THIS HDL CODE AS ONE POSSIBLE IMPLEMENTATION OF THIS STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THE PROVIDED IMPLEMENTATION OF THE 8051 MICROCONTROLLER BUS IS FREE FROM ANY CLAIMS OF INFRINGEMENT BY ANY THIRD PARTY. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY OR CONDITIOns, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE, THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OR REPRESENTATION THAT THE IMPLEMENTATION IS FREE FROM CLAIMS OF ANY THIRD PARTY. FURTHERMORE, XILINX IS PROVIDING THIS REFERENCE DESIGns "AS IS" AS A COURTESY TO YOU. XAPP349 - http://www.xilinx.com / products / xaw / coolvhdlq.htm
Conclusion
This document has detailed the design of a 8051 microcontroller interface for a CoolRunner XPLA3 CPLD. Though the design has been extensively verified in simulations, Xilinx assumes no responsibility for the accuracy or the functionality of this design.
Revision History
The following table shows the revision history for this document. Date 12 / 07 / 00 10 / 01 / 02 01 / 15 / 03 03 / 25 / 05 Version 1.0 1.1 1.2 1.3 Initial Xilinx release. Minor revisions. Minor revisions. Fixes to PDF only. Revision
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