XAPP349 (v1.3) March 2005 Summary This document details VHDL

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XAPP349 (v1.3) March 2005 Summary This document details VHDL

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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
XAPP349 (v1.3) March 2005
Summary
This document details VHDL implementation 8051 microcontroller interface Xilinx CoolRunnerXPLA3 CPLD. CoolRunner XPLA3 CPLDs lowest power CPLDs available, making these CPLDs perfect interface devices many today's popular microcontrollers. obtain VHDL code described this document, section VHDL Code Download Disclaimer, page instructions. implementation with CoolRunner-IICPLD, refer XAPP393 found http://www.xilinx.com.
Introduction
interface 8051 microcontroller been implemented CoolRunner XPLA3 CPLD. This design consists state machine that interprets 8051 cycles read write data registers called register file. high-level block diagram shown Figure Communication between 8051 microcontroller application logic accomplished through register file. 8051 microcontroller writes data register file configure control application logic. application logic writes status information service requests microcontroller through register file. Data transfer also done through registers. Flags designed that denote when registers empty and/or full depending application. number registers their definitions defined general terms should customized application.
CoolRunner CPLD
Address Microcontroller Data Control Microcontroller Interface Register File Application Logic
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Figure CoolRunner CPLD 8051 Microcontroller Interface
8051 Microcontroller Protocol
This section describes main protocol 8051 microcontroller bus. more details specific timing parameters, please refer supplier's datasheet 8051 microcontroller chosen system. 8051 executes synchronous cycles, there handshaking between peripheral microcontroller. 8051 microcontroller utilizes multiplexed address/data through PORT falling edge Address Latch Enable (ALE_N) used
2005 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, further disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice. NOTICE DISCLAIMER: Xilinx providing this design, code, information is." providing design, code, information possible implementation this feature, application, standard, Xilinx makes representation that this implementation free from claims infringement. responsible obtaining rights require your implementation. Xilinx expressly disclaims warranty whatsoever with respect adequacy implementation, including limited warranties representations that this implementation free from claims infringement implied warranties merchantability fitness particular purpose.
XAPP349 (v1.3) March 2005
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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface capture lower address byte from PORT0 that port then used data transfer. Program Store Enable (PSEN_N) only asserted accesses read-only program memory thus remains negated during external memory read write cycles. Figure shows flow chart operations that occur when 8051 accesses peripheral.
Microcontroller
Address Device
Place high byte address ADDR[15:8] Place byte address ADDR_DATA[7:0] Assert Address Latch Enable (ALE_N) Negate Program Store Enable (PSEN_N)
Peripheral
Decode Address
Latch address Decode address determine CPLD being addressed
Transfer Data
Remove data from ADDR_DATA{7:0] write cycle, place data ADDR_DATA[7:0] assert Write Strobe (WR_N) read cycle, assert Read Strobe (RD_N)
Transfer Data
write cycle, latch data ADDR_DATA[7:0] into addressed register read cycle, output data from addressed register ADDR_DATA[7:0]
Terminate Transfer
write cycle, negate Write Strobe (WR_N) then remove data from ADDR_DATA[7:0] read cycle, latch data from ADDR_DATA{7:0] then negate Read Strobe (RD_N)
Terminate Transfer
read cycle, remove data from ADDR_DATA[7:0]
Terminate Cycle
Remove Address Latch Enable (ALE_N)
Start Next Cycle
X349_02_112500
Figure 8051 Protocol External Memory Accesses
Cycle Timing Diagrams
numerical values parameters shown these timing diagrams provided. data sheet 8051 used system must consulted these parameters. External Memory Read Cycle external memory read cycle (Figure PORT0 contains address target peripheral TAVLL before ALE_N asserts. address held PORT0 TLLAX then 3-stated TRLAZ before RD_N asserts. Once RD_N asserts, addressed peripheral drive requested data onto bus. This data must valid TRLDV after RD_N
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XAPP349 (v1.3) March 2005
CoolRunner XPLA3 CPLD 8051 Microcontroller Interface asserts. microcontroller negates RD_N after retrieved data from ends cycle negating ALE_N.
ALE_N TWHLH PSEN_N TLLWL RD_N TAVLL PORT TLLAX A[7:0] TAVOV TAVWL PORT A[15:8]
X349_03_112500
TLLDV TRLRH
TRLAZ
TRLDV
TRHDZ DATA
Figure 8051 Microcontroller External Data Memory Read Cycle External Memory Write Cycle External memory write cycles (Figure quite similar external memory read cycles with exception: instead 3-stating PORT after address been latched, data written addressed device placed PORT TQVWX before WR_N asserts. WR_N then asserts held TWLWH After WR_N negates, data held PORT TWHDX cycle ends with negation ALE_N.
ALE_N TWHLH PSEN_N TLLWL WR_N TAVLL PORT TLLAX A[7:0] TAVWL PORT A[15:8]
X349_04_112500
TWLWH
TQVWX DATA
TWHDX
Figure 8051 Microcontroller External Data Memory Write Cycle
XAPP349 (v1.3) March 2005
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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
CoolRunner CPLD 8051 Microcontroller Interface Signals
signals CoolRunner CPLD 8051 microcontroller interface described Table numbers have been assigned this design, this done meet system requirements designer. Table CoolRunner CPLD 8051 Interface Signal Description Name ADDR[15:8] ADDR_DATA[7:0] ALE_N Direction Input Bidirectional Input Description Address Bus. High byte address bus. Multiplexed Address/Data Bus. Address Latch Enable. Active control signal indicating that data present multiplexed address/data valid address. Program Store Enable. Active control signal indicating that current cycle access external program memory. Read Strobe. Active control signal indicating that current cycle read cycle. Write Strobe. Active control signal indicating that current cycle write cycle. Interrupt Request. Active signal generate interrupt This signal asserted based application logic. Clock. This clock input from system. Reset. Active High reset from system. When asserted, logic CoolRunner CPLD reset.
PSEN_N
Input
RD_N WR_N INT_N
Input Input Output
RESET
Input Input
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XAPP349 (v1.3) March 2005
CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
CoolRunner CPLD Block Diagram
block diagram CoolRunner CPLD 8051 Interface consists address decode logic, interface state machine, interrupt logic, user definable registers, data multiplexor supply requested data during read cycle shown Figure
Data from Application Logic
ADDR[15:8] ALE_N PSEN_N
Address/Decode Logic
reg_en[N:0]
reg_en0 WR_N data_trs
Register
data_trs data_oe Data Application Logic
X349_05_112500
Interface State Machine
reg_en1 WR_N data_trs
Register
WR_N RD_N INT_N
Interrupt Logic
ADDR_DATA[7:0]
reg_en1 WR_N data_trs
Register
data_trs RD_N reg_en[N:0]
Data Mux/Register
Figure CoolRunner CPLD 8051 Microcontroller Interface Block Diagram
Address Decode Logic
CoolRunner CPLD 8051 Microcontroller Interface logic decodes upper address byte present ADDR device address. This address compared constant BASE_ADDR VHDL code determine whether device being addressed not. upper address byte equal BASE_ADDR, ADDR_MATCH signal asserted. address decode logic also contains registers clocked ALE_N capture lower address bits from multiplexed ADDR_DATA bus. This lower address byte represents addresses registers register file. This allows possibility registers register file even addresses allowed, registers only even addresses allowed. current implementation VHDL code instantiates four registers even addresses. lower address byte compared register address constants VHDL code. there match, register enable register being addressed asserted.
XAPP349 (v1.3) March 2005
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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface address decoding implemented VHDL code must modified addressing scheme system. address bits that represent device address address bits that represent register address within device must also adjusted system requirements. These parameters modified changing constants shown Table VHDL code. Table Address Decode Parameters Constant BASE_ADDR DEVICE_ADDR_BITS REG_ADDR_BITS Description Device Address Number address bits used decode device address Number address bits used decode register addresses Default Value 00\h
Interface State Machine
8051 protocol implemented state machine shown Figure
IDLE
ale_n=0 psen_n=1
addr_match=0
ADDrd_n=0 wr_n=0 addr_match=1 rd_n=0 wr_n=0
DATA_TRS
rd_n=1 wr_n=1 ale_n=1
END_CYCLE
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Figure Interface State Machine first cycle, places address address asserts address latch enable (ALE_N). ALE_N indicates that data multiplexed address/data valid address that address ADDR[15:0] also valid. Upon assertion ALE_N, state machine transitions ADDR_DECODE state wait ADDRESS/DECODE logic decode address determine device being addressed. this write cycle, removes address from multiplexed address/data places data written onto these signals. write strobe (WR_N) then asserted. this read cycle, 3-states multiplexed address/data asserts read strobe (RD_N) indicating that CoolRunner CPLD place data from addressed register data bus. CoolRunner CPLD being addressed either RD_N WR_N asserted, state machine progresses DATA_TRS state. this read cycle, requested data placed this write cycle, data from data latched addressed register. latches data present this read cycle then negates read strobe (RD_N). this write cycle, removes data from then negates write strobe (WR_N). negation either RD_N WR_N causes state machine
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XAPP349 (v1.3) March 2005
CoolRunner XPLA3 CPLD 8051 Microcontroller Interface progress END_CYCLE state. CoolRunner CPLD will 3-state multiplexed address/data this state, removing data read cycle.
this point, ends cycle negating address latch enable (ALE_N), which causes CoolRunner CPLD return IDLE state.
Register File
Register File consists bank registers used communication between 8051 application logic. These registers defined needed application. example, most applications require control register which sets certain required parameters such interrupt enables, start/stop, clock divisors, clock phases polarities, and/or master/slave operation. This register address then defined VHDL code 8051 reads writes this register configure application. Likewise, many applications required provide status information back 8051 such data error, data operation complete, data available, transmit buffer empty, etc. status register address then defined VHDL code 8051 reads possibly writes this register reset status conditions) determine application's progress status. registers currently implemented CoolRunner 8051 Microcontroller Interface described Table user will have examine VHDL code create registers required application define addressing scheme required system.The register definition will determine input register comes from 8051 data application logic. Once user defines registers required application, VHDL code available with this application note will need modified support correct register implementation. constants VHDL code representing register addresses will also need modified. Table Register File Addresses Address BASE $80\h BASE $82\h BASE $84\h BASE $86\h Register STATUS_REG CTRL_REG DATAIN_REG DATAOUT_REG VHDL Constant STATUS_ADDR CTRL_ADDR DATAIN_ADDR DATAOUT_ADDR Description Example Status Register Example Control Register Example Data Input Register Example Data Output Register
Example Status Register
This register example status register containing status typical application. This status register read-only with exception certain bits which software clearable described Table Note that software testability, determined that bits
XAPP349 (v1.3) March 2005
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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface status register writable, however, VHDL code available with this application note does support this. Table Example Status Register Bits Location Name DONE Access Read Description Done Bit. Data operation completed. operation complete operation progress ERROR Read Software Clearable Error Bit. error requiring 8051 interaction occurred. This will cause interrupt 8051 interrupts have been enabled control register. This reset when 8051 writes this bit. Interrupt Bit. This asserted (active high) when interrupt pending which causes processor interrupt request interrupts enabled (INT_EN set).This reset when 8051 writes this bit. Need Data Bit. This when data input register empty. cleared when writes data into data input register. interrupt will asserted when this interrupts enabled (INT_EN set). Data Ready Bit. This whenever data output register full. cleared when reads from data output register. interrupt will asserted when this interrupts enabled. Unused Bits. These bits will read when status register read.
Read Software Clearable
NEED_DATA
Read
DATA_RDY
Read
Unused
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XAPP349 (v1.3) March 2005
CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
Example Control Register
This register example control register providing bits configure control operation typical application. bits this register written read from 8051 shown Table Table Control Register Bits Location Name APP_EN Access Read/Write Description Application Enable. This enables user application logic must before other bits control register have effect enables user application resets disables user application INT_EN Read/Write Interrupt Enable. enables interrupts. interrupt occurs INT_N status register also disables interrupts does clear cause currently pending interrupts START Read/Write Application Start. When changes this from "1", application logic begins operation data provided DATA_IN register. Control Bits. These bits need defined user application.
CTRL_BIT
Read/Write
Example Data Input Register
This register example data input register containing data from 8051 that application performs some operation such transmission over bus. This data register both readable writable described Table Table Example Data Input Register Location Name DATA_IN Access Read/Write Description Data Input. Data byte from 8051 perform application's operation
Example Data Output Register
This register example data output register containing results data operation. This data register read only described Table Note that software testability, determined that bits data output register writable, however, VHDL code available with this application note does support this. Table Example Data Output Register Location Name DATA_OUT Access Read Only Description Data Output. Resulting data byte from application's operation.
XAPP349 (v1.3) March 2005
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CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
Application Logic
CoolRunner CPLD 8051 Microcontroller Interface intended used front additional application logic. preceding paragraphs have described code available implement this interface; however, modifications address decode logic, device register addresses, register definitions will required suit application.
VHDL Testbench Functional Simulation
VHDL testbench been developed that verifies CoolRunner 8051 Microcontroller Interface through various read write cycles. This testbench contains process that emulates cycles 8051 Constants provided testbench file base address CoolRunner CPLD registers contained within device. These constants should modified match addressing scheme designer's system. testbench also contains constant data arrays specification data input application logic expected data output from application logic. user needs modify constants these arrays size these arrays match cycles desired simulation. testbench contains dummy processes emulate application logic. These processes assert NEED_DATA DATA_RDY flags well provide load signal data output data registers. These processes should removed from testbench when application logic available. ModelSim command file, func_sim.do, used open correct waveform window simulation.
CoolRunner XPLA3 CPLD Implementation
CoolRunner 8051 Microcontroller Interface utilizes only macrocells been targeted XPLA3 macrocell device. speed grade chosen dependent system clock frequencies should analyzed designer determine which speed grade required. Once application logic been added design, user should target CoolRunner CPLD with enough macrocells accommodate 8051 Microcontroller Interface described this application note required application logic.
Post-fit Timing Simulation
Xilinx Project Navigator software package outputs timing VHDL model fitted design. This post-fit VHDL simulated with original VHDL test benches insure design functionality using ModelTech Xilinx Edition (MXE). Please note that verification this design been done through simulations. user this design strongly encouraged thoroughly inspect timing report this design insure that design meets timing specification system. user also strongly encouraged perform post-fit timing simulations well. ModelSim command file, post_sim.do, used open correct waveform window simulation.
VHDL Code Download Disclaimer
VHDL source code, VHDL testbenches, software files associated with this design available. Note that this reference design intended used front-end interface user's application logic. standalone design. Therefore, modifications VHDL code will required support addressing scheme, register structures, interrupt logic, process flow application. This VHDL code provided example that considered starting point your application. DESIGN PROVIDED IS". XILINX MAKES RECEIVE WARRANTIES CONDITIOns, EXPRESS, IMPLIED, STATUTORY OTHERWISE, XILINX SPECIFICALLY DISCLAIMS IMPLIED WARRANTIES MERCHANTABILITY, NON-INFRINGEMENT, FITNESS PARTICULAR PURPOSE. This design should used only example design, fully functional core. XILINX does warrant performance, functionality, operation this Design will meet your requirements, that operation Design will uninterrupted error free, that defects Design will
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XAPP349 (v1.3) March 2005
CoolRunner XPLA3 CPLD 8051 Microcontroller Interface
corrected. Furthermore, XILINX does warrant make representations regarding results Design terms correctness, accuracy, reliability otherwise. THIRD PARTIES HAVE PATENTS 8051 MICROCONTROLLER BUS. PROVIDING THIS CODE POSSIBLE IMPLEMENTATION THIS STANDARD, XILINX MAKING REPRESENTATION THAT PROVIDED IMPLEMENTATION 8051 MICROCONTROLLER FREE FROM CLAIMS INFRINGEMENT THIRD PARTY. XILINX EXPRESSLY DISCLAIMS WARRANTY CONDITIOns, EXPRESS, IMPLIED, STATUTORY OTHERWISE, XILINX SPECIFICALLY DISCLAIMS IMPLIED WARRANTIES MERCHANTABILITY, NON-INFRINGEMENT, FITNESS PARTICULAR PURPOSE, ADEQUACY IMPLEMENTATION, INCLUDING LIMITED WARRANTY REPRESENTATION THAT IMPLEMENTATION FREE FROM CLAIMS THIRD PARTY. FURTHERMORE, XILINX PROVIDING THIS REFERENCE DESIGns COURTESY YOU. XAPP349
Conclusion
This document detailed design 8051 microcontroller interface CoolRunner XPLA3 CPLD. Though design been extensively verified simulations, Xilinx assumes responsibility accuracy functionality this design.
Revision History
following table shows revision history this document. Date 12/07/00 10/01/02 01/15/03 03/25/05 Version Initial Xilinx release. Minor revisions. Minor revisions. Fixes only. Revision
XAPP349 (v1.3) March 2005
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XAPP349 (v1.3) March 2005 Summary This document details VHDL

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