Getting Started with Nucleus PLUS RTOS EDGE Tools MicroBlaze Processor

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Getting Started with Nucleus PLUS RTOS EDGE Tools MicroBlaze Processor

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XAPP1016 (v1.0) September 2007
Getting Started with Nucleus PLUS RTOS EDGE Tools MicroBlaze Processor
Author: Mounir Maaref
Abstract
This application note provides introduction Nucleus RTOS MicroBlazeprocessor using Xilinx Platform Studio (XPS) tools Mentor Graphics EDGE tools. This document tutorial building MicroBlaze hardware Nucleus Real Time Operating System, configuring (Board Support Package) within (Xilinx Platform Studio), using EDGE features, such application debug. target board this application note Xilinx SpartanTM-3E Starter board.
Included Systems Introduction
Included with this application note reference system:
This application note describes procedure required started with Nucleus PLUS RTOs. provides necessary tools setup required build debug Nucleus PLUS based software application targeting Xilinx MicroBlaze Embedded Processor.
Hardware Software Requirements
software requirements are: Mentor Graphics EDGE Tools Evaluation fully Licensed version MicroBlaze Nucleus PLUS Xilinx Platform Studio 9.1i with service packs later Xilinx ISE9.1i with service packs later HyperTerminal another terminal emulator
Hardware requirements are: Xilinx SpartanTM-3E Starter board RS232 Serial Cable Xilinx Parallel Cable Programming Cable
design ported MicroBlaze-capable board.
System Specifics
Nucleus PLUS product Accelerated Technology, Mentor Graphics Division. Nucleus PLUS real-time multitasking kernel. Approximately Nucleus PLUS written ANSI This portion PLUS identical across hardware platforms. Hardware dependent code limited three assembly code files header file.
2007 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, further disclaimers listed PowerPC trademark Inc. other trademarks registered trademarks property their respective owners. specifications subject change without notice. NOTICE DISCLAIMER: Xilinx providing this design, code, information is." providing design, code, information possible implementation this feature, application, standard, Xilinx makes representation that this implementation free from claims infringement. responsible obtaining rights require your implementation. Xilinx expressly disclaims warranty whatsoever with respect adequacy implementation, including limited warranties representations that this implementation free from claims infringement implied warranties merchantability fitness particular purpose.
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System Specifics
Nucleus PLUS RTOS Characteristics
Some Nucleus PLUS RTOS characteristics listed below. Small footprint High speed, multi-tasking kernel Scaleable hard real-time kernel Priority, pre-emptive scheduler Inter-task communication Inter-task synchronization memory management Dynamic creation deletion objects
Nucleus PLUS RTOS Components
main components Nucleus PLUS listed below. Common Services (CS) Initialization (IC) Thread Control (TC) Timer (TM) Mailbox (MB) Queue (QM) Pipe (PI) Semaphore (SM) Event Group (EV) Partition Memory (PM) Dynamic Memory (DM) Input/Output Driver (IO) History (HI) Error (ER) License (LI) Release (RL)
Nucleus PLUS RTOS Architecture
Nucleus PLUS RTOS requires periodic interrupt provide time-oriented services such time-slicing, service call time outs, application timers. default setup timer interrupt period. Nucleus RTOS designed used library. Nucleus services used inside application extracted from PLUS library combined with application objects produce complete executable image. files that access Nucleus PLUS services must include header file nucleus.h. Application_Initialize function starting point user application. Nucleus PLUS defines several standard data types include file nucleus.h. These data types guaranteed remain common across platforms assigning appropriate basic data type target compiler. This allows PLUS perform identical manner multiple platforms.
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Installing EDGE Environment MicroBlaze
Nucleus PLUS Integration Xilinx
Xilinx FPGAs embedded systems grows, need facilitate integration RTOS Design Flow into FPGA design cycles increases. Xilinx provides (Embedded Developers Kit) Tools with (Xilinx Platform Studio) user interface. Embedded Development (EDK) bundle integrated software solution designing embedded processing systems. This pre-configured includes Platform Studio tool suite (XPS) along with documentation that required designing Xilinx Platform FPGAs with embedded PowerPChard processor cores MicroBlaze soft processor cores, both. Microprocessor Library Definition (MLD) Technology used auto-customization libraries Board Support Package (BSPs). data-driven process based user supplied configuration parameters. supports specification specific requirements services support which data-driven capability that generates RTOS tailored defined platform. Xilinx includes device driver library definition commercial RTOS, such Nucleus. Nucleus provides device driver abstraction layer supported peripherals. Based user specification, (specifically LibGen Tools XPS) generates Nucleus corresponding hardware platform design.
Installing EDGE Environment MicroBlaze
Mentor Graphics EDGE Tools Overview
Mentor Graphics Embedded Developers Graphical Environment (EDGE) Tools comprehensive embedded tools environment based Eclipse. EDGE provides specialized Perspectives such Project Perspective which fully featured project management solution, builder with support multiple tool chains, source control, including Debug Perspective. This provides fully featured debugger with kernel awareness tailored embedded applications, including Profiler Perspective, feature rich source profile.
Getting Nucleus PLUS MicroBlaze
Nucleus MicroBlaze provided Mentor Graphics available from Mentor Graphics site Getting EDGE Tools Evaluation Version MicroBlaze Mentor Graphics provides evaluation version EDGE Tools MicroBlaze which downloaded from Mentor Graphics site
Installing EDGE Evaluation Version Tools License
Once request access EDGE Tools been done, confirmation E-mail which includes license.zip archive sent. install, following steps. Extract license.zip archive directory. Copy demo_license.txt root directory downloaded extracted EDGE installation files. Launch EDGE Tools setup.exe installer follow instructions install EDGE Tools.
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Installing EDGE Environment MicroBlaze evaluation license installed configured EDGE installer. When Nucleus EDGE launched first time, required tools (Xilinx MicroBlaze Toolset v9.1) must enabled Nucleus EDGE preferences. Under Windows Preferences menu, select Nucleus EDGE Builder Toolsets enable appropriate check box. Confirm setup clicking
Installing Nucleus PLUS MicroBlaze
file, contains auto installer Nucleus PLUS builder required Nucleus PLUS Library MicroBlaze. Unzip File temporary directory executable install Nucleus PLUS MicroBlaze. Nucleus PLUS fully-functional version RTOS compiled into library format (rather than normal source code distribution) with single restriction will stop working after minutes, thus facilitating evaluation full functionality. With purchase full license Nucleus PLUS from Mentor Graphics, full source code with time restriction provided. Nucleus PLUS RTOS configured execute from off-chip SRAM SDRAM/DDR module. Once full license RTOS available, configured from memory system. other Nucleus products provided with 9.1i consists fully functional product compiled into library format. Nucleus products contain robust support Xilinx technology. With Nucleus evaluation, configuration options within Library/OS Parameters Software Platform Settings dialog functional. This restriction removed when full version purchased.
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Creating MicroBlaze System Nucleus RTOS
Once Nucleus PLUS builder been run, will install necessary Tools into \edk_user_repository\. Figure shows layout created directories under:
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Figure Nucleus PLUS Directory Layout
Creating MicroBlaze System Nucleus RTOS
Using Base System Builder create Embedded System
FPGA based Embedded System consists following Peripherals:. MicroBlaze processor with Kbyte instruction data caches 8-KB Local on-chip memory (LMB) shared between instructions data sides MicroBlaze processor controller on-board SDRAM controller on-board flash memory timer UART input/output user interface interrupt controller with connection MicroBlaze system debug
design above system with EDK, Base System Builder used described Figure through Figure Figure shows launch Wizard.
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Creating MicroBlaze System Nucleus RTOS When first launched, click Figure launch BSB. already open, select File from menu, then Project launch Wizard.
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Figure Launching Wizard Figure shows start design using Wizard.
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Figure Starting Nucleus PLUS Platform design using
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Creating MicroBlaze System Nucleus RTOS Figure illustrates select Spartan3E Starter Board target board.
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Figure Spartan-3E Starter Board Selection Wizard
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Creating MicroBlaze System Nucleus RTOS Figure shows configure MicroBlaze processors some system features.
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Figure Setting MicroBlaze Soft Processor
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Creating MicroBlaze System Nucleus RTOS Figure shows select UART Lite peripheral setup parameters.
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Figure UART Lite Selection Setup
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Creating MicroBlaze System Nucleus RTOS Figure illustrates select interface flash memory.
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Figure Selection
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Creating MicroBlaze System Nucleus RTOS Figure shows select peripheral interface SDRAM Memory.
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Figure Controller Selection
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Creating MicroBlaze System Nucleus RTOS Figure shows Timer system.
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Figure Adding Timer System
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Creating MicroBlaze System Nucleus RTOS Figure shows configure timer.
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Figure Configuring Timer Figure shows setup MicroBlaze caches. Cache Size allowed value selected depending Application needs available BRAM resources target FPGA.
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Figure Configuring MicroBlaze Caches
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Creating MicroBlaze System Nucleus RTOS Figure shows generated system.
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Figure Generated System
Configuring generated System
this stage, required design Nucleus PLUS RTOS based applications almost finished. decrease download time application images JTAG cable system main memory, optional (Fast Simplex Link) added system. This Link point point connection between MicroBlaze soft processor peripheral. used download Link customize some other features MicroBlaze soft processor.
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Creating MicroBlaze System Nucleus RTOS This download feature enabled MicroBlaze soft processor adding Slave interface core shown Figure Figure shows customize MicroBlaze soft core features using XPS.
access this GUI, System Assembly view, double-click microblaze_0 processor instance, then select Enable Barrel Shifter.
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Figure Customizing MicroBlaze Core
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Creating MicroBlaze System Nucleus RTOS Figure shows Slave interface MicroBlaze soft core. same shown Figure select Buses tab, select Number Links field.
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Figure Adding Interface MicroBlaze Soft Core
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Creating MicroBlaze System Nucleus RTOS Figure shows enable Fast Download Link Core. System Assembly view, double-click debug_module instance. Check Enable Fast Download Write Port.
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Figure Enabling JTAG Fast Download Link
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Creating MicroBlaze System Nucleus RTOS Figure shows System. Catalog tab, right click Fast Simplex Link (FSL) Bus, then System Assembly view.
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Figure Adding Link System Figure shows connect added Link MicroBlaze soft core slave interface master interface.
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Figure Making Connections JTAG Fast Download
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Creating MicroBlaze System Nucleus RTOS
Implementing Design
XPS, select Device Configuration Update Bitstream generate download.bit bitstream. This FPGA Bitstream version auto-generated TestApp_Memory Standalone Application Executable initialization file embedded inside MicroBlaze BRAM memory. Upon FPGA configuration, this application executed MicroBlaze processor test SDRAM memory starter kit. Start HyperTerminal session with following settings. com1 Bits second: 9600 Data bits: Parity: none Stop bits: Flow control: none Download bitstream Device Configuration Download Bitstream. memory test output appears HyperTerminal shown Figure
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Figure Running TestApp_Memory Starter Another bitstream version generated. This version will include simple BootLoop only initialization file MicroBlaze BRAM Memory. Select microblaze_0_bootloop application block initialization, deselect TestApp_Memory application from block initialization. Select Device Configuration Update Bitstream generate download.bit. Download bitstream Device Configuration Download Bitstream.
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Configuring
Configuring
this stage Platform been built generated automatically using Libgen Mentor Graphics based builder previously installed into /edk_user_repository/.
Setting File
first step generation process configure Microprocessor Software Specification (MSS) file. Software Platform Setting used configuring Nucleus PLUS system. launch Software Platform Setting, select Software Software Platform Setting. Figure shows Software Platform Settings window. Processor Parameters subwindow, MicroBlaze core clock frequency value select Nucleus PLUS Library Settings sub-window.
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Figure Core Clock Frequency Setup RTOS Selection
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Configuring Select Libraries Tab, then configure Nucleus shown Figure this window, Nucleus Library Services included excluded according Application needs. Template Projects services Demos could also requested this stage. default, every Nucleus Library Service Demo Project selected.
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Figure Nucleus PLUS Configuration
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Configuring Figure shows Serial Driver.
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Figure Nucleus PLUS Serial Drivers Configuration
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Configuring Figure shows some Nucleus PLUS Library setup features.
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Figure Nucleus PLUS Library Setup Click save configuration Nucleus PLUS settings file.
Generating Nucleus PLUS Libraries
this stage Nucleus PLUS Libraries generated running Libgen from Software Generate Libraries BSPs.
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Configuring Once LibGen run, Nucleus Source Code Configuration Wizard launched automatically shown Figure Other Nucleus Services configured they were selected during setup process.
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Figure Nucleus Source Code Configuration Wizard Click Next reach last screen generation Wizard.
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Creating Nucleus Project EDGE
Creating Nucleus Project EDGE
Once Generate Libraries BSPs step completed XPS, nucleus folder created under Processor Instance Name (microblaze_0) folder within Project directory. Figure shows hierarchy created folder. Under plus folder, EDGE Template Project tailored associated Project created. This Template Project used starting point Application development process.
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Figure Nucleus PLUS Folder layout
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Creating Nucleus Project EDGE
Building Application EDGE
plus_demo EDGE project used. Launch EDGE software, then select Workspace EDGE, necessary, shown Figure
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Figure Launching EDGE Specifying Workspace
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Creating Nucleus Project EDGE Import plus_demo project EDGE Workspace illustrated Figure Figure
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Figure Importing existing EDGE Project into Workspace Step-1
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Figure Importing Existing EDGE Project into Workspace Step-2
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Creating Nucleus Project EDGE Specify plus_demo project directory import into Workspace shown Figure Figure
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Figure Specifying plus_demo Project Directory Step-1
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Figure Specifying plus_demo Project Directory Step-2
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Creating Nucleus Project EDGE Click Finish. this stage Project built EDGE shown Figure
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Figure Building plus_demo Project EDGE
Downloading Nucleus PLUS Applications target using
this stage Nucleus PLUS image downloaded target test system functionality. (Xilinx Microprocessor Debugger) used download image SDRAM memory Spartan-3E Starter Kit. tool that facilitates program debugging system verification using PowerPC405GP (Virtex-II Virtex-4) MicroBlaze microprocessors. debug programs running hardware board, Cycle-Accurate Instruction Simulator (ISS), MicroBlaze Cycle-Accurate Virtual Platform (VP) system. provides Tool Command Language (Tcl) interface which used command line control debugging target, well running complex verification test scripts directly test complete system. supports Debugger (GDB) Remote protocol control debugging target. Some graphical debuggers this interface debugging, including PowerPC MicroBlaze (powerpc-eabi-gdb mb-gdb), Platform Studio Software Development (SDK), Eclipse-based Software IDE. Mentor Graphics EDGE Debugger also uses this protocol. either case, debugger connects running same computer remote computer network. FPGA been previously configured with Embedded System designed earlier XPS.
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Creating Nucleus Project EDGE connect Target, Debug Options must first. From menu, click Debug Debug Options. This will open Debug Options setup Window. Select Hardware Connector Type shown Figure then click
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Figure Selecting Hardware connection Target
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Creating Nucleus Project EDGE Launch from connect MicroBlaze processor over JTAG interface shown Figure
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Figure connection Hardware Board command download plus_demo.out executable file Target. command Start executing target from using command. this stage, outputs Terminal Window which been opened previously, appear shown Figure
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Figure Output plus_demo UART Console Stop executing target from using stop command. Exit using exit command.
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Debugging Nucleus PLUS Applications using EDGE
Debugging Nucleus PLUS Applications using EDGE
Connecting Board
debug Application using EDGE Debugger, launch connect hardware board from menu, Click Debug Launch detailed above. Note: provided Port 1234 must used within EDGE Debugger Settings connect XMD.
Connecting EDGE Debugger target
EDGE menu, click open MicroBlaze Target Settings. Select Connection Tab. Comfirm that Ethernet Value 1234, Port number returned Board connection stage. Figure illustrates this step.
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Figure Launching EDGE Debugger this stage application debugged EDGE debugger.
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Adding Bootloader from Flash memory memory Design
Adding Bootloader from Flash memory memory Design
Generating bootloadable image Nucleus PLUS application
used generate bootable S-Records Image Nucleus PLUS application using Flash Writer utility. Before starting this step, Board should configured connected target. From menu, select Device Configuration Program Flash Memory From Program Flash Memory wizard, browse location Nucleus PLUS Image previously built EDGE Tools shown Figure
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Figure Launching Flash Writer Wizard Browse Nucleus PLUS plus_demo.out location under folder listed below.
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Adding Bootloader from Flash memory memory Design Note: Specify Files Files type field able specify *.out file SRecords generation utility shown Figure
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Figure Specifying Nucleus PLUS Image Convert into S-Records Click Open. Check Auto-convert file bootloadable select SREC format when programming flash wizard shown Figure
Programming Flash with bootloadable S-Records Image Nucleus PLUS application from
Programming Flash wizard shown Figure location where S-Records Image Nucleus PLUS Application should programmed changed, necessary. Under Scratch Memory Properties, select ilmb_cntlr Instance Name field. this stage, Bootloader Application created Programming Flash wizard selecting Create Flash Bootloader Application. name Bootloader Application changed Nucleus_Bootloader, example, shown Figure Click automatically accomplish following procedures. Convert Image plus_demo.out file bootable S-Records file, plus_demo.out.srec. Create Bootloader Application bootload plus_demo.out.srec file from flash SDRAM Memory. Program Flash with plus_demo.out.srec file.
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Adding Bootloader from Flash memory memory Design
Customizing Bootloader building
selected earlier Flash Programming Interface (Figure 35), "Nucleus_Bootloader" application been automatically added Projects. This simple Bootloader that converts S-Records Image into executable format while copying from Flash memory SDRAM memory where executable image originally built from). bootloader.c source file edited customize Bootloader application. Applications Tab, expand sources under Nucleus_Bootloader Project. Open bootloader.c source file, line then uncomment file named #define DISPLAY_PROGRESS Save Close file. This will speed boot from Flash SDRAM memory process disabling Bootloader displaying every S-Records line conversion. XPS, select Software Software Platform Settings. Choose Standalone Select Libraries Tab, make sure that "stdin" "stdout" RS232_DCE, Click save settings file. Build "Nucleus_Bootloader" Application XPS. Make sure that other Application selected initialize BRAMs. Select "Nucleus_Bootloader" Application initialize BRAMs. this stage "Nucleus_Bootloader" Application ready boot Nucleus image from Flash SDRAM Memory. XPS, select Device Configuration Download Bitstream, Bootloader launched once FPGA reconfigured shown Figure
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Figure Bootloading Nucleus Application from Flash Memory
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Conclusion
Conclusion
This application note describes Base System Builder (BSB) build hardware platform capable running Nucleus PLUS RTOS based application. describes steps needed EDGE Tools order build application debug provides load Nucleus PLUS application target board using interface. provides example Bootloader Nucleus PLUS application required steps program Flash memory with bootloadable S-Records image Application. This application note ported board capable hosting MicroBlaze based embedded system.
References
more details Nucleus PLUS characteristics, components, architecture, Mentor Graphics site www.mentor.com.
Revision History
following table shows revision history this document.
Date 9/13/07 Version Initial Xilinx release. Revision
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XAPP1016 (v1.0) September 2007

Getting Started with Nucleus PLUS RTOS EDGE Tools MicroBlaze Processor

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