WM9708 high-quality stereo audio codec compliant with AC'97 Revision s

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WM9708 high-quality stereo audio codec compliant with AC'97 Revision s

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AC'97 Revision Audio CODEC
WM9708 high-quality stereo audio codec compliant with AC'97 Revision specification. performs full duplex 18-bit codec functions supports variable sample rates from samples/s offers excellent quality with high SNR. Additional features include line-level outputs hardware sample rate conversion. WM9708 fully operable 3.3V mixed 3.3/5V supplies, packaged 28-lead SSOP package.
WM9708
AC'97 FEATURES
18-bit stereo codec ratio 95dB Multiple stereo input mixer Mono stereo volume control Power management features Very standby power Variable rate audio (VRA) support Line level outputs Supports Rev. specified audio modem sample rates filtering 3.3V operation 28-lead SSOP package
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS
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Copyright ©2007 Wolfson Microelectronics
WM9708 TABLE CONTENTS
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DESCRIPTION AC'97 FEATURES BLOCK DIAGRAM TABLE CONTENTS CONFIGURATION.3 ORDERING INFORMATION DESCRIPTION ABSOLUTE MAXIMUM RATINGS.5 RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS
DETAILED TIMING DIAGRAMS. AC-LINK POWER MODE. COLD RESET WARM RESET CLOCK SPECIFICATIONS DATA SETUP HOLD (50PF EXTERNAL LOAD) SIGNAL RISE FALL TIMES
SYSTEM INFORMATION DEVICE DESCRIPTION.12
INTRODUCTION. VARIABLE SAMPLE RATE SUPPORT GAIN CONTROL REGISTER LOCATION. MASTER SUPPORT CONTROL INTERFACE. AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL. AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT) AC-LINK AUDIO INPUT FRAME (SDATA_IN) AC-LINK POWER MODE. WAKING AC-LINK. SERIAL INTERFACE REGISTER DESCRIPTION. POWERDOWN CONTROL/STATUS REGISTER (INDEX 26H) REVISION REGISTERS (INDEX 58H) VENDOR RESERVED REGISTERS (INDEX 7AH)
SERIAL INTERFACE REGISTER RECOMMENDED EXTERNAL COMPONENTS
RECOMMENDED EXTERNAL COMPONENTS VALUES. RECOMMENDATIONS 3.3V OPERATION.
PACKAGE DIMENSIONS
ADDRESS:
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WM9708
CONFIGURATION
DVDD XTLIN XTLOUT SDATAOUT BITCLK DGND SDATAIN SYNC RESETB PCBEEP CDGND AGND AVDD MONOOUT LINEOUTR LINEOUTL VREFOUT VREF AGND LINEINR LINEINL MIC1
ORDERING INFORMATION
DEVICE WM9708SCDS WM9708SCDS/R Note: Reel quantity 2,000 TEMPERATURE RANGE 70oC
PACKAGE 28-lead SSOP (Pb-free) 28-lead SSOP (Pb-free, tape reel)
MOISTURE SENSITIVITY LEVEL MSL1 MSL1
PEAK SOLDERING TEMPERATURE 260oC
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WM9708 28-PIN SSOP DVDD XTLIN XTLOUT SDATAOUT BITCLK DGND SDATAIN SYNC RESETB PCBEEP CDGND MIC1 LINEINL LINEINR AGND VREF VREFOUT LINEOUTL LINEOUTR MONOOUT AVDD AGND Analogue output Analogue output Analogue output Supply Supply Supply Digital input Digital output Digital input Digital output Supply Digital output Digital input Digital input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Supply Analogue output Analogue output Analogue input NAME TYPE internal connection internal connection Digital positive supply Clock crystal connection clock input (XTAL used) Clock crystal connection Serial data input Serial interface clock output AC'97 controller Digital ground supply Serial data output AC'97 controller Serial interface sync pulse from AC'97 controller reset input (active low, resets registers) Mixer input, typically PCBEEP signal Mixer input, typically signal input common mode reference (ground) Mixer input, typically signal Mixer input with extra gain required Mixer input, typically LINE signal Mixer input, typically LINE signal Analogue ground supply, chip substrate Buffered CAP, used MIXER reference Reference microphones; buffered Reference input/output; pulls midrail driven internal connection Main analogue output left channel Main analogue output right channel Main mono output Analogue positive supply Analogue ground supply, chip substrate Internal Connection
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WM9708
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings stress ratings only. Permanent damage device caused continuously operating beyond these limits. Device functional operating limits guaranteed performance specifications given under Electrical Characteristics test conditions specified. Sensitive Device. This device manufactured CMOS process. therefore generically susceptible damage from excessive static voltages. Proper precautions must taken during handling storage this device. Wolfson tests package types according IPC/JEDEC J-STD-020B Moisture Sensitivity determine acceptable storage conditions prior surface mount assembly. These levels are: MSL1 unlimited floor life <30°C Relative Humidity. normally stored moisture barrier bag. MSL2 storage year <30°C Relative Humidity. Supplied moisture barrier bag. MSL3 storage hours <30°C Relative Humidity. Supplied moisture barrier bag. Moisture Sensitivity Level each package type specified Ordering Information. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, Storage prior soldering Storage temperature after soldering Note: digital supply voltage (DVDD) must always less than equal analogue supply voltage (AVDD). -0.3V -0.3V DVSS -0.3V AVDD -0.3V
DVDD +0.3V AVDD +0.3V +70oC +150oC
30oC
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Digital ground Analogue ground Difference DGND AGND Analogue supply current Digital supply current Standby supply current (all set) Analogue supply current Digital supply current Standby supply current (all set) Note: Both supplies should powered same time. DVDD, AVDD DVDD, AVDD DVDD, AVDD DVDD, AVDD 3.3V DVDD, AVDD 3.3V DVDD, AVDD 3.3V SYMBOL DVDD AVDD DGND AGND -0.3 TEST CONDITIONS -10% -10% +0.3 +10% +10% UNIT
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WM9708 ELECTRICAL CHARACTERISTICS
Test Characteristics: AVDD 25oC, unless otherwise stated DVDD 3.3V, 25oC, unless otherwise stated PARAMETER Input level Input HIGH level Output Output HIGH Input level Output level Reference Levels Reference input/output CAP2 impedance Mixer reference reference MIDBUFF current sink (pins VREF VREFOUT) MIDBUFF current source (pins VREF VREFOUT) MIDBUFF current source (pins VREF VREFOUT) MIDBUFF current sink (pins VREF VREFOUT) A-weighted (Note Full scale output voltage Frequency response Transition band Stop band band rejection Spurious tone reduction PSRR A-weighted (Note input full scale output Frequency response Transition band Stop band Stop band rejection PSRR 20kHz VREF 2.5V -6dBv input 19,200 28,800 20kHz Circuit Specifications (AVDD 48kHz sampling 19,200 28,800 VREF 2.5V -3dBfs input (0.02%) 19,200 28,800 -100 VREF VREFOUT AVDD AVDD AVDD 3.3V AVDD 3.3V CAP2 AVDD AVDD/2 Buffered CAP2 Buffered CAP2 SYMBOL Minimum input impedance Into load 0.90 AGND -100mV AGND +300mV Near rail rail AVDD +100mV AVDD -300mV TEST CONDITIONS AGND -0.3
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UNIT
Digital Logic Levels (DVDD 5.0V) AVDD +0.3 0.10
Analogue Levels (Input Signals inputs, Outputs LINEOUT MONOOUT)
AVDD
Circuit Specifications (AVDD 48kHz sampling 19,200 28,800 Vrms Vrms
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Production Data Test Characteristics: AVDD 25oC, unless otherwise stated DVDD 3.3V, 25oC, unless otherwise stated PARAMETER path A-weighted (Note Other paths A-weighted (Note Maximum input voltage Maximum output voltage LINEOUT Frequency response (+/-1dB) Input impedance inputs) Input impedance (other mixer inputs) Input impedance inputs PSRR A-weighted (Note Full scale output voltage Frequency response Transition band Stop band band rejection Spurious tone reduction PSRR A-weighted (Note input full scale output Frequency response Transition band Stop band Stop band rejection PSRR 20kHz VREF 1.65V -6dBv input 19,200 28,800 20kHz Circuit Specifications (AVDD 3.3V) 48kHz sampling 19,200 28,800 VREF 1.65V -3dBFS input 19,200 28,800 -100 gain gain gain gain gain 20kHz Circuit Specifications (AVDD 3.3V) 48kHz sampling 19,200 28,800 0dBv input SYMBOL TEST CONDITIONS AGND 20,000 AVDD
WM9708
UNIT Vrms Vrms Vrms Vrms
Mixer Circuit Specifications (AVDD 48kHz sampling
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WM9708
Test Characteristics: AVDD 25oC, unless otherwise stated DVDD 3.3V, 25oC, unless otherwise stated PARAMETER path A-weighted (Note Other paths A-weighted (Note Maximum input voltage Maximum output voltage LINEOUT (Note Frequency response (+/-1dB) Input impedance inputs) Input impedance (other Mixer inputs) Input impedance inputs PSRR Clock Frequency Range Crystal clock BITCLK frequency SYNC frequency Notes: 24.576 12.288 48.0 gain gain gain gain gain 20kHz -3.6dBv input SYMBOL TEST CONDITIONS 20,000
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UNIT Vrms Vrms
Mixer Circuit Specifications (AVDD 3.3V) 48kHz sampling
ratio signal output output level with signal, measured A-weighted over 20Hz 20kHz bandwidth. Inputs scaled AVDD 0dBv 5.0V equivalent -3.6dBv 3.3V.
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WM9708
Test Characteristics: AVDD 25oC, unless otherwise stated. DVDD 3.3V, 25oC, unless otherwise stated. measurements taken VDD, unless otherwise stated. following timing information guaranteed, tested.
DETAILED TIMING DIAGRAMS
AC-LINK POWER MODE
SYNC
SLOT
SLOT
BITCLK
SDATAOUT
WRITE 0X20
DATA
DON'T CARE
tS2_PDOWN SDATAIN
Figure AC-Link Powerdown Timing PARAMETER slot BITCLK SDATIN SYMBOL tS2_PDOWN UNIT
COLD RESET
tRST_LOW RESETB tRST2CLK
BITCLK
Figure Cold Reset Timing PARAMETER RESETB active pulse width RESETB release rising edge) BITCLK startup delay SYMBOL tRST_LOW tRST2_CLK 162.8 UNIT
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WM9708
WARM RESET
tSYNC_HIGH SYNC tSYNC2CLK
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BITCLK
Figure Warm Reset Timing PARAMETER SYNC active high pulse width SYNC release falling edge) BITCLK startup delay SYMBOL tSYNC_HIGH tSYNC2_CLK 162.4 UNIT
CLOCK SPECIFICATIONS
tCLK_HIGH BITCLK tCLK_LOW
tCLK_PERIOD tSYNC_HIGH tSYNC_LOW
SYNC
tSYNC_PERIOD
Figure Clock Specifications (50pF External Load) PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width (See Note) BITCLK pulse width (See Note) SYNC frequency SYNC period SYNC high pulse width SYNC pulse width tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW tCLK_HIGH tCLK_LOW 32.56 32.56 40.7 40.7 48.0 20.8 19.5 tCLK_PERIOD SYMBOL 12.288 81.4 48.84 48.84 UNIT
Note: Worst case duty cycle restricted 40/60.
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WM9708
DATA SETUP HOLD (50pF EXTERNAL LOAD)
tSETUP BITCLK tHOLD SYNC SDATAOUT
Figure Data Setup Hold (50pF External Load) Note: Setup hold time parameters SDATA_IN with respect AC'97 Controller. PARAMETER Setup falling edge BITCLK Hold from falling edge BITCLK SYMBOL tSETUP tHOLD 15.0 UNIT
SIGNAL RISE FALL TIMES
triseCLK BITCLK triseSYNC SYNC triseDIN SDATAIN triseDOUT SDATAOUT tfallDOUT tfallDIN tfallSYNC tfallCLK
Figure Signal Rise Fall Times (50pF external load) PARAMETER BITCLK rise time BITCLK fall time SYNC rise time SYNC fall time SDATAIN rise time SDATAIN fall time SDATAOUT rise time SDATAOUT fall time SYMBOL triseCLK tfallCLK triseSYNC tfallSYNC triseDIN triseDIN triseDOUT tfallDOUT UNIT
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WM9708 SYSTEM INFORMATION
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MIC1 PCBEEP
LINEINL/R
LINEOUTL/R
RESETB
AC'97 DIGITAL CONTROLLER
BITCLK SYNC SDATAIN SDATAOUT
WM9708
MONO_OUT
Figure Revision Compliant 2-Channel Codec
DEVICE INTRODUCTION
WM9708 comprises stereo 18-bit Codec, (that ADCs DACs) comprehensive analogue mixer with sets stereo inputs, phone, microphone, PC-beep inputs. Additionally, on-chip reference generation circuits generate necessary bias voltages device, bidirectional serial interface allows transfer control data words from AC'97 controller. WM9708 supports 18-bit resolution within functions, AC'97 serial interface specification allows word length 20-bits written read from, AC'97 Codec. These words justified, LSBs used will simply default Normally anticipated that 16-bit words will used most type systems. Therefore, DAC, 16-bit words will downloaded into Codec from controller, along with padding make 16-bit word 20-bit length. this case, WM9708 will process 16-bit word along with padding bits locations make 18-bit). output, WM9708 will provide 18-bit word, again with locations (20-bit). AC'97 controller will then ignore LSBs 20-bit word. When WM9708 interrogated Register 00h, responds indicating 18-bit device. WM9708 functions implemented using oversampled, sigma-delta converters, uses on-chip digital filters convert these 1-bit signals from 48ks/s 16/18bit words that AC'97 controller requires. digital parts device powered separately from analogue optimise performance, 3.3V digital analogue supplies used same device further optimise performance. Digital I/Os tolerant when analogue supplies WM9708 connected controller running supplies, 3.3V digital section WM9708. WM9708 also capable operating with 3.3V supply only (digital analogue). internally generated midrail reference provided which used chip reference. This should heavily decoupled. Refer Figure more details. WM9708 limited PC-only applications. ability power down sections device selectively, option choose alternative master clock, hence sample rates, means that many alternative applications areas such telecoms, anticipated.
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WM9708
DACs ADCs this device support recommended sample rates specified Intel Revision specification audio rates. default rate 48ks/s. alternative rates selected variable rate audio enabled (Register 2Ah, AC'97 interface continues words second, data transferred across link bursts such that sample rate selected achieved. AC'97 Revision compliant controller ensure that data supplied link, received from link, appropriate rate. device supports demand sampling. That when signal processing circuits need another sample, sample request sent controller which must respond with data sample next frame sends. example, rate 24ks/s selected, average device will request sample from controller every other frame, each stereo DACs. Note that unsupported rate written rate registers, rate will default nearest rate supported. Register will then respond when interrogated with default sample rate. left right channels ADCs DACs always sample same rate. AUDIO SAMPLE RATE 8000 11025 16000 22050 32000 44100 48000 CONTROL VALUE D15-D0 1F40 2B11 3E80 5622 7D00 AC44 BB80
VARIABLE SAMPLE RATE SUPPORT
Table Variable Sample Rates Supported
GAIN CONTROL REGISTER LOCATION
Mixer Volume CONTROL REGISTER MUTE DEFAULT Muted (bit-15) Not-muted (bit-15) Muted (15)
Table Gain Control Register Location
MASTER SUPPORT
WM9708 supports operation master codec. Fundamentally, device identified master produces BITCLK input.
CONTROL INTERFACE
digital interface been provided control WM9708 transfer data from This serial interface compatible with Intel AC'97 specification. main control interface functions are: Control analogue gain signal paths through mixer Bi-directional transfer words from AC'97 controller Selection Powerdown down modes.
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WM9708
AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
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WM9708 incorporates 5-pin digital serial interface that links AC'97 controller. AClink bi-directional, fixed rate, serial digital stream. handles multiple input output audio streams, well control Register accesses, employing time division multiplexed (TDM) scheme. AC-link architecture divides each audio frame into outgoing incoming data streams, each with 20-bit sample resolution 16-bit header slot. With minimum required resolution 16-bits, AC'97 also implemented with 20-bit DAC/ADC resolution, given headroom that AC-link architecture provides. WM9708 provides support 18-bit operation.
SLOT NUMBER
SYNC
SDATAOUT
CODEC
DATA
LEFT
RIGHT
RSRVD
CENTRE
SURR
SURR
RSRVD (n+1)
RSRVD (n+1)
RSRVD (n+1)
SDATAIN
STATUS ADDR
STATUS DATA
LEFT
RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
SLOTREQ 3-12
DATA PHASE PHASE
Figure AC'97 Standard Bi-directional Audio Frame
PHASE
DATA PHASE 20.8µS (48kHz)
SYNC
12.288MHz 81.4nS
BITCLK
SDATAOUT
VALID FRAME
SLOT(1)
SLOT(2)
SLOT(12)
(ID1)
(ID0)
SLOT
SLOT
SLOT
SLOT (12)
PREVIOUS AUDIO FRAME
TIME SLOT 'VALID' BITS ('1' TIME SLOT CONTAINS VALID DATA)
Figure AC-link Audio Output Frame
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Production Data datastreams currently defined AC'97 specification include: playback output slots record data input slots Control output slots Status input slots Optional modem line codec output output slot Optional modem line codec input input slot Optional dedicated microphone input input slot
WM9708
2-channel composite output stream 2-channel composite input stream Control Register write port Control Register read port Modem line codec input stream Modem line codec output stream Dedicated microphone input stream support stereo and/or other voice applications.
Synchronisation AC-link data transactions signalled WM9708 controller. WM9708 drives serial clock onto AC-link, which AC'97 controller then qualifies with synchronisation signal construct audio frames. SYNC, fixed 48kHz, derived dividing down serial clock (BITCLK). BITCLK, fixed 12.288MHz, provides necessary clocking granularity support 20-bit outgoing incoming time slots slot. AC-link serial data transitioned each rising edge BITCLK. receiver AC-link data, (WM9708 outgoing data AC'97 controller incoming data), samples each serial falling edges BITCLK. AC-link protocol provides special 16-bit time slot (slot wherein each conveys valid corresponding time slot within current audio frame. given position slot indicates that corresponding time slot within current audio frame been assigned data stream, contains valid data. slot tagged invalid, responsibility source data, (the WM9708 input stream, AC'97 controller output stream), stuff positions with during that slot's active time. SYNC remains high total duration BITCLKs beginning each audio frame. portion audio frame where SYNC high defined Phase. remainder audio frame where SYNC defined Data Phase. Additionally, power savings, clock, sync, data signals halted. This requires that WM9708 implemented static design allow register contents remain intact when entering power savings mode.
AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT)
audio output frame data streams correspond multiplexed bundles digital output data targeting WM9708's inputs, control registers. briefly mentioned earlier, each audio output frame supports 20-bit outgoing data time slots. Slot special reserved time slot containing 16-bits, which used AC-link protocol infrastructure.
OUTPUT SLOT (16-BITS)
(15) (14) (13) (12:3) (1:0) Frame Valid Slot Valid Command Address Slot Valid Command Data Slot 3-12 Valid bits defined AC'97 Reserved 2-bit Message field (Set reserved Primary; indicates Secondary) (Primary Codec only) (Primary Codec only)
Within slot first global (SDATAOUT slot which flags validity entire audio frame. Valid Frame this indicates that current audio frame contains least time slot valid data. next 12-bit positions sampled WM9708 indicate which corresponding time slots contain valid data. should noted that URA, even when slot tagged invalid, request bits still valid. this data streams differing sample rates transmitted across AC-link fixed 48kHz audio frame rate. Figure illustrates time slot based AC-link protocol.
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WM9708
Production Data When Codec slave device, bits used validate data slots Instead, message bits (1:0) match Codec then address valid from slot then indicates slot valid.
WM9707 SAMPLES SYNC ASSERTION HERE
SYNC
WM9707 SAMPLES FIRST SDATA_OUT FRAME HERE
BIT_CLK
SDATA_OUT
VALID FRAME
SLOT
SLOT
PREVIOUS AUDIO FRAME
Figure Start Audio Output Frame audio output frame begins with high transition SYNC shown Figure SYNC synchronous rising edge BITCLK. immediately following falling edge BITCLK, WM9708 samples assertion SYNC. This falling edge marks time when both sides AC-link aware start audio frame. next rising edge BITCLK, AC'97 transitions SDATAOUT into first position slot (Valid Frame bit). Each position presented AC-link rising edge BITCLK, subsequently sampled WM9708 following falling edge BITCLK. This sequence ensures that data transitions subsequent sample points both incoming outgoing data streams time aligned. Baseline AC'97 specified audio functionality MUST ALWAYS sample rate convert from fixed 48ks/s AC'97 controller. This requirement necessary ensure that interoperability between AC'97 controller WM9708, among other things, guaranteed definition baseline specified AC'97 features. SDATAOUT's composite stream justified (MSB first) with non-valid slot positions stuffed with AC'97 controller. event that there less than valid bits within assigned valid time slot, AC'97 controller always stuffs trailing non-valid positions 20-bit slot with
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WM9708
example, consider 8-bit sample stream that being played WM9708's DACs. first positions presented (MSB justified) followed next positions, which stuffed with AC'97 controller. This ensures that regardless resolution implemented (16, 20-bit), biasing will introduced least significant bits. When mono audio sample streams output from AC'97 controller, necessary that BOTH left right sample stream time slots filled with same data.
SLOT COMMAND ADDRESS PORT
command port used control features, monitor status WM9708 functions including, limited mixer settings, power management (refer Serial Interface Register Map). control interface architecture supports 128, 16-bit read/write registers, however only those addressable even byte boundaries used 2.1. Only even Registers (00h, 02h, etc.) valid. register read/write will have effect WM9708. Audio output frame slot communicates control register address, read/write command information WM9708.
COMMAND ADDRESS PORT ASSIGNMENTS
(19) (18:12) (11:0) Read/write command read, write) Control register index 16-bit locations, addressed even byte boundaries) Reserved (stuffed with
first (MSB) sampled WM9708 indicates whether current control transaction read write operation. following positions communicate targeted control register address. trailing positions within slot reserved must stuffed with AC'97 controller.
SLOT COMMAND DATA PORT
command data port used deliver 16-bit control register write data event that current command port operation write cycle. indicated slot 19). (19:4) (3:0) Control register write data (stuffed with current operation read) Reserved (stuffed with
current command port operation read then entire time slot must stuffed with AC'97 controller.
SLOT PLAYBACK LEFT CHANNEL
Audio output frame slot composite digital audio left playback stream. typical Games Compatible this slot composed standard (.wav) output samples digitally mixed AC'97 controller host processor) with music synthesis output samples. sample stream resolution less than 20-bits transferred, AC'97 controller must stuff trailing non-valid positions within this time slot with
SLOT PLAYBACK RIGHT CHANNEL
Audio output frame slot composite digital audio right playback stream. typical Games Compatible this slot composed standard (.wav) output samples digitally mixed AC'97 controller host processor) with music synthesis output samples. sample stream resolution less than 20-bits transferred, AC'97 controller must stuff trailing non-valid positions within this time slot with
SLOT OPTIONAL MODEM LINE CODEC
Audio output frame slot contains justified modem input data. This optional AC'97 feature supported WM9708, data written this location ignored. This determined AC'97 controller interrogating WM9708 3Ch.
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WM9708
SLOTS SURROUND SOUND DATA
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Audio output frame slots used send surround sound data. Unsupported WM9708.
SLOTS LINE2 HANDSET
These data slots supported.
SLOT GPIO CONTROL
These data slots supported.
AC-LINK AUDIO INPUT FRAME (SDATA_IN)
PHASE DATA PHASE 20.8µS (48kHz) SYNC
12.288MHz 81.4nS
BITCLK
SDATAIN
CODEC READY
SLOT(1)
SLOT(2)
SLOT(12)
SLOT
SLOT
SLOT
SLOT (12)
PREVIOUS AUDIO FRAME
TIME SLOT 'VALID' BITS ('1' TIME SLOT CONTAINS VALID DATA)
Figure AC-link Audio Input Frame audio input frame data streams correspond multiplexed bundles digital input data targeting AC'97 controller. case audio output frame, each AC-link audio input frame consists 20-bit time slots plus slot. Slot special reserved time slot containing 16-bits, which used AC-link protocol infrastructure. Within slot first global (SDATAIN slot which flags whether WM9708 Codec Ready state not. Codec Ready this indicates that WM9708 ready normal operation. This condition normal following desertion power reset example, while WM9708's voltage references settle. When AC-link Codec Ready indicator indicates that AC-link WM9708 control status registers fully operational state. AC'97 controller must further probe Powerdown Control/Status Register determine exactly which subsections, any, ready. Prior attempts putting WM9708 into operation AC'97 controller should poll first audio input frame (SDATAIN slot indication that WM9708 gone Codec Ready. Once WM9708 sampled Codec Ready then next positions sampled AC'97 controller indicate which corresponding time slots assigned input data streams, that they contain valid data. Figure illustrates time slot based AC-link protocol. There several subsections within WM9708 that independently busy/ready. responsibility WM9708 controller probe more deeply into WM9708 register file determine which WM9708 subsections actually ready.
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WM9707 SAMPLES SYNC ASSERTION HERE
WM9708
SYNC BITCLK
AC'97 CONTROLLER SAMPLES FIRST SDATA_IN FRAME HERE
SDATAIN
CODEC READY
SLOT
SLOT
PREVIOUS AUDIO FRAME
Figure Start Audio Input Frame audio input frame begins with high transition SYNC shown Figure SYNC incident with rising edge BITCLK. immediately following falling edge BITCLK, AC'97 samples assertion SYNC. This falling edge marks time when both sides AC-link aware start audio frame. next rising BITCLK, AC'97 transitions SDATAIN into first position slot ("Codec Ready" bit). Each position presented AC-link rising edge BITCLK, subsequently sampled AC'97 Controller following falling edge BITCLK. This sequence ensures that data transitions subsequent sample points both incoming outgoing data streams time aligned. SDATAIN's composite stream justified (MSB first) with non-valid positions (for assigned and/or unassigned time slots) stuffed with WM9708. SDATAIN should sampled falling edges BITCLK.
SLOT STATUS ADDRESS PORT
status port used monitor status WM9708 functions including, limited mixer settings, power management. Audio input frame slot echoes control register index, historical reference, data returned slot (Assuming that slots been tagged valid WM9708 during slot
STATUS ADDRESS PORT ASSIGNMENTS:
(19) (18:12) (11:2) (1:0) RESERVED (stuffed with Control register index (echo register index which data being returned) Variable sample rate SLOTREQ bits. RESERVED (stuffed with
first (MSB) generated WM9708 always stuffed with following positions communicate associated control register address. next bits support AC'97 variable sample rate signalling protocol, trailing positions stuffed with AC'97. slot requests slot (bits 11-3) always valid regardless slot tag.
SLOT STATUS DATA PORT
status data port delivers 16-bit control register read data. (19:4) (3:0) Control register read data (stuffed with tagged invalid WM9701) RESERVED (stuffed with
slot tagged invalid WM9708, then entire slot will stuffed with WM9708.
SLOT RECORD LEFT CHANNEL
Audio input frame slot left channel output WM9708's input Mux, post-ADC. WM9708 sends output data (MSB first), stuffs trailing non-valid positions with fill 20-bit time slot.
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WM9708
SLOT RECORD RIGHT CHANNEL
Production Data
Audio input frame slot right channel output WM9708's input Mux, post-ADC. WM9708's ADCs implemented support 20-bit resolution. WM9708 ships output data (MSB first), stuffs trailing non-valid positions with fill 20-bit time slot.
SLOT OPTIONAL MODEM LINE CODEC
supported WM9708.
SLOT OPTIONAL DEDICATED MICROPHONE RECORD DATA
supported WM9708.
SLOTS RESERVED
Audio input frame slots reserved future always stuffed with WM9708.
AC-LINK POWER MODE
AC-link signals placed power mode. When WM9708's Powerdown Register 26h, programmed appropriate value, both BITCLK SDATAIN will brought held logic voltage level. BITCLK SDATAIN transitioned immediately following decode write Powerdown Register with PR4. When AC'97 controller driver point where ready program AC-link into power mode, slots assumed only valid stream audio output frame. this point time strongly recommended that sources audio input have also been neutralised. AC'97 controller should also drive SYNC SDATAOUT after programming WM9708 this power, halted mode. Once WM9708 been instructed halt BITCLK, special wake protocol must used bring AC-link active mode since normal audio output input frames communicated absence BITCLK.
WAKING AC-LINK
There methods bringing AC-link power, halted mode. Regardless method, AC'97 controller that performs wake task. AC-link protocol provides Cold WM9708 Reset, Warm WM9708 Reset. current Powerdown state would ultimately dictate which form WM9708 reset appropriate. Unless cold register reset write Reset Register 00h) performed, wherein WM9708 registers initialised their default values, registers required keep state during Powerdown modes. Once powered down, re-activation AC-link re-assertion SYNC signal must occur minimum audio frame times following frame which Powerdown triggered. When AC-link powers indicates readiness Codec Ready (input slot 15).
COLD WM9708 RESET
cold reset achieved asserting RESETB minimum specified time (1µs). driving RESETB low, BITCLK, SDATAOUT will activated, re-activated case WM9708 control registers will initialised their default power reset values. RESETB asynchronous WM9708 input. Figure
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WM9708
WARM WM9708 RESET
warm WM9708 reset will re-activate AC-link without altering current WM9708 register values. warm reset signalled driving SYNC high minimum absence BITCLK. Figure Within normal audio frames SYNC synchronous input. absence BITCLK, SYNC treated asynchronous input used generation warm reset WM9708. WM9708 will respond with activation BITCLK until SYNC been sampled again WM9708. This will preclude false detection audio frame.
SERIAL INTERFACE REGISTER (See Table serial interface bits perform control functions described follows: register fully specified AC'97 specification, this description simply repeated below, with optional unsupported features omitted.
RESET REGISTER (INDEX 00h)
Writing value this register performs register reset, which causes registers 0-2B inclusive revert their default values. Reading this register returns code part, indication modem support (not supported WM9708) code type stereo enhancement (not supported WM9708). decodes capabilities WM9708 based following: SE4.SE0 FUNCTION Dedicated channel Modem line codec support Bass treble control Simulated stereo (mono stereo) Headphone support Loudness (bass boost) support 18-bit resolution 20-bit resolution 18-bit resolution 20-bit resolution support VALUE WM9708 00000
Table Reset Register Function Note that WM9708 defaults indicate 18-bit compatibility.
PLAY MASTER VOLUME REGISTERS (INDEX 02h, 06h)
These registers manage output signal volumes. Register controls stereo master volume (both right left channels), Register controls optional stereo headphone out, Register controls mono volume output. Each step corresponds 1.5dB. register mute bit. When this level that channel -dB. left channel level, right channel mono channel. Support volume level provided WM9708. written then WM9708 detects when that sets LSBs Example: driver writes 1xxxxx WM9708 interprets that x11111. will also respond when read with x11111 rather than 1xxxxx, value written driver this feature detect support there not. default value both mono stereo registers 8000h (1000 0000 0000 0000), which corresponds gain with mute
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WM9708
MUTE MX4.MX0 0000 0001 1111 xxxx FUNCTION attenuation 1.5dB attenuation 46.5dB attenuation
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attenuation
Table Volume Register Function
MASTER TONE CONTROL REGISTERS (INDEX 08h)
Optional register support tone controls (bass treble). WM9708 does support bass treble writing this register will have effect, reading will result zeros.
BEEP REGISTER (INDEX 0Ah)
This controls level PC-beep input. Each step corresponds approximately attenuation. register mute bit. When this level that channel -dB. WM9708 defaults PC-beep path being muted, this path will remain muted when device held reset. Therefore separate external speaker should provided within alert user power self-test problems. MUTE PV3.PV0 0000 1111 xxxx FUNCTION attenuation 45dB attenuation
attenuation
Table PC-beep Register Function
ANALOGUE MIXER INPUT GAIN REGISTERS (INDEX 72h)
This controls gain/attenuation each analogue inputs mixer PGA. Each step corresponds approximately 1.5dB. register mute bit. When this level that channel -dB.
REGISTER (MIC VOLUME REGISTER)
This extra that 20dB boost. When 20dB boost default value 8008h, which corresponds gain with mute default value mono registers 8008h, which corresponds gain with mute default value stereo registers 8808h, which corresponds gain with mute MUTE GX4.GX0 00000 01000 11111 xxxxx FUNCTION +12dB gain gain -34.5dB gain gain
Table Mixer Gain Control Register Function
RECORD SELECT CONTROL REGISTER (INDEX 1Ah)
Used select record source independently right left (see Table default value 0000h, which corresponds
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Production Data RIGHT RECORD SOURCE supported supported Line Stereo Mono Phone
WM9708
LEFT RECORD SOURCE supported supported Line Stereo Mono Phone
Table Record Select Register Function
RECORD GAIN REGISTERS (INDEX 1Ch)
stereo input. Each step corresponds 1.5dB. 22.5dB corresponds 0F0Fh. register mute bit. When this level that channel(s) -dB. default value 8000h, which corresponds gain with mute MUTE GX3.GX0 1111 0000 xxxxx FUNCTION +22.5dB gain gain gain
Table Record Gain Register Function
GENERAL PURPOSE REGISTER (INDEX 20h)
This register used control several miscellaneous functions WM9708. Below summary each function. Only MIX, LPBK bits supported WM9708. controls selector. LPBK enables loopback output input without involving AC-link, allowing full system performance measurements. function default value 8000h which off. LLBK RLBK LPBK FUNCTION path mute Simulated stereo enhancement, on/off stereo enhancement on/off, Loudness (bass boost) on/off, Local loop back modem, line codec Remote loop back modem, line codec Mono output select Mix, select Mic1, Mic2 ADC/DAC loopback mode WM9708 SUPPORT
Table General Purpose Register Function
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WM9708
POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)
Production Data
This read/write register used program Powerdown states monitor subsystem readiness. lower half this register read only status, indicating that subsection ready. Ready defined subsection able perform nominal state. When this register written values that come AC-link will have effect read only bits When AC-link Codec Ready indicator (SDATAIN slot indicates that AClink WM9708 control status registers fully operational state. AC'97 controller must further probe this Powerdown Control/Status Register determine exactly which subsections, any, ready. READ FUNCTION VREFs nominal level Analogue mixers, ready section ready accept data section ready transmit data
Table Powerdown Status Register Function powerdown modes follows. first three bits used individually rather than combination with each other. last used combination with itself. control ADCs DACs only. supported WM9708. WRITE EAPD FUNCTION ADCs input Powerdown DACs Powerdown Analogue mixer Powerdown (VREF still Analogue mixer Powerdown (VREF off) Digital interface (AC-link) Powerdown (external clock off) Internal clock disable Powerdown supported External amplifier Powerdown
Table Powerdown Control Register Function
NORMAL
ADCs
DACs
ANALOGUE
DIGITAL
SHUT CODA LINK
WARM RESET
READY DEFAULT
COLD RESET
Figure Example WM9708 Powerdown/Powerup Flow Figure illustrates example procedure complete Powerdown WM9708. From normal operation sequential writes Powerdown Register performed Powerdown WM9708 piece time. After everything been shut (PR0 set), final write PR4) executed shut down WM9708's digital interface (AC-link).
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WM9708
part will remain sleep mode with registers holding their static values. wake WM9708, AC'97 controller will send pulse sync line issuing warm reset. This will restart WM9708's digital interface (resetting WM9708 also woken with cold reset. cold reset will cause loss values registers, cold reset will them their default states. When section powered back Powerdown Control/Status Register (index 26h) should read verify that section ready (i.e. stable) before attempting operation that requires
ADCs
DACs
ANALOGUE
DIGITAL
SHUT CODA LINK
WARM RESET
Figure WM9708 Powerdown/Flow with Analogue Still Alive Figure illustrates state when mixers will work with static volume settings that contained their associated registers. This used when user could playing external LINEIN source) through WM9708 speakers have most system power mode. procedure this follows previous except that analogue mixer never shut down.
POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)
Note that order into ultimate power mode, required which turns oscillator circuit. Asserting SYNC resets re-starts oscillator same link restarted.
REVISION REGISTERS (INDEX 58h)
These registers specified Revision AC'97 specification have following functions WM9708:
REGISTER EXTENDED AUDIO
Extended Audio register read only register that identifies which extended audio features supported addition original AC'97 features identified reading reset register index 00h). zero value indicates feature supported. DATA CDAC SDAC LDAC AMAP FUNCTION Variable rate audio support Double rate audio support Variable rate support Centre support Surround support support Slot front mapping support Codec configuration fixed 9707 supported MODE supported
Table Extended Audio Register
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WM9708
Production Data
REGISTER EXTENDED AUDIO STATUS CONTROL REGISTER
Extended Audio Status Control Register read/write register that provides status control extended audio features. DATA CDAC SDAC LDAC MADC FUNCTION Enables variable rate audio mode Enable double rate audio mode Enables variable rate Indicates centre ready Indicates surround ready Indicates ready Indicates ready turn centre turn surround DACs turn DACs turn READ/WRITE Read/write Read/write Read/write Read Read Read Read Read/write Read/write Read/write Read/write WM9708 SUPPORT
Table Extended Audio Status Control Register
REGISTER AUDIO SAMPLE RATE CONTROL REGISTERS
These registers read/write registers that written select alternative sample rates audio converters. Default 48ks/s rate. Note that only Revision recommended rates supported WM9708, selection other unsupported rates will cause rate default nearest supported rate, supported rate value latched read back.
REGISTERS CHANNEL VOLUME CONTROL
These read/write registers control output volume optional four channels. (not supported WM9708)
VENDOR RESERVED REGISTERS (INDEX 7Ah)
These registers vendor specific. write these registers unless Vendor register been checked first ensure that driver knows source component.
VENDOR SPECIFIC REGISTER (INDEX 5Ch)
WM9708 programmed automute DACs. setting mute bit, WM9708 will mute DACs when detects continuous sequence 1024 zeros.
VENDOR SPECIFIC GAIN CONTROL REGISTERS (INDEX 72h)
This register controls gain mute functions applied mixer path. This accommodated Intel specification, required order allow option simultaneous recording mixer output playback signals. function other mixer PGA's. However, default value register not-muted. used will transparent user.
VENDOR REGISTERS (INDEX 7Eh)
This register specific vendor identification desired. method Microsoft's Plug Play Vendor code. first character that second character third These three characters ASCII encoded. REV7 REV0 field Vendor Revision number. WM9708 vendor WML3. Wolfson registered Microsoft Plug Play vendor.
VENDOR REGISTERS (INDEX 74h)
This register describes data mapped AC'97 DACs. Register used change incoming data slots that used on-board DACs. This allows software control multiple codecs. used recommended that configured before other registers before data applied system.
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WM9708
SURROUND SOUND DSS1, DSS0 LEFT RIGHT
Table Vendor Registers [1:0] This allows user connect multiple codecs host controller using single AC-link interface. volume control register still rate register 2Ch. pins have effect this mapping.
SERIAL INTERFACE REGISTER
following table shows function address various control bits that loaded through serial interface during write operations. Name Reset Master volume LNLVL volume Master volume mono PCBEEP volume volume Line volume volume volume select gain General purpose Mute Mute Mute Mute Mute Mute LPBK 20dB 8000h 8008h 8808h 8808h 8808h 0000h 8000h 0000h 000Fh Mute Mute Mute Default 6150h 8000h 8000h 8000h
Power/down control EAPD status Ext'd audio Ext'd audio stat/ctrl Front rate Audio rate Vendor specific Front mixer volume Surround sound Vendor reserved Vendor Mute
Amap Ldac Madc Ldac
Sdac Cdac Sdac Cdac
1001h 0000h BB80h BB80h 1000h 0808h 0000h 0000h 574Dh 4C03h
SR15 SR14 SR13 SR12 SR11 SR10 SR15 SR14 SR13 SR12 SR11 SR10 REVISION
DSS1 DSS0 Rev0
Vendor Table Serial Interface Register Description
Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1
Note: unused bits should have zeros written them will return same when read.
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WM9708 RECOMMENDED EXTERNAL COMPONENTS
DVDD AVDD
Production Data
DVDD
AVDD
DGND DGND
AGND AGND
AGND
PCBEEP CDGND MIC1
MIXER INPUTS
VREF VREFOUT
WM9708
AGND LINEOUTL LINEOUTR MONOOUT
LINEINL LINEINR
STEREO OUTPUT MONO OUTPUT
SDATAOUT BITCLK SDATAIN SYNC RESETB XTLIN
AC-LINK
XTLOUT
DGND
Notes: C12, should close WM9708 possible. AGND DGND should connected together close WM9708 possible.
Figure External Components Diagram
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Production Data
WM9708
SUGGESTED VALUE 10µF 0.1µF 0.1µF 10µF 470nF 0.1µF 0.1µF 10µF 0.1µF 10µF 10µF 22pF 24.576 Output coupling caps remove VREF level from outputs. Capacitors crystal frequency stability. AC'97 master clock frequency. bias resistor required, connected will affect operation value large (above 1M). De-coupling DVDD De-coupling DVDD De-coupling AVDD De-coupling AVDD coupling capacitors setting level analogue inputs VCAP. Value chosen give corner frequency below 20Hz input impedance. Reference de-coupling capacitors ADC, Mixer references.
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE
Table External Component Values
RECOMMENDATIONS 3.3V OPERATION
device's performance with AVDD 3.3V shown Electrical Characteristics. 3.3V analogue operation, mid-rail reference scales 1.5V. references 3/5ths their nominal value. Input output signals that 1Vrms applications, scale 660mVrms 3.3V applications. 1Vrms output required, mixer gain adjust PGAs need increased times 1.5dB steps.
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WM9708 PACKAGE DIMENSIONS
SSOP (10.2 1.75
Production Data
DM007.E
GAUGE PLANE
-C0.10
SEATING PLANE
0.25
Symbols REF: -0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55
Dimensions (mm) -1.75 0.30 -10.20 0.65 7.80 5.30 0.75 1.25 JEDEC.95, MO-150
0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95
NOTES: LINEAR DIMENSIONS MILLIMETERS. THIS DRAWING SUBJECT CHANGE WITHOUT NOTICE. BODY DIMENSIONS INCLUDE MOLD FLASH PROTRUSION, EXCEED 0.20MM. MEETS JEDEC.95 MO-150, VARIATION REFER THIS SPECIFICATION FURTHER DETAILS.
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Production Data
WM9708
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WM9708 high-quality stereo audio codec compliant with AC'97 Revision s

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