05-04-15 Thomas Hess SHEET SHEET STATUS SHEETS SHEET PREPARE
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REVISIONS DESCRIPTION Made technical change paragraph 1.3. Update boilerplate MIL-PRF-38535 requirements. Made technical changes section table vendor CAGE F7400. Update boilerplate MIL-PRF-38535 requirements. DATE (YR-MO-DA) 02-05-29 APPROVED Thomas Hess
05-04-15
Thomas Hess
SHEET SHEET STATUS SHEETS SHEET PREPARED Thanh Nguyen
PMIC
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING AVAILABLE DEPARTMENTS AGENCIES DEPARTMENT DEFENSE
CHECKED Thanh Nguyen APPROVED Monica Poelking DRAWING APPROVAL DATE 00-06-06 REVISION LEVEL SIZE
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil
MICROCIRCUIT, DIGITAL, DIGITAL SIGNAL PROCESSOR, BITS, MONOLITHIC SILICON
CAGE CODE
AMSC
SHEET
67268
5962-99539
DSCC FORM 2233
5962-E304-05
SCOPE Scope. This drawing documents product assurance class levels consisting high reliability (device classes space application (device class choice case outlines lead finishes available reflected Part Identifying Number (PIN). When available, choice Radiation Hardness Assurance (RHA) levels reflected PIN. PIN. shown following example: 5962 99539
Federal stock class designator
designator (see 1.2.1) Drawing number
Device type (see 1.2.2)
Device class designator (see 1.2.3)
Case outline (see 1.2.4)
Lead finish (see 1.2.5)
1.2.1 designator. Device classes marked devices meet MIL-PRF-38535 specified levels marked with appropriate designator. Device class marked devices meet MIL-PRF-38535, appendix specified levels marked with appropriate designator. dash indicates non-RHA device. 1.2.2 Device type(s). device type(s) identify circuit function follows: Device type Generic number 21020F Circuit function 32-bit digital signal processor Frequency 20.0
1.2.3 Device class designator. device class designator single letter identifying product assurance level follows: Device class Device requirements documentation Vendor self-certification requirements MIL-STD-883 compliant, non-JAN class level microcircuits accordance with MIL-PRF-38535, appendix Certification qualification MIL-PRF-38535
1.2.4 Case outline(s). case outline(s) designated MIL-STD-1835 follows: Outline letter Descriptive designator figure Terminals Package style Ceramic quad flat package
1.2.5 Lead finish. lead finish specified MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class
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Absolute maximum ratings. Supply voltage range (VDD). -0.5 +7.0 Input voltage range (VIN). -0.5 Output current (IOUT) Lead temperature (soldering, seconds) +265°C Storage temperature range (TSTG) -65°C +150°C Maximum power dissipation (continuous) (PD) Thermal resistance junction-to-case (JC) 3°C/W Junction temperature (TJ) +165°C Recommended operating conditions. Operating supply voltage range (VDD). +4.5 +5.5 Case operating temperature range (TC) -55°C +125°C APPLICABLE DOCUMENTS Government specification, standards, handbooks. following specification, standards, handbooks form part this drawing extent specified herein. Unless otherwise specified, issues these documents those cited solicitation contract. DEPARTMENT DEFENSE SPECIFICATION MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines.
DEPARTMENT DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 List Standard Microcircuit Drawings. Standard Microcircuit Drawings.
(Copies these documents available online http://assist.daps.dla.mil from Standardization Document Order Desk, Robbins Avenue, Building Philadelphia, 19111-5094.)
Stress above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. Device functional from +4.5 +5.5 with reference ground. (VDD should exceed +7.0 This maximum current single output. Duration seconds maximum distance less than from device body, same lead shall resoldered until minutes have elapsed.
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Non-Government publications. following document(s) form part this document extent specified herein. Unless otherwise specified, issues these documents cited solicitation contract. INSTITUTE ELECTRICAL ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 IEEE Standard Test Access Port Boundary Scan Architecture. (Applications copies should addressed Institute Electrical Electronics Engineers, Hoes Lane, Piscataway, 08854-4150.) (Non-Government standards other publications normally available from organizations that prepare distribute documents. These documents also available through libraries other informational services.) Order precedence. event conflict between text this drawing references cited herein, text this drawing takes precedence. Nothing this document, however, supersedes applicable laws regulations unless specific exemption been obtained. REQUIREMENTS Item requirements. individual item requirements device classes shall accordance with MIL-PRF-38535 specified herein modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. individual item requirements device class shall accordance with MIL-PRF-38535, appendix non-JAN class level devices specified herein. Design, construction, physical dimensions. design, construction, physical dimensions shall specified MIL-PRF-38535 herein device classes MIL-PRF-38535, appendix herein device class 3.2.1 Case outline. case outline shall accordance with 1.2.4 herein figure herein. 3.2.2 Terminal connections. terminal connections shall specified figure 3.2.3 Block diagram. block diagram shall specified figure 3.2.4 Test circuit timing waveforms. test circuit timing waveforms shall specified figure 3.2.5 Boundary scan instruction codes. boundary scan instruction codes shall specified figure Electrical performance characteristics postirradiation parameter limits. Unless otherwise specified herein, electrical performance characteristics postirradiation parameter limits specified table shall apply over full case operating temperature range.
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Electrical test requirements. electrical test requirements shall subgroups specified table electrical tests each subgroup defined table Marking. part shall marked with listed herein. addition, manufacturer's also marked. packages where marking entire number feasible space limitations, manufacturer option marking "5962-" device. product using this option, designator shall still marked. Marking device classes shall accordance with MIL-PRF-38535. Marking device class shall accordance with MIL-PRF-38535, appendix 3.5.1 Certification/compliance mark. certification mark device classes shall "QML" required MIL-PRF-38535. compliance mark device class shall required MIL-PRF-38535, appendix Certificate compliance. device classes certificate compliance shall required from QML-38535 listed manufacturer order supply requirements this drawing (see 6.6.1 herein). device class certificate compliance shall required from manufacturer order listed approved source supply MIL-HDBK-103 (see 6.6.2 herein). certificate compliance submitted DSCC-VA prior listing approved source supply this drawing shall affirm that manufacturer's product meets, device classes requirements MIL-PRF-38535 herein device class requirements MIL-PRF-38535, appendix herein. Certificate conformance. certificate conformance required device classes MIL-PRF-38535 device class MIL-PRF-38535, appendix shall provided with each microcircuits delivered this drawing. Notification change device class device class notification DSCC-VA change product (see herein) involving devices acquired this drawing required change that affects this drawing. Verification review device class device class DSCC, DSCC's agent, acquiring activity retain option review manufacturer's facility applicable required documentation. Offshore documentation shall made available onshore option reviewer. 3.10 Microcircuit group assignment device class Device class devices covered this drawing shall microcircuit group number (see MIL-PRF-38535, appendix 3.11 IEEE 1149.1 compliance. Theses devices shall compliant IEEE 1149.1. VERIFICATION Sampling inspection. device classes sampling inspection procedures shall accordance with MIL-PRF-38535 modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. device class sampling inspection procedures shall accordance with MIL-PRF-38535, appendix Screening. device classes screening shall accordance with MIL-PRF-38535, shall conducted devices prior qualification technology conformance inspection. device class screening shall accordance with method 5004 MIL-STD-883, shall conducted devices prior quality conformance inspection. 4.2.1 Additional criteria device class Burn-in test, method 1015 MIL-STD-883. Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1015 MIL-STD-883 +125°C, minimum.
Interim final electrical test parameters shall specified table herein.
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TABLE Electrical performance characteristics. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified Group subgroups Device type Limits Unit
High level input voltage level input voltage High level output voltage
VIHCR VILC
=4.5 -1.0
Minimum maximum values recorded level output voltage =4.5 Minimum maximum values recorded High level input current level input current IILT Three-state leakage current Three-state leakage current Supply current (idle) IVDD pins Supply current (internal) IVDD pins Input capacitance 25°C 4.4.1c 1.45 1.55 4.4.1b IDDIN IDDIDLE IOZL IOZH
Functional test
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified Group subgroups Device type Limits Unit
Clock signals reset CLKIN period CLKIN width high CLKIN width RESET width RESET setup before CLKIN high Interrupt timer IRQ3 setup before CLKIN high IRQ3 hold after CLKIN high IRQ3 pulse width CLKIN high TIMEXP Flags tSFI tHFI tDWRFI figure FLAG3-0IN setup before CLKIN high FLAG3-0IN hold afer CLKIN high FLAG3-0IN delay from
tCKH tCKL tWRST tSRST
figure
tSIR
figure
tHIR
tIPW tDTEX
FLAG3-0IN hold after
deasserted
tHFIWR
FLAG3-0OUT delay from CLKIN high FLAG3-0OUT hold after CLKIN high CLKIN high FLAG3-0 enable CLKIN high FLAG3-0OUT disable footnotes table.
tDFO tHFO tDFOE tDFOD
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified Group subgroups Device type Limits Unit
request/grant
tHBR tSBR figure
hold after CLKIN high setup before CLKIN
high Memory interface disable CLKIN high memory interface enable CLKIN high CLKIN high high tDBGL tDBGH tDME tDMDBGL
External memory three-state control PMTS DMTS setup before CLKIN high PMTS DMTS delay after address, select PMTS DMTS delay after
tSTS
figure
tDADTS
tDSTS
Memory interface disable before CLKIN high PMTS DMTS high address, select enable Memory read valid
DATA valid
tDTSD tDTSAE
tDAD tDRLD tHAD tHDRH figure
Address, select DATA
DATA hold from address, select DATA hold from high footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified figure Group subgroups Device type Limits Unit
Memory read Continued xACK delay from address xACK delay from xACK setup before CLKIN high xACK hold after CLKIN high Address, select xPAGE delay from address, select CLKIN high
pulse width high
tDAAK tDRAK tSAK tHAK tDARL tDAP tDCKRL tRWR
Memory write select xACK delay from xACK setup before CLKIN high xACK hold after CLKIN high Address, select deasserted Address, select tDAWL tDAWH tHAK tSAK tDWAK tDAAK figure xACK delay from address,
pulse width
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified figure Group subgroups Device type Limits Unit
Memory write Continued Data setup before high Address, select hold after
deasserted
tDDWH
tDWHA
Data hold after deasserted xPAGE delay from address, select
tHDWH
tDAP tDCKWL tWWR
CLKIN high
high
Data disable before
data enabled
tDDWR
tWDE tTCK tSTAP tHTAP tSSYS tHSYS tTRSTW tDTDO tDSYS figure
IEEE 1149.1 test access port period TDI, setup before high TDI, hold after high System inputs setup before high System inputs hold after high TRST pulse width delay from System outputs delay from footnotes next sheet.
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TABLE Electrical performance characteristics Continued. recorded Tested go/no during functional test. Applies PMD47-0, PMACK, PMTS DMD39-0, DMACK, DMTS IRQ3 FLAG3-0, TMS, TDI. Applies CLKIN, TCK. Applies RESET TRST Applies PMA23-0, PMD47-0, PMS1 PMRD PMWR PMPAGE, DMA31-0, DMD39-0, DMS3 DMRD DMWR DMPAGE, FLAG3-0, TIMEXP, Applies PMACK, PMTS DMACK, DMTS IRQ3 CLKIN, RESET TCK. Applies TMS, TDI, TRST Applies PMA23-0, PMD47-0, PMS1 PMRD PMWR PMPAGE, DMA31-0, DMD39-0, DMS3 DMRD DMWR DMPAGE, FLAG3-0, TDO. Tested during tests recorded.
Memory interface PMA23-0, PMD47-0, PMS1 PMRD PMWR PMPAGE, DMA31-0, DMD39-0, DMS3 DMRD
DMWR DMPAGE.
Address PMA23-0, DMA31-0. Select PMS1- DMS3 Data PMD47-0, DMD39-0. System inputs PMD47-0, PMACK, PMTS DMD39-0, DMACK, DMTS CLKIN, IRQ3 RESET FLAG3-0, System outputs PMA23-0, PMD47-0, PMS1 PMRD PMWR PMPAGE, DMA31-0, DMD39-0, DMS3 DMRD
DMWR DMPAGE, FLAG3-0, TIMEXP,
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Case
FIGURE Case outline.
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Case Symbol D1/E1 0.095 0.081 0.002 0.006 0.004 2.095 1.450 Inches 0.125 0.101 0.014 0.010 0.008 2.195 1.470 Millimeters 2.41 2.06 53.23 36.83 3.18 2.56 55.74 37.34
0.020 0.323 0.362
8.20 9.20
FIGURE Case outline Continued.
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Device type Case outline number name IGND IVDD DMD19 DMD18 DMD17 DMD16 EGND DMD15 DMD14 DMD13 DMD12 EVDD DMD11 DMD10 DMD9 DMD8 IGND IVDD EGND DMD7 DMD6 number name DMD5 DMD4 EVDD DMD3 DMD2 DMD1 DMD0 EGND PMD0 PMD1 PMD2 IGND IVDD PMD3 EVDD PMD4 PMD5 PMD6 PMD7 EGND PMD8
number name PMD9 PMD10 PMD11 EVDD PMD12 PMD13 IGND IVDD PMD14 PMD15 EGND PMD16 PMD17 PMD18 PMD19 EVDD PMD20 PMD21 PMD22 PMD23 EGND number name PMD24 IGND IVDD PMD25 PMD26 PMD27 EVDD PMD28 PMD29 PMD30 PMD31 EGND PMD32 PMD33 PMD34 PMD35 EVDD IGND IVDD PMD36 PMD37
FIGURE Terminal connections.
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Device type Case outline number name PMD38 PMD39 EGND PMD40 PMD41 PMD42 PMD43 EVDD PMD44 PMD45 PMD46 PMD47 IGND IVDD EGND PMTS
PMWR
number name RESET CLKIN
DMRD
number
name PMA20 EVDD IGND IVDD PMA19 PMA18 PMA17 PMA16 EGND PMA15 PMA14 PMA13 PMA12 EVDD PMA11 PMA10 PMA9 PMA8 IGND IVDD EGND
number
name PMA7 PMA6 PMA5 PMA4 EVDD PMA3 PMA2 PMA1 PMA0 EGND TIMEXP EVDD EGND IGND IVDD IRQ3 IRQ2 IRQ1 IRQ0 EVDD FLAG0
DMACK
DMWR
EVDD DMTS IGND IVDD TRST PMPAGE PMS0 PMS1 EGND PMA23 PMA22 PMA21
PMACK
PMRD
RCMP EVDD
FIGURE Terminal connections Continued.
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Device type Case outline number name FLAG1 FLAG2 FLAG3 EGND DMA0 DMA1 DMA2 DMA3 IGND IVDD EVDD DMA4 DMA5 DMA6 DMA7 EGND DMA8 DMA9 DMA10 DMA11 EVDD DMA12 number name DMA13 DMA14 IGND IVDD DMA15 EGND DMA16 DMA17 DMA18 DMA19 EVDD DMA20 DMA21 DMA22 DMA23 EGND DMA24 DMA25 IGND IVDD DMA26 DMA27
number name EVDD DMA28 DMA29 DMA30 DMA31 EGND DMPAGE
number
name DMD34 EVDD DMD33 DMD32 DMD31 DMD30 IGND IVDD EGND DMD29 DMD28 DMD27 DMD26 EVDD DMD25 DMD24 DMD23 EGND DMD22 DMD21 DMD20 EVDD
DMS0 DMS1 EVDD IGND IVDD DMS2 DMS3 DMD39 DMD38 EGND DMD37 DMD36 DMD35
FIGURE Terminal connections Continued.
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FIGURE Block diagram.
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NOTE: timing specifications calculated derating following pins: PMA23-0, PMS1- PMRD
PMWR PMPAGE, DMA31-0, DMS3 DMRD DMWR DMPAGE.
FIGURE Test circuit timing waveforms.
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FIGURE Test circuit timing waveforms Continued.
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FIGURE Test circuit timing waveforms Continued.
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FIGURE Test circuit timing waveforms Continued.
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FIGURE Test circuit timing waveforms Continued.
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FIGURE Test circuit timing waveforms Continued.
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Device type Instruction name BYPASS EXTEST SAMPLE/PRELOAD INTEST Reserved emulation Reserved emulation Instruction code XXX1 0000 1000 1100 0100 XX10
FIGURE Boundary scan instruction codes.
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4.2.2 Additional criteria device classes burn-in test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. burn-in test circuit shall maintained under document revision level control device manufacturer's Technology Review Board (TRB) accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1015 MIL-STD-883. Interim final electrical test parameters shall specified table herein. Additional screening device class beyond requirements device class shall specified MIL-PRF-38535, appendix
Qualification inspection device classes Qualification inspection device classes shall accordance with MIL-PRF-38535. Inspections performed shall those specified MIL-PRF-38535 herein groups inspections (see 4.4.1 through 4.4.4). Conformance inspection. Technology conformance inspection classes shall accordance with MIL-PRF-38535 including groups inspections specified herein. Quality conformance inspection device class shall accordance with MIL-PRF-38535, appendix specified herein. Inspections performed device class shall those specified method 5005 MIL-STD-883 herein groups inspections (see 4.4.1 through 4.4.4). 4.4.1 Group inspection. Tests shall specified table herein. device class subgroups tests shall verify instruction set. instruction forms part vendor's test tape shall maintained available review from approved sources supply. device classes subgroups shall include verifying functionality device. Subgroup (CIN measurement) shall measured only initial test after process design changes which affect input capacitance. minimum sample devices with zero rejects shall required.
4.4.2 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.2.1 Additional criteria device class Steady-state life test conditions, method 1005 MIL-STD-883: Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1005 MIL-STD-883. +125°C, minimum. Test duration: 1,000 hours, except permitted method 1005 MIL-STD-883.
4.4.2.2 Additional criteria device classes steady-state life test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. test circuit shall maintained under document revision level control device manufacturer's accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1005 MIL-STD-883.
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TABLE Electrical test requirements. Test requirements Subgroups accordance with MIL-STD-883, method 5005, table Device class Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group test requirements (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) applies subgroup applies subgroups Subgroups accordance with MIL-PRF-38535, table III) Device class Device class
4.4.3 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.4 Group inspection. Group inspection required only parts intended marked radiation hardness assured (see herein). End-point electrical parameters shall specified table herein. device classes devices test vehicle shall subjected radiation hardness assured tests specified MIL-PRF-38535 level being tested. device class devices shall subjected radiation hardness assured tests specified MIL-PRF-38535, appendix level being tested. device classes must meet postirradiation end-point electrical parameter limits defined table +25°C ±5°C, after exposure, subgroups specified table herein.
PACKAGING Packaging requirements. requirements packaging shall accordance with MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class NOTES Intended use. Microcircuits conforming this drawing intended Government microcircuit applications (original equipment), design applications, logistics purposes.
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6.1.1 Replaceability. Microcircuits covered this drawing will replace same generic device covered contractor-prepared specification drawing. 6.1.2 Substitutability. Device class devices will replace device class devices. Configuration control SMD's. proposed changes existing SMD's will coordinated with users record individual documents. This coordination will accomplished using Form 1692, Engineering Change Proposal. Record users. Military industrial users should inform Defense Supply Center Columbus (DSCC) when system application requires configuration control which SMD's applicable that system. DSCC will maintain record users this list will used coordination distribution changes drawings. Users drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. Comments. Comments this drawing should directed DSCC-VA, Columbus, Ohio 43218-3990 telephone (614) 692-0547. Abbreviations, symbols, definitions. abbreviations, symbols, definitions used herein defined MIL-PRF-38535, MIL-HDBK-1331, table herein. Sources supply. 6.6.1 Sources supply device classes Sources supply device classes listed QML-38535. vendors listed QML-38535 have submitted certificate compliance (see herein) DSCC-VA have agreed this drawing. 6.6.2 Approved sources supply device class Approved sources supply class listed MIL-HDBK-103. vendors listed MIL-HDBK-103 have agreed this drawing certificate compliance (see herein) been submitted accepted DSCC-VA.
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TABLE III. descriptions. name PMA23-0 PMD47-0 Type Description Program memory address. processor outputs address program memory these pins. Program memory data. processor inputs outputs data instructions these pins. 32-bit fixed-point data 32-bit single-precision floating-point data transferred over bits 47-16 bus. Program memory select lines. These pins asserted chip selects corresponding banks program memory. Memory banks must defined memory control registers. These pins decoded program memory address lines provide early indication possible cycle. Program memory read strobe. This asserted when processor reads from program memory. Program memory write strobe. This asserted when processor writes program memory. Program memory acknowledge. external device deasserts this input wait states memory access. Program memory page boundary. processor asserts this signal that program memory page boundary been crossed. Memory pages must defined memory control registers. Program memory three-state control. PMTS places program memory address, data, selects, strobes high-impedance state. PMTS asserted while access occurring, processor will halt memory access will completed. PMACK must asserted least cycle when PMTS deasserted allow pending memory access complete properly. PMTS should only asserted (low) during active memory access cycle. DMA31-0 DMD39-0 Data memory address. processor outputs address data memory these pins. Data memory data. processor inputs outputs data thes pins. 32-bit fixed-point data 32-bit single-precision floating-point data transferred over bits 39-8 bus. Data memory select lines. These pins asserted chip selects corresponding banks data memory. Memory banks must defined memory control registers. These pins decoded data memory address lines provide early indication possible cycle. Data memory read strobe. This asserted when processor reads from data memory. Data memory write strobe. This asserted when processor writes data memory. Data memory acknowledge. external device deasserts this input wait states memory access. Data memory page boundary. processor asserts this signal that data memory page boundary been crossed. Memory pages must defined memory control registers. Data memory three-state control. DMTS places data memory address, data, selects, strobes high-impedance state. DMTS asserted while access occurring, processor will halt memory access will completed. DMACK must asserted least cycle when DMTS deasserted allow pending memory access complete properly. DMTS should only asserted (low) during active memory access cycle. footnote table.
PMS1
PMRD PMWR
PMACK PMPAGE
PMTS
DMS3
DMRD DMWR
DMACK DMPAGE
DMTS
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5962-99539
SHEET
TABLE III. descriptions Continued. name CLKIN Type I/O/A Description External clock input processor. instruction cycle rate equal CLKIN. CLKIN halted, changed, operated below specified frequency. Sets processor known state begins execution program memory location specified hardware reset vector (address). This input must asserted (low) power-up. Interrupt request lines; either edge-triggered level-sensitive. External flags. Each configured control bits either input output. input, tested condition. output, used signal external peripherals. request. Used external device request control memory interface. When asserted, processor halts execution after completion current cycle, places memory data, addresses, selects, strobes high-impedance state, asserts processor continues normal operation when released. grant. Acknowledges request indicating that external device take control memory interface. asserted (held low) until released. TIMEXP RCOMP Timer expired. Asserted four cycles when value TCOUNT decremented zero. Compensation resistor input. Controls compensated output buffers. Connect RCOMP through ±15% resistor EVDD. capacitor (approximately pF), placed parallel with resistor recommended. Test clock. Provides asynchronous clock JTAG boundary scan. Test mode select. Used control test state machine. internal pullup resistor. Test data input. Provides serial data boundary scan logic. internal pullup resistor. Test data output. Serial scan output boundary scan path. Test reset. Resets test state machine. TRST must asserted (pulled low) after power-up held proper operation processor. TRST internal pullup resistor. IVDD IGND EVDD EGND Power supply (for internal circuitry), nominally Power suply return (for internal circuitry). Power supply (for output drivers), nominally Power suply return (for output drivers).
RESET IRQ3 FLAG3-0
TRST
Output Input Synchronous Asynchronous Power supply Ground
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
SIZE
REVISION LEVEL
5962-99539
SHEET
STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 05-04-15 Approved sources supply 5962-99539 listed below immediate acquisition information only shall added MIL-HDBK-103 QML-38535 during next revision. MIL-HDBK-103 QML-38535 will revised include addition deletion sources. vendors listed below have agreed this drawing certificate compliance been submitted accepted DSCC-VA. This information bulletin superseded next dated revision MIL-HDBK-103 QML-38535. DSCC maintains online database current sources supply
Standard microcircuit drawing 5962-9953901VXC 5962-9953901QXC
Vendor CAGE number F7400 F7400
Vendor similar TSC21020F-20SBSV TSC21020F-20MBMQ
lead finish shown each representing hermetic package most readily available from manufacturer listed that part. desired lead finish listed, contact vendor determine availability. Caution. this number item acquisition. Items acquired this number satisfy performance requirements this drawing.
Vendor CAGE number F7400
Vendor name address Atmel Nantes Chantrerie 70602 44306 NANTES CEDEX France
information contained herein disseminated convenience only Government assumes liability whatsoever inaccuracies information bulletin.
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