Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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High-performance, Low-power AVR® Core Enhanced RISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 4000V Operating Ranges: 2.7V 5.50V Compliant with GSM, 3GPP 2000 Specifications, Industry Compatible Available Wafers, Modules, Industry-standard Packages
Memory
Bytes FLASH Program Memory Bytes EEPROM, Including Bytes 64-byte Bit-addressable Bytes
128-byte Program Erase Program Erase Typically 500,000 Write/Erase Cycles Temperature 25oC Years Data Retention bytes Memory
Secure Microcontroller Smart Cards AT90SC1650U Summary
Peripherals
Port 16-bit Timer Random Number Generator (RNG) 2-level, 4-vector Interrupt Controller
Security
Environmental Protection Systems Voltage Monitor Frequency Monitor Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
Voyager Emulation Platform (ATV2 ATV4) Support Software Development Embedded Workbench® V4.21 Debugger Above Software Libraries Application Notes
6548AS-SPD-30Mar07
Note: This summary document. complete document will available under NDA. more information, please contact your local Atmel sales office.
Description
AT90SC1650U low-power, high-performance, 8-bit microcontroller with FLASH program memory EEPROM data memory, based enhanced RISC architecture. executing powerful instructions single clock cycle, AT90SC1650U achieves throughputs close MIPS MHz. Harvard architecture includes general-purpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. AT90SC1650U includes bytes Atmel's high density memory block, used both FLASH EEPROM. on-chip downloadable FLASH allows program memory reprogrammed in-system. This technology combined with versatile 8/16-bit monolithic chip provides highly flexible cost-effective solution many smart card applications.Figure shows block diagram AT90SC12036RU
Figure AT90SC1650U Enhanced RISC Architecture
Data 8-bit EEPROM User Memory Program Memory Instruction Register Instruction Decoder Control Lines Status Register Timer Reset Circuit General Purpose Registers
Access Control
Secure Control
Data Memory
Access Control
Interrupt Unit
7816 Port
IN/OUT0
AT90SC1650U
6548AS-SPD-30Mar07
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6548AS-SPD-30Mar07

Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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