Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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High-performance, Low-power AVRRISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 6000V Operating Ranges: 5.5V Compliant with GSM, 3GPP 2000 Specifications Available Wafers, Modules, Industry-standard Packages
Memory
Bytes Program Memory Bytes EEPROM, Including Bytes 192-byte Bit-addressable Bytes
64-byte Program Erase 1.25 Program 1.25 Erase Typically 500,000 Write/Erase Cycles Temperature 25oC Years Data Retention Bytes
Secure Microcontroller Smart Cards AT90SC 9604RU Summary
Peripherals
7816 controller
kpbs Compliant with Protocols Port 16-bit Timers Random Number Generator (RNG) 2-level, 7-vector Interrupt Controller Hardware Triple Resistant Checksum Accelerator Engine (Compliant with ISO/IEC 3309)
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack, Including Active Shield Environmental Protection Systems Voltage Monitor Frequency Monitor Temperature Monitor Light Protection Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
Voyager Emulation Platform (ATV2 ATV4) Support Software Development Embedded Workbench® V4.20 Debugger Atmel's Studio® Version 4.07
Above
Software Libraries Application Notes
Certification targeted
EAL4+ VISA CAST
6540BS-SPD-02May07
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Description
AT90SC9604RU low-power, high-performance, 8/16-bit microcontroller with program memory, EEPROM data memory, based secureAVR RISC architecture. executing powerful instructions single clock cycle, AT90SC9604RU achieves throughputs close MIPS MHz. Harvard architecture includes general-purpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. AT90SC9604RU uses secureAVR that allows linear addressing bytes code bytes data well number functional security features. ability EEPROM code space allows parts program memory reprogrammed in-system. This technology combined with versatile 8/16-bit monolithic chip provides highly flexible cost-effective solution many smart card applications. Figure shows block diagram AT90SC9604RU
Figure AT90SC9604RU SecureAVR RISC Architecture
Data 8-bit EEPROM User Memory Program Memory Instruction Register Instruction Decoder Control Lines Status Register Timer Timer DES/ Triple Counter measures Checksum Accelerator Reset Circuit General Purpose Registers
Access Control
Secure Control
Data Memory Interrupt Unit 7816 Controller 7816 Port
IN/OUT0
Access Control
AT90SC9604RU
6540BS-SPD-02May07
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6540BS-SPD-02May07

Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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