AT91 Thumb Microcontrollers AT91SAM9263 Preliminary Summary 6249C

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AT91 Thumb Microcontrollers AT91SAM9263 Preliminary Summary 6249C

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Instruction Extensions, Jazelle® Technology Java® Acceleration Kbyte Data Cache, Kbyte Instruction Cache, Write Buffer MIPS Memory Management Unit EmbeddedICETM, Debug Communication Channel Support Mid-level Implementation Embedded Trace MacrocellBus Matrix Nine 32-bit-layer Matrix, Allowing Total 28.8 Gbps On-chip Bandwidth Boot Mode Select Option, Remap Command Embedded Memories Kbyte Internal ROM, Single-cycle Access Maximum Matrix Speed Kbyte Internal SRAM, Single-cycle Access Maximum Processor Matrix Speed Kbyte Internal SRAM, Single-cycle Access Maximum Matrix Speed Dual External Interface (EBI0 EBI1) EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash CompactFlash® EBI1 Supports SDRAM, Static Memory ECC-enabled NAND Flash Controller (DMAC) Acts Matrix Master Embeds Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering Control Twenty Peripheral Controller Channels (PDC) Controller Supports Passive Active Displays bits Pixel Mode, bits Pixel Color Mode Colors Mode, Resolution 2048x2048, Supports Virtual Screen Buffers Graphics Accelerator Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing Image Sensor Interface ITU-R 601/656 External Interface, Programmable Frame Capture Rate 12-bit Data Interface Support High Sensibility Sensors Synchronization, Preview Path with Scaler, YCbCr Format Full Speed Mbits second) Host Double Port Dual On-chip Transceivers Integrated FIFOs Dedicated Channels Full Speed Mbits second) Device Port On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM Ethernet 10/100 Base-T Media Independent Interface Reduced Media Independent Interface 28-byte FIFOs Dedicated Channels Receive Transmit Fully-featured System Controller, including Reset Controller, Shutdown Controller Twenty 32-bit Battery Backup Registers Total Bytes Clock Generator Power Management Controller Advanced Interrupt Controller Debug Unit
AT91 Thumb Microcontrollers AT91SAM9263 Preliminary Summary
6249CS-ATARM-01-Jun-07
Periodic Interval Timer, Watchdog Timer Double Real-time Timer
Reset Controller (RSTC) Based Power-on Reset Cells, Reset Source Identification Reset Output Control Shutdown Controller (SHDWC) Programmable Shutdown Control Wake-up Circuitry Clock Generator (CKGR) 32768Hz Low-power Oscillator Battery Backup Power Supply, Providing Permanent Slow Clock On-chip Oscillator PLLs Power Management Controller (PMC) Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) 2-wire UART Support Debug Communication Channel, Programmable Access Prevention Periodic Interval Timer (PIT) 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) Key-protected, Programmable Only Once, Windowed 16-bit Counter Running Slow Clock Real-time Timers (RTT) 32-bit Free-running Backup Counter Running Slow Clock with 16-bit Prescaler Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD PIOE) Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up Resistor Synchronous Output Part 2.0A Part 2.0B-compliant Controller Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Multimedia Card Interface (MCI) SDCard/SDIO MultiMediaCardCompliant Automatic Protocol Control Fast Automatic Data Transfers with SDCard Slots Support eAch Controller Synchronous Serial Controllers (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer AC97 Controller (AC97C) 6-channel Single AC97 Analog Front Interface, Slot Assigner Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding Support ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Master/Slave Serial Peripheral Interface (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Synchronous Communications 90Mbits/sec Three-channel 16-bit Timer/Counters (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Four-channel 16-bit Controller (PWMC) Two-wire Interface (TWI) Master Mode Support, Two-wire Atmel® EEPROMs Supported
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
IEEE® 1149.1 JTAG Boundary Scan Digital Pins Required Power Supplies
1.08V 1.32V VDDCORE VDDBU 3.0V 3.6V VDDOSC VDDPLL 2.7V 3.6V VDDIOP0 (Peripheral I/Os) 1.65V 3.6V VDDIOP1 (Peripheral I/Os) Programmable 1.65V 1.95V 3.0V 3.6V VDDIOM0/VDDIOM1 (Memory I/Os) Available 324-ball Green Package
Description
AT91SAM9263 32-bit microcontroller, based ARM926EJ-S processor, architectured 9-layer matrix, allowing maximum internal bandwidth nine 32-bit buses. also features independent external memory buses, EBI0 EBI1, capable interfacing with wide range memory devices hard disk. external buses prevent bottlenecks, thus guaranteeing maximum performance. AT91SAM9263 embeds Controller supported Graphics Controller 2channel Controller, Image Sensor Interface. also integrates several standard peripherals, such USART, SPI, TWI, Timer Counters, Generators, Multimedia Card interface Controller. When coupled with external engine, AT91SAM9263 provides ideal solution navigation systems.
6249CS-ATARM-01-Jun-07
Figure 2-1.
AT91SAM9263 Block Diagram
TDRS
MASTER
SLAVE
TPYN TPS0 LCDD 0LCDV LCDH LCDD LCDD ETXCK ECXEN-ER ERXE EMDC
MCI0_, MCI_1
RTS0- AC97C AC97R TF0-T 0-TK1 RF0-R
SPI0_, SPI1_
SYNC
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Block Diagram
System Controller DBGU
JTAG Boundary Scan
Transc. Transc.
EBI0
In-Circuit Emulator
IRQ0-IRQ1 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XOUT PLLA PLLB VDDCORE VDDBU XIN32 XOUT32 SHDN WKUP
ARM926EJ-S Processor
EICache bytes DCache bytes
Controller
FIFO
10/100 Ethernet
FIFO FIFO
OHCI
CompactFlash NAND Flash
Interface ITCM DTCM
Interface
SDRAM Controller Static Memory Controller Controller
Fast SRAM Kbytes
9-layer Matrix
PIOA PIOB PIOC PIOD SRAM Kbytes Peripheral Bridge 20-channel Peripheral
20GPREG RTT0 RTT1 SHDWC
2-channel
RSTC VDDCORE NRST
PIOE
Kbytes
Graphics Controller
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKE RAS, SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 NCS3/NANDCS A25/CFRNW CFCE1-CFCE2 D16-D31 NCS2 D0-D15 A0/NBS0 A1/NWR2 A2-A15/A18-A20 A16/BA0 A17/BA1 NCS0 NWR0/NWE NWR1/NBS1 SDCK A21/NANDALE A22/NANDCLE NWAIT NWR3/NBS3 NCS1/SDCS NCS2/NANDCS D16-D31 SDCKE RAS, SDWE, SDA10 NANDOE, NANDWE
EBI0_
EBI1_
EBI1
NAND Flash
SDRAM Controller Device Port Static Memory Controller Controller
MCI0 MCI1
USART0 USART1 USART2
SPI0 SPI1 PWMC
AC97C
SSC0 SSC1
Image Sensor Interface
Transc.
AT91SAM9263 Preliminary
Signal Description
Table gives details signal name classified peripheral. Table 3-1.
Signal Name
Signal Description List
Function Power Supplies Type Active Level Comments
VDDIOM0 VDDIOM1 VDDIOP0 VDDIOP1 VDDBU VDDPLL VDDOSC VDDCORE GNDPLL GNDBU
EBI0 Lines Power Supply EBI1 Lines Power Supply Peripherals Lines Power Supply Peripherals Lines Power Supply Backup Lines Power Supply Power Supply Oscillator Power Supply Core Chip Power Supply Ground Ground Backup Ground
Power Power Power Power Power Power Power Power Ground Ground Ground
1.65V 3.6V 1.65V 3.6V 2.7V 3.6V 1.65V 3.6V 1.08V 1.32V 3.0V 3.6V 3.0V 3.6V 1.08V 1.32V
Clocks, Oscillators PLLs XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Filter Filter Programmable Clock Output Input Output Input Output Input Input Output
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-up Input JTAG NTRST JTAGSEL RTCK Test Reset Signal Test Clock Test Data Test Data Test Mode Select JTAG Selection Return Test Clock Input Input Input Output Input Input Output pull-up resistor Pull-down resistor. Accepts between VDDBU. Pull-up resistor pull-up resistor pull-up resistor Output Input Driven only. over VDDBU. Accepts between VDDBU.
6249CS-ATARM-01-Jun-07
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Embedded Trace Module EActive Level Comments
TSYNC TCLK TPS0 TPS2 TPK0 TPK15
Trace Synchronization Signal Trace Clock Trace Pipeline Status Trace Packet Port Reset/Test
Output Output Output Output
NRST
Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit DBGU
Input Input
Pull-up resistor Pull-down resistor
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
Advanced Interrupt Controller IRQ0 IRQ1 External Interrupt Inputs Fast Interrupt Input Input Input
Controller PIOA PIOB PIOC PIOD PIOE PA31 PB31 PC31 PD31 PE31 Parallel Controller Parallel Controller Parallel Controller Parallel Controller Parallel Controller Pulled-up input reset Pulled-up input reset Pulled-up input reset Pulled-up input reset Pulled-up input reset
Direct Memory Access Controller DMARQ0-DMARQ3 Requests Input
External Interface EBI0 EBI1 EBIx_D0 EBIx_D31 EBIx_A0 EBIx_A25 EBIx_NWAIT Data Address External Wait Signal Output Input Pulled-up input reset reset
Static Memory Controller EBI0_NCS0 EBI0_NCS5, EBI1_NCS0 EBI1_NCS2 EBIx_NWR0 -EBIx_NWR3 EBIx_NRD EBIx_NWE EBIx_NBS0 EBIx_NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output CompactFlash Support EBI0_CFCE1 EBI0_CFCE2 CompactFlash Chip Enable Output
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Table 3-1.
Signal Name EBI0_CFOE EBI0_CFWE EBI0_CFIOR EBI0_CFIOW EBI0_CFRNW EBI0_CFCS0 EBI0_CFCS1
Signal Description List (Continued)
Function CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read CompactFlash Write CompactFlash Read Write CompactFlash Chip Select Lines NAND Flash Support Type Output Output Output Output Output Output Active Level Comments
EBIx_NANDCS EBIx_NANDOE EBIx_NANDWE
NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable SDRAM Controller
Output Output Output
EBIx_SDCK EBIx_SDCKE EBIx_SDCS EBIx_BA0 EBIx_BA1 EBIx_SDWE EBIx_RAS EBIx_CAS EBIx_SDA10
SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Column Signal SDRAM Address Line
Output Output Output Output Output Output Output High
Multimedia Card Interface MCIx_CK MCIx_CDA MCIx_CDB MCIx_DA0 MCIx_DA3 MCIx_DB0 MCIx_DB3 Multimedia Card Clock Multimedia Card Slot Command Multimedia Card Slot Command Multimedia Card Slot Data Multimedia Card Slot Data Output
Universal Synchronous Asynchronous Receiver Transmitter USART SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request Send USARTx Clear Send Input Output Input
Synchronous Serial Controller SSCx Transmit Data SSCx Receive Data SSCx Transmit Clock SSCx Receive Clock Output Input
6249CS-ATARM-01-Jun-07
Table 3-1.
Signal Name
Signal Description List (Continued)
Function SSCx Transmit Frame Sync SSCx Receive Frame Sync AC97 Controller AC97C Type Active Level Comments
AC97RX AC97TX AC97FS AC97CK
AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Timer/Counter
Input Output Output Input
TCLKx TIOAx TIOBx
Channel External Clock Input Channel Line Channel Line
Input
Pulse Width Modulation Controller- PWMC PWMx Pulse Width Modulation Output Output
Serial Peripheral Interface SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1 SPIx_NPCS3 Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select Two-Wire Interface TWCK Two-wire Serial Data Two-wire Serial Clock Controllers CANRX CANTX Input Output Input Output Controller LCDC LCDD0 LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC Data Vertical Synchronization Horizontal Synchronization Clock Data Enable Contrast Control Ethernet 10/100 ETXCK ERXCK Transmit Clock Reference Clock Receive Clock Input Input only, REFCK RMII only Output Output Output Output Output Output Output
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Table 3-1.
Signal Name ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Signal Description List (Continued)
Function Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. Device Port Type Output Output Output Input Input Input Input Input Output Output High RMII only only only ETX0-ETX1 only RMII only RXDV MII, CRSDV RMII ERX0-ERX1 only RMII Active Level Comments
Device Port Data Device Port Data Host Port
Analog Analog
HDPA HDMA HDPB HDMB
Host Port Data Host Port Data Host Port Data Host Port Data
Analog Analog Analog Analog
Image Sensor Interface ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data Clock Input Output Input Input Input
6249CS-ATARM-01-Jun-07
Package Pinout
AT91SAM9263 available 324-ball Green package, 0.8mm ball pitch.
324-ball LFBGA Package Outline
Figure shows orientation 324-ball package. detailed mechanical description given section "AT91SAM9263 Mechanical Characteristics" product datasheet.
Figure 4-1.
324-ball Pinout (Top View)
Corner
VIEW
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
324-ball Package Pinout
AT91SAM9263 Pinout 324-ball Package
Signal Name PC31 PC22 PC15 PC11 PB30 PB31 HDPA EBI0_D13 EBI0_D9 EBI0_D11 EBI0_D12 EBI0_NCS0 EBI0_A16_BA0 EBI0_A12 EBI0_A6 PC27 PC18 PC13 PB26 PB25 PB29 PB27 HDMA PD17 PD12 EBI0_D14 PD10 NC(1) PB21 PB20 PB23 PB28 PB22 PB18 PD24 PD13 PD15 PD11 Signal Name PD28 PD27 PD31 PD29 PD25 VDDIOM0 VDDIOM0 PB3/BMS PA14 PA15 PE10 VDDIOP1 VDDIOM1 VDDIOM0 VDDIOP0 GNDBU PA13 PA12 PA10 PA11 PE18 PE14 PE15 PE11 PE13 PE12 VDDBU EBI1_A21 VDDIOM1 VDDIOM1 Signal Name EBI1_NCS0 EBI1_NWE_NWR0 EBI1_D4 EBI1_D10 PE28 PLLRCB XOUT32 PA18 PA25 PA30 EBI1_A2 EBI1_A14 EBI1_A13 EBI1_A17_BA1 EBI1_D1 EBI1_D8 EBI1_D12 EBI1_D15 PE26 EBI1_SDCK PE30 XOUT VDDOSC VDDIOM1 PA19 PA21 PA26 PA31 EBI1_A7 EBI1_A12 EBI1_A18 EBI1_D0 EBI1_D7 EBI1_D14 PE23 PE25 PE29 PE31 GNDPLL PA17 PA20 PA23 PA24 PA28 Signal Name EBI0_D2 EBI0_SDCKE EBI0_NWE_NWR0 EBI0_NCS1_SDCS EBI0_A19 EBI0_A11 EBI0_A10 EBI0_A5 EBI0_A1_NBS2_NWR2 PC30 PC26 PC24 PC19 PC12 VDDCORE VDDIOP0 EBI0_D4 EBI0_NANDOE EBI0_CAS EBI0_RAS EBI0_NBS3_NWR3 EBI0_A22 EBI0_A15 EBI0_A7 EBI0_A4 PC28 PC21 PC17 PB16 EBI0_D6 EBI0_D0 EBI0_NANDWE EBI0_SDWE EBI0_SDCK EBI0_A21 EBI0_A13 EBI0_A8 EBI0_A3 PC29 PC23 PC14
Table 4-1.
6249CS-ATARM-01-Jun-07
Table 4-1.
AT91SAM9263 Pinout 324-ball Package
Signal Name PD14 PD16 VDDIOM0 VDDCORE PB19 PB17 PB15 PB13 PB24 PB14 PB12 PD30 PD26 PD22 PD19 PD18 PD23 PD21 PD20 PB11 PB10 Signal Name PE19 NC(1) PE17 PE16 EBI1_A6 EBI1_A11 EBI1_A22 EBI1_D2 EBI1_D6 EBI1_D9 GNDPLL XIN32 SHDN PA16 WKUP JTAGSEL PE20 EBI1_A8 EBI1_A4 EBI1_A19 Signal Name EBI1_A0_NBS0 EBI1_A5 EBI1_A10 EBI1_A16_BA0 EBI1_NRD EBI1_D3 EBI1_D13 PE22 PE27 RTCK NTRST VDDPLLA PLLRCA VDDCORE PA22 PA27 PA29 EBI1_A1_NWR2 EBI1_A3 EBI1_A9 EBI1_A15 EBI1_A20 EBI1_NBS1_NWR1 EBI1_D5 EBI1_D11 PE21 PE24 NRST VDDPLLB
Signal Name
VDDIOP0 HDPB EBI0_D10 EBI0_D3 NC(1) EBI0_D1 EBI0_A20 EBI0_A17_BA1 EBI0_A18 EBI0_A9 EBI0_A2 PC25 PC20 PC16 PC10 HDMB EBI0_D15 EBI0_D7 EBI0_D5 EBI0_D8 EBI0_NBS1_NWR1 EBI0_NRD EBI0_A14 EBI0_SDA10 EBI0_A0_NBS0
Note:
pins must left unconnected.
Power Considerations
Power Supplies
AT91SAM9263 several types power supply pins: VDDCORE pins: Power core, including processor, embedded memories peripherals; voltage ranges from 1.08V 1.32V, 1.2V nominal. VDDIOM0 VDDIOM1 pins: Power External Interface lines External Interface lines, respectively; voltage ranges between 1.65V 1.95V (1.8V nominal) between 3.0V 3.6V (3.3V nominal). VDDIOP0 pins: Power Peripheral lines transceivers; voltage ranges from 2.7V 3.6V, 3.3V nominal. VDDIOP1 pins: Power Peripheral lines involving Image Sensor Interface; voltage ranges from 1.65V 3.6V, 1.8V, 2.5V, 3.3V nominal. VDDBU pin: Powers Slow Clock oscillator part System Controller; voltage ranges from 1.08V 1.32V, 1.2V nominal.
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
VDDPLL pin: Powers cells; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDOSC pin: Powers Main Oscillator cells; voltage ranges from 3.0V 3.6V, L3.3V nominal. power supplies VDDIOM0, VDDIOM1 VDDIOP0, VDDIOP1 identified pinout table multiplexing tables. These supplies enable user power device differently interfacing with memories interfacing with peripherals. Ground pins common VDDOSC, VDDCORE, VDDIOM0, VDDIOM1, VDDIOP0 VDDIOP1 pins power supplies. Separated ground pins provided VDDBU VDDPLL. These ground pins respectively GNDBU GNDPLL.
Power Consumption
AT91SAM9263 consumes about (worst case) static current VDDCORE 25°C. This static current rises temperature increases 85°C. VDDBU, current does exceed @25°C, rise @85°C. software-controllable switch VDDCORE guarantees zero power consumption battery when system dynamic power consumption, AT91SAM9263 consumes maximum VDDCORE maximum conditions (1.2V, 25°C, processor running full-performance algorithm).
Programmable Lines Power Supplies
power supply pins VDDIOM0 VDDIOM1 accept voltage ranges. This allows device reach maximum speed, either 1.8V 3.0V external memories. maximum speed SDCK (SDRAM Clock) loaded with power supply 1.8V 50pF power supply 3.3V. other signals (control, address data signals) over 50MHz. voltage ranges determined programming registers Chip Configuration registers located Matrix User Interface. reset, selected voltage defaults 3.3V nominal power supply pins accept either 1.8V 3.3V. However, device cannot reach maximum speed voltage supplied pins only 1.8V without reprogramming EBI0 voltage range. user must sure program EBI0 voltage range before getting device Slow Clock Mode.
Line Considerations
JTAG Port Pins
TMS, Schmitt trigger inputs have pull-up resistors. RTCK outputs, driven VDDIOP0, have pull-up resistors. JTAGSEL used select JTAG boundary scan when asserted high level (VDDBU). integrates permanent pull-down resistor about GNDBU, that left unconnected normal operations. NTRST signal described Section 6.3. JTAG signals except JTAGSEL (VDDBU) supplied with VDDIOP0.
6249CS-ATARM-01-Jun-07
Test
used manufacturing test purposes when asserted high. integrates permanent pull-down resistor about GNDBU, that left unconnected normal operations. Driving this line high level leads unpredictable results. This supplied with VDDBU.
Reset Pins
NRST open-drain output integrating non-programmable pull-up resistor. driven with voltage VDDIOP0. NTRST input which allows reset JTAG Test Access port. action processor. product integrates power-on reset cells, which manage processor JTAG reset, NRST NTRST pins left unconnected. NRST NTRST pins both integrate permanent pull-up resistor minimum VDDIOP0. NRST signal inserted Boundary Scan.
Controllers
lines managed Controllers integrate programmable pull-up resistor typical. Programming this pull-up resistor performed independently each line through Controllers. After reset, lines default inputs with pull-up resistors enabled, except those which multiplexed with External Interface signals that require enabled Peripheral reset. This explicitly indicated column "Reset State" Controller multiplexing tables page following.
Shutdown Logic Pins
SHDN output only, which driven Shutdown Controller. WKUP input only. accept voltages only between VDDBU.
Processor Architecture
ARM926EJ-S Processor
RISC Processor based v5TEJ Harvard Architecture with Jazelle technology Java acceleration Instruction Sets High-performance 32-bit Instruction Thumb High Code Density 16-bit Instruction Instruction Extensions 5-stage Pipeline Architecture Instruction Fetch Instruction Decode
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Execute Data Memory Register Write Kbyte Data Cache, Kbyte Instruction Cache Virtually-addressed 4-way Associative Cache Eight words line Write-through Write-back Operation Pseudo-random Round-robin Replacement Write Buffer Main Write Buffer with 16-word Data Buffer 4-address Buffer DCache Write-back Buffer with 8-word Entries Single Address Entry Software Control Drain Standard Memory Management Unit (MMU) Access Permission Sections Access Permission large pages small pages specified separately each quarter page embedded domains Interface Unit (BIU) Arbitrates Schedules Requests Separate Masters both instruction data access providing complete Matrix system flexibility Separate Address Data Buses both 32-bit instruction interface 32-bit data interface Address Data Buses, data 8-bit (Bytes), 16-bit (Half-words) 32-bit (Words)
Matrix
9-layer Matrix, handling requests from masters Programmable Arbitration strategy Fixed-priority Arbitration Round-Robin Arbitration, either with default master, last accessed default master fixed default master Burst Management Breaking with Slot Cycle Limit Support Undefined Burst Length Support Address Decoder provided Master Three different slaves assigned each decoded memory area: internal boot, external boot, after remap Boot Mode Select Non-volatile Boot Memory internal external Selection made sampled reset Remap Command
6249CS-ATARM-01-Jun-07
Allows Remapping Internal SRAM Place Boot Non-Volatile Memory Allows Handling Dynamic Exception Vectors
Matrix Masters
Matrix AT91SAM9263 manages nine masters, thus each master perform access concurrently with others available slave peripheral memory. Each master decoder, which defined specifically each master. Table 7-1.
Master Master Master Master Master Master Master Master Master
List Matrix Masters
OHCI Host Controller Image Sensor Interface Graphic Controller Controller Ethernet Controller Peripheral Controller ARM926 Data ARM926Instruction
Matrix Slaves
Matrix AT91SAM9263 manages eight slaves. Each slave arbiter, thus allowing program different arbitration slave. Controller, Controller, Host have user interface mapped slave Matrix. They share same layer, programming them does require high bandwidth. Table 7-2.
Slave Slave Slave
List Matrix Slaves
Internal Internal Kbyte SRAM Internal Kbyte SRAM Controller User Interface
Slave
Controller User Interface Host User Interface
Slave Slave Slave
External Interface External Interface Peripheral Bridge
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Master Slave Access
most cases, masters access slaves. However, some paths make sense, example, allowing access from Ethernet Internal Peripherals. Thus, these paths forbidden simply wired, shown Table 7-3. Table 7-3. Masters Slaves Access
OHCI Host Controller Image Sensor Interface Graphics Controller Controller Ethernet Controller Peripheral Controller ARM926 Data Instruction
Master Slave Internal Internal Kbyte SRAM Internal Kbyte SRAM Bank Controller User Interface Controller User Interface Host User Interface External Interface External Interface Peripheral Bridge
Peripheral Controller
Acts Matrix Master Allows data transfers between peripheral memory without intervention processor Next Pointer support, removes heavy real-time constraints buffer management. Twenty channels each USART Debug Unit each Serial Synchronous Controller each Serial Peripheral Interface AC97 Controller each Multimedia Card Interface Peripheral Controller handles transfer requests from channel according following priorities (low high priorities): DBGU Transmit Channel USART2 Transmit Channel
6249CS-ATARM-01-Jun-07
USART1 Transmit Channel USART0 Transmit Channel AC97 Transmit Channel SPI1 Transmit Channel SPI0 Transmit Channel SSC1 Transmit Channel SSC0 Transmit Channel DBGU Receive Channel USART2 Receive Channel USART1 Receive Channel USART0 Receive Channel AC97 Receive Channel SPI1 Receive Channel SPI0 Receive Channel SSC1 Receive Channel SSC0 Receive Channel MCI1 Transmit/Receive Channel MCI0 Transmit/Receive Channel
Controller
Acts Matrix Master Embeds unidirectional channels with programmable priority Address Generation Source/destination address programming Address increment, decrement change chaining support multiple non-contiguous data blocks through linked lists Scatter support placing fields into system memory area from contiguous transfer. Writing stream data into non-contiguous fields system memory. Gather support extracting fields from system memory area into contiguous transfer User enabled auto-reloading source, destination control registers from initially programmed values block transfer Auto-loading source, destination control registers from system memory block transfer block chaining mode Unaligned system address data transfer width supported hardware Channel Buffering 8-word FIFOs Automatic packing/unpacking data FIFO width Channel Control Programmable multiple transaction size each channel Support cleanly disabling channel without data loss
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Suspend operation Programmable lock transfer support. Transfer Initiation Supports four external Requests Support software handshaking interface. Memory mapped registers used control flow transfer place hardware handshaking interface Interrupt Programmable interrupt generation transfer completion, Block transfer completion, Single/Multiple transaction completion Error condition
Debug Test ARM926 Real-time In-circuit Emulator real-time Watchpoint Units Independent Registers: Debug Control Register Debug Status Register Test Access Port Accessible through JTAG Protocol Debug Communications Channel Debug Unit Two-pin UART Debug Communication Channel Interrupt Handling Chip Register Embedded Trace Macrocell: ETM9- Medium+ Level Implementation Half-rate Clock Mode Four Pairs Address Comparators Data Comparators Eight Memory Decoder Inputs 16-bit Counters 3-stage Sequencer 45-byte FIFO IEEE1149.1 JTAG Boundary-scan Digital Pins
6249CS-ATARM-01-Jun-07
Memories
Figure 8-1. AT91SAM9263 Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF
Internal Memory Mapping
0x0000 0000 0x0010 0000 0x0020 0000 Boot Memory ITCM DTCM SRAM SRAM0 Notes: ROM, EBI0_NCS0 SRAM depending REMAP Software programmable
256M Bytes
0x1000 0000 EBI0 Chip Select
0x1FFF FFFF 0x0030 0000
256M Bytes
0x0040 0000 0x0050 0000
0x2000 0000 EBI0 Chip Select EBI0 SDRAMC 256M Bytes
0x0060 0000 0x0070 0000
Reserved Controller
0x2FFF FFFF
0x3000 0000 EBI0 Chip Select
0x3FFF FFFF
256M Bytes
0x0080 0000 DMAC 0x0090 0000 Reserved HOST 0x00B0 0000 Reserved
0x4000 0000
EBI0 Chip Select NANDFlash EBI0 Chip Select Compact Flash Slot EBI0 Chip Select Compact Flash Slot EBI1 Chip Select
0x00A0 0000
256M Bytes
0x4FFF FFFF
0x5000 0000
256M Bytes
0xF000 0000
Peripheral Mapping
Reserved 0xFFF7 8000 0xFFF7 C000 TCO, TC1, 0xFFF8 0000 MCI0 Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes 0xFFFF EE00 AC97C 0xFFFA 4000 SPI0 0xFFFA 8000 SPI1 Bytes Bytes 0xFFFA C000 CAN0 0xFFFB 0000 Reserved 0xFFFB 8000 PWMC 0xFFFB C000 EMAC 0xFFFC 0000 Reserved 0xFFFC 4000 0xFFFC 8000 Bytes Bytes Bytes Bytes Bytes 0xFFFF FC00 0xFFFF FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 Bytes 0xFFFF FDB0 Reserved 0xFFFF FFFF RSTC SHDWC RTT0 RTT1 GPBR Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes 0xFFFF F800 0xFFFF FA00 0xFFFF F600 PIOC PIOD PIOE bytes bytes bytes Bytes 0xFFFF F200 0xFFFF F400 PIOB Bytes Bytes DBGU 0xFFFF F000 PIOA bytes bytes 0xFFFF E000 0xFFFF E200 0xFFFF E400 0xFFFF E600 0xFFFF E800 SDRAMC1 0xFFFF EA00 0xFFFF EC00 0xFFFF ED10 SSC1 0xFFFA 0000 CCFG Bytes SMC1 MATRIX Bytes Bytes Bytes Bytes Bytes Bytes
0x5FFF FFFF
0x6000 0000
System Controller Mapping
0xFFFF C000 Reserved ECC0 SDRAMC0 SMC0 ECC1 Bytes Bytes Bytes bytes
256M Bytes
0x6FFF FFFF
0x7000 0000 256M Bytes
0xFFF8 4000 MCI1 0xFFF8 8000
0x7FFF FFFF
0x8000 0000 EBI1 Chip Select EBI1 SDRAMC
0x8FFF FFFF
256M Bytes
0xFFF8 C000 USART0 0xFFF9 0000 USART1
0x9000 0000 EBI1 Chip Select NANDFlash
0x9FFF FFFF
256M Bytes
0xFFF9 4000 USART2 0xFFF9 8000 SSC0 0xFFF9 C000
0xA000 0000
Undefined (Abort)
1,280M Bytes
0xEFFF FFFF
2DGE 0xFFFC C000 Reserved
0xF000 0000 Internal Peripherals
0xFFFF FFFF
256M Bytes
0xFFFF C000 SYSC 0xFFFF FFFF
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
first level address decoding performed Matrix, i.e., implementation Advanced High Performance (AHB) master slave interfaces with additional features. Decoding breaks bytes address space into banks 256M bytes. banks directed EBI0 that associates these banks external chip selects EBI0_NCS0 EBI0_NCS5 EBI1_NCS0 EBI1_NCS2. bank reserved addressing internal memories, second level decoding provides bytes internal memory area. Bank reserved peripherals provides access Advanced Peripheral (APB). Other areas unused performing access within them provides abort master requesting such access. Each master decoder, thus allowing different memory mapping each master. However, order simplify mappings, masters have similar address decoding. Regarding Master Master (ARM926 Instruction Data), three different slaves assigned memory space decoded address 0x0: internal boot, external boot after remap. Refer Table 8-1, "Internal Memory Mapping," page details. complete memory presented Figure page
Embedded Memories
Kbyte Single Cycle Access full matrix speed Kbyte Fast SRAM Single Cycle Access full matrix speed Supports ARM926EJ-S interface full processor speed Allows internal Frame Buffer screen Kbyte Fast SRAM Single Cycle Access full matrix speed
8.1.1
Internal Memory Mapping Table summarizes Internal Memory Mapping, depending Remap status state reset. Table 8-1. Internal Memory Mapping
REMAP Address 0x0000 0000 EBI0_NCS0 SRAM REMAP
8.1.1.1
Internal Kbyte Fast SRAM AT91SAM9263 device embeds high-speed Kbyte SRAM. This internal SRAM split into three areas. memory mapping presented Figure page Internal SRAM ARM926EJ-S Instruction TCM. user this SRAM block anywhere ARM926 instruction memory space using CP15 instructions
6249CS-ATARM-01-Jun-07
configuration register located Chip Configuration User Interface. This SRAM block also accessible ARM926 Data Master Masters through address 0x0010 0000. Internal SRAM ARM926EJ-S Data TCM. user this SRAM block anywhere ARM926 data memory space using CP15 instructions. This SRAM block also accessible ARM926 Data Master Masters through address 0x0020 0000. Internal SRAM only accessible Masters. After reset until Remap Command performed, this SRAM block accessible through address 0x0030 0000 Masters. After Remap, this SRAM block also becomes accessible through address ARM926 Instruction ARM926 Data Masters. Within Kbytes SRAM available, amount memory assigned each block software programmable multiple Kbytes shown Table 8-2. This table provides size Internal SRAM according size internal SRAM internal SRAM Table 8-2. Internal SRAM Block Size
Internal SRAM (ITCM) Size Internal SRAM Internal SRAM (DTCM) size Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
Note that among five Kbyte blocks making Internal SRAM, permanently assigned Internal SRAM reset, whole memory Kbytes) assigned Internal SRAM memory blocks assigned SRAM SRAM SRAM areas contiguous when user dynamically changes Internal SRAM configuration, Kbyte block organization affect previous configuration from software point view. Table illustrates different configurations related Kbyte blocks assignments (RB0 RB4). Table 8-3. Kbyte Block Allocation
Configuration examples related Kbyte block assignments Decoded Area Internal SRAM (ITCM) Internal SRAM (DTCM)
ITCM Kbyte DTCM Kbyte Kbytes ITCM Kbytes DTCM Kbytes Kbytes ITCM Kbytes DTCM Kbytes Kbytes ITCM Kbytes DTCM Kbytes Kbytes ITCM Kbytes DTCM Kbytes Kbytes
Address 0x0010 0000 0x0010 4000 0x0020 0000 0x0020 4000
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AT91SAM9263 Preliminary
Table 8-3. Kbyte Block Allocation (Continued)
Configuration examples related Kbyte block assignments Decoded Area
ITCM Kbyte DTCM Kbyte Kbytes ITCM Kbytes DTCM Kbytes Kbytes ITCM Kbytes DTCM Kbytes Kbytes ITCM Kbytes DTCM Kbytes Kbytes ITCM Kbytes DTCM Kbytes Kbytes
Address 0x0030 0000
Internal SRAM (AHB)
0x0030 4000 0x0030 8000 0x0030 C000 0x0031 0000
Note:
Configuration after reset.
When accessed from Matrix, internal Kbytes Fast SRAM single cycle accessible full matrix speed (MCK). When accessed from processor's Interface, they also single cycle accessible full processor speed. 8.1.1.2 Internal Kbyte Fast SRAM AT91SAM9263 integrates Kbyte SRAM, mapped address 0x0050 0000. This SRAM single cycle accessible full Matrix speed. Boot Strategies system always boots address 0x0. ensure maximum boot possibilities, memory layout changed with parameters. REMAP allows user layout internal SRAM bank 0x0. This done software once system booted. When REMAP ignored. Refer section "AT91SAM9263 Matrix" product datasheet more details. When REMAP allows user layout address either external memory. This done hardware reset.
Note: Memory blocks affected these parameters always seen their specified base addresses. complete memory presented Figure page
8.1.2
AT91SAM9263 Matrix manages boot memory that depends level reset. internal memory area mapped between address 0x000F FFFF reserved this effect. detected boot memory embedded ROM. detected boot memory memory connected Chip Select External Interface. 8.1.2.1 Boot Embedded system boots Boot Program. Boot slow clock Auto baudrate detection Downloads runs application from external storage media into internal SRAM Downloaded code size depends embedded SRAM size Automatic detection valid application Bootloader non-volatile memory
6249CS-ATARM-01-Jun-07
DataFlash® connected NPCS0 SPI0 Interface with SAM-BAGraphic User Interface enable code loading via: Serial communication DBGU Bulk Device Port 8.1.2.2 Boot External Memory Boot slow clock Boot with default configuration Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled Chip Select, allows boot 16-bit non-volatile memory. customer-programmed software must perform complete configuration. speed boot sequence when booting EBI0 (BMS=0) user must: Program (main oscillator enable bypass mode). Program Start PLL. Reprogram setup, cycle, hold, mode timings registers adapt them clock. Switch main clock value.
External Memories
external memories accessed through External Interfaces Each Chip Select line Mbyte memory area assigned. Refer Figure page
8.2.1
External Interfaces AT91SAM9263 features External Interfaces offer more bandwidth system prevent bottlenecks while accessing external memories. External Interface Integrates three External Memory Controllers: Static Memory Controller SDRAM Controller Controller Additional logic NANDFlash CompactFlash Optional Full 32-bit External Data 26-bit Address Mbytes linear chip select) Chip Selects, Configurable Assignment: Static Memory Controller NCS0 SDRAM Controller Static Memory Controller NCS1 Static Memory Controller NCS2 Static Memory Controller NCS3, Optional NAND Flash support Static Memory Controller NCS4 NCS5, Optional CompactFlash support
8.2.1.1
AT91SAM9263 Preliminary
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AT91SAM9263 Preliminary
8.2.1.2 External Interface Integrates three External Memory Controllers: Static Memory Controller SDRAM Controller Controller Additional logic NANDFlash Optional Full 32-bit External Data 23-bit Address Mbytes linear) Chip Selects, Configurable Assignment: Static Memory Controller NCS0 SDRAM Controller Static Memory Controller NCS1 Static Memory Controller NCS2, Optional NAND Flash support 8.2.2 Static Memory Controller 32-bit Data Multiple Access Modes supported Byte Write Byte Select Lines Asynchronous read Page Mode supported 32-byte page size) Multiple device adaptability Compliant with Module Control signals programmable setup, pulse hold time each Memory Bank Multiple Wait State Management Programmable Wait State Generation External Wait Request Programmable Data Float Time Slow Clock mode supported 8.2.3 SDRAM Controller Supported devices Standard Low-power SDRAM (Mobile SDRAM) Numerous configurations supported Address Memory Parts SDRAM with four Internal Banks SDRAM with 32-bit Data Path Programming facilities Word, half-word, byte access Automatic page break when Memory Boundary been reached Multibank Ping-pong Access Timing parameters specified software Automatic refresh operation, refresh rate programmable Energy-saving capabilities
6249CS-ATARM-01-Jun-07
Self-refresh, power down deep power down modes supported Error detection Refresh Error Interrupt SDRAM Power-up Initialization software Latency supported Auto Precharge Command used 8.2.4 Error Corrected Code Controller Tracking accesses NAND Flash device trigging corresponding chip select Single-bit error correction two-bit random detection Automatic Hamming Code Calculation while writing value available register Automatic Hamming Code Calculation while reading Error Report, including error flag, correctable error flag word address being detected erroneous Support 16-bit NAND Flash devices with 512-, 1024-, 2048- 4096-byte pages
System Controller
System Controller peripherals that allow handling elements system, such power, resets, clocks, time, interrupts, watchdog, etc. System Controller User Interface also embeds registers that used configure Matrix registers chip configuration. chip configuration registers used configure: EBI0 EBI1 chip select assignment voltage range external memories Processor Tightly Coupled Memories System Controller peripherals mapped within highest Kbytes address space, between addresses 0xFFFF C000 0xFFFF FFFF. However, registers System Controller mapped address space. This allows registers System Controller addressed from single pointer using standard instruction set, Load/Store instructions have indexing mode Kbytes. Figure page shows System Controller block diagram. Figure page shows mapping User Interfaces System Controller peripherals.
AT91SAM9263 Preliminary
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AT91SAM9263 Preliminary
System Controller Block Diagram
AT91SAM9263 System Controller Block Diagram
System Controller VDDCORE Powered irq0-irq1 periph_irq[2.29] pit_irq rtt0_irq rtt1_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK Real-Time Timer Real-Time Timer rtt0_irq rtt0_alarm rtt1_irq rtt1_alarm UDPCK periph_clk[24] periph_nreset periph_irq[24] Shut-Down Controller backup_nreset XIN32 XOUT32 SLOW CLOCK rtt0_alarm rtt1_alarm SLCK XOUT PLLRCA PLLRCB MAIN PLLA PLLB MAINCK Power Management Controller General-Purpose Backup Registers Voltage Controller battery_save UHPCK periph_clk[29] periph_nreset periph_irq[29] Host Port Device Port Advanced Interrupt Controller por_ntrst ntrst ARM926EJ-S nirq nfiq
Figure 9-1.
Debug Unit
dbgu_irq dbgu_txd
proc_nreset debug
pit_irq jtag_nreset wdt_irq periph_nreset Matrix Boundary Scan Controller
VDDCORE VDDBU
VDDBU battery_save
SLCK backup_nreset SLCK backup_nreset SLCK SHDN WKUP
periph_clk[2.29] pck[0-3] OTGCK UDPCK
periph_clk[26] periph_nreset periph_irq[26] Controller
PLLACK PLLBCK
pmc_irq
periph_nreset idle
periph_clk[7.27] periph_nreset
periph_nreset periph_clk[2.6] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD31 PE0-PE31
Controllers
periph_irq[2.6] irq0-irq1 dbgu_txd
Embedded Peripherals periph_irq[7.27] enable
6249CS-ATARM-01-Jun-07
Reset Controller
Based Power-on-Reset cells VDDBU VDDCORE Status last reset Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset watchdog reset Controls internal resets NRST output Allows shaping reset signal external devices
Shutdown Controller
Shutdown Wake-up logic Software programmable assertion SHDN (SHDN push-pull) Deassertion programmable WKUP level change alarm
Clock Generator
Embeds low-power 32768 Slow Clock Oscillator Provides permanent Slow Clock SLCK system Embeds Main Oscillator Oscillator bypass feature Supports crystals Embeds PLLs Output clocks Integrates input divider increase output accuracy Minimum input frequency
Figure 9-2.
Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK
PLLRCA
Divider Divider Status Control
PLLA Clock PLLACK PLLB Clock PLLBCK
PLLRCB
Power Management Controller
AT91SAM9263 Preliminary
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AT91SAM9263 Preliminary
Power Management Controller
Provides: Processor Clock Master Clock MCK, particular Matrix memory interfaces Device Clock UDPCK Host Clock UHPCK independent peripheral clocks, typically frequency four programmable clock outputs: PCK0 PCK3 Five flexible operating modes: Normal Mode with processor peripherals running programmable frequency Idle Mode with processor stopped while waiting interrupt Slow Clock Mode with processor peripherals running frequency Standby Mode, Idle Backup Mode, with peripherals running frequency, processor stopped waiting interrupt Backup Mode with Main Power Supplies off, VDDBU powered battery Figure 9-3. AT91SAM9263 Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,.,/64 Divider /1,/2,/3,/4 Peripherals Clock Controller ON/OFF Idle Mode
periph_clk[.]
Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,.,/64 pck[.]
Clock Controller PLLBCK Divider /1,/2,/4 ON/OFF UDPCK UHPCK
Periodic Interval Timer
Includes 20-bit Periodic Counter, with less than accuracy Includes 12-bit Interval Overlay Counter Real-time Linux®/WindowsCE® compliant tick generator
Watchdog Timer
16-bit key-protected Counter, programmable only once
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Windowed, prevents processor deadlocking watchdog access
Real-time Timer
Real-time Timers, allowing backup time with different accuracies 32-bit Free-running back-up counter Integrates 16-bit programmable prescaler running embedded 32.768Hz oscillator Alarm Register capable generating wake-up system through Shutdown Controller
General-purpose Backup Registers
Twenty 32-bit general-purpose backup registers
9.10
Backup Power Switch
Automatic switch VDDBU VDDCORE guaranteeing very power consumption VDDBU while VDDCORE present
9.11
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Thirty-two individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (PIT, RTT, PMC, DBGU, etc.) Programmable Edge-triggered Level-sensitive Internal Sources Programmable Positive/Negative Edge-triggered High/Low Level-sensitive Four External Sources plus Fast Interrupt signal 8-level Priority Controller Drives Normal Interrupt processor Handles priority interrupt sources Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes Interrupt Service Routine Branch Execution 32-bit Vector Register interrupt source Interrupt Vector Register reads corresponding current Interrupt Vector Protect Mode Easy debugging preventing automatic operations when protect models enabled Fast Forcing Permits redirecting normal interrupt source Fast Interrupt processor
9.12
Debug Unit
Composed functions Two-pin UART
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Debug Communication Channel (DCC) support Two-pin UART Implemented features 100% compatible with standard Atmel USART Independent receiver transmitter with common programmable Baud Rate Generator Even, Odd, Mark Space Parity Generation Parity, Framing Overrun Error Detection Automatic Echo, Local Loopback Remote Loopback Channel Modes Support channels with connection receiver transmitter Debug Communication Channel Support Offers visibility interrupt trigger from COMMRX COMMTX signals from Processor's Interface
9.13
Chip Identification
Chip 0x019607A0 JTAG 0x05B0C03F ARM926 0x0792603F
9.14
Controllers
Five Controllers, PIOA PIOE, controlling total Lines Each Controller controls programmable Lines PIOA Lines PIOB Lines PIOC Lines PIOD Lines PIOE Lines Fully programmable through Set/Clear Registers Multiplexing peripheral functions Line each Line (whether assigned peripheral used general-purpose I/O) Input change interrupt Glitch filter Multi-drive option enables driving open drain Programmable pull-up each line data status register, supplies visibility level time Synchronous output, provides Clear several lines single write
6249CS-ATARM-01-Jun-07
Peripherals
10.1 User Interface
Peripherals mapped upper Mbytes address space between addresses 0xFFFA 0000 0xFFFC FFFF. Each User Peripheral allocated Kbytes address space. complete memory presented Figure page
10.2
Identifiers
Table 10-1 defines Peripheral Identifiers. peripheral identifier required control peripheral interrupt with Advanced Interrupt Controller control peripheral clock with Power Management Controller.
Table 10-1.
AT91SAM9263 Peripheral Identifiers
Peripheral Mnemonic SYSC PIOA PIOB PIOC PIOE reserved reserved MCI0 MCI1 SPI0 SPI1 SSC0 SSC1 AC97C TC0, TC1, PWMC EMAC reserved 2DGE LCDC reserved Host Port Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 Graphic Engine Device Port Image Sensor Interface Controller Controller USART USART USART Multimedia Card Interface Multimedia Card Interface Controller Two-Wire Interface Serial Peripheral Interface Serial Peripheral Interface Synchronous Serial Controller Synchronous Serial Controller AC97 Controller Timer/Counter Pulse Width Modulation Controller Ethernet Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel Controller Parallel Controller Parallel Controller External Interrupt
Peripheral
Note:
Setting AIC, SYSC, IRQ0 bits clock set/clear registers effect.
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
10.2.1 10.2.1.1 Peripheral Interrupts Clock Control System Interrupt System Interrupt Source wired-OR interrupt signals coming from: SDRAM Controller Debug Unit Periodic Interval Timer Real-Time Timer Watchdog Timer Reset Controller Power Management Controller clock these peripherals cannot deactivated Peripheral only used within Advanced Interrupt Controller. 10.2.1.2 External Interrupts external interrupt signals, i.e., Fast Interrupt signal Interrupt signals IRQ0 IRQ1, dedicated Peripheral However, there clock control associated with these peripheral IDs. Timer Counter Interrupts three Timer Counter channels interrupt signals OR-wired together provide interrupt source Advanced Interrupt Controller. This forces programmer read Timer Counter status registers before branching right Interrupt Service Routine. Timer Counter channels clocks cannot deactivated independently. Switching clock Peripheral disables clock channels.
10.2.1.3
10.3
Peripherals Signals Multiplexing Lines
AT91SAM9263 device features controllers, PIOA, PIOB, PIOC, PIOD PIOE, which multiplex lines peripheral set. Each Controller controls lines. Each line assigned peripheral functions, multiplexing tables define lines peripherals multiplexed Controllers. columns "Function" "Comments" have been inserted this table user's comments; they used track pins defined application. Note that some peripheral functions which output only duplicated within both tables. column "Reset State" indicates whether Line resets mode peripheral mode. specified, Line resets input with pull-up enabled, that device maintained static state soon reset released. result, corresponding Line register PIO_PSR (Peripheral Status Register) resets low. signal name specified "Reset State" column, Line assigned this function corresponding PIO_PSR resets high. This case pins controlling memories, particular address lines, which require driven soon reset released. Note that pull-up resistor also enabled this case.
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10.3.1
Controller Multiplexing Multiplexing Controller
Controller Application Usage Reset State PCK0 IRQ0 IRQ1 EBI1_D16 EBI1_D17 EBI1_D18 EBI1_D19 EBI1_D20 EBI1_D21 EBI1_D22 EBI1_D23 EBI1_D24 EBI1_D25 EBI1_D26 EBI1_D27 EBI1_D28 EBI1_D29 EBI1_D30 EBI1_D31 Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 Function Comments
Table 10-2.
Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
Peripheral MCI0_DA0 MCI0_CDA
Peripheral SPI0_MISO SPI0_MOSI SPI0_SPCK
MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI1_CK MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI0_CK CANTX CANRX TCLK2 MCI0_CDB MCI0_DB0 MCI0_DB1 MCI0_DB2 MCI0_DB3 MCI1_CDB MCI1_DB0 MCI1_DB1 MCI1_DB2 MCI1_DB3 TXD0 RXD0 RTS0 CTS0 SCK0 DMARQ0
SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS0 PCK2
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AT91SAM9263 Preliminary
10.3.2 Controller Multiplexing Multiplexing Controller
Controller Line PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PWM2 TCLK0 PWM3 DMARQ3 Peripheral AC97FS AC97CK AC97TX AC97RX TWCK SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 PCK1 TIOA2 TIOB2 Peripheral DMARQ1 PWM0 PWM1 LCDCC PCK1 SPI0_NPCS3 Reset State Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Application Usage Function Comments
Table 10-3.
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10.3.3
Controller Multiplexing Multiplexing Controller
Controller Application Usage Reset State PWM1 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 ETX2 ETX3 ERX2 ERX3 ETXER ERXDV ECOL ERXCK TCLK1 PWM2 Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function Comments
Table 10-4.
Line PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
Peripheral LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM0 PCK0 DRXD DTXD
Peripheral
AT91SAM9263 Preliminary
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AT91SAM9263 Preliminary
10.3.4 Controller Multiplexing Multiplexing Controller
Controller Line PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 EBI0_NCS2 EBI0_A23 EBI0_A24 EBI0_A25_CFRNW EBI0_NCS3/NANDCS EBI0_D16 EBI0_D17 EBI0_D18 EBI0_D19 EBI0_D20 EBI0_D21 EBI0_D22 EBI0_D23 EBI0_D24 EBI0_D25 EBI0_D26 EBI0_D27 EBI0_D28 EBI0_D29 EBI0_D30 EBI0_D31 Peripheral TXD1 RXD1 TXD2 RXD2 EBI0_NWAIT EBI0_NCS4/CFCS0 EBI0_NCS5/CFCS1 EBI0_CFCE1 EBI0_CFCE2 Peripheral SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS2 SPI1_NPCS3 DMARQ2 RTS2 CTS2 RTS1 CTS1 SCK2 SCK1 TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 Reset State Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 Application Usage Function Comments
Table 10-5.
6249CS-ATARM-01-Jun-07
10.3.5
Controller Multiplexing Multiplexing Controller
Controller Application Usage Reset State TIOA1 TIOB1 PWM3 PCK3 ISI_D8 ISI_D9 ISI_D10 ISI_D11 TIOA0 TIOB0 EBI1_NWAIT ETXCK ECRS ETX0 ETX1 ERX0 ERX1 ERXER ETXEN EMDC EMDIO EF100 EBI1_SDCKE EBI1_RAS EBI1_CAS EBI1_SDWE EBI1_SDA10 EBI1_NANDWE EBI1_NCS2/NANDCS EB1_NANDOE EBI1_NWR3/NBS3 EBI1_NCS1/SDCS Power Supply VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 Function Comments
Table 10-6.
Line PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31
Peripheral ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_HSYNC ISI_VSYNC ISI_MCK
Peripheral
AT91SAM9263 Preliminary
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AT91SAM9263 Preliminary
10.4
10.4.1
System Resource Multiplexing
Controller Controller interface with several panels. supports bits pixel (bpp), without limitation. Interfacing panels prevents using Ethernet MAC. panels interfaced through peripheral functions, color data output LCDD3 LCDD7, LCDD11 LCDD15 LCDD19 LCDD23. Intensity output LCDD10. Using peripheral does prevent using lines. panels interfaced through peripheral color data output LCDD0 LCDD15, thus lines used peripheral Mapping signals peripheral peripheral makes possible panels bits (peripheral bits (peripheral reprogramming controller thus without hardware modification.
10.4.2
ETMUsing Eprevents EBI0 32-bit mode. Only 16-bit mode (EBI0_D0 EBI0_D15) available, makes EBI0 unable interface CompactFlash NandFlash cards, reduces EBI0's address width which makes unable address memory ranges bigger than 0x7FFFFF finally makes impossible EBI0_NCS2.
10.4.3
EBI1 Using following features prevents using EBI1 32-bit mode: second slots MCI0 and/or MCI1 USART0 request (DMARQ0) Ethernet 10/100
10.4.4
Using SSC0 prevents using AC97 Controller Two-wire Interface. Using SSC1 prevents using Request PWM0, PWM1, LCDCC PCK1.
10.4.5
USART Using USART2 prevents using EBI0's NWAIT signal, Chip Select CompactFlash Chip Enable Using USART1 prevents using EBI0's Chip Select CompactFlash Chip Enable1.
10.4.6
NAND Flash Using NAND Flash interface EBI1 prevents using Ethernet MAC.
10.4.7
CompactFlash Using CompactFlash interface prevents using NCS4 and/or NCS5 access other parallel devices.
10.4.8
SPI0 Interface SPI0 signals MCI0 signals multiplexed, DataFlash Card hardware-compatible with SDCard. Only used time.
6249CS-ATARM-01-Jun-07
10.4.9
Interrupts Using IRQ0 prevents using controller. Using prevents using Request
10.4.10
Image Sensor Interface Using 8-bit data mode prevents using timers TIOA1, TIOB1. Timers Using TIOA2 TIOB2, this order, prevents using SPI1's Chip Selects [2-3].
10.4.11
10.5
10.5.1
Embedded Peripherals Overview
Serial Peripheral Interface Supports communication with serial external devices Four chip selects with external decoder support allow communication with peripherals Serial memories, such DataFlash 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface 16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays between consecutive transfers between clock data chip select Programmable delay between consecutive transfers Selectable mode fault detection Very fast transfers supported Transfers with baud rates chip select line left active speed transfers same device
10.5.2
Two-wire Interface Master Mode only Compatibility with standard two-wire serial memory One, three bytes slave address Sequential read/write operations
10.5.3
USART Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection MSB- LSB-first
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Optional break generation detection by-16 over-sampling receiver frequency Hardware handshaking RTS-CTS Receiver time-out transmitter timeguard Optional Multi-drop Mode with address generation detection Optional Manchester Encoding RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit IrDA modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo 10.5.4 Serial Synchronous Controller Provides serial synchronous communication links used audio telecom applications (with CODECs Master Slave Modes, I2S, Buses, Magnetic Card Reader, etc.) Contains independent receiver transmitter common clock divider Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal 10.5.5 AC97 Controller Compatible with AC97 Component Specification V2.2 interface with single analog front Three independent Channels three independent Channels channel dedicated AC97 analog front control channel data transfers, associated with channel data transfers with Time Slot Assigner that assign time slots channel Channels support mono stereo 20-bit sample length Variable sampling rate AC97 Codec Interface below) 10.5.6 Timer Counter Three 16-bit Timer Counter Channels Wide range functions including: Frequency Measurement Event Counting Interval Measurement Pulse Generation
6249CS-ATARM-01-Jun-07
Delay Timing Pulse Width Modulation Up/down Capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs multi-purpose input/output signals global registers that three Channels 10.5.7 Pulse Width Modulation Controller channels, 16-bit counter channel Common clock generator, providing thirteen different clocks Modulo counter providing eleven clocks independent Linear Dividers working modulo counter outputs Independent channel programming Independent Enable Disable commands Independent clock selection Independent period duty cycle, with double bufferization Programmable selection output waveform polarity Programmable center left aligned output waveform 10.5.8 Multimedia Card Interface double-channel Multimedia Card Interfaces, allowing concurrent transfers with cards Compatibility with MultiMediaCard Specification Version Compatibility with Memory Card Specification Version Compatibility with SDIO Specification Version V1.0. Cards clock rate Master Clock divided Embedded power management slow down clock rate when used Each slots, each supporting slot MultiMediaCard cards) Memory Card Support stream, block multi-block data read write 10.5.9 Controller Fully compliant with 16-mailbox 2.0A 2.0B Controllers rates 1Mbit/s. Object-oriented mailboxes, each with following properties: Specification Part Part programmable each message Object Configurable receive (with overwrite not) transmit Local Mask Filters 29-bit Identifier/Channel bits access Data registers each mailbox data object Uses 16-bit time stamp receive transmit message
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Hardware concatenation unmasked bitfields speedup family processing 16-bit internal timer Time Stamping Network synchronization Programmable reception buffer length mailbox object Priority Management between transmission mailboxes Autobaud listening mode power mode programmable wake-up activity application Data, Remote, Error Overload Frame handling 10.5.10 Host Port Compliant with Open Specification Compliant with V2.0 full-speed low-speed specification Supports both low-speed Mbps full-speed Mbps devices Root integrated with downstream ports embedded transceivers Supports power management Operates master matrix 10.5.11 Device Port V2.0 full-speed compliant, Mbits second Embedded V2.0 full-speed transceiver Embedded 2,432-byte dual-port endpoints Suspend/Resume logic Ping-pong mode (two memory banks) isochronous bulk endpoints general-purpose endpoints Endpoint bytes, ping-pong mode Endpoint bytes, ping-pong mode Endpoint bytes, ping-pong mode 10.5.12 Controller Single Dual scan color monochrome passive panels supported Single scan active panels supported 4-bit single scan, 8-bit single dual scan, 16-bit dual scan interfaces supported 24-bit single scan interfaces supported gray levels mono 4096 colors color displays bits pixel (palletized), bits pixel (non-palletized) mono bits pixel (palletized), bits pixel (non-palletized) color bits pixel (palletized), bits pixel (non-palletized) Single clock domain architecture Resolution supported 2048x2048 Controller management virtual Frame Buffer Allows management frame buffer larger than screen size moving view over this virtual frame buffer
6249CS-ATARM-01-Jun-07
Automatic resynchronization frame buffer pointer prevent flickering 10.5.13 Graphics Controller Acts Matrix Master Commands passed through User Interface Operates directly frame buffer Controller Line draw Block transfer Polygon fill Clipping Commands queuing through FIFO 10.5.14 Ethernet 10/100 Compatibility with IEEE Standard 802.3 Mbits second data throughput capability Full- half-duplex operations RMII interface physical layer Register Interface address, data, status control registers Interface, operating master Memory Controller Interrupt generation signal receive transmit completion 28-byte transmit 28-byte receive FIFOs Automatic generation transmitted frames Address checking logic recognize four 48-bit addresses Support promiscuous mode where valid frames copied memory Support physical layer management through MDIO interface control alarm update time/calendar data 10.5.15 Image Sensor Interface ITU-R 601/656 8-bit mode external interface support Support ITU-R BT.656-4 synchronization Vertical horizontal resolutions 2048 2048 Preview Path 640*480 Support packed data formatting YCbCr 4:2:2 formats Preview scaler generate smaller size image Programmable frame capture rate
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Package Drawing
Figure 11-1. 324-ball TFBGA Package Drawing
Table 11-1.
Ball Land
Soldering Information
0.05 0.275 0.03
Soldering Mask Opening
Table 11-2.
Device 324-balls TFBGA Package Maximum Weight
Table 11-3.
324-balls TFBGA Package Characteristics
Moisture Sensitivity Level
Table 11-4.
Package Reference
MO-210
JEDEC Drawing Reference JESD97 Classification
This package respects recommendations NEMI User Group.
6249CS-ATARM-01-Jun-07
AT91SAM9263 Ordering Information
Table 12-1. AT91SAM9263 Ordering Information
Package BGA324 Package Type Green Temperature Operating Range Industrial -40°C 85°C Ordering Code AT91SAM9263-CU
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Revision History
Table 13-1. Revision History
Comments Section "324-ball LFBGA Package Outline" page corrected package view. information Table 7-1, "List Matrix Masters," page Table 7-2, "List Matrix Slaves," page Table 7-3, "Masters Slaves Access," page Section "Shutdown Controller" page corrected reference shutdown pin. Section "Power Consumption" page specified static current consumption worst case. Corrected Section 10.4.6 "NAND Flash" page with information EMAC. Section 10.4.3 "EBI1" page added Ethernet 10/100 System Resource Multiplexing list EBI1. Section 10.4.10 "Image Sensor Interface" page Section 10.4.11 "Timers" page removed mention keyboard interfaces. Corrected typo hard disk Section "Description" page 6249BS Corrected ordering code Section "AT91SAM9263 Ordering Information" page First issue. Change Request Ref. Document Ref. 6249CS 4463
4466
3870
3825
4064 4407 3804 3805
6249AS
6249CS-ATARM-01-Jun-07
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6249CS-ATARM-01-Jun-07

AT91 Thumb Microcontrollers AT91SAM9263 Preliminary Summary 6249C

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