Download

PDF Abstract Text:

AT91 ARM Thumb Microcontrollers AT91SAM9263 Preliminary Summary

6249CS­ATARM­01-Jun-07

Features
· Incorporates the ARM926EJ-S ARM® Thumb® Processor
- DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration - 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer - 220 MIPS at 200 MHz - Memory Management Unit - EmbeddedICETM, Debug Communication Channel Support - Mid-level Implementation Embedded Trace Macrocell Bus Matrix - Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth - Boot Mode Select Option, Remap Command Embedded Memories - One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed - One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus Matrix Speed - One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed Dual External Bus Interface (EBI0 and EBI1) - EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® - EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash DMA Controller (DMAC) - Acts as one Bus Matrix Master - Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control Twenty Peripheral DMA Controller Channels (PDC) LCD Controller - Supports Passive or Active Displays - Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode - Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers 2D Graphics Accelerator - Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing Image Sensor Interface - ITU-R BT. 601 / 656 External Interface, Programmable Frame Capture Rate - 12-bit Data Interface for Support of High Sensibility Sensors - SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format USB 2.0 Full Speed (12 Mbits per second) Host Double Port - Dual On-chip Transceivers - Integrated FIFOs and Dedicated DMA Channels USB 2.0 Full Speed (12 Mbits per second) Device Port - On-chip Transceiver, 2, 432-byte Configurable Integrated DPRAM Ethernet MAC 10 / 100 Base-T - Media Independent Interface or Reduced Media Independent Interface - 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Fully-featured System Controller, including - Reset Controller, Shutdown Controller - Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit
AT91 ARM Thumb Microcontrollers AT91SAM9263 Preliminary Summary
6249CS-ATARM-01-Jun-07
- Periodic Interval Timer, Watchdog Timer and Double Real-time Timer
· Reset Controller (RSTC) · ·
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
· IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins · Required Power Supplies
- 1.08V to 1.32V for VDDCORE and VDDBU - 3.0V to 3.6V for VDDOSC and VDDPLL - 2.7V to 3.6V for VDDIOP0 (Peripheral I / Os) - 1.65V to 3.6V for VDDIOP1 (Peripheral I / Os) - Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM0 / VDDIOM1 (Memory I / Os) · Available in a 324-ball BGA Green Package
1. Description
The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent bottlenecks, thus guaranteeing maximum performance. The AT91SAM9263 embeds an LCD Controller supported by a 2D Graphics Controller and a 2channel DMA Controller, and one Image Sensor Interface. It also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM Generators, Multimedia Card interface and one CAN Controller. When coupled with an external GPS engine, the AT91SAM9263 provides the ideal solution for navigation systems.
6249CS-ATARM-01-Jun-07
Figure 2-1.
2. AT91SAM9263 Block Diagram
MASTER
SLAVE
TC TS LK TPYN C TPS0 K -TP BM 0-T S2 S PK1 5 LC LCDD 0LCDV LC S LCDH YN DD S LCDD YNC 23 O LCDD TCC EN K D C ET C ETXCK ECXEN-ER R - X ER S- ETX CK E ERXE CO ER ERE R L FC ET X0- -ER K X E X EM 0-E RX DV 3 EMDC TX 3 EF DIO 10 0 H D H PA D M H A D H PB D M B
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Block Diagram
System Controller AIC DBGU
JTAG Boundary Scan
Transc. Transc.
In-Circuit Emulator
FIQ IRQ0-IRQ1 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XIN XOUT PLLA PLLB OSC WDT VDDCORE VDDBU XIN32 XOUT32 SHDN WKUP POR OSC
ARM926EJ-S Processor
ICache 16K bytes MMU DCache 16K bytes
LCD Controller
LUT FIFO
10 / 100 Ethernet MAC
FIFO DMA FIFO
USB OHCI
CompactFlash NAND Flash
TCM Interface ITCM DTCM
Bus Interface
DMA SDRAM Controller Static Memory Controller ECC Controller DMA
Fast SRAM 80 Kbytes PIT
9-layer Bus Matrix
PIOA PIOB PIOC PIOD SRAM 16 Kbytes Peripheral Bridge 20-channel Peripheral DMA
20GPREG RTT0 RTT1 SHDWC
2-channel
RSTC VDDCORE NRST POR
ROM 128 Kbytes APB
2D Graphics Controller
D0-D15 A0 / NBS0 A1 / NBS2 / NWR2 A2-A15, A18-A20 A16 / BA0 A17 / BA1 NCS0 NCS1 / SDCS NRD NWR0 / NWE NWR1 / NBS1 NWR3 / NBS3 SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21 / NANDALE A22 / NANDCLE NWAIT A23-A24 NCS4 / CFCS0 NCS5 / CFCS1 NCS3 / NANDCS A25 / CFRNW CFCE1-CFCE2 D16-D31 NCS2 D0-D15 A0 / NBS0 A1 / NWR2 A2-A15 / A18-A20 A16 / BA0 A17 / BA1 NCS0 NRD NWR0 / NWE NWR1 / NBS1 SDCK A21 / NANDALE A22 / NANDCLE NWAIT NWR3 / NBS3 NCS1 / SDCS NCS2 / NANDCS D16-D31 SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE
NAND Flash
SDRAM Controller PDC DMA USB Device Port Static Memory Controller ECC Controller
PDC MCI0 MCI1 TWI
PDC USART0 USART1 USART2 CAN
PDC SPI0 SPI1 PWMC TC0 TC1 TC2
PDC AC97C
SSC0 SSC1
Image Sensor Interface
Transc.
AT91SAM9263 Preliminary
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral. Table 3-1.
Signal Name
Signal Description List
Function Power Supplies Type Active Level Comments
VDDIOM0 VDDIOM1 VDDIOP0 VDDIOP1 VDDBU VDDPLL VDDOSC VDDCORE GND GNDPLL GNDBU
EBI0 I / O Lines Power Supply EBI1 I / O Lines Power Supply Peripherals I / O Lines Power Supply Peripherals I / O Lines Power Supply Backup I / O Lines Power Supply PLL Power Supply Oscillator Power Supply Core Chip Power Supply Ground PLL Ground Backup Ground
Power Power Power Power Power Power Power Power Ground Ground Ground
1.65V to 3.6V 1.65V to 3.6V 2.7V to 3.6V 1.65V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V
Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output PLL A Filter PLL B Filter Programmable Clock Output Input Output Input Output Input Input Output
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-up Input ICE and JTAG NTRST TCK TDI TDO TMS JTAGSEL RTCK Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Return Test Clock Input Input Input Output Input Input Output No pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. Low Pull-up resistor No pull-up resistor No pull-up resistor Output Input Driven at 0V only. Do not tie over VDDBU. Accepts between 0V and VDDBU.
6249CS-ATARM-01-Jun-07
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Embedded Trace Module - E Active Level Comments
TSYNC TCLK TPS0 - TPS2 TPK0 - TPK15
Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Trace Packet Port Reset / Test
Output Output Output Output
NRST TST BMS
Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit - DBGU
I / O Input Input
Pull-up resistor Pull-down resistor
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
Advanced Interrupt Controller - AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input Input Input
PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0 - PA31 PB0 - PB31 PC0 - PC31 PD0 - PD31 PE0 - PE31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D Parallel IO Controller E I / O I / O I / O I / O I / O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset
Direct Memory Access Controller - DMA DMARQ0-DMARQ3 DMA Requests Input
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Table 3-1.
Signal Description List (Continued)
Function CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines NAND Flash Support Type Output Output Output Output Output Output Low Active Level Low Low Low Low Comments
NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable SDRAM Controller
Output Output Output
Low Low Low
SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line
Output Output Output Output Output Output Output Low Low High Low
Universal Synchronous Asynchronous Receiver Transmitter USART SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send I / O I / O Input Output Input
Synchronous Serial Controller SSC TDx RDx TKx RKx SSCx Transmit Data SSCx Receive Data SSCx Transmit Clock SSCx Receive Clock Output Input I / O I / O
6249CS-ATARM-01-Jun-07
Table 3-1.
Signal Name TFx RFx
Signal Description List (Continued)
Function SSCx Transmit Frame Sync SSCx Receive Frame Sync AC97 Controller - AC97C Type I / O I / O Active Level Comments
AC97RX AC97TX AC97FS AC97CK
AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Timer / Counter - TC
Input Output Output Input
TCLKx TIOAx TIOBx
TC Channel x External Clock Input TC Channel x I / O Line A TC Channel x I / O Line B
Pulse Width Modulation Controller- PWMC PWMx Pulse Width Modulation Output Output
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Table 3-1.
Signal Name ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Signal Description List (Continued)
Function Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input / Output Force 100Mbit / sec. USB Device Port Type Output Output Output Input Input Input Input Input Output I / O Output High RMII only MII only MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII Active Level Comments
DDM DDP
USB Device Port Data USB Device Port Data + USB Host Port
Analog Analog
HDPA HDMA HDPB HDMB
USB Host Port A Data + USB Host Port A Data USB Host Port B Data + USB Host Port B Data -
Analog Analog Analog Analog
6249CS-ATARM-01-Jun-07
4. Package and Pinout
The AT91SAM9263 is available in a 324-ball Green BGA package, 15 x 15 mm, 0.8mm ball pitch.
324-ball LFBGA Package Outline
Figure 4-1 shows the orientation of the 324-ball BGA package. A detailed mechanical description is given in the section "AT91SAM9263 Mechanical Characteristics" in the product datasheet.
Figure 4-1.
324-ball BGA Pinout (Top View)
Pin A1 Corner
TOP VIEW
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
324-ball BGA Package Pinout
AT91SAM9263 Pinout for 324-ball BGA Package
Table 4-1.
6249CS-ATARM-01-Jun-07
Table 4-1.
Pin C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E5 E6 E7 E8 E9 PC3 GND
AT91SAM9263 Pinout for 324-ball BGA Package
Signal Name
Note:
1. NC pins must be left unconnected.
5. Power Considerations
5.1 Power Supplies
AT91SAM9263 has several types of power supply pins: · VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals voltage ranges from 1.08V to 1.32V, 1.2V nominal. · VDDIOM0 and VDDIOM1 pins: Power the External Bus Interface 0 I / O lines and the External Bus Interface 1 I / O lines, respectively voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). · VDDIOP0 pins: Power the Peripheral I / O lines and the USB transceivers voltage ranges from 2.7V to 3.6V, 3.3V nominal. · VDDIOP1 pins: Power the Peripheral I / O lines involving the Image Sensor Interface voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. · VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller voltage ranges from 1.08V to 1.32V, 1.2V nominal. 12
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
· VDDPLL pin: Powers the PLL cells voltage ranges from 3.0V to 3.6V, 3.3V nominal. · VDDOSC pin: Powers the Main Oscillator cells voltage ranges from 3.0V to 3.6V, L3.3V nominal. The power supplies VDDIOM0, VDDIOM1 and VDDIOP0, VDDIOP1 are identified in the pinout table and the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDOSC, VDDCORE, VDDIOM0, VDDIOM1, VDDIOP0 and VDDIOP1 pins power supplies. Separated ground pins are provided for VDDBU and VDDPLL. These ground pins are respectively GNDBU and GNDPLL.
Power Consumption
The AT91SAM9263 consumes about 700 µA (worst case) of static current on VDDCORE at 25°C. This static current rises at up to 7 mA if the temperature increases to 85°C. On VDDBU, the current does not exceed 3 µA @25°C, but can rise at up to 20 µA @85°C. A software-controllable switch to VDDCORE guarantees zero power consumption on the battery when the system is on. For dynamic power consumption, the AT91SAM9263 consumes a maximum of 70 mA on VDDCORE at maximum conditions (1.2V, 25°C, processor running full-performance algorithm).
Programmable I / O Lines Power Supplies
The power supply pins VDDIOM0 and VDDIOM1 accept two voltage ranges. This allows the device to reach its maximum speed, either out of 1.8V or 3.0V external memories. The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for power supply at 1.8V and 50pF for power supply at 3.3V. The other signals (control, address and data signals) do not go over 50MHz. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. However, the device cannot reach its maximum speed if the voltage supplied to the pins is only 1.8V without reprogramming the EBI0 voltage range. The user must be sure to program the EBI0 voltage range before getting the device out of its Slow Clock Mode.
6. I / O Line Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (VDDBU). It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 6.3. All JTAG signals except JTAGSEL (VDDBU) are supplied with VDDIOP0.
6249CS-ATARM-01-Jun-07
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU.
Reset Pins
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells, which manage the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 k minimum to VDDIOP0. The NRST signal is inserted in the Boundary Scan.
PIO Controllers
All the I / O lines managed by the PIO Controllers integrate a programmable pull-up resistor of 100 k typical. Programming of this pull-up resistor is performed independently for each I / O line through the PIO Controllers. After reset, all the I / O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing tables on page 34 and following.
Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.
7. Processor and Architecture
7.1 ARM926EJ-S Processor
· RISC Processor based on ARM v5TEJ Harvard Architecture with Jazelle technology for Java acceleration · Two Instruction Sets - ARM High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set · DSP Instruction Extensions · 5-stage Pipeline Architecture - Instruction Fetch (F) - Instruction Decode (D)
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
- Execute (E) - Data Memory (M) - Register Write (W) · 16 Kbyte Data Cache, 16 Kbyte Instruction Cache - Virtually-addressed 4-way Associative Cache - Eight words per line - Write-through and Write-back Operation - Pseudo-random or Round-robin Replacement · Write Buffer - Main Write Buffer with 16-word Data Buffer and 4-address Buffer - DCache Write-back Buffer with 8-word Entries and a Single Address Entry - Software Control Drain · Standard ARM v4 and v5 Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for large pages and small pages can be specified separately for each quarter of the page - 16 embedded domains · Bus Interface Unit (BIU) - Arbitrates and Schedules AHB Requests - Separate Masters for both instruction and data access providing complete Matrix system flexibility - Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface - On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
Bus Matrix
· 9-layer Matrix, handling requests from 9 masters · Programmable Arbitration strategy - Fixed-priority Arbitration - Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master · Burst Management - Breaking with Slot Cycle Limit Support - Undefined Burst Length Support · One Address Decoder provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap · Boot Mode Select - Non-volatile Boot Memory can be internal or external - Selection is made by BMS pin sampled at reset · Remap Command
6249CS-ATARM-01-Jun-07
- Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory - Allows Handling of Dynamic Exception Vectors
Matrix Masters
The Bus Matrix of the AT91SAM9263 manages nine masters, thus each master can perform an access concurrently with others to an available slave peripheral or memory. Each master has its own decoder, which is defined specifically for each master. Table 7-1.
Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 Master 6 Master 7 Master 8
List of Bus Matrix Masters
OHCI USB Host Controller Image Sensor Interface 2D Graphic Controller DMA Controller Ethernet MAC LCD Controller Peripheral DMA Controller ARM926 Data ARM926 Instruction
Matrix Slaves
The Bus Matrix of the AT91SAM9263 manages eight slaves. Each slave has its own arbiter, thus allowing to program a different arbitration per slave. The LCD Controller, the DMA Controller, the USB OTG and the USB Host have a user interface mapped as a slave on the Matrix. They share the same layer, as programming them does not require a high bandwidth. Table 7-2.
Slave 0 Slave 1 Slave 2
List of Bus Matrix Slaves
Internal ROM Internal 80 Kbyte SRAM Internal 16 Kbyte SRAM LCD Controller User Interface
Slave 3
DMA Controller User Interface USB Host User Interface
Slave 4 Slave 5 Slave 6
External Bus Interface 0 External Bus Interface 1 Peripheral Bridge
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
7.5 Master to Slave Access
In most cases, all the masters can access all the slaves. However, some paths do not make sense, for example, allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and are shown as "-" in Table 7-3. Table 7-3. Masters to Slaves Access
0 OHCI USB Host Controller X X X X X 1 Image Sensor Interface X X X X X 2 2D Graphics Controller X X X X X 3 DMA Controller X X X X X X 4 Ethernet MAC X X X X X 5 LCD Controller X X X X X 6 Peripheral DMA Controller X X X X X X 7&8 ARM926 Data & Instruction X X X X X X X X X
Master Slave 0 1 2 Internal ROM Internal 80 Kbyte SRAM Internal 16 Kbyte SRAM Bank LCD Controller User Interface 3 DMA Controller User Interface USB Host User Interface 4 5 6 External Bus Interface 0 External Bus Interface 1 Peripheral Bridge
Peripheral DMA Controller
· Acts as one Matrix Master · Allows data transfers between a peripheral and memory without any intervention of the processor · Next Pointer support, removes heavy real-time constraints on buffer management. · Twenty channels - Two for each USART - Two for the Debug Unit - Two for each Serial Synchronous Controller - Two for each Serial Peripheral Interface - Two for the AC97 Controller - One for each Multimedia Card Interface The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (low to high priorities): - DBGU Transmit Channel - USART2 Transmit Channel
6249CS-ATARM-01-Jun-07
- USART1 Transmit Channel - USART0 Transmit Channel - AC97 Transmit Channel - SPI1 Transmit Channel - SPI0 Transmit Channel - SSC1 Transmit Channel - SSC0 Transmit Channel - DBGU Receive Channel - USART2 Receive Channel - USART1 Receive Channel - USART0 Receive Channel - AC97 Receive Channel - SPI1 Receive Channel - SPI0 Receive Channel - SSC1 Receive Channel - SSC0 Receive Channel - MCI1 Transmit / Receive Channel - MCI0 Transmit / Receive Channel
DMA Controller
· Acts as one Matrix Master · Embeds 2 unidirectional channels with programmable priority · Address Generation - Source / destination address programming - Address increment, decrement or no change - DMA chaining support for multiple non-contiguous data blocks through use of linked lists - Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of data into non-contiguous fields in system memory. - Gather support for extracting fields from a system memory area into a contiguous transfer - User enabled auto-reloading of source, destination and control registers from initially programmed values at the end of a block transfer - Auto-loading of source, destination and control registers from system memory at end of block transfer in block chaining mode - Unaligned system address to data transfer width supported in hardware · Channel Buffering - Two 8-word FIFOs - Automatic packing / unpacking of data to fit FIFO width · Channel Control - Programmable multiple transaction size for each channel - Support for cleanly disabling a channel without data loss
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
- Suspend DMA operation - Programmable DMA lock transfer support. · Transfer Initiation - Supports four external DMA Requests - Support for software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface · Interrupt - Programmable interrupt generation on DMA transfer completion, Block transfer completion, Single / Multiple transaction completion or Error condition
Debug and Test Features
· ARM926 Real-time In-circuit Emulator - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel · Debug Unit - Two-pin UART - Debug Communication Channel Interrupt Handling - Chip ID Register · Embedded Trace Macrocell: ETM9 - Medium+ Level Implementation - Half-rate Clock Mode - Four Pairs of Address Comparators - Two Data Comparators - Eight Memory Map Decoder Inputs - Two 16-bit Counters - One 3-stage Sequencer - One 45-byte FIFO · IEEE1149.1 JTAG Boundary-scan on All Digital Pins
6249CS-ATARM-01-Jun-07
8. Memories
Figure 8-1. AT91SAM9263 Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF
Internal Memory Mapping
256M Bytes
0x1000 0000 EBI0 Chip Select 0
0x1FFF FFFF 0x0030 0000
256M Bytes
0x0040 0000 0x0050 0000
0x2000 0000 EBI0 Chip Select 1 / EBI0 SDRAMC 256M Bytes
0x0060 0000 0x0070 0000
Reserved LCD Controller
0x2FFF FFFF
0x3000 0000 EBI0 Chip Select 2
0x3FFF FFFF
256M Bytes
0x0080 0000 DMAC 0x0090 0000 Reserved USB HOST 0x00B0 0000 Reserved
0x4000 0000
EBI0 Chip Select 3 / NANDFlash EBI0 Chip Select 4 / Compact Flash Slot 0 EBI0 Chip Select 5 / Compact Flash Slot 1 EBI1 Chip Select 0
0x00A0 0000
256M Bytes
0x4FFF FFFF
0x5000 0000
256M Bytes
0xF000 0000
Peripheral Mapping
Reserved 0xFFF7 8000 UDP 0xFFF7 C000 TCO, TC1, TC2 0xFFF8 0000 MCI0 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF EE00 AC97C 0xFFFA 4000 SPI0 0xFFFA 8000 SPI1 16K Bytes 16K Bytes 0xFFFA C000 CAN0 0xFFFB 0000 Reserved 0xFFFB 8000 PWMC 0xFFFB C000 EMAC 0xFFFC 0000 Reserved 0xFFFC 4000 ISI 0xFFFC 8000 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FC00 0xFFFF FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 16K Bytes 0xFFFF FDB0 Reserved 0xFFFF FFFF PMC RSTC SHDWC RTT0 PIT WDT RTT1 GPBR 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 80 Bytes 0xFFFF F800 0xFFFF FA00 0xFFFF F600 PIOC PIOD PIOE 512 bytes 512 bytes 512 bytes 16K Bytes 0xFFFF F200 0xFFFF F400 PIOB 512 Bytes 16K Bytes DBGU 0xFFFF F000 AIC PIOA 512 bytes 512 bytes 0xFFFF E000 0xFFFF E200 0xFFFF E400 0xFFFF E600 0xFFFF E800 SDRAMC1 0xFFFF EA00 0xFFFF EC00 0xFFFF ED10 SSC1 0xFFFA 0000 CCFG 512 Bytes SMC1 MATRIX 512 Bytes 512 Bytes 512 Bytes 16K Bytes 16K Bytes 16K Bytes
0x5FFF FFFF
0x6000 0000
System Controller Mapping
0xFFFF C000 Reserved ECC0 SDRAMC0 SMC0 ECC1 512 Bytes 512 Bytes 512 Bytes 512 bytes
256M Bytes
0x6FFF FFFF
0x7000 0000 256M Bytes
0xFFF8 4000 MCI1 0xFFF8 8000
0x7FFF FFFF
0x8000 0000 EBI1 Chip Select 1 / EBI1 SDRAMC
0x8FFF FFFF
256M Bytes
0xFFF8 C000 USART0 0xFFF9 0000 USART1
0x9000 0000 EBI1 Chip Select 2 / NANDFlash
0x9FFF FFFF
256M Bytes
0xFFF9 4000 USART2 0xFFF9 8000 SSC0 0xFFF9 C000
0xA000 0000
Undefined (Abort)
1, 280M Bytes
0xEFFF FFFF
2DGE 0xFFFC C000 Reserved
0xF000 0000 Internal Peripherals
0xFFFF FFFF
256M Bytes
0xFFFF C000 SYSC 0xFFFF FFFF
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Embedded Memories
· 128 Kbyte ROM - Single Cycle Access at full matrix speed · One 80 Kbyte Fast SRAM - Single Cycle Access at full matrix speed - Supports ARM926EJ-S TCM interface at full processor speed - Allows internal Frame Buffer for up to 1 / 4 VGA 8 bpp screen · 16 Kbyte Fast SRAM - Single Cycle Access at full matrix speed
Internal Memory Mapping Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap status and the BMS state at reset. Table 8-1. Internal Memory Mapping
Internal 80 Kbyte Fast SRAM The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split into three areas. Its memory mapping is presented in Figure 8-1 on page 20. · Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR
6249CS-ATARM-01-Jun-07
configuration register located in the Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000. · Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000. · Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 80 Kbytes of SRAM available, the amount of memory assigned to each block is software programmable as a multiple of 16 Kbytes as shown in Table 8-2. This table provides the size of the Internal SRAM C according to the size of the internal SRAM A and the internal SRAM B. Table 8-2. Internal SRAM Block Size
Internal SRAM A (ITCM) Size Internal SRAM C Internal SRAM B (DTCM) size 0 16 Kbytes 32 Kbytes 0 80 Kbytes 64 Kbytes 48 Kbytes 16 Kbytes 64 Kbytes 48 Kbytes 32 Kbytes 32 Kbytes 48 Kbytes 32 Kbytes 16 Kbytes
Note that among the five 16 Kbyte blocks making up the Internal SRAM, one is permanently assigned to Internal SRAM C. At reset, the whole memory (80 Kbytes) is assigned to Internal SRAM C. The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the previous configuration from a software point of view. Table 8-3 illustrates different configurations and the related 16 Kbyte blocks assignments (RB0 to RB4). Table 8-3. 16 Kbyte Block Allocation
Configuration examples and related 16 Kbyte block assignments Decoded Area Internal SRAM A (ITCM) Internal SRAM B (DTCM)
Address 0x0010 0000 0x0010 4000 0x0020 0000 0x0020 4000
RB1 RB0 RB3 RB2
RB1 RB0
RB3 RB2
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Table 8-3. 16 Kbyte Block Allocation (Continued)
Configuration examples and related 16 Kbyte block assignments Decoded Area
Address 0x0030 0000
RB4 RB3 RB2 RB1 RB0
RB4 RB0
RB4 RB2
RB4 RB2 RB0
Internal SRAM C (AHB)
0x0030 4000 0x0030 8000 0x0030 C000 0x0031 0000
Note:
1. Configuration after reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 20.
6249CS-ATARM-01-Jun-07
External Memories
The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256 Mbyte memory area assigned. Refer to Figure 8-1 on page 20.
External Bus Interfaces The AT91SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent bottlenecks while accessing external memories. External Bus Interface 0 · Integrates three External Memory Controllers: - Static Memory Controller - SDRAM Controller - ECC Controller · Additional logic for NANDFlash and CompactFlash · Optional Full 32-bit External Data Bus · Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select) · Up to 6 Chip Selects, Configurable Assignment: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3, Optional NAND Flash support - Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
8.2.1.2 External Bus Interface 1 · Integrates three External Memory Controllers: - Static Memory Controller - SDRAM Controller - ECC Controller · Additional logic for NANDFlash · Optional Full 32-bit External Data Bus · Up to 23-bit Address Bus (up to 8 Mbytes linear) · Up to 3 Chip Selects, Configurable Assignment: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2, Optional NAND Flash support 8.2.2 Static Memory Controller · 8-, 16- or 32-bit Data Bus · Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) · Multiple device adaptability - Compliant with LCD Module - Control signals programmable setup, pulse and hold time for each Memory Bank · Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time · Slow Clock mode supported 8.2.3 SDRAM Controller · Supported devices - Standard and Low-power SDRAM (Mobile SDRAM) · Numerous configurations supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with two or four Internal Banks - SDRAM with 16- or 32-bit Data Path · Programming facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached - Multibank Ping-pong Access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable · Energy-saving capabilities
6249CS-ATARM-01-Jun-07
- Self-refresh, power down and deep power down modes supported · Error detection - Refresh Error Interrupt · SDRAM Power-up Initialization by software · CAS Latency of 1, 2 and 3 supported · Auto Precharge Command not used 8.2.4 Error Corrected Code Controller · Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select · Single-bit error correction and two-bit random detection · Automatic Hamming Code Calculation while writing - ECC value available in a register · Automatic Hamming Code Calculation while reading - Error Report, including error flag, correctable error flag and word address being detected erroneous - Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages
9. System Controller
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
9.1 System Controller Block Diagram
AT91SAM9263 System Controller Block Diagram
Figure 9-1.
Debug Unit
VDDCORE VDDBU
PLLACK PLLBCK
PIO Controllers
6249CS-ATARM-01-Jun-07
Reset Controller
· Based on two Power-on-Reset cells - One on VDDBU and one on VDDCORE · Status of the last reset - Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset · Controls the internal resets and the NRST pin output - Allows shaping a reset signal for the external devices
Shutdown Controller
· Shutdown and Wake-up logic - Software programmable assertion of the SHDN pin (SHDN is push-pull) - Deassertion programmable on a WKUP pin level change or on alarm
Clock Generator
· Embeds the low-power 32768 Hz Slow Clock Oscillator - Provides the permanent Slow Clock SLCK to the system · Embeds the Main Oscillator - Oscillator bypass feature - Supports 3 to 20 MHz crystals · Embeds 2 PLLs - Output 80 to 240 MHz clocks - Integrates an input divider to increase output accuracy - 1 MHz Minimum input frequency
Figure 9-2.
Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK
PLLRCA
PLL and Divider A PLL and Divider B Status Control
PLLA Clock PLLACK PLLB Clock PLLBCK
PLLRCB
Power Management Controller
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
9.5 Power Management Controller
· Provides: - the Processor Clock PCK - the Master Clock MCK, in particular to the Matrix and the memory interfaces - the USB Device Clock UDPCK - the USB Host Clock UHPCK - independent peripheral clocks, typically at the frequency of MCK - four programmable clock outputs: PCK0 to PCK3 · Five flexible operating modes: - Normal Mode with processor and peripherals running at a programmable frequency - Idle Mode with processor stopped while waiting for an interrupt - Slow Clock Mode with processor and peripherals running at low frequency - Standby Mode, mix of Idle and Backup Mode, with peripherals running at low frequency, processor stopped waiting for an interrupt - Backup Mode with Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9263 Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler / 1, / 2, / 4, .., / 64 Divider / 1, / 2, / 3, / 4 Peripherals Clock Controller ON / OFF Idle Mode MCK PCK int
Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON / OFF Prescaler / 1, / 2, / 4, .., / 64 pck.
USB Clock Controller PLLBCK Divider / 1, / 2, / 4 ON / OFF UDPCK UHPCK
Periodic Interval Timer
· Includes a 20-bit Periodic Counter, with less than 1 µs accuracy · Includes a 12-bit Interval Overlay Counter · Real-time OS or Linux® / WindowsCE® compliant tick generator
Watchdog Timer
· 16-bit key-protected Counter, programmable only once
6249CS-ATARM-01-Jun-07
· Windowed, prevents the processor deadlocking on the watchdog access
Real-time Timer
· Two Real-time Timers, allowing backup of time with different accuracies - 32-bit Free-running back-up counter - Integrates a 16-bit programmable prescaler running on the embedded 32.768Hz oscillator - Alarm Register capable of generating a wake-up of the system through the Shutdown Controller
General-purpose Backup Registers
· Twenty 32-bit general-purpose backup registers
Backup Power Switch
· Automatic switch of VDDBU to VDDCORE guaranteeing very low power consumption on VDDBU while VDDCORE is present
Advanced Interrupt Controller
· Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor · Thirty-two individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) - Programmable Edge-triggered or Level-sensitive Internal Sources - Programmable Positive / Negative Edge-triggered or High / Low Level-sensitive · Four External Sources plus the Fast Interrupt signal · 8-level Priority Controller - Drives the Normal Interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt · Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector · Protect Mode - Easy debugging by preventing automatic operations when protect models are enabled · Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
Debug Unit
· Composed of two functions - Two-pin UART
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
Chip Identification
· Chip ID: 0x019607A0 · JTAG ID: 0x05B0C03F · ARM926 TAP ID: 0x0792603F
PIO Controllers
· Five PIO Controllers, PIOA to PIOE, controlling a total of 160 I / O Lines · Each PIO Controller controls up to 32 programmable I / O Lines - PIOA has 32 I / O Lines - PIOB has 32 I / O Lines - PIOC has 32 I / O Lines - PIOD has 32 I / O Lines - PIOE has 32 I / O Lines · Fully programmable through Set / Clear Registers · Multiplexing of two peripheral functions per I / O Line · For each I / O Line (whether assigned to a peripheral or used as general-purpose I / O) - Input change interrupt - Glitch filter - Multi-drive option enables driving in open drain - Programmable pull-up on each I / O line - Pin data status register, supplies visibility of the level on the pin at any time · Synchronous output, provides Set and Clear of several I / O lines in a single write
6249CS-ATARM-01-Jun-07
10. Peripherals
10.1 User Interface
The Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 20.
Identifiers
Table 10-1 defines the Peripheral Identifiers. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
Table 10-1.
AT91SAM9263 Peripheral Identifiers
Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC to PIOE reserved reserved US0 US1 US2 MCI0 MCI1 CAN TWI SPI0 SPI1 SSC0 SSC1 AC97C TC0, TC1, TC2 PWMC EMAC reserved 2DGE UDP ISI LCDC DMA reserved UHP AIC AIC USB Host Port Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 2D Graphic Engine USB Device Port Image Sensor Interface LCD Controller DMA Controller USART 0 USART 1 USART 2 Multimedia Card Interface 0 Multimedia Card Interface 1 CAN Controller Two-Wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 AC97 Controller Timer / Counter 0, 1 and 2 Pulse Width Modulation Controller Ethernet MAC Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I / O Controller A Parallel I / O Controller B Parallel I / O Controller C, D and E External Interrupt FIQ
Peripheral ID
Note:
Setting AIC, SYSC, UHP and IRQ0 - 1 bits in the clock set / clear registers of the PMC has no effect.
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
10.2.1 10.2.1.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: · the SDRAM Controller · the Debug Unit · the Periodic Interval Timer · the Real-Time Timer · the Watchdog Timer · the Reset Controller · the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. Timer Counter Interrupts The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 19 of the Advanced Interrupt Controller. This forces the programmer to read all Timer Counter status registers before branching the right Interrupt Service Routine. The Timer Counter channels clocks cannot be deactivated independently. Switching off the clock of the Peripheral 19 disables the clock of the 3 channels.
Peripherals Signals Multiplexing on I / O Lines
6249CS-ATARM-01-Jun-07
PIO Controller A Multiplexing Multiplexing on PIO Controller A
Table 10-2.
I / O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
10.3.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B
Table 10-3.
6249CS-ATARM-01-Jun-07
PIO Controller C Multiplexing Multiplexing on PIO Controller C
PIO Controller C Application Usage Reset State I / O I / O I / O PWM1 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 ETX2 ETX3 ERX2 ERX3 ETXER ERXDV ECOL ERXCK TCLK1 PWM2 I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function Comments
Table 10-4.
I / O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
Peripheral A LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM0 PCK0 DRXD DTXD
Peripheral B
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
10.3.4 PIO Controller D Multiplexing Multiplexing on PIO Controller D
Table 10-5.
6249CS-ATARM-01-Jun-07
PIO Controller E Multiplexing Multiplexing on PIO Controller E
Table 10-6.
I / O Line PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31
Peripheral B
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
System Resource Multiplexing
LCD Controller The LCD Controller can interface with several LCD panels. It supports 4 bits per pixel (bpp), 8 bpp or 16 bpp without limitation. Interfacing 24 bpp TFT panels prevents using the Ethernet MAC. 16 bpp TFT panels are interfaced through peripheral B functions, as color data is output on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on LCDD10. Using the peripheral B does not prevent using MAC lines. 16 bpp STN panels are interfaced through peripheral A and color data is output on LCDD0 to LCDD15, thus MAC lines can be used on peripheral B. Mapping the LCD signals on peripheral A and peripheral B makes is possible to use 24 bpp TFT panels in 24 bits (peripheral A) or 16 bits (peripheral B) by reprogramming the PIO controller and thus without hardware modification.
EBI1 Using the following features prevents using EBI1 in 32-bit mode: · the second slots of MCI0 and / or MCI1 · USART0 · DMA request 0 (DMARQ0) · Ethernet 10 / 100 MAC
SSC Using SSC0 prevents using the AC97 Controller and Two-wire Interface. Using SSC1 prevents using DMA Request 1, PWM0, PWM1, LCDCC and PCK1.
NAND Flash Using the NAND Flash interface on EBI1 prevents using Ethernet MAC.
CompactFlash Using the CompactFlash interface prevents using NCS4 and / or NCS5 to access other parallel devices.
SPI0 and MCI Interface SPI0 signals and MCI0 signals are multiplexed, as the DataFlash Card is hardware-compatible with the SDCard. Only one can be used at a time.
6249CS-ATARM-01-Jun-07
Interrupts Using IRQ0 prevents using the CAN controller. Using FIQ prevents using DMA Request 2.
Embedded Peripherals Overview
Serial Peripheral Interface · Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors · Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection · Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device
Two-wire Interface · Master Mode only · Compatibility with standard two-wire serial memory · One, two or three bytes for slave address · Sequential read / write operations
USART · Programmable Baud Rate Generator · 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
- Delay Timing - Pulse Width Modulation - Up / down Capabilities · Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input / output signals · Two global registers that act on all three TC Channels 10.5.7 Pulse Width Modulation Controller · 4 channels, one 16-bit counter per channel · Common clock generator, providing thirteen different clocks - Modulo n counter providing eleven clocks - Two independent Linear Dividers working on modulo n counter outputs · Independent channel programming - Independent Enable Disable commands - Independent clock selection - Independent period and duty cycle, with double bufferization - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform 10.5.8 Multimedia Card Interface · Two double-channel Multimedia Card Interfaces, allowing concurrent transfers with 2 cards · Compatibility with MultiMediaCard Specification Version 2.2 · Compatibility with SD Memory Card Specification Version 1.0 · Compatibility with SDIO Specification Version V1.0. · Cards clock rate up to Master Clock divided by 2 · Embedded power management to slow down clock rate when not used · Each MCI has two slots, each supporting - One slot for one MultiMediaCard bus (up to 30 cards) or - One SD Memory Card · Support for stream, block and multi-block data read and write 10.5.9 CAN Controller · Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers · Bit rates up to 1Mbit / s. · Object-oriented mailboxes, each with the following properties: - CAN Specification 2.0 Part A or 2.0 Part B programmable for each message - Object Configurable as receive (with overwrite or not) or transmit - Local Tag and Mask Filters up to 29-bit Identifier / Channel - 32 bits access to Data registers for each mailbox data object - Uses a 16-bit time stamp on receive and transmit message
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
- Hardware concatenation of ID unmasked bitfields to speedup family ID processing - 16-bit internal timer for Time Stamping and Network synchronization - Programmable reception buffer length up to 16 mailbox object - Priority Management between transmission mailboxes - Autobaud and listening mode - Low power mode and programmable wake-up on bus activity or by the application - Data, Remote, Error and Overload Frame handling 10.5.10 USB Host Port · Compliant with Open HCI Rev 1.0 Specification · Compliant with USB V2.0 full-speed and low-speed specification · Supports both low-speed 1.5 Mbps and full-speed 12 Mbps devices · Root hub integrated with two downstream USB ports · Two embedded USB transceivers · Supports power management · Operates as a master on the matrix 10.5.11 USB Device Port · USB V2.0 full-speed compliant, 12 Mbits per second · Embedded USB V2.0 full-speed transceiver · Embedded 2, 432-byte dual-port RAM for endpoints · Suspend / Resume logic · Ping-pong mode (two memory banks) for isochronous and bulk endpoints · Six general-purpose endpoints - Endpoint 0 and 3: 64 bytes, no ping-pong mode - Endpoint 1 and 2: 64 bytes, ping-pong mode - Endpoint 4 and 5: 512 bytes, ping-pong mode 10.5.12 LCD Controller · Single and Dual scan color and monochrome passive STN LCD panels supported · Single scan active TFT LCD panels supported · 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported · Up to 24-bit single scan TFT interfaces supported · Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays · 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN · 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN · 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT · Single clock domain architecture · Resolution supported up to 2048x2048 · 2D DMA Controller for management of virtual Frame Buffer - Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer
6249CS-ATARM-01-Jun-07
· Automatic resynchronization of the frame buffer pointer to prevent flickering 10.5.13 2D Graphics Controller · Acts as one Matrix Master · Commands are passed through the APB User Interface · Operates directly in the frame buffer of the LCD Controller - Line draw - Block transfer - Polygon fill - Clipping · Commands queuing through a FIFO 10.5.14 Ethernet 10 / 100 MAC · Compatibility with IEEE Standard 802.3 · 10 and 100 Mbits per second data throughput capability · Full- and half-duplex operations · MII or RMII interface to the physical layer · Register Interface to address, data, status and control registers · DMA Interface, operating as a master on the Memory Controller · Interrupt generation to signal receive and transmit completion · 28-byte transmit and 28-byte receive FIFOs · Automatic pad and CRC generation on transmitted frames · Address checking logic to recognize four 48-bit addresses · Support promiscuous mode where all valid frames are copied to memory · Support physical layer management through MDIO interface control of alarm and update time / calendar data in 10.5.15 Image Sensor Interface · ITU-R BT. 601 / 656 8-bit mode external interface support · Support for ITU-R BT.656-4 SAV and EAV synchronization · Vertical and horizontal resolutions up to 2048 x 2048 · Preview Path up to 640480 · Support for packed data formatting for YCbCr 4:2:2 formats · Preview scaler to generate smaller size image · Programmable frame capture rate
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
11. Package Drawing
Figure 11-1. 324-ball TFBGA Package Drawing
Table 11-1.
Ball Land
Soldering Information
0.4 mm + / - 0.05 0.275 mm + / - 0.03
Soldering Mask Opening
Table 11-2.
Device and 324-balls TFBGA Package Maximum Weight
Table 11-3.
324-balls TFBGA Package Characteristics
Moisture Sensitivity Level
Table 11-4.
Package Reference
MO-210 e1
JEDEC Drawing Reference JESD97 Classification
This package respects the recommendations of the NEMI User Group.
6249CS-ATARM-01-Jun-07
12. AT91SAM9263 Ordering Information
Table 12-1. AT91SAM9263 Ordering Information
Package BGA324 Package Type Green Temperature Operating Range Industrial -40°C to 85°C Ordering Code AT91SAM9263-CU
AT91SAM9263 Preliminary
6249CS-ATARM-01-Jun-07
AT91SAM9263 Preliminary
13. Revision History
Table 13-1. Revision History
Comments In Section 4.1 "324-ball LFBGA Package Outline" on page 10 corrected package top view. All new information for Table 7-1, "List of Bus Matrix Masters, " on page 16, Table 7-2, "List of Bus Matrix Slaves, " on page 16 and Table 7-3, "Masters to Slaves Access, " on page 17. In Section 9.3 "Shutdown Controller" on page 28, corrected reference to shutdown pin. In Section 5.2 "Power Consumption" on page 13, specified static current consumption as worst case. Corrected Section 10.4.6 "NAND Flash" on page 39, with information on EMAC. In Section 10.4.3 "EBI1" on page 39, added Ethernet 10 / 100 MAC to the System Resource Multiplexing list of EBI1. In Section 10.4.10 "Image Sensor Interface" on page 40 and Section 10.4.11 "Timers" on page 40, removed mention of keyboard interfaces. Corrected typo to IDE hard disk in Section 1. "Description" on page 3. 6249BS Corrected ordering code in Section 12. "AT91SAM9263 Ordering Information" on page 46. First issue. Change Request Ref. Document Ref. 6249CS 4463
6249AS
6249CS-ATARM-01-Jun-07
Headquarters
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF / Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Microcontrollers
International
Atmel Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-47-50 Fax: (33) 4-76-58-47-60
Atmel Europe
Le Krebs 8, rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11
ASIC / ASSP / Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Atmel Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com / literature
6249CS-ATARM-01-Jun-07