AT91 Thumb-based Microcontrollers AT91SAM9261S Preliminary Summary

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AT91 Thumb-based Microcontrollers AT91SAM9261S Preliminary Summary

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Instruction Extensions Jazelle® Technology Java® Acceleration Kbyte Data Cache, Kbyte Instruction Cache, Write Buffer MIPS Memory Management Unit EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support Additional Embedded Memories Kbytes Internal ROM, Single-cycle Access Maximum Speed Kbytes Internal SRAM, Single-cycle Access Maximum Speed External Interface (EBI) Supports SDRAM, Static Memory, NANDFlash CompactFlash® Controller Supports Passive Active Displays 16-bits Pixel Color Mode Colors Mode (24-bit Pixel), Resolution 2048 2048 Full Speed Mbits second) Host Double Port Dual On-chip Transceivers Integrated FIFOs Dedicated Channels Full Speed Mbits second) Device Port On-chip Transceiver, Kbyte Configurable Integrated FIFOs Matrix Handles Five Masters Five Slaves Boot Mode Select Option Remap Command Fully Featured System Controller (SYSC) Efficient System Management, including Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers Total Bytes Clock Generator Power Management Controller Advanced Interrupt Controller Debug Unit Periodic Interval Timer, Watchdog Timer Real-time Timer Three 32-bit Controllers Reset Controller (RSTC) Based Power-on Reset Cells, Reset Source Identification Reset Output Control Shutdown Controller (SHDWC) Programmable Shutdown Control Wake-up Circuitry Clock Generator (CKGR) 32.768 Low-power Oscillator Battery Backup Power Supply, Providing Permanent Slow Clock On-chip Oscillator PLLs Power Management Controller (PMC) Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
AT91 Thumb-based Microcontrollers AT91SAM9261S Preliminary Summary
6242BS-ATARM-14-Sep-07
Three External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU) 2-wire USART support Debug Communication Channel, Programmable Access Prevention Periodic Interval Timer (PIT) 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) Protected, Programmable Only Once, Windowed 12-bit Counter, Running Slow Clock Real-Time Timer (RTT) 32-bit Free-running Backup Counter Running Slow Clock Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB PIOC Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up Resistor Synchronous Output Nineteen Peripheral (PDC) Channels MultiMedia Card Interface (MCI) MultiMediaCardand SDCard Compliant Automatic Protocol Control Fast Automatic Data Transfers with PDC, SDCard Compliant Three Synchronous Serial Controllers (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation Support ISO7816 T0/T1 Smart Card, Hardware Software Handshaking, RS485 Support Master/Slave Serial Peripheral Interface (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three-channel 16-bit Timer/Counters (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Two-wire Interface (TWI) Master, Multi-master Slave Mode Operation General Call supported Slave Mode IEEE® 1149.1 JTAG Boundary Scan Digital Pins Required Power Supplies: 1.08V 1.32V VDDCORE VDDBU 3.0V 3.6V VDDOSC VDDPLL 1.6V 1.95V 3.0V 3.6V VDDIOM (Memory I/Os) 2.7V 3.6V VDDIOP (Peripheral I/Os) Available 217-ball LFBGA RoHS-compliant Package
AT91SAM9261S Preliminary
6242BS-ATARM-14-Sep-07
AT91SAM9261S Preliminary
Description
AT91SAM9261S complete system-on-chip built around ARM926EJ-S Thumb processor with extended instruction Jazelle Java accelerator. achieves MIPS MHz. AT91SAM9261S optimized host processor applications with display. integrated controller supports color, active passive displays. External Interface incorporates controllers synchronous DRAM (SDRAM) Static memories features specific interface circuitry CompactFlash NAND Flash. AT91SAM9261S integrates software controlled Power Management Controller (PMC) that keeps system power consumption minimum selectively enabling/disabling processor various peripherals adjustment operating frequency. AT91SAM9261S also benefits from integration wide range debug features including JTAG-ICE dedicated UART debug channel (DBGU). This enables development debug applications, especially those with real-time constraints.
6242BS-ATARM-14-Sep-07
Block Diagram
Figure 2-1.
JTAGSEL NTRST RTCK
AT91SAM9261S Block Diagram
ARM926EJ-S Core
JTAG Boundary Scan Instruction Cache bytes
Data Cache bytes
System Controller IRQ0-IRQ2 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XOUT DBGU Fast SRAM bytes
CompactFlash NAND Flash
PLLA PLLB Fast bytes 5-layer Matrix Peripheral Bridge Peripheral Controller RSTC PIOA PIOB PIOC FIFO Device Host FIFO Transceiver
SDRAM Controller
GPBREG XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST SHDWC
Static Memory Controller
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A21 A22/REG A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 NWAIT A23-A24 A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 NCS6/NANDOE NCS7/NANDWE D16-D31 HDMA HDPA HDMB HDPB
Transceiver
MCCK MCCDA MCDA0-MCDA3 FIFO RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK Controller LCDD0-LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWCK
USART0
SSC0
USART1
SSC1 SSC2 Timer Counter
USART2
SPI0
SPI1
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Signal Description
Table 3-1.
Signal Name
Signal Description Peripheral
Function Power Type Active Level Comments
VDDIOM VDDIOP VDDBU VDDPLL VDDOSC VDDCORE GNDPLL GNDOSC GNDBU
Lines Power Supply Peripherals Lines Power Supply Backup Lines Power Supply Power Supply Oscillator Power Supply Core Chip Power Supply Ground Ground Oscillator Ground Backup Ground
Power Power Power Power Power Power Ground Ground Ground Ground
1.65V 1.95V 3.0V 3.6V 2.7V 3.6V 1.08V 1.32V 3.0V 3.6V 3.0V 3.6V 1.08V 1.32V
Clocks, Oscillators PLLs XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Filter Filter Programmable Clock Output Input Output Input Output Input Input Output
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-Up Input Output Input JTAG RTCK NTRST JTAGSEL Test Clock Returned Test Clock Test Data Test Data Test Mode Select Test Reset Signal JTAG Selection Input Output Input Output Input Input Input Reset/Test NRST Microcontroller Reset Test Mode Select Boot Mode Select Input Input Pull-up resistor Pull-down resistor. pull-up resistor. Pull-up resistor. Pull-down resistor. over VDDBU. pull-up resistor. pull-up resistor. pull-up resistor. over VDDBU Accept between VDDBU.
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Table 3-1.
Signal Name
Signal Description Peripheral (Continued)
Function Type Debug Unit Active Level Comments
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
IRQ0 IRQ2
External Interrupt Inputs Fast Interrupt Input
Input Input
PA31 PB31 PC31
Parallel Controller Parallel Controller Parallel Controller
Pulled-up input reset Pulled-up input reset Pulled-up input reset
NWAIT
Data Address External Wait Signal
Output Input
Pulled-up input reset reset
NCS0 NCS7 NWR0 NWR3 NBS0 NBS3
Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal
Output Output Output Output Output CompactFlash Support
CFCE1 CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 CFCS1
CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read CompactFlash Write CompactFlash Read Write CompactFlash Chip Select Lines
Output Output Output Output Output Output Output
NANDFlash Support NANDOE NANDWE NANDCS NANDFlash Output Enable NANDFlash Write Enable NANDFlash Chip Select Output Output Output SDRAM Controller SDCK SDCKE SDCS SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Output Output Output High
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Table 3-1.
Signal Name SDWE SDA10
Signal Description Peripheral (Continued)
Function Bank Select SDRAM Write Enable Column Signal SDRAM Address Line Type Output Output Output Output Multimedia Card Interface Active Level Comments
MCCK MCCDA MCDA0 MCDA3
Multimedia Card Clock Multimedia Card Command Multimedia Card Data USART
Output
SCK0 SCK2 TXD0 TXD2 RXD0 RXD2 RTS0 RTS2 CTS0 CTS2
Serial Clock Transmit Data Receive Data Request Send Clear Send
Output Input Output Input Synchronous Serial Controller
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input Timer/Counter
TCLK0 TCLK2 TIOA0 TIOA2 TIOB0 TIOB2
External Clock Input Line Line
Input
SPI0_MISO SPI1_MISO SPI0_MOSI SPI1_MOSI SPI0_SPCK SPI1_SPCK SPI0_NPCS0, SPI1_NPCS0 SPI0_NPCS1 SPI0_NPCS3 SPI1_NPCS1 SPI1_NPCS3
Master Slave Master Slave Serial Clock Peripheral Chip Select
Peripheral Chip Select
Output
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Table 3-1.
Signal Name
Signal Description Peripheral (Continued)
Function Type Two-Wire Interface Active Level Comments
TWCK
Two-wire Serial Data Two-wire Serial Clock
Controller
LCDD0 LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC
Data Vertical Synchronization Horizontal Synchronization Clock Data Enable Contrast Control
Output Output Output Output Output Output Device Port
Device Port Data Device Port Data
Analog Analog Host Port
HDMA HDPA HDMB HDPB
Host Port Data Host Port Data Host Port Data Host Port Data
Analog Analog Analog Analog
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Package Pinout
AT91SAM9261S available 217-ball LFBGA RoHS-compliant package, ball pitch
217-ball LFBGA Package Outline
Figure shows orientation 217-ball LFBGA Package. detailed mechanical description given section "AT91SAM9261S Mechanical Characteristics" product datasheet. Figure 4-1. 217-ball LFBGA Package Outline (Top View)
Ball
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Pinout
AT91SAM9261S Pinout 217-ball LFBGA Package (4.2)
Signal Name A16/BA0 XOUT32 XIN32 HDPB HDMB PB27 PB24 A1/NBS2/NWR2 VDDBU JTAGSEL WKUP PB31 HDMA PB26 PB25 PB19 VDDIOM A17/BA1 VDDIOM VDDIOM GNDBU HDPA PB30 VDDIOP PB21 Signal Name VDDCORE A0/NBS0 SHDN VDDIOP PB29 PB28 PB23 PB20 PB17 NWR1/NBS1/CFIOR NWR0/NWE/CFWE NRD/CFOE SDA10 PB22 PB18 PB15 SDCKE NWR3/NBS3/CFIOW NCS0 PB16 NRST NTRST SDWE NCS3/NANDCS PB14 PB12 PB11 VDDIOM SDCK PB10 PB13 Signal Name VDDIOP VDDCORE PB3/BMS VDDIOM PA30 PA27 PA31 PC18 VDDCORE PA25 PA26 PA28 PA29 PC17 PC31 VDDIOM PA22 PA21 PA23 PA24 PC16 PC30 PC22 PC24 PC28 PC11 GNDPLL VDDIOP Signal Name PA20 PC19 PC21 PC27 PC29 PC12 PC14 VDDPLL PA10 PA13 PA17 PA18 PC20 PC23 PC26 VDDIOP PC10 PC15 VDDOSC GNDOSC PA11 PA14 PC25 VDDIOP PC13 PLLRCB PLLRCA XOUT PA12
Table 4-1.
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Table 4-1.
AT91SAM9261S Pinout 217-ball LFBGA Package (4.2) (Continued)
Signal Name NCS2 NCS1/SDCS VDDIOM Signal Name Signal Name VDDCORE PA15 PA16 VDDIOP PA19 Signal Name RTCK
Note:
Shaded cells define pins powered VDDIOM.
Power Considerations
Power Supplies
AT91SAM9261S types power supply pins: VDDCORE pins: Power core, including processor, memories peripherals; voltage ranges from 1.08V 1.32V, 1.2V nominal. VDDIOM pins: Power External Interface lines; voltage ranges from 1.65 1.95V 3.0V 3.6V, 3.3V nominal. VDDIOP pins: Power Peripheral lines transceivers; voltage ranges from 2.7V 3.6V, 3.3V nominal. VDDBU pin: Powers Slow Clock oscillator part System Controller; voltage ranges from 1.08V 1.32V, 1.2V nominal. VDDPLL pin: Powers cells; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDOSC pin: Powers Main Oscillator cells; voltage ranges from 3.0V 3.6V, 3.3V nominal. double power supplies VDDIOM VDDIOP identified Table page These supplies enable user power device differently interfacing with memories interfacing with peripherals. Ground pins common VDDCORE, VDDIOM VDDIOP pins power supplies. Separated ground pins provided VDDBU, VDDOSC VDDPLL. ground pins GNDBU, GNDOSC GNDPLL, respectively.
Power Consumption
AT91SAM9261S consumes about static current VDDCORE 25°C. This static current rises temperature increases 85°C. VDDBU, current does exceed @25°C, rise @85°C. dynamic power consumption, AT91SAM9261S consumes maximum VDDCORE maximum speed typical conditions (1.2V, 25°C), processor running full-performance algorithm.
Line Considerations
JTAG Port Pins
TMS, Schmitt trigger inputs have pull-up resistors.
6242BS-ATARM-14-Sep-07
RTCK outputs, driven VDDIOP, have pull-up resistor. JTAGSEL used select JTAG boundary scan when asserted high level (tied VDDBU). integrates permanent pull-down resistor about GNDBU, that left unconnected normal operations. NTRST used initialize embedded Controller when asserted level. integrates permanent pull-up resistor about VDDIOP, that left unconnected normal operations.
Test
used manufacturing test purposes when asserted high. integrates permanent pull-down resistor about GNDBU, that left unconnected normal operations. Driving this line high level leads unpredictable results.
Reset
NRST open-drain output integrating non-programmable pull-up resistor. driven with voltage VDDIOP. product integrates power-on reset cells, NRST left unconnected case reset from system needs applied product. NRST integrates permanent pull-up resistor minimum VDDIOP. NRST signal inserted Boundary Scan.
Controller Lines
lines PA31, PB31, PC31 integrate programmable pull-up resistor Programming this pull-up resistor performed independently each line through Controllers. After reset, lines default inputs with pull-up resistors enabled, except those which multiplexed with External Interface signals that require enabled Peripherals reset. This explicitly indicated column "Reset State" Controller multiplexing tables.
Shutdown Logic Pins
SHDN output only, driven Shutdown Controller. WKUP input only. accept voltages only between VDDBU.
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Processor Architecture
ARM926EJ-S Processor
RISC Processor Based v5TEJ Architecture with Jazelle technology Java acceleration Instruction Sets High-performance 32-bit Instruction Thumb High Code Density 16-bit Instruction Instruction Extensions 5-Stage Pipeline Architecture: Instruction Fetch Instruction Decode Execute Data Memory Register Write Kbyte Data Cache, Kbyte Instruction Cache Virtually-addressed 4-way Associative Cache Eight words line Write-through Write-back Operation Pseudo-random Round-robin Replacement Write Buffer Main Write Buffer with 16-word Data Buffer 4-address Buffer DCache Write-back Buffer with 8-word Entries Single Address Entry Software Control Drain Standard Memory Management Unit (MMU) Access Permission Sections Access Permission large pages small pages specified separately each quarter page embedded domains Interface Unit (BIU) Arbitrates Schedules Requests Separate Masters both instruction data access providing complete system flexibility Separate Address Data Buses both 32-bit instruction interface 32-bit data interface Address Data Buses, data 8-bit (Bytes), 16-bit (Half-words) 32-bit (Words)
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Debug Test Integrated Embedded In-circuit Emulator Real-Time real-time Watchpoint Units Independent Registers: Debug Control Register Debug Status Register Test Access Port Accessible through JTAG Protocol Debug Communications Channel Debug Unit Two-pin UART Debug Communication Channel Interrupt Handling Chip Register Embedded Trace MacrocellTM: ETM9- Medium+ Level Implementation Half-rate Clock Mode Four Pairs Address Comparators Data Comparators Eight Memory Decoder Inputs 16-bit Counters 3-stage Sequencer 45-byte FIFO IEEE1149.1 JTAG Boundary-scan Digital Pins
Matrix
Five Masters Five Slaves handled Handles Requests from ARM926EJ-S, Host Port, Controller Peripheral Controller internal ROM, internal SRAM, EBI, APB, Controller Host Port. Round-Robin Arbitration (three modes supported: default master, last accessed default master, fixed default master) Burst Breaking with Slot Cycle Limit Address Decoder Provided Master Three different slaves assigned each decoded memory area: internal boot, external boot, after remap. Boot Mode Select Option Non-volatile Boot Memory Internal External. Selection made sampled reset. Remap Command Allows Remapping Internal SRAM Place Boot Non-Volatile Memory Allows Handling Dynamic Exception Vectors
Peripheral Controller
Transfers from/to peripheral to/from memory space without intervention processor. Next Pointer Support, forbids strong real-time constraints buffer management.
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Nineteen channels each USART Debug Unit each Serial Synchronous Controller each Serial Peripheral Interface Multimedia Card Interface
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Memories
Figure 8-1. AT91SAM9261S Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF 0x0000 0000
Internal Memory Mapping
Notes ROM, EBI_NCS0 SRAM depending REMAP
256M Bytes
0x10 0000
Boot Memory
0x1000 0000 Chip Select
0x1FFF FFFF
Reserved 256M Bytes
0x20 0000
Reserved
0x30 0000
0x2000 0000 Chip Select SDRAMC 256M Bytes
SRAM
0x40 0000
Bytes
0x2FFF FFFF
0x3000 0000 Chip Select
0x3FFF FFFF 0x50 0000
256M Bytes User Interface
0x60 0000
Bytes
Bytes
0x4000 0000
Chip Select NANDFlash Chip Select Compact Flash Slot Chip Select Compact Flash Slot Chip Select
256M Bytes
0x70 0000
User Interface
Bytes
0x4FFF FFFF
0x5000 0000
Reserved 256M Bytes
0x0FFF FFFF
0x5FFF FFFF
0x6000 0000
256M Bytes System Controller Mapping
0xFFFF C000
0x6FFF FFFF
0x7000 0000 256M Bytes Peripheral Mapping
0xF000 0000
0x7FFF FFFF
Reserved
0x8000 0000 Chip Select
0x8FFF FFFF
256M Bytes
0xFFFA 0000
Reserved
0xFFFF EA00
SDRAMC TCO, TC1,
Bytes Bytes 0xFFFF EE00 Bytes 0xFFFF F000 Bytes 0xFFFF F200 0xFFFF EC00
Bytes
0x9000 0000
0xFFFA 4000
Bytes
0xFFFA 8000
MATRIX
Bytes
0xFFFA C000
0xFFFB 0000
DBGU
0xFFFF F400
Bytes
USART0
0xFFFB 4000
Bytes Bytes 0xFFFF F600
Bytes
USART1
0xFFFB 8000
PIOA
Bytes
Undefined (Abort)
1,518M Bytes
0xFFFB C000
USART2 SSC0
0xFFFC 0000
Bytes
PIOB
0xFFFF F800 Bytes
bytes
PIOC
0xFFFF FA00 Bytes
bytes
SSC1
0xFFFC 4000
Reserved
Bytes 0xFFFF FC00
SSC2
0xFFFC 8000
Bytes Bytes 0xFFFF FD00
Bytes Bytes Bytes Bytes Bytes Bytes Bytes
SPI0
0xFFFC C000
RSTC
0xFFFF FD10 0xFFFF FD20 0xFFFF FD30
SHDWC GPBR Reserved
SPI1
0xFFFC D000 0xEFFF FFFF
0xF000 0000 Internal Peripherals
0xFFFF FFFF
Reserved 256M Bytes
0xFFFF C000
0xFFFF FD40 0xFFFF FD50 0xFFFF FD60
SYSC
0xFFFF FFFF
Bytes 0xFFFF FFFF
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
first level address decoding performed Matrix, i.e., implementation Advanced High performance (AHB) Master Slave interfaces with additional features. Decoding breaks Gbytes address space into areas Mbytes. areas directed that associates these areas external chip selects NCS0 NCS7. area reserved addressing internal memories, second level decoding provides Mbyte internal memory area. area reserved peripherals provides access Advanced Peripheral (APB). Other areas unused performing access within them provides abort master requesting such access. Matrix manages five Masters five Slaves. Each Master decoder, thus allowing different memory mapping Master. Regarding Master Master (ARM926Instruction Data), three different Slaves assigned memory space decoded address 0x0: internal boot, external boot, after remap. Refer Table details. Table 8-1.
Master Master Master Master Master
List Matrix Masters
ARM926 Instruction ARM926 Data Controller Host
Each Slave arbiter, thus allowing different arbitration Slave. Table 8-2.
Slave Slave Slave Slave Slave
List Matrix Slaves
Internal SRAM Internal Controller Host Port Interfaces External Interface Internal Peripherals
Embedded Memories
Single Cycle Access full speed Fast SRAM Single Cycle Access full speed
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8.1.1
Internal Memory Mapping Table summarizes Internal Memory Mapping each Master, depending Remap status state reset. Internal Memory Mapping
Master ARM926 Instruction REMAP(RCB0) NCS0(1) Int. RAM(2) REMAP (RCB0) Master ARM926 Data REMAP (RCB1) Int. NCS0(1) Int. RAM(2) REMAP (RCB1)
Table 8-3.
Address
0x0000 0000 Notes:
Int.
NCS0 connected 16-bit non-volatile memory. access configuration defined reset state Setup, Pulse, Cycle Mode registers. Other masters (e.g. PDC) cannot access internal SRAM 0x0, only 0x300 000.
8.1.1.1
Internal AT91SAM9261S integrates Kbyte Internal mapped address 0x0040 0000. also accessible address after reset before remap tied high during reset. Host Port AT91SAM9261S integrates Host Port Open Host Controller Interface (OHCI). registers this interface directly accessible mapped like standard internal memory address 0x0050 0000. Controller AT91SAM9261S integrates Controller. interface directly accessible mapped like standard internal memory address 0x0060 0000. Boot Strategies system always boots address 0x0. ensure maximum number possibilities boot, memory layout configured with parameters. REMAP allows user first internal SRAM bank ease development. This done software once system booted each Master Matrix. When REMAP ignored. Refer Matrix Section more details. When REMAP allows user 0x0, convenience, external memory. This done hardware reset.
Note: Memory blocks affected these parameters always seen their specified base addresses. complete memory presented Figure page
8.1.1.2
8.1.1.3
8.1.2
AT91SAM9261S Matrix manages boot memory that depends level reset. internal memory area mapped between address 0x000F FFFF reserved this purpose. detected boot memory embedded ROM. detected boot memory memory connected Chip Select External Interface. 8.1.2.1 Boot Embedded system boots using Boot Program.
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
DataFlash Boot Downloads runs application from DataFlash into internal SRAM Downloaded code size from DataFlash depends embedded SRAM size Automatic detection valid application DataFlash connected NPCS0 NANDFlash Boot Boot Uploader case valid program detected external DataFlash Small monitor functionalities (read/write/run) interface with SAM-BAapplication Automatic detection communication link Serial communication DBGU (XModem protocol) Device Port (CDC Protocol) 8.1.2.2 Boot External Memory Boot slow clock (32,768 Boot with default configuration Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled Chip Select, allows boot 16-bit non-volatile memory. customer-programmed software must perform complete configuration. speed boot sequence when booting (BMS=0), user must take following steps: Program (main oscillator enable bypass mode). Program start PLL. Reprogram setup, cycle, hold, mode timings registers adapt them clock Switch main clock value.
External Memories
external memories accessed through External Interface (Bus Matrix Slave Refer memory Figure page
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System Controller
System Controller manages vital blocks microcontroller: interrupts, clocks, power, time, debug reset. System Peripherals mapped within highest Kbytes address space, between addresses 0xFFFF EA00 0xFFFF FFFF. Each peripheral address space Bytes, representing registers. Figure page shows System Controller block diagram. Figure page shows mapping User Interfaces System Controller peripherals.
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Block Diagram
System Controller Block Diagram
System Controller irq0-irq2 periph_irq[2.21] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK debug idle proc_nreset VDDCORE Powered NRST VDDCORE ice_nreset jtag_nreset periph_nreset proc_nreset backup_nreset rstc_irq SLCK SLCK backup_nreset SLCK rtt_alarm Real-Time Timer rtt_irq rtt_alarm Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC periph_nreset Matrix Debug Unit nirq nfiq
Figure 9-1.
Advanced Interrupt Controller ice_nreset force_ntrst dbgu_irq force_ntrst dbgu_txd pit_irq
ntrst
ARM926EJ-S
proc_nreset debug
wdt_irq
jtag_nreset
Boundary Scan Controller
Reset Controller
UDPCK periph_clk[10] periph_nreset periph_irq[10] usb_suspend Device Port
VDDBU
SHDN WKUP
Shutdown Controller
UHPCK periph_clk[20] Host Port
backup_nreset VDDBU Powered General-purpose Backup Registers
periph_nreset periph_irq[20] LCDCK periph_clk[21] periph_nreset periph_irq[21]
XIN32 XOUT32 XOUT PLLRCA PLLRCB
SLOW CLOCK
SLCK periph_clk[2.21] pck[0-3] MAINCK Power Management Controller UDPCK UHPCK LCDCK pmc_irq idle
MAIN PLLA PLLB periph_nreset usb_suspend periph_nreset periph_clk[2.4] dbgu_rxd
Controller
PLLACK PLLBCK
periph_clk[6.21] periph_nreset Embedded Peripherals
PA0-PA31 PB0-PB31 PC0-PC31
Controllers
periph_irq{2.4] irq0-irq2 dbgu_txd
periph_irq[6.21]
enable
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Reset Controller
Based Power-on-Reset cells Status last reset Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset Controls internal resets NRST output
Shutdown Controller
Shutdown Wake-up logic: Software programmable assertion SHDN Deassertion Programmable WKUP level change alarm
General-purpose Backup Registers
Four 32-bit general-purpose backup registers
Clock Generator
Embeds Low-power 32768 Slow Clock Oscillator Provides permanent Slow Clock system Embeds Main Oscillator Oscillator bypass feature Supports crystals Embeds PLLs Outputs clocks Integrates input divider increase output accuracy minimum input frequency Provides SLCK, MAINCK, PLLACK PLLBCK. Figure 9-2. Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK
PLLRCA
Divider Divider Status Control
PLLA Clock PLLACK PLLB Clock PLLBCK
PLLRCB
Power Management Controller
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AT91SAM9261S Preliminary
Power Management Controller
Power Management Controller provides: Processor Clock Master Clock Clock USBCK (HCK0) Controller Clock LCDCK (HCK1) thirty peripheral clocks four programmable clock outputs: PCK0 PCK3 Figure 9-3. Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,.,/64 Divider /1,/2,/3,/4 Peripherals Clock Controller ON/OFF Peripherals Clock Controller ON/OFF Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,.,/64 pck[0.3] Idle Mode periph_clk[2.21]
HCKx
PLLBCK
Clock Controller ON/OFF Divider /1,/2,/4
usb_suspend UDPCK UHPCK
Periodic Interval Timer
Includes 20-bit Periodic Counter with less than accuracy Includes 12-bit Interval Overlay Counter Real time Linux®/WindowsCE® compliant tick generator
Watchdog Timer
12-bit key-protected only-once programmable counter Windowed, prevents processor dead-lock watchdog access
Real-time Timer
32-bit Free-running backup counter Alarm Register capable generate wake-up system
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9.10
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Thirty-two individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (PIT, RTT, PMC, DBGU, etc.) Source Source control thirty embedded peripheral interrupts external interrupts Programmable edge-triggered level-sensitive internal sources Programmable positive/negative edge-triggered high/low level-sensitive Four External Sources 8-level Priority Controller Drives normal interrupt processor Handles priority interrupt sources Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes Interrupt Service Routine Branch Execution 32-bit Vector Register interrupt source Interrupt Vector Register reads corresponding current Interrupt Vector Protect Mode Easy debugging preventing automatic operations when protect mode enabled Fast Forcing Permits redirecting normal interrupt source Fast Interrupt processor General Interrupt Mask Provides processor synchronization events without triggering interrupt
9.11
Debug Unit
Composed four functions Two-pin UART Debug Communication Channel (DCC) support Chip Registers Access Prevention Two-pin UART Implemented features 100% compatible with standard Atmel USART Independent receiver transmitter with common programmable Baud Rate Generator Even, Odd, Mark Space Parity Generation Parity, Framing Overrun Error Detection Automatic Echo, Local Loopback Remote Loopback Channel Modes Support channels with connection receiver transmitter Debug Communication Channel Support
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Offers visibility COMMRX COMMTX signals from Processor Chip Registers Identification device revision, sizes embedded memories, peripherals Access prevention Enables software prevent system access through Processor's Prevention made asserting NTRST line Processor's
9.12
Chip Identification
Chip 0x019903A0 JTAG 0x05B2503F ARM926 0x0792603F
9.13
Controllers
Three Controllers, each controlling programmable Lines PIOA Lines PIOB Lines PIOC Lines Fully programmable through Set/Clear Registers Multiplexing peripheral functions Line each Line (whether assigned peripheral used general-purpose I/O) Input change interrupt Glitch filter Multi-drive option enables driving open drain Programmable pull each line data status register, supplies visibility level time Synchronous output, provides Clear several lines single write
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Peripherals
10.1 User Interface
User Peripherals mapped upper Mbytes address space between addresses 0xFFFA 0000 0xFFFC FFFF. Each User Peripheral allocated Kbytes address space. complete memory presented Figure page
10.2
Peripheral Identifiers
Table 10-1 defines Peripheral Identifiers AT91SAM9261S. peripheral identifier required control peripheral interrupt with Advanced Interrupt Controller control peripheral clock with Power Management Controller.
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Table 10-1.
Peripheral
Peripheral Identifiers
Peripheral Mnemonic SYSIRQ PIOA PIOB PIOC SPI0 SPI1 SSC0 SSC1 SSC2 LCDC Peripheral Name Advanced Interrupt Controller System Interrupt Parallel Controller Parallel Controller Parallel Controller Reserved USART USART USART Multimedia Card Interface Device Port Two-Wire Interface Serial Peripheral Interface Serial Peripheral Interface Synchronous Serial Controller Synchronous Serial Controller Synchronous Serial Controller Timer/Counter Timer/Counter Timer/Counter Host Port Controller Reserved Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 External Interrupt
Note:
Setting AIC, SYSIRQ, UHP, LCDC IRQ0 IRQ2 bits clock set/clear registers effect.
10.3
Peripheral Multiplexing Lines
AT91SAM9261S features three controllers, PIOA, PIOB PIOC, that multiplex lines peripheral set. Each Controller controls thirty-two lines. Each line assigned peripheral functions, Table 10-2 page Table 10-3 page Table 10-4 page define lines peripherals multiplexed Controllers. columns "Function" "Comments" have been inserted user's comments; they used track pins defined application. Note that some output only peripheral functions might duplicated within tables.
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column "Reset State" indicates whether line resets mode peripheral mode. mentioned, line resets input with pull-up enabled, that device maintained static state soon reset released. result, corresponding line register PIO_PSR (Peripheral Status Register) resets low. signal name mentioned "Reset State" column, line assigned this function corresponding PIO_PSR resets high. This case pins controlling memories, particular address lines, which require driven soon reset released. Note that pull-up resistor also enabled this case. 10.3.1 10.3.1.1 Resource Multiplexing Controller Controller interface with several panels. supports bit-per-pixel without limitation. Interfacing bit-per-pixel TFTs panel prevents using SSC0 chip select line SPI1. bit-per-pixel panels interfaced through peripheral functions, color data output LCDD3 LCDD7, LCDD11 LCDD15 LCDD19 LCDD23. Intensity output LCDD2, LCDD10 LCDD18. Using peripheral does prevent using SSC0 SPI1 lines. 10.3.1.2 required, NWAIT function (external wait request) deactivated software, allowing this used PIO. 10.3.1.3 32-bit Data Using 32-bit Data prevents: using three Timer Counter channels' outputs trigger inputs using SSC2 10.3.1.4 NAND Flash Interface Using NAND Flash interface prevents: using NCS3, NCS6 NCS7 access other parallel devices 10.3.1.5 Compact Flash Interface Using CompactFlash interface prevents: using NCS4 and/or NCS5 access other parallel devices 10.3.1.6 SPI0 MultiMedia Card Interface DataFlash Card compatible with SDCard, useful multiplex MCI. Here, SPI0 signal multiplexed with MCI. USARTs Using USART0 with control signals prevents using some clock outputs interrupt lines. 10.3.1.8 Clock Outputs Using clock outputs multiplexed with prevents using Debug Unit and/or Wire Interface.
10.3.1.7
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Alternatively, using second implementation clock outputs prevents using Controller Interface and/or USART0. 10.3.1.9 Interrupt Lines Using prevents using USART0 control signals. Using IRQ0 prevents using NWAIT signal. Using IRQ1 and/or IRQ2 prevents using SPI1.
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10.3.2
Controller Multiplexing Multiplexing Controller
Controller Application Usage Comments Reset State MCDA1 MCDA2 MCDA3 PCK0 PCK1 PCK2 PCK3 SCK1 RTS1 CTS1 SCK2 RTS2 CTS2 RTS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 Function Comments
Table 10-2.
Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
Peripheral SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 TWCK DRXD DTXD
Peripheral MCDA0 MCCDA MCCK
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AT91SAM9261S Preliminary
10.3.3 Controller Multiplexing Multiplexing Controller
Controller Line PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Peripheral LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 SPI1_NPCS1 SPI1_NPCS0 SPI1_SPCK SPI1_MISO SPI1_MOSI LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 IRQ2 IRQ1 PCK2 PCK0 Peripheral Reset State Application Usage Function Comments
Table 10-3.
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10.3.4
Controller Multiplexing Multiplexing Controller
Controller Application Usage Reset State PCK2 PCK3 SCK0 NCS6 NCS7 SPI1_NPCS2 SPI1_NPCS3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 PCK1 Function Comments
Table 10-4.
Line PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
Peripheral NANDOE NANDWE NWAIT A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 TXD0 RXD0 RTS0 CTS0 TXD1 RXD1 TXD2 RXD2
Peripheral NCS6 NCS7 IRQ0
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AT91SAM9261S Preliminary
10.3.5 System Interrupt System Interrupt Source wired-OR interrupt signals coming from: SDRAM Controller Debug Unit Periodic Interval Timer Real-Time Timer Watchdog Timer Reset Controller Power Management Controller clock these peripherals cannot deactivated Peripheral only used within Advanced Interrupt Controller. 10.3.6 External Interrupts external interrupt signals, i.e., Fast Interrupt signal Interrupt signals IRQ0 IRQ2, dedicated Peripheral However, there clock control associated with these peripheral IDs.
10.4
External Interface
Integrates External Memory Controllers: Static Memory Controller SDRAM Controller Additional logic NAND Flash CompactFlash support NAND Flash support: 8-bit well 16-bit devices supported CompactFlash support: modes (Attribute Memory, Common Memory, I/O, True IDE) supported signals -IOIS16 (I/O True modes) -ATA (True mode) handled. Optimized External 32-bit Data 26-bit Address Bus, Mbytes addressable Eight Chip Selects, each reserved eight Memory Areas Optimized multiplexing reduce latencies External Memories Configurable Chip Select Assignment Managed EBI_CSA Register located MATRIX user interface Static Memory Controller NCS0 SDRAM Controller Static Memory Controller NCS1 Static Memory Controller NCS2 Static Memory Controller NCS3, Optional NAND Flash Support Static Memory Controller NCS4 NCS5, Optional CompactFlash Support Static Memory Controller NCS6 NCS7
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10.5
Static Memory Controller
External memory mapping, Mbyte address space Chip Select Line Eight Chip Select Lines 32-bit Data Multiple Access Modes supported Byte Write Byte Select Lines Asynchronous read Page Mode supported 32-byte page size) Multiple device adaptability Compliant with Module Control signal programmable setup, pulse hold time each Memory Bank Multiple Wait State Management Programmable Wait State Generation External Wait Request Programmable Data Float Time Slow Clock Mode Supported
10.6
SDRAM Controller
Supported Devices Standard Power SDRAM (Mobile SDRAM) Numerous configurations supported Address Memory Parts SDRAM with four Internal Banks SDRAM with 32-bit Data Path Programming Facilities Word, half-word, byte access Automatic page break when Memory Boundary been reached Multibank Ping-pong Access Timing parameters specified software Automatic refresh operation, refresh rate programmable Energy-saving Capabilities Self-refresh, power down deep power down modes supported Error detection Refresh Error Interrupt SDRAM Power-up Initialization software Latency supported Auto Precharge Command used
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
10.7 Serial Peripheral Interface
Supports communication with serial external devices Four chip selects with external decoder support allow communication with fifteen peripherals Serial memories, such DataFlash 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface 16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays between consecutive transfers between clock data chip select Programmable delay between consecutive transfers Selectable mode fault detection Very fast transfers supported Transfers with baud rates chip select line left active speed transfers same device
10.8
Two-wire Interface
Master, Multi-master Slave Modes supported General call supported Slave Mode
10.9
USART
Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection MSB- LSB-first Optional break generation detection By-8 by-16 over-sampling receiver frequency Hardware handshaking RTS-CTS Receiver time-out transmitter timeguard Optional Multi-drop Mode with address generation detection Optional Manchester Encoding RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit IrDA modulation demodulation Communication 115.2 Kbps
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Test Modes Remote Loopback, Local Loopback, Automatic Echo
10.10 Synchronous Serial Controller
Provides serial synchronous communication links used audio telecom applications (with CODECs Master Slave Modes, I2S, Buses, Magnetic Card Reader more). Contains independent receiver transmitter common clock divider. Offers configurable frame sync data length. Receiver transmitter programmed start automatically detection different event frame sync signal. Receiver transmitter include data signal, clock signal frame synchronization signal.
10.11 Timer Counter
Three 16-bit Timer Counter Channels Wide range functions including: Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up/down Capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs multi-purpose input/output signals global registers that three Channels
10.12 Multimedia Card Interface
Compatibility with MultiMedia Card Specification Version Compatibility with Memory Card Specification Version Cards clock rate Master Clock divided Embedded power management slow down clock rate when used Each slots, each supporting slot MultiMedia Card cards) Memory Card Support stream, block multi-block data read write
10.13
Host Port:
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
Compliance with Open specification Compliance with V2.0 Full-speed Low-speed Specification Supports both Low-speed Mbps Full-speed Mbps devices Root integrated with downstream ports embedded transceivers overcurrent detection Supports power management Operates master Matrix Device Port: V2.0 full-speed compliant, Mbits second Embedded V2.0 full-speed transceiver Embedded dual-port endpoints Suspend/Resume logic Ping-pong mode (two memory banks) isochronous bulk endpoints general-purpose endpoints: Endpoint bytes, ping-pong mode Endpoint Endpoint bytes, ping-pong mode Endpoint bytes, ping-pong mode Endpoint Endpoint bytes, ping-pong mode Embedded pull-up configurable USB_PUCR Register located MATRIX user interface
10.14 Controller
Single Dual scan color monochrome passive panels supported Single scan active panels supported. 4-bit single scan, 8-bit single dual scan, 16-bit dual scan interfaces supported 24-bit single scan interfaces supported gray levels mono 4096 colors color displays bits pixel (palletized), bits pixel (non-palletized) mono bits pixel (palletized), bits pixel (non-palletized) color bits pixel (palletized), bits pixel (non-palletized) Single clock domain architecture Resolution supported 2048 2048
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AT91SAM9261S Mechanical Characteristics
11.1 Package Drawings
Figure 11-1. 217-ball LFBGA Package Drawing
Table 11-1.
Ball Land
Soldering Information
0.43 0.05 0.30 0.05
Solder Mask Opening
Table 11-2.
Device 217-ball LFBGA Package Maximum Weight
Table 11-3.
217-ball LFBGA Package Characteristics
Moisture Sensitivity Level
Table 11-4.
Package Reference
MO-205
JEDEC Drawing Reference JESD97 Classification
AT91SAM9261S Preliminary
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AT91SAM9261S Preliminary
11.2 Soldering Profile
Table 11-5 gives recommended soldering profile from J-STD-20. Table 11-5. Soldering Profile
Green Package C/sec. max. sec. max. sec. sec. sec. sec. C/sec. max. min. max.
Profile Feature Average Ramp-up Rate (217°C Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time Peak Temperature Note:
recommended apply soldering temperature higher than 250°C.
maximum three reflow passes allowed component.
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AT91SAM9261S Ordering Information
Table 12-1. AT91SAM9261S Ordering Information
Package BGA217 Package Type Green Temperature Operating Range Industrial -40°C 85°C Ordering Code AT91SAM9261S-CU
AT91SAM9261S Preliminary
6242BS-ATARM-14-Sep-07
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6242BS-ATARM-14-Sep-07

AT91 Thumb-based Microcontrollers AT91SAM9261S Preliminary Summary

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