Product Description AT91SAM7X512 AT91SAM7X256 AT91SAM7X128 Preliminary

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Product Description AT91SAM7X512 AT91SAM7X256 AT91SAM7X128 Preliminary

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High-performance 32-bit RISC Architecture High-density 16-bit Instruction Leader MIPS/Watt EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash Kbytes (AT91SAM7X512) Organized Banks 1024 Pages Bytes (Dual Plane) Kbytes (AT91SAM7X256) Organized 1024 Pages Bytes (Single Plane) Kbytes (AT91SAM7X128) Organized Pages Bytes (Single Plane) Single Cycle Access Worst Case Conditions Prefetch Buffer Optimizing Thumb Instruction Execution Maximum Speed Page Programming Time: Including Page Auto-erase, Full Erase Time: 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Fast Flash Programming Interface High Volume Production Internal High-speed SRAM, Single-cycle Access Maximum Speed Kbytes (AT91SAM7X512) Kbytes (AT91SAM7X256) Kbytes (AT91SAM7X128) Memory Controller (MC) Embedded Flash Controller, Abort Status Misalignment Detection Reset Controller (RSTC) Based Power-on Reset Cells Low-power Factory-calibrated Brownout Detector Provides External Reset Signal Shaping Reset Source Status Clock Generator (CKGR) Low-power Oscillator, On-chip Oscillator Power Management Controller (PMC) Power Optimization Capabilities, Including Slow Clock Mode (Down Idle Mode Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) 2-wire UART Support Debug Communication Channel interrupt, Programmable Access Prevention Periodic Interval Timer (PIT) 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) 12-bit key-protected Programmable Counter Provides Reset Interrupt Signals System Counter Stopped While Processor Debug State Idle Mode
Product Description AT91SAM7X512 AT91SAM7X256 AT91SAM7X128 Preliminary Summary
NOTE: This summary document. complete document available Atmel website www.atmel.com.
6120ES-ATARM-08-Oct-07
Real-time Timer (RTT)
32-bit Free-running Counter with Alarm Runs Internal Oscillator Parallel Input/Output Controllers (PIO) Sixty-two Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up Resistor Synchronous Output Thirteen Peripheral Controller (PDC) Channels Full Speed Mbits second) Device Port On-chip Transceiver, 1352-byte Configurable Integrated FIFOs Ethernet 10/100 base-T Media Independent Interface (MII) Reduced Media Independent Interface (RMII) Integrated 28-byte FIFOs Dedicated Channels Transmit Receive Part 2.0A Part 2.0B Compliant Controller Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Synchronous Serial Controller (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation Support ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Full Modem Line Support USART1 Master/Slave Serial Peripheral Interfaces (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three-channel 16-bit Timer/Counter (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Four-channel 16-bit Power Width Modulation Controller (PWMC) Two-wire Interface (TWI) Master Mode Support Only, Two-wire Atmel EEPROMs Compatible Devices Supported 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os SAM-BABoot Assistance Default Boot program Interface with SAM-BA Graphic User Interface IEEE® 1149.1 JTAG Boundary Scan Digital Pins 5V-tolerant I/Os, Including Four High-current Drive lines, Each Power Supplies Embedded 1.8V Regulator, Drawing Core External Components 3.3V VDDIO Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply 1.8V VDDCORE Core Power Supply with Brownout Detector Fully Static Operation: 1.65V 85°C Worst Case Conditions Available 100-lead LQFP Green 100-ball TFBGA Green Packages
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Description
Atmel's AT91SAM7X512/256/128 member series highly integrated Flash microcontrollers based 32-bit RISC processor. features 512/256/128 Kbyte high-speed Flash 128/64/32 Kbyte SRAM, large peripherals, including 802.3 Ethernet controller. complete system functions minimizes number external components. embedded Flash memory programmed in-system JTAG-ICE interface parallel interface production programmer prior mounting. Built-in lock bits security protect firmware from accidental overwrite preserve confidentiality. AT91SAM7X512/256/128 system controller includes reset controller capable managing power-on sequence microcontroller complete system. Correct device operation monitored built-in brownout detector watchdog running integrated oscillator. combining ARM7TDMI processor with on-chip Flash SRAM, wide range peripheral functions, including USART, SPI, Controller, Ethernet MAC, Timer Counter, Analog-to-Digital Converters monolithic chip, AT91SAM7X512/256/128 powerful device that provides flexible, cost-effective solution many embedded control applications requiring communication over, example, Ethernet, wired Zigbee wireless networks.
Configuration Summary AT91SAM7X512/256/128
AT91SAM7X512, AT91SAM7X256 AT91SAM7X128 differ only memory sizes. Table summarizes configurations three devices. Table 1-1.
Device AT91SAM7X512 AT91SAM7X256 AT91SAM7X128
Configuration Summary
Flash Kbytes Kbytes Kbytes Flash Organization dual plane single plane single plane SRAM Kbytes Kbytes Kbytes
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AT91SAM7X512/256/128 Block Diagram
Figure 2-1.
JTAGSEL
AT91SAM7X512/256/128 Block Diagram
JTAG SCAN
ARM7TDMI Processor
Voltage Regulator
VDDIN VDDOUT VDDCORE
System Controller
IRQ0-IRQ1
Memory Controller
VDDIO
DRXD DTXD
DBGU
Embedded Flash Controllers Abort Status
SRAM
128/64/32 Kbytes
Address Decoder Misalignment Detection
PCK0-PCK3 PLLRC XOUT
VDDFLASH
RCOSC Peripheral Bridge
Flash
512/256/128 Kbytes
ERASE
VDDCORE VDDFLASH VDDCORE NRST
Reset Controller
Peripheral Controller
Channels
Fast Flash Programming Interface
PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1
PIOA
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADTRG ADVREF
SAM-BA
FIFO Ethernet 10/100
PIOB
USART0
FIFO
Transceiver
ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL, ECRSDV ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO EF100 VDDFLASH
USART1
Device
PWMC
SPI0
Timer Counter SPI1
PWM0 PWM1 PWM2 PWM3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWCK CANRX CANTX
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Signal Description
Table 3-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL
Voltage Regulator Power Supply Input Voltage Regulator Output Flash Power Supply Lines Power Supply Core Power Supply Ground
Power Power Power Power Power Power Ground
3.6V 1.85V 3.6V 3.6V 1.65V 1.95V 1.65V 1.95V
Clocks, Oscillators PLLs XOUT PLLRC PCK0 PCK3 Main Oscillator Input Main Oscillator Output Filter Programmable Clock Output Input Output Input Output JTAG JTAGSEL Test Clock Test Data Test Data Test Mode Select JTAG Selection Input Input Output Input Input Flash Memory ERASE Flash Configuration Bits Erase Command Reset/Test NRST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data IRQ0 IRQ1 External Interrupt Inputs Fast Interrupt Input PA30 PB30 Parallel Controller Parallel Controller Pulled-up input reset Pulled-up input reset Input Input Input Output Input High Pull-up resistor, Open Drain Output Pull-down resistor Input High Pull-down resistor pull-up resistor. Pull-down resistor. pull-up resistor pull-up resistor.
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Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Device Port Active Level Comments
Device Port Data Device Port Data USART
Analog Analog
SCK0 SCK1 TXD0 TXD1 RXD0 RXD1 RTS0 RTS1 CTS0 CTS1 DCD1 DTR1 DSR1
Serial Clock Transmit Data Receive Data Request Send Clear Send Data Carrier Detect Data Terminal Ready Data Ready Ring Indicator
Input Output Input Input Output Input Input Synchronous Serial Controller
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input Timer/Counter
TCLK0 TCLK2 TIOA0 TIOA2 TIOB0 TIOB2
External Clock Inputs Line Line
Input Controller
PWM0 PWM3
Channels
Output Serial Peripheral Interface SPIx
SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1-NPCS3
Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select
Output
Two-wire Interface TWCK Two-wire Serial Data Two-wire Serial Clock
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Analog-to-Digital Converter Active Level Comments
AD0-AD3 AD4-AD7 ADTRG ADVREF
Analog Inputs Analog Inputs Trigger Reference
Analog Analog Input Analog Fast Flash Programming Interface
Digital pulled-up inputs reset Analog Inputs
PGMEN0-PGMEN1 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD
Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command
Input Input Output Output Input Input Input Controller High
CANRX CANTX
Input Output
Input Output Ethernet 10/100
EREFCK ETXCK ERXCK ETXEN ETX0 ETX3 ETXER ERXDV ECRSDV ERX0 ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Reference Clock Transmit Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Carrier Sense Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force Mbits/sec.
Input Input Input Output Output Output Input Input Input Input Input Input Output Output High
RMII only only only
ETX0 ETX1 only RMII only only RMII only ERX0 ERX1 only RMII
only only
RMII only
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Package
AT91SAM7X512/256/128 available 100-lead LQFP Green 100-ball TFBGA RoHScompliant packages.
100-lead LQFP Package Outline
Figure shows orientation 100-lead LQFP package. detailed mechanical description given Mechanical Characteristics section. Figure 4-1. 100-lead LQFP Package Outline (Top View)
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
100-lead LQFP Pinout
Pinout 100-lead LQFP Package
PA18/PGMD6 PB14 PB13 VDDIO PB15 PB17 VDDCORE PB12 PB10 PB11 PA19/PGMD7 PA20/PGMD8 VDDIO PA21/PGMD9 PA22/PGMD10 PB16 PA23/PGMD11 PA24/PGMD12 NRST PA25/PGMD13 PA26/PGMD14 VDDIO VDDCORE PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PA27/PGMD15 PA28 PA29 JTAGSEL PA30 PA0/PGMEN0 PA1/PGMEN1 VDDIO VDDCORE PA4/PGMNCMD PA5/PGMRDY PA6/PGMNOE PA7/PGMNVALID ERASE VDDFLASH XIN/PGMCK XOUT PLLRC VDDPLL ADVREF VDDOUT VDDIN PB27/AD0 PB28/AD1 PB29/AD2 PB30/AD3 PA8/PGMM0 PA9/PGMM1 VDDCORE VDDIO PA10/PGMM2 PA11/PGMM3 PA12/PGMD0 PA13/PGMD1 PA14/PGMD2 PA15/PGMD3 PA16/PGMD4 PA17/PGMD5
Table 4-1.
6120ES-ATARM-08-Oct-07
100-ball TFBGA Package Outline
Figure shows orientation 100-ball TFBGA package. detailed mechanical description given Mechanical Characteristics section full datasheet. Figure 4-2. 100-ball TFBGA Package Outline (Top View)
VIEW
BALL
100-ball TFBGA Pinout
Signal Name Signal Name Signal Name Signal Name
Pinout 100-ball TFBGA Package
PA22/PGMD10 PA21/PGMD9 PA20/PGMD8 PA18/PGMD6 VDDIO PA19/PGMD7 PB11 PB12 PB15 PB14 PA14/PGMD2 PA16/PGMD4 PA17/PGMD5 PB16 PB10 PB17 PB13 PA13/PGMD1 PA12/PGMD0 PA15/PGMD3 PA23/PGMD11 PA24/PGMD12 NRST PB19 PA10/PGMM2 VDDIO PB27/AD0 PA11/PGMM3 PA25/PGMD13 PA26/PGMD14 PB18 PB20 VDDIO PB28/AD1 VDDIO PB21 PB23 PB25 PB26 PA6/PGMNOE ERASE VDDCORE VDDIN PB22 PB24 PA27/PGMD15 PA5/PGMRDY VDDCORE PB30/AD3 VDDOUT VDDCORE PA28 JTAGSEL PA4/PGMNCMD PA7/PGMNVALID PA9/PGMM1 PA8/PGMM0 PB29/AD2 PLLRC PA29 PA30 PA0/PGMEN0 PA1/PGMEN1 VDDFLASH XIN/PGMCK XOUT VDDPLL VDDCORE VDDCORE ADVREF
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Power Considerations
Power Supplies
AT91SAM7X512/256/128 types power supply pins integrates voltage regulator, allowing device supplied with only voltage. power supply types are: VDDIN pin. powers voltage regulator ADC; voltage ranges from 3.0V 3.6V, 3.3V nominal. order decrease current consumption, voltage regulator used, VDDIN, ADVREF, AD4, AD5, should connected GND. this case, VDDOUT should left unconnected. VDDOUT pin. output 1.8V voltage regulator. VDDIO pin. powers lines; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDFLASH pin. powers transceivers part Flash required Flash operate correctly; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDCORE pins. They power logic device; voltage ranges from 1.65V 1.95V, 1.8V typical. connected VDDOUT with decoupling capacitor. VDDCORE required device, including embedded Flash, operate correctly. VDDPLL pin. powers oscillator PLL. connected directly VDDOUT pin. separate ground pins provided different power supplies. Only pins provided should connected shortly possible system ground plane.
Power Consumption
AT91SAM7X512/256/128 static current less than VDDCORE 25°C, including oscillator, voltage regulator power-on reset when brownout detector deactivated. Activating brownout detector adds static current. dynamic power consumption VDDCORE less than full speed when running Flash. Under same conditions, power consumption VDDFLASH does exceed
Voltage Regulator
AT91SAM7X512/256/128 embeds voltage regulator that managed System Controller. Normal Mode, voltage regulator consumes less than static current draws output current. voltage regulator also Low-power Mode. this mode, consumes less than static current draws output current. Adequate output supply decoupling mandatory VDDOUT reduce ripple avoid oscillations. best achieve this capacitors parallel: external capacitor should connected between VDDOUT close chip possible. external capacitor should connected between VDDOUT GND.
6120ES-ATARM-08-Oct-07
Adequate input supply decoupling mandatory VDDIN order improve startup stability reduce source voltage drop. input decoupling capacitor should placed close chip. example, capacitors used parallel: X7R.
Typical Powering Schematics
AT91SAM7X512/256/128 supports 3.3V single supply mode. internal regulator input connected 3.3V source output feeds VDDCORE VDDPLL. Figure shows power schematics used bus-powered systems. Figure 5-1. 3.3V System Single Power Supply Schematic
VDDFLASH Power Source ranges from 4.5V (USB)
DC/DC Converter
VDDIO
VDDIN 3.3V VDDOUT Voltage Regulator
VDDCORE
VDDPLL
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Lines Considerations
JTAG Port Pins
TMS, schmitt trigger inputs tolerant. TMS, integrate pull-up resistor. output, driven VDDIO, pull-up resistor. JTAGSEL used select JTAG boundary scan when asserted high level. JTAGSEL integrates permanent pull-down resistor about GND, that left unconnected normal operations.
Test
used manufacturing test fast programming mode AT91SAM7X512/256/128 when asserted high. integrates permanent pull-down resistor about GND, that left unconnected normal operations. enter fast programming mode, pins should tied high tied low. Driving high level while driven leads unpredictable results.
Reset
NRST bidirectional with open drain output buffer. handled on-chip reset controller driven provide reset signal external components asserted externally reset microcontroller. There constraint length reset pulse, reset controller guarantee minimum pulse length. This allows connection simple push-button NRST system user reset, signal NRST reset components system. NRST integrates permanent pull-up resistor VDDIO.
ERASE
ERASE used re-initialize Flash content some bits. integrates permanent pull-down resistor about GND, that left unconnected normal operations. This debounced oscillator improve glitch tolerance. When tied high during less than ERASE taken into account. must tied high during more than perform re-initialization Flash.
Controller Lines
lines, PA30 PB30, 5V-tolerant integrate programmable pull-up resistor. Programming this pull-up resistor performed independently each line through controllers. 5V-tolerant means that lines drive voltage level according VDDIO, driven with voltage 5.5V. However, driving line with voltage over VDDIO while programmable pull-up resistor enabled will create current path through pull-up resistor from line VDDIO. Care should taken, particular reset, lines default input with pull-up resistor enabled reset.
6120ES-ATARM-08-Oct-07
Lines Current Drawing
lines high-drive current capable. Each these lines drive permanently. remaining lines draw only However, total current drawn lines cannot exceed
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Processor Architecture
ARM7TDMI Processor
RISC processor based ARMv4T Neumann architecture Runs MHz, providing MIPS/MHz instruction sets high-performance 32-bit instruction Thumb high code density 16-bit instruction Three-stage pipeline architecture Instruction Fetch Instruction Decode Execute
Debug Test Integrated embedded in-circuit emulator watchpoint units Test access port accessible through JTAG protocol Debug communication channel Debug Unit Two-pin UART Debug communication channel interrupt handling Chip Register IEEE1149.1 JTAG Boundary-scan digital pins
Memory Controller
Programmable Arbiter Handles requests from ARM7TDMI, Ethernet Peripheral Controller Address decoder provides selection signals Three internal Mbyte memory areas Mbyte embedded peripheral area Abort Status Registers Source, Type parameters access leading abort saved Facilitates debug detection pointers Misalignment Detector Alignment checking data accesses Abort generation case misalignment Remap Command Remaps SRAM place embedded non-volatile memory Allows handling dynamic exception vectors
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Embedded Flash Controller Embedded Flash interface, three programmable wait states Prefetch buffer, buffering anticipating 16-bit requests, reducing required wait states Key-protected program, erase lock/unlock sequencer Single command erasing, programming locking operations Interrupt generation case forbidden operation
Peripheral Controller
Handles data transfer between peripherals memories Thirteen channels each USART Debug Unit Serial Synchronous Controller each Serial Peripheral Interface Analog-to-digital Converter arbitration overhead Master Clock cycle needed transfer from memory peripheral Master Clock cycles needed transfer from peripheral memory Next Pointer management reducing interrupt latency requirements Peripheral Controller (PDC) priority follows (from highest priority lowest):
Receive Receive Receive Receive Receive Receive Receive Transmit Transmit Transmit Transmit Transmit Transmit DBGU USART0 USART1 SPI0 SPI1 DBGU USART0 USART SPI0 SPI1
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Memories
AT91SAM7X512
Kbytes dual-plane Flash Memory contiguous banks 1024 pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, protecting sectors pages Protection Mode secure contents Flash Kbytes Fast SRAM Single-cycle access full speed
AT91SAM7X256
Kbytes Flash Memory 1024 pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, each protecting sectors pages Protection Mode secure contents Flash Kbytes Fast SRAM Single-cycle access full speed
AT91SAM7X128
Kbytes Flash Memory pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, each protecting sectors pages Protection Mode secure contents Flash Kbytes Fast SRAM Single-cycle access full speed
6120ES-ATARM-08-Oct-07
Figure 8-1.
AT91SAM7X512/256/128 Memory Mapping
Internal Memory Mapping
0x0000 0000
Note: ROM, Flash SRAM depending GPNVM2 REMAP
Boot Memory Flash before Remap SRAM after Remap
MBytes
0x000F 0x0010 0000
Internal Flash
0x001F 0x0020 0000
MBytes
Internal SRAM
0x002F 0x0030 0000
MBytes
Address Memory Space 0x0000 0000
0x003F 0x0040 0000
Internal
MBytes
Internal Memories
MBytes
Reserved
MBytes
0x0FFF FFFF 0x1000 0000
0x0FFF FFFF System Controller Mapping 0xFFFF F000 0xFFFF F1FF 0xFFFF F200 DBGU 0xFFFF F3FF 0xFFFF F400 PIOA Kbytes 0xFFFF F5FF 0xFFFF F600 PIOB Reserved USART0 USART1 Reserved PWMC EMAC SPI0 SPI1 Reserved 0xFFFF EFFF 0xFFFF F000 0xFFFF FFFF SYSC 0xFFFF FFFF Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 VREG Reserved Bytes/64 registers Bytes/1 register Kbytes Kbytes 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F Kbytes 0xFFFF F7FF 0xFFFF F800 Reserved 0xFFFF FBFF 0xFFFF FC00 Bytes/64 registers Bytes/128 registers Bytes/128 registers Bytes/128 registers Bytes/128 registers
Peripheral Mapping 0xF000 0000 Reserved 0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF 0xFFFA 4000 0xFFFA FFFF 0xFFFB 0000 0xFFFB 3FFF 0xFFFB 4000 Reserved 0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000
0xEFFF FFFF
Undefined (Abort)
MBytes 3,584 MBytes
TC0, TC1, Reserved
Kbytes
0xF000 0000
0xFFFB FFFF 0xFFFC 0000 0xFFFC 3FFF 0xFFFC 4000
Internal Peripherals
MBytes
0xFFFC 7FFF 0xFFFC 8000 0xFFFC BFFF 0xFFFC C000
RSTC Reserved
Bytes/4 registers
0xFFFF FFFF
0xFFFC FFFF 0xFFFD 0000 0xFFFD 3FFF 0xFFFD 4000 0xFFFD 7FFF 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 0xFFFD FFFF 0xFFFE 0000 0xFFFE 3FFF 0xFFFE 4000 0xFFFE 7FFF 0xFFFE 8000
0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F
Reserved
Bytes/4 registers Bytes/4 registers Bytes/4 registers
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
8.4.1
Memory Mapping
Internal SRAM AT91SAM7X512 embeds high-speed Kbyte SRAM bank. AT91SAM7X256 embeds high-speed Kbyte SRAM bank. AT91SAM7X128 embeds high-speed Kbyte SRAM bank. After reset until Remap Command performed, SRAM only accessible address 0x0020 0000. After Remap, SRAM also becomes available address 0x0.
8.4.2
Internal AT91SAM7X512/256/128 embeds Internal ROM. time, mapped address 0x30 0000. contains FFPI SAM-BA program.
8.4.3
Internal Flash AT91SAM7X512 features banks (dual plane) Kbytes Flash. AT91SAM7X256 features bank (single plane) Kbytes Flash. AT91SAM7X128 features bank (single plane) Kbytes Flash. time, Flash mapped address 0x0010 0000. also accessible address after reset, GPNVM cleared before Remap Command. general purpose (GPNVM) used boot either (default) from Flash. This GPNVM cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface. Setting GPNVM selects boot from Flash. Asserting ERASE clears GPNVM thus selects boot from default. Figure 8-2. Internal Memory Mapping with GPNVM (default)
0x0000 0000
0x000F FFFF
Before Remap SRAM After Remap Internal FLASH
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes Bytes Bytes
Internal
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
6120ES-ATARM-08-Oct-07
Figure 8-3.
Internal Memory Mapping with GPNVM
0x0000 0000
0x000F FFFF
Flash Before Remap SRAM After Remap Internal FLASH
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes Bytes Bytes
Internal
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
8.5.1
Embedded Flash
Flash Overview Flash AT91SAM7X512 organized banks (dual plane) 1024 pages bytes. 524,288 bytes organized 32-bit words. Flash AT91SAM7X256 organized 1024 pages bytes (single plane). reads 65,536 32-bit words. Flash AT91SAM7X128 organized pages bytes (single plane). reads 32,768 32-bit words. Flash contains 256-byte write buffer, accessible through 32-bit interface. Flash benefits from integration power reset cell from brownout detector. This prevents code corruption during power supply changes, even worst conditions. When Flash used (read write access), automatically placed into standby mode.
8.5.2
Embedded Flash Controller Embedded Flash Controller (EFC) manages accesses performed masters system. enables reading Flash writing write buffer. also contains User Interface, mapped within Memory Controller APB. User Interface allows: programming access parameters Flash (number wait states, timings, etc.) starting commands such full erase, page erase, page program, set, clear, etc. getting status last command getting error status programming interrupts last commands errors Embedded Flash Controller also provides dual 32-bit Prefetch Buffer that optimizes 16-bit access Flash. This particularly efficient when processor running Thumb mode. EFCs embedded AT91SAM7X512 control each bank KBytes. Dualplane organization allows concurrent read program functionality. Read from memory
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
plane performed even while program erase functions being executed other memory plane. embedded AT91SAM7X256/128 control single plane 256/128 KBytes. 8.5.3 8.5.3.1 Lock Regions AT91SAM7X512 Embedded Flash Controllers each manage lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7X512 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. locked-region's erase program command occurs, command aborted trigs interrupt. bits software programmable through both User Interfaces. command "Set Lock Bit" enables protection. command "Clear Lock Bit" unlocks lock region. Asserting ERASE clears lock bits, thus unlocking entire Flash. 8.5.3.2 AT91SAM7X256 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7X256 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. locked-region's erase program command occurs, command aborted trigs interrupt. bits software programmable through User Interface. command "Set Lock Bit" enables protection. command "Clear Lock Bit" unlocks lock region. Asserting ERASE clears lock bits, thus unlocking entire Flash. 8.5.3.3 AT91SAM7X128 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7X128 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. locked-region's erase program command occurs, command aborted trigs interrupt. bits software programmable through User Interface. command "Set Lock Bit" enables protection. command "Clear Lock Bit" unlocks lock region. Asserting ERASE clears lock bits, thus unlocking entire Flash. 8.5.4 Security Feature AT91SAM7X512/256/128 features security bit, based specific NVM-Bit. When security enabled, access Flash, either through interface through Fast
6120ES-ATARM-08-Oct-07
Flash Programming Interface, forbidden. This ensures confidentiality code programmed Flash. This security only enabled, through Command "Set Security Bit" User Interface. Disabling security only achieved asserting ERASE after full flash erase performed. When security deactivated, accesses flash permitted. important note that assertion ERASE should always longer than ERASE integrates permanent pull-down, left unconnected during normal operation. However, safer connect directly final application. 8.5.5 Non-volatile Brownout Detector Control general purpose (GPNVM) bits used controlling brownout detector (BOD), that even after power loss, brownout detector operations remain their state. These GPNVM bits cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface. GPNVM used brownout detector enable bit. Setting GPNVM enables BOD, clearing disables BOD. Asserting ERASE clears GPNVM thus disables brownout detector default. GPNVM used brownout reset enable signal reset controller. Setting GPNVM enables brownout reset when brownout detected, Clearing GPNVM disables brownout reset. Asserting ERASE disables brownout reset default. 8.5.6 Calibration Bits Eight bits used calibrate brownout detector voltage regulator. These bits factory configured cannot changed user. ERASE effect calibration bits.
Fast Flash Programming Interface
Fast Flash Programming Interface allows programming device through either serial JTAG interface through multiplexed fully-handshaked parallel port. allows gang-programming with market-standard industrial programmers. FFPI supports read, page program, page erase, full erase, lock, unlock protect commands. Fast Flash Programming Interface enabled Fast Programming Mode entered when pins tied high.
SAM-BA Boot Assistant
SAM-BA Boot Assistant default Boot Program that provides easy program insitu on-chip Flash memory. SAM-BA Boot Assistant supports serial communication DBGU Device Port. Communication DBGU supports wide range crystals from software auto-detection.
AT91SAM7X512/256/128 Preliminary
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AT91SAM7X512/256/128 Preliminary Summary
Communication Device Port limited 18.432 crystal. SAM-BA Boot provides interface with SAM-BA Graphic User Interface (GUI). SAM-BA Boot mapped address when GPNVM When GPNVM device boots from Flash. When GPNVM device boots from (SAM-BA).
6120ES-ATARM-08-Oct-07
System Controller
System Controller manages vital blocks microcontroller: interrupts, clocks, power, time, debug reset. System Controller peripherals mapped highest Kbytes address space, between addresses 0xFFFF F000 0xFFFF FFFF. Figure page shows System Controller Block Diagram. Figure page shows mapping User Interface System Controller peripherals. Note that Memory Controller configuration user interface also mapped within this address space.
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Figure 9-1. System Controller Block Diagram
System Controller
jtag_nreset
Boundary Scan Controller
irq0-irq1 periph_irq[2.19]
nirq
Advanced Interrupt Controller
nfiq proc_nreset debug
ARM7TDMI
pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset gpnvm[0] gpnvm[1] flash_wrdis power_on_reset jtag_nreset bod_rst_en dbgu_irq force_ntrst dbgu_txd
power_on_reset force_ntrst
Debug Unit
security_bit
Periodic Interval Timer Real-Time Timer Watchdog Timer
wdt_fault WDRPROC
pit_irq
flash_poe rtt_irq flash_wrdis wdt_irq gpnvm[0.2]
Embedded Flash
efc_irq proc_nreset
Memory Controller
flash_poe
Reset Controller
periph_nreset proc_nreset
NRST SLCK
rstc_irq
Voltage Regulator Mode Controller
standby
Voltage Regulator
RCOSC
SLCK
periph_clk[2.18] pck[0-3]
UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend
XOUT
MAINCK
Power Management Controller
UDPCK
Device Port
PLLRC
PLLCK pmc_irq idle periph_clk[4.19] periph_nreset
periph_nreset usb_suspend
periph_nreset periph_clk[2-3] dbgu_rxd
periph_irq{2-3] irq0-irq1
Embedded Peripherals
periph_irq[4.19]
Controller
dbgu_txd
PA0-PA30 PB0-PB30 enable
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Reset Controller
Based power-on reset cell brownout detector Status last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset Controls internal resets NRST output Allows shape signal NRST line, guaranteeing that length pulse meets requirement.
9.1.1
Brownout Detector Power-on Reset AT91SAM7X512/256/128 embeds brownout detection circuit power-on reset cell. power-on reset supplied with monitors VDDCORE. Both signals provided Flash prevent code corruption during power-up powerdown sequences brownouts occur power supplies. power-on reset cell limited-accuracy threshold around 1.5V. output remains during power-up until VDDCORE goes over this voltage level. This signal goes reset controller allows full re-initialization device. brownout detector monitors VDDCORE VDDFLASH levels during operation comparing them fixed trigger level. secures system operations most difficult environments prevents code corruption case brownout VDDCORE VDDFLASH. When brownout detector enabled VDDCORE decreases value below trigger level (Vbot18-, defined Vbot18 hyst/2), brownout output immediately activated. When VDDCORE increases above trigger level (Vbot18+, defined Vbot18 hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. VDDCORE threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 1.68V with accuracy factory calibrated. When brownout detector enabled VDDFLASH decreases value below trigger level (Vbot33-, defined Vbot33 hyst/2), brownout output immediately activated. When VDDFLASH increases above trigger level (Vbot33+, defined Vbot33 hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. VDDFLASH threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 2.80V with accuracy 3.5% factory calibrated. brownout detector low-power, consumes less than static current. However, deactivated save static current. this case, consumes less than 1µA. deactivation configured through GPNVM Flash.
AT91SAM7X512/256/128 Preliminary
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AT91SAM7X512/256/128 Preliminary Summary
Clock Generator
Clock Generator embeds low-power Oscillator, Main Oscillator with following characteristics: Oscillator ranges between Main Oscillator frequency ranges between Main Oscillator bypassed output ranges between provides SLCK, MAINCK PLLCK. Figure 9-2. Clock Generator Block Diagram
Clock Generator
Embedded Oscillator
Slow Clock SLCK
XOUT
Main Oscillator
Main Clock MAINCK
PLLRC
Divider
Clock PLLCK
Status
Control
Power Management Controller
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Power Management Controller
Power Management Controller uses Clock Generator outputs provide: Processor Clock Master Clock Clock UDPCK peripheral clocks, independently controllable four programmable clock outputs Master Clock (MCK) programmable from hundred maximum operating frequency device. Processor Clock (PCK) switches when entering processor idle mode, thus allowing reduced power consumption while waiting interrupt. Figure 9-3. Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64 Peripherals Clock Controller ON/OFF Idle Mode
periph_clk[2.18]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64
pck[0.3]
Clock Controller ON/OFF PLLCK Divider /1,/2,/4
UDPCK
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) Other sources control peripheral interrupts external interrupts Programmable edge-triggered level-sensitive internal sources Programmable positive/negative edge-triggered high/low level-sensitive external sources 8-level Priority Controller Drives normal interrupt nIRQ processor Handles priority interrupt sources
AT91SAM7X512/256/128 Preliminary
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AT91SAM7X512/256/128 Preliminary Summary
Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes interrupt service routine branch execution 32-bit vector register interrupt source Interrupt vector register reads corresponding current interrupt vector Protect Mode Easy debugging preventing automatic operations Fast Forcing Permits redirecting interrupt source fast interrupt General Interrupt Mask Provides processor synchronization events without triggering interrupt
Debug Unit
Comprises: two-pin UART Interface Debug Communication Channel (DCC) support Chip Registers Interface providing Access Prevention Two-pin UART USART-compatible User Interface Programmable Baud Rate Generator Parity, Framing Overrun Error Automatic Echo, Local Loopback Remote Loopback Channel Modes Debug Communication Channel Support Offers visibility COMMRX COMMTX signals from Processor Chip Registers Identification device revision, sizes embedded memories, peripherals Chip 0x275C 0A40 (VERSION AT91SAM7X512 Chip 0x275B 0940 (VERSION AT91SAM7X256 Chip 0x275A 0740 (VERSION AT91SAM7X128
Periodic Interval Timer
20-bit programmable counter plus 12-bit interval counter
Watchdog Timer
12-bit key-protected Programmable Counter running prescaled SLCK Provides reset interrupt signals system Counter stopped while processor debug state idle mode
6120ES-ATARM-08-Oct-07
Real-time Timer
32-bit free-running counter with alarm running prescaled SLCK Programmable 16-bit prescaler SLCK accuracy compensation
Controllers
Controllers, each controlling lines Fully programmable through set/clear registers Multiplexing peripheral functions line each line (whether assigned peripheral used general-purpose I/O) Input change interrupt Half clock period glitch filter Multi-drive option enables driving open drain Programmable pull-up each line data status register, supplies visibility level time Synchronous output, provides Clear several lines single write
9.10
Voltage Regulator Controller
purpose this controller select Power Mode Voltage Regulator between Normal Mode (bit cleared) Standby Mode (bit set).
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Peripherals
10.1 User Interface
User Peripherals mapped Mbytes address space between 0xF000 0000 0xFFFF EFFF. Each peripheral allocated Kbytes address space. complete memory provided Figure page
10.2
Peripheral Identifiers
AT91SAM7X512/256/128 embeds wide range peripherals. Table 10-1 defines Peripheral Identifiers AT91SAM7X512/256/128. Unique peripheral identifiers defined both Advanced Interrupt Controller Power Management Controller.
Table 10-1.
Peripheral
Peripheral Identifiers
Peripheral Mnemonic SYSC PIOA PIOB SPI0 SPI1 PWMC EMAC
Peripheral Name Advanced Interrupt Controller System Controller Parallel Controller Parallel Controller Serial Peripheral Interface Serial Peripheral Interface USART USART Synchronous Serial Controller Two-wire Interface Pulse Width Modulation Controller Device Port Timer/Counter Timer/Counter Timer/Counter Controller Ethernet Analog-to Digital Converter
External Interrupt
Reserved Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1
Note:
Setting SYSC bits clock set/clear registers effect. System Controller continuously clocked.
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10.3
Peripheral Multiplexing Lines
AT91SAM7X512/256/128 features controllers, PIOA PIOB, that multiplex lines peripheral set. Each Controller controls lines. Each line assigned peripheral functions, Some them also multiplexed with analog inputs Controller. Table 10-2 page Table 10-3 page defines lines peripherals analog inputs multiplexed Controller Controller columns "Function" "Comments" have been inserted user's comments; they used track pins defined application. Note that some peripheral functions that output only, duplicated table. reset, lines automatically configured input with programmable pull-up enabled, that device maintained static state soon reset detected.
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
10.4 Controller Multiplexing
Multiplexing Controller
Controller Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 Peripheral RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 TWCK SPI_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK CANRX CANTX DRXD DTXD IRQ0 SPI1_NPCS3 PCK2 SPI1_NPCS0 SPI1_SPCK SPI1_MOSI SPI1_MISO SPI1_NPCS1 SPI1_NPCS2 PCK3 PCK1 IRQ1 TCLK2 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 Peripheral Comments High-Drive High-Drive High-Drive High-Drive Application Usage Function Comments
Table 10-2.
6120ES-ATARM-08-Oct-07
10.5
Controller Multiplexing
Multiplexing Controller
Controller Application Usage Comments Function Comments
Table 10-3.
Line PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30
Peripheral ETXCK/EREFCK ETXEN ETX0 ETX1 ECRS ERX0 ERX1 ERXER EMDC EMDIO ETX2 ETX3 ETXER ERX2 ERX3 ERXDV/ECRSDV ECOL ERXCK EF100 PWM0 PWM1 PWM2 PWM3 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 PCK1 PCK2
Peripheral PCK0
SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2
SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 PWM0 PWM1 PWM2 PWM3
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
10.6 Ethernet
Master Receive Transmit Channels Compatible with IEEE Standard 802.3 Mbit/s operation Full- half-duplex operation Statistics Counter Registers MII/RMII interface physical layer Interrupt generation signal receive transmit completion 28-byte transmit FIFO 28-byte receive FIFO Automatic generation transmitted frames Automatic discard frames received with errors Address checking logic supports four specific 48-bit addresses Support Promiscuous Mode where valid received frames copied memory Hash matching unicast multicast destination addresses Physical layer management through MDIO interface Half-duplex flow control forcing collisions incoming frames Full-duplex flow control with recognition incoming pause frames Support 802.1Q VLAN tagging with recognition incoming VLAN priority tagged frames Multiple buffers receive transmit frame Jumbo frames 10240 bytes supported
10.7
Serial Peripheral Interface
Supports communication with external serial devices Four chip selects with external decoder allow communication with peripherals Serial memories, such DataFlash® 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface 16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays chip select, between consecutive transfers between clock data Programmable delay between consecutive transfers Selectable mode fault detection Maximum frequency Master Clock
10.8
Two-wire Interface
Master Mode only Compatibility with compatible devices (refer section datasheet)
6120ES-ATARM-08-Oct-07
One, three bytes internal address registers easy Serial Memory access 7-bit 10-bit slave addressing Sequential read/write operations
10.9
USART
Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection first Optional break generation detection over-sampling receiver frequency Hardware handshaking Modem Signals Management DTR-DSR-DCD-RI USART1 Receiver time-out transmitter timeguard Multi-drop Mode with address generation detection RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit IrDA modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo
10.10 Serial Synchronous Controller
Provides serial synchronous communication links used audio telecom applications Contains independent receiver transmitter common clock divider Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal
10.11 Timer Counter
Three 16-bit Timer Counter Channels output compare input capture channel Wide range functions including: Frequency measurement Event counting Interval measurement
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Pulse generation Delay timing Pulse Width Modulation Up/down capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs, defined Table 10-4 Table 10-4. Timer Counter Clocks Assignment
Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5
multi-purpose input/output signals global registers that three channels
10.12 Pulse Width Modulation Controller
Four channels, 16-bit counter channel Common clock generator, providing thirteen different clocks Modulo counter providing eleven clocks independent linear dividers working modulo counter outputs Independent channel programming Independent enable/disable commands Independent clock selection Independent period duty cycle, with double buffering Programmable selection output waveform polarity Programmable center left aligned output waveform
10.13 Device Port
V2.0 full-speed compliant,12 Mbits second Embedded V2.0 full-speed transceiver Embedded 1352-byte dual-port endpoints endpoints Endpoint bytes Endpoint bytes ping-pong Endpoint bytes Endpoint bytes ping-pong Ping-pong Mode (two memory banks) bulk endpoints
6120ES-ATARM-08-Oct-07
Suspend/resume logic
10.14 Controller
Fully compliant with 2.0A 2.0B rates 1Mbit/s Eight object oriented mailboxes each with following properties: Specification Part Part Programmable each Message Object configurable receive (with overwrite not) transmit Local mask filters 29-bit identifier/channel 32-bit access data registers each mailbox data object Uses 16-bit time stamp receive transmit message Hardware concatenation unmasked bitfields speedup family processing 16-bit internal timer time stamping network synchronization Programmable reception buffer length mailbox objects Priority management between transmission mailboxes Autobaud listening mode power mode programmable wake-up activity application Data, remote, error overload frame handling
10.15 Analog-to-Digital Converter
8-channel 10-bit samples/sec. Successive Approximation Register Integral Linearity, Differential Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs External voltage reference better accuracy voltage inputs Individual enable disable each channel Multiple trigger sources Hardware software trigger External trigger Timer Counter outputs TIOA0 TIOA2 trigger Sleep Mode conversion sequencer Automatic wakeup trigger back sleep mode after conversions enabled channels Four eight analog inputs shared with digital signals
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Package Drawings
Figure 11-1. LQFP Package Drawing
6120ES-ATARM-08-Oct-07
Table 11-1.
Symbol
100-lead LQFP Package Dimensions
Millimeter 0.05 1.35 1.40 16.00 14.00 16.00 14.00 0.08 0.08 0.09 0.45 0.20 0.17 0.20 0.50 12.00 12.00 Tolerances Form Position 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.27 0.60 1.00 0.008 0.007 0.008 0.020 0.472 0.472 0.011 0.20 0.75 3.5° 0.20 0.003 0.003 0.004 0.018 0.024 0.039 0.008 0.030 3.5° 1.60 0.15 1.45 0.002 0.053 0.055 0.630 0.551 0.630 0.551 0.008 Inch 0.63 0.006 0.057
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Figure 11-2. TFBGA Package Drawing
dimensions
6120ES-ATARM-08-Oct-07
Ordering Information
Table 12-1. Ordering Information
Package LQFP TFBGA LQFP TFBGA LQFP TFBGA Package Type Green Green Green Temperature Operating Range Industrial (-40°C 85°C) Industrial (-40°C 85°C) Industrial (-40°C 85°C)
Ordering Code AT91SAM7X512-AU AT91SAM7X512-CU AT91SAM7X256-AU AT91SAM7X256-CU AT91SAM7X128-AU AT91SAM7X128-CU
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
AT91SAM7X512/256/128 Preliminary Summary
Revision History
Table 12-2. Revision History
Change Request Ref.
Doc. 6120AS
Comments First issue Unqualified Intranet Legal page updated.Qualified Intranet
6120BS
Corrections maintain consistency with full datasheet: "Features" page corrected Page Programming Time Full Erase Time; corrected number channels, removed Wake-on-LAN support. Figure page corrected number channels. Figure page Table page Table 10-2 page Table 10-3 page changed names. Section "Power Consumption" page changed value static current level value dynamic power consumption level VDDCORE Section "Test Pin" page removed reference SAM-BA boot recovery. Section "I/O Lines Current Drawing" page changed value total current level. Section "Peripheral Controller" page corrected number channels. Section "Memories" page corrected Page Programming Time Full Erase Time. Section "SAM-BA Boot Assistant" page updated section. Figure page changed range periph_irq periph_clk Embedded Peripherals block. Section 10.6 "Ethernet MAC" page updated features.
05-388
Update product functionalities including changes "Features" page Figure page Section "Debug Unit" page Peripheral mapping. 6120CS Updated output range value Section "Clock Generator" page Updated information Section "Power Supplies" page Updated ordering information "Ordering Information" page Added AT91SAM7X512 product family."Features" page global Reformatted Memories Section "Memories" page Reordered sections Peripherals Section "Peripherals" page Consolidated Memory Mapping Figure page Added TFBGA information Section "100-ball TFBGA Package Outline" page added LQFP TFBGA package drawings Section page System Controller block diagram Figure page "ice_nreset" signals changed "power_on_reset". Section 10.1 "User Interface" User Peripherals mapped between 0xF000 0000 0XFFFF EFFF. Table 10-1 page SYSIRQ changed SYSC "Peripheral Identifiers"
05-457 05-462 05-491
05-471 2723 2728
6120DS
review
6120ES-ATARM-08-Oct-07
Table 12-2.
Revision History
Change Request Ref. 4247 4774 4210 4007
Doc.
Comments "Features" ,TWI updated include Atmel compatibility with Standard. Section 10.8 "Two-wire Interface", updated. Section "Peripheral Controller", added priority list. Section 10.11 "Timer Counter", output compare input capture channel. Section 10.15 "Analog-to-Digital Converter", updated.
6120ES
AT91SAM7X512/256/128 Preliminary
6120ES-ATARM-08-Oct-07
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6120ES-ATARM-08-Oct-07

Product Description AT91SAM7X512 AT91SAM7X256 AT91SAM7X128 Preliminary

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