NPe405H PowerNP NPe405H Embedded Processor PowerNPtechnology
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Part Number NPe405H Revision 1.02 November 2007
NPe405H
PowerNP NPe405H Embedded Processor
PowerNPtechnology using AMCC PowerPC® 32-bit RISC processor core operating PC-133 synchronous DRAM (SDRAM) interface 32-bit interface non-ECC applications 40-bit interface serves bits data plus check bits applications External peripheral devices Flash interface Direct support 16-, 32-bit SRAM external peripherals devices External mastering supported support external peripherals, internal UARTs memory Scatter-gather chaining supported Four channels Revision compliant interface (32-bit, 66MHz) Asynchronous interface Internal arbiter which disabled with external arbiter Four 10/100 Ethernet MACs supporting four external PHYs MII, RMII, SMII interfaces HDLC interface with channels through ports 4.096 Mbps each 8.192 Mbps single port HDLC interface with channels through ports 2.048 Mbps maximum Programmable interrupt controller Seven external internal Edge triggered level-sensitive Positive negative active Non-critical critical interrupt processor core
Data Sheet
Programmable critical interrupt priority ordering Programmable critical interrupt vector Programmable timers serial ports (16550 compatible UART) interface General Purpose (GPIO) available Supports JTAG board level testing Internal processor local (PLB) runs SDRAM interface frequency Supports PowerPC processor boot from memory User accessible performance counters
DESCRIPTION
Designed specifically address embedded applications, NPe405H provides high-performance, lowpower solution that interfaces wide range peripherals incorporating on-chip power management features lower power dissipation requirements. This chip contains high-performance RISC processor core, SDRAM controller, bridge, Ethernet EMACs, HDLC controllers, external controller ROM, Flash, peripherals, with scatter-gather support, serial ports, interface, general purpose I/O. Technology: CMOS SA-12E 0.25 (0.18 Leff) Package: 35mm, 580-ball enhanced plastic ball grid array (E-PBGA) Power (typical): MHz, 2.9W 200MHz, 3.4W 266MHz
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
TABLE CONTENTS
FEATURES DESCRIPTION ORDERING, PVR, JTAG INFORMATION AMCC Part Number NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM ADDRESS SUPPORT SYSTEM ADDRESS ADDRESS BRIDGE SDRAM MEMORY CONTROLLER EXTERNAL CONTROLLER (EBC) CONTROLLER SERIAL INTERFACE INTERFACE EEPROM CONTROLLER HDLCEX INTERFACE HDLCMP INTERFACE GENERAL PURPOSE (GPIO) CONTROLLER UNIVERSAL INTERRUPT CONTROLLER (UIC) 10/100 MBPS ETHERNET JTAG PERFORMANCE COUNTERS 580-BALL E-PBGA PACKAGE SIGNAL LISTS SIGNALS LISTED ALPHABETICALLY SIGNALS LISTED BALL ASSIGNMENT SIGNAL DESCRIPTION SUMMARY Multiplexed Pins Multipurpose Pins Initialization Strapping Pull-up Pull-down Resistors Unused I/Os External Peripheral Control Signals SIGNAL FUNCTIONAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS V-TOLERANT INPUT CURRENT INPUT CAPACITANCE ELECTRICAL CHARACTERISTICS
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
TEST CONDITIONS CLOCKING SPECIFICATIONS CLOCKING WAVEFORM SPREAD SPECTRUM CLOCKING PERIPHERAL INTERFACE CLOCK TIMINGS INPUT SETUP HOLD WAVEFORM OUTPUT DELAY FLOAT TIMING WAVEFORM SPECIFICATIONS-ALL SPECIFICATIONS(A)-133 SPECIFICATIONS(A)-266 INITIALIZATION Strapping STRAPPING ASSIGNMENTS EEPROM DOCUMENT REVISION HISTORY
AMCC Proprietary
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NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
LIST FIGURES
Figure NPe405H Embedded Controller Functional Block Diagram Figure 35mm, 580-Ball E-PBGA Package Figure 5V-Tolerant Input Current Figure Clocking Waveform Figure Input Setup Hold Waveform Figure Output Delay Float Timing Waveform
LIST TABLES
Table System Address Total System Memory Table Address Device Configuration Register Table Signals Listed Alphabetically Table Signals Listed Ball Assignment Table Summary Table Signal Functional Description Table Absolute Maximum Ratings Table Package Thermal Specifications Table Recommended Operating Conditions Table Input Capacitance Table Electrical Characteristics Table Clocking Specifications Table Peripheral Interface Clock Timings Table Specifications-All Table Specifications-133 200MHz Table Specifications-266MHz Table Strapping Assignments
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
ORDERING, PVR, JTAG INFORMATION
Product Name NPe405H NPe405H NPe405H NPe405H NPe405H NPe405H NPe405H NPe405H Order Part Number1 NPe405H-3JA200C NPe405H-3JA200CZ NPe405H-3JA266C NPe405H-3JA266CZ NPe405H-3BA200C NPe405H-3BA200CZ NPe405H-3BA266C NPe405H-3BA266CZ Processor Frequency 200MHz 200MHz 266MHz 266MHz 200MHz 200MHz 266MHz 266MHz Package 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA Level Value 0x41410140 0x41410140 0x41410140 0x41410140 0x41410140 0x41410140 0x41410140 0x41410140 JTAG 0x04267049 0x04267049 0x04267049 0x04267049 0x04267049 0x04267049 0x04267049 0x04267049
Order Part Number indicates tape reel shipping package. Otherwise, chips shipped tray. Package type contains lead; package type lead-free.
This section provides part numbering nomenclature NPe405H. availability, contact your local AMCC sales office. part number contains part modifier. This modifier provides identification future enhancements (for example, higher performance). Each part number also contains revision code. This refers mask revision number specified part numbering scheme identification purposes only. (Processor Version Register) software accessible contains additional information about revision level part. Refer NPe405H User's Manual details register content. AMCC Part Number
NPe405H-3xA200Cx
AMCC Part Number Grade Reliability Package (E-PBGA) Leaded Lead Free
Shipping Package Blank Tray Tape reel Operational Case Temperature Range (-40°C +85°C) Processor Speed Revision Level
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM
Figure NPe405H Embedded Controller Functional Block Diagram
Universal Interrupt Controller
Clock Control Reset Timers PPC405 Processor Core JTAG
Power Mgmt DCRs
Peripheral Interface
GPIO
UART
Trace 16KB I-Cache On-chip Peripheral (OPB)
D-Cache
Controller (4-Channel)
Bridge
Processor Local (PLB) Ethernet
MAL0
MAL1 SDRAM Controller 13-bit addr 32-bit data External Controller External Master Controller Bridge
HDLCEX
MAL2
HDLCMP
ZMII
32-bit addr 32-bit data
(async) 32-channel ports MII, RMII, single-channel ports SMII
NPe405H designed using Microelectronics Blue Logicmethodology which major functional blocks integrated create application-specific ASIC product. This approach provides consistent generate complex ASICs using CoreConnectBus Architecture.
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
ADDRESS SUPPORT
NPe405H incorporates separate address maps. first fixed processor address that serves PowerPC family processors. This address defines possible contents various address regions which processor access. second address Device Configuration Registers (DCRs). DCRs accessed software running NPe405H processor through mtdcr mfdcr commands.
SYSTEM ADDRESS
Table System Address Total System Memory
Function Subfunction SDRAM, External peripherals, memory Note: address ranges listed right above functions. Start Address 0x00000000 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xEF900000 Boot-up External peripheral boot boot Configuration registers Interrupt Acknowledge special cycle Local configuration registers UART0 UART1 IIC0 arbiter GPIO0 controller registers GPIO1 controller registers Internal peripherals Ethernet registers Ethernet registers Ethernet registers Ethernet registers ZMII control registers HDLCEX HDLCMP 0xFFE00000 0xFFFE0000 0xE8000000 0xE8800000 0xEEC00000 0xEED00000 0xEF400000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600780 0xEF600800 0xEF600900 0xEF600A00 0xEF600B00 0xEF600C10 0xEF610000 0xEF620000 Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xE800FFFF 0xEBFFFFFF 0xEEC00007 0xEED00003 0xEF40003F 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6007FF 0xEF6008FF 0xEF6009FF 0xEF600AFF 0xEF600BFF 0xEF600C1F 0xEF61FFFF 0xEF62FFFF Size 3712MB 44MB 263MB 128KB 64KB 56MB 128B 128B 256B 256B 256B 256B 64KB 64KB
General
Notes: When external peripheral boot selected, peripheral bank automatically configured reset address range listed above. boot selected, PLB-to-PCI mapping automatically configured reset address range listed above. After boot process, software reassign boot memory regions other uses. address ranges listed above reserved.
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
ADDRESS
Table Address Device Configuration Register
Function address space1 Reserved Memory controller registers External controller registers Reserved registers Performance counters Reserved bridge-out registers Reserved Clock, control reset Power management Interrupt controller Interrupt controller Reserved Miscellaneous controller registers Reserved MAL0 registers (Ethernet) MAL1 registers (HDLCEX) MAL2 registers (HDLCMP) Reserved Start 0x000 0x3FF Size (4KB)1 108W 128W 128W 128W 256W
0x000 0x010 0x012 0x014 0x080 0x090 0x092 0x0A0 0x0A8 0x0B0 0x0B8 0x0C0 0x0D0 0x0E0 0x0F0 0x100 0x140 0x180 0x200 0x280 0x300
0x00F 0x011 0x013 0x07F 0x08F 0x091 0x09F 0x0A7 0x0AF 0x0B7 0x0BF 0x0CF 0x0DF 0x0EF 0x0FF 0x13F 0x17F 0x1FF 0x27F 0x2FF 0x3FF
Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register, kiloword (KW) (which equals KB).
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NPe405H PowerNP NPe405H Embedded Processor
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BRIDGE
bridge provides mechanism connecting devices processor, peripherals, memory. This interface Specification compliant. Features include: Internal arbiter external devices speeds 66MHz. Internal arbiter optional disabled systems which employ external arbiter. frequency 66MHz Asynchronous operation from frequency 66MHz maximum 32-bit Address/Data Power Management: Power Management v1.1 compliant Buffering between PCI: Target 64-byte write post buffer Target 96-byte read prefetch buffer Slave 32-byte write post buffer Slave 64-byte read prefetch buffer Error tracking/status Supports Target side configuration Supports processor access address spaces: Single-byte reads writes memory single-beat prefetch-burst reads single-beat writes Single-byte configuration reads writes (type type interrupt acknowledge special cycle Supports target access address spaces Supports PowerPC processor boot from memory
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NPe405H PowerNP NPe405H Embedded Processor
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SDRAM MEMORY CONTROLLER
NPe405H Memory Controller provides latency access path SDRAM memory. memory controller supports four logical banks. 256MB bank supported, maximum total. Memory access refresh timing, address bank sizes, memory addressing modes programmable. Features include: 11x8 13x11 row-column address modes 4-bank devices supported) Memory operates same frequency 32-bit memory interface support Programmable address range each bank memory address space Industry standard 168-pin DIMMS supported (some configurations) NPe405H supports memory with PC100 support NPe405H supports memory with PC133 support 256MB bank Programmable timing Auto refresh Page Mode Accesses with open pages Power Management (self-refresh) Error Checking Correction (ECC) support Standard single error correct, double error detect coverage Aligned nibble error detect Address error logging
EXTERNAL CONTROLLER (EBC)
Supports eight ROM, EPROM, SRAM, Flash, Slave Peripheral banks supported 66.66MHz operation Burst non-burst devices 16-, 32-bit byte-addressable data width support Latch data Ready, Synchronous Asynchronous Programmable clock-cycle time-out counter with disable Ready Programmable access timing device 0-255 wait states non-bursting devices Burst Wait States first access Wait States subsequent accesses Programmable chip select assertion/negation relative driving address Programmable output write-enable assertion/negation relative assertion chip select Programmable address mapping Peripheral device wait "Ready" External master interface Write posting from external master Read prefetching external master reads Bursting capable from external master Allows external master access non-EBC slaves External master control slaves access control
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NPe405H PowerNP NPe405H Embedded Processor
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CONTROLLER
Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/Gather capability programming multiple operations 16-, 32-bit peripheral support (OPB external attached) 32-bit addressing Address increment decrement Internal 32-byte data buffering capability Supports internal external peripherals Support memory mapped peripherals Support peripherals running slower frequency buses
SERIAL INTERFACE
8-pin UART interfaces provided Selectable internal external serial clock allow wide range baud rates Register compatibility with NS16550 register Complete status reporting capability Transmitter receiver each buffered with 16-byte FIFOs when FIFO mode Fully programmable serial-interface characteristics Supports using internal engine
INTERFACE
Compliant with Phillips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers programmable interrupt request signal Provides full management protocol Programmable error recovery
EEPROM CONTROLLER
Supports setting processor configuration from serial EEPROM during system reset.
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HDLCEX INTERFACE
32-channel HDLC controller full-duplex Pulse Code Modulation (PCM) Highway ports speeds 4.096 Mbps port 8.192 Mbps when using single port Supports HDLC protocol well Transparent mode single channel port, autonomous management I-Frames S-Frames Normal Response mode (NRM) protocol channel port. U-frames handled software. Supports software emulation channels
HDLCMP INTERFACE
HDLC controller provides eight full-duplex serial ports 2.048Mbps data rate Supports HDLC protocol well Transparent mode Software emulation
GENERAL PURPOSE (GPIO) CONTROLLER
GPIO controllers 32-signal system GPIO (GPIO0) 32-signal communications GPIO (GPIO1) Most GPIOs pin-shared with other functions. Configuration registers provided determine whether particular that GPIO capabilities acts GPIO used another purpose. Both GPIO functions have I/Os. Each GPIO output separately programmable emulate open-drain driver (drives zero, three-stated output
UNIVERSAL INTERRUPT CONTROLLER (UIC)
cascaded Universal Interrupt Controllers (UICs) provide control, status, communications necessary interrupt sources PowerPC processor. Features include: Seven external internal interrupts Edge triggered level-sensitive Positive negative active Selectable non-critical critical interrupt requests PPC405 processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector generation reduced latency interrupt handling
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10/100 MBPS ETHERNET
Four units capable full- half-duplex, Mbps Mbps operation Integrated ZMII Bridge supports MII, SMII RMII connections external PHYs (PHYs included chip) Reduced Media Independent Interface (RMII) Serial Media Independent Interface (SMII) four applications Media Independent Interface (MII) single dual applications Dedicated media access layer (MAL) provides support
JTAG
IEEE 1149.1 Test Access Port Debugger support JTAG boundary scan support (BSDL file available)
PERFORMANCE COUNTERS
series software accessible transaction event counters that used analyze performance.
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NPe405H PowerNP NPe405H Embedded Processor
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580-BALL E-PBGA PACKAGE
Figure 35mm, 580-Ball E-PBGA Package
View
Gold gate release corresponds ball location Note: dimensions
Bottom View
35.0
0.60 0.30
35.0
0.60 Solder Ball
2.65
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NPe405H PowerNP NPe405H Embedded Processor
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SIGNAL LISTS
following table lists external signals alphabetical order shows ball number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal signals brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin.
SIGNALS LISTED ALPHABETICALLY
Table Signals Listed Alphabetically (Sheet
Signal Name AVDD BankSel0 BankSel1 BankSel2 BankSel3 [BE0]PCIC0 [BE1]PCIC1 [BE2]PCIC2 [BE3]PCIC3 BusReq ClkEn0 ClkEn1 [DMAAck0]GPIO0_13 [DMAAck1]GPIO0_14 [DMAAck2]GPIO0_15 [DMAAck3]GPIO0_16[PerCS5] [DMAReq0]GPIO0_09 [DMAReq1]GPIO0_10 [DMAReq2]GPIO0_11 [DMAReq3]GPIO0_12[PerCS4] DQM0 DQM1 DQM2 DQM3 DQMCB ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMC0MDClk Ball AN31 AM31 AL21 AP23 AM22 AN23 AN22 AP21 AN21 AB34 AB33 AA31 AC34 AA34 AA33 AA32 AN20 AN15 AP12 AN09 AM20 AP24 AN24 AM24 AN25 AP26 AM25 AN26 AL25 Ethernet SDRAM SDRAM SDRAM External Slave Peripheral External Slave Peripheral External Master Peripheral SDRAM SDRAM SDRAM Power SDRAM Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name EMC0MDIO [EMC0Sync]EMC0TxEn[EMC0Tx0En] EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] EMC0TxD2[EMC0Tx1D0][EMC0Tx2D] EMC0TxD3[EMC0Tx1D1][EMC0Tx3D] EMC0TxEn[EMC0Tx0En][EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC0Tx0En]EMC0TxEn[EMC0Sync] [EMC0Tx1En]EMC0TxErr [EOT0/TC0]GPIO0_24 [EOT1/TC1]GPIO0_25 [EOT2/TC2]GPIO0_26 [EOT3/TC3]GPIO0_27[PerCS7] ExtAck ExtReq ExtReset Ball AF34 AE32 AF33 AE31 External Master Peripheral External Master Peripheral External Master Peripheral External Slave Peripheral Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name Ball N13-N22 P13-P22 R13-R22 T13-T22 U13-U22 Power Note: Balls N13-N22, P13-P22, R13-R22, T13T22, U13-U22, V13-V22, W13-W22, Y13Y22, AA13-AA22, AB13-AB22 also thermal balls. Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name [Gnt]PCIReq0 Ball V13-V22 W13-W22 Y13-Y22 AA13-AA22 AB13-AB22 AC04 AC31 AE01 AE34 AJ01 AJ34 AL04 AL12 AL17 AL18 AL23 AL31 AM03 AM17 AM32 AN01 AN02 AN33 AN34 AP01 AP02 AP06 AP10 AP15 AP20 AP25 AP29 AP33 AP34 Power Note: Balls N13-N22, P13-P22, R13-R22, T13T22, U13-U22, V13-V22, W13-W22, Y13-Y22, AA13-AA22, AB13-AB22 also thermal balls. Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name GPIO0_00 GPIO0_01[TS1E] GPIO0_02[TS2E] GPIO0_03[TS1O] GPIO0_04[TS2O] GPIO0_05[TS3] GPIO0_06[TS4] GPIO0_07[TS5] GPIO0_08[TS6] GPIO0_09[DMAReq0] GPIO0_10[DMAReq1] GPIO0_11[DMAReq2] GPIO0_12[DMAReq3][PerCS4] GPIO0_13[DMAAck0] GPIO0_14[DMAAck1] GPIO0_15[DMAAck2] GPIO0_16[DMAAck3][PerCS5] GPIO0_17[IRQ0] GPIO0_18[IRQ1] GPIO0_19[IRQ2] GPIO0_20[IRQ3] GPIO0_21[IRQ4] GPIO0_22[IRQ5] GPIO0_23[IRQ6][PerCS6] GPIO0_24[EOT0/TC0] GPIO0_25[EOT1/TC1] GPIO0_26[EOT2/TC2] GPIO0_27[EOT3/TC3][PerCS7] GPIO0_28[PerCS1] GPIO0_29[PerCS2] GPIO0_30[PerCS3] GPIO0_31[TrcClk] Ball AA34 AA33 AA32 AB34 AB33 AA31 AC34 AB32 AC33 AD34 AC32 AD33 AD32 AE33 AF34 AE32 AF33 AE31 AG34 AF32 AG33 AH34 System Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name GPIO1_15[HDLCMPTxClk7] GPIO1_16[HDLCMPTxData7] GPIO1_18[HDLCMPRxClk7] GPIO1_19[HDLCMPRxData7] GPIO1_23[HDLCMPTxEn3][UART1_RI] GPIO1_26[UART0_CTS] GPIO1_27[UART0_DSR] GPIO1_28[UART0_DCD] GPIO1_29[UART0_RI]x GPIO1_30[UART0_RTS] GPIO1_31[UART0_DTR] Halt HDLCEXRxClk HDLCEXRxDataA HDLCEXRxDataB HDLCEXRxFS HDLCEXTxClk HDLCEXTxDataA HDLCEXTxDataB HDLCEXTxFS Ball AJ31 AK33 AL34 AM33 AL32 AK32 AM34 AL33 System HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel System Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name HDLCMPRxClk0 HDLCMPRxClk1 HDLCMPRxClk2 HDLCMPRxClk3 [HDLCMPRxClk7]GPIO1_18] HDLCMPRxData0 HDLCMPRxData1 HDLCMPRxData2 HDLCMPRxData3 [HDLCMPRxData7]GPIO1_19 HDLCMPTxClk0 HDLCMPTxClk1 HDLCMPTxClk2 HDLCMPTxClk3 [HDLCMPTxClk7]GPIO1_15 HDLCMPTxData0 HDLCMPTxData1 HDLCMPTxData2 HDLCMPTxData3 [HDLCMPTxData7]GPIO1_16 [HDLCMPTxEn3]GPIO1_23[UART1_RI] [HDLCMPTxEn4]GPIO1_02[PHYRx3D0] HoldAck HoldPri HoldReq IICSCL[IECSCL] IICSDA[IECSDA] Ball AK34 AJ32 Internal Peripheral External Master Peripheral HDLC 8-Port HDLC 8-Port HDLC 8-Port HDLC 8-Port HDLC 8-Port HDLC 8-Port HDLC 8-Port HDLC 8-Port HDLC 8-Port Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name [IRQ0]GPIO0_17 [IRQ1]GPIO0_18 [IRQ2]GPIO0_19 [IRQ3]GPIO0_20 [IRQ4]GPIO0_21 [IRQ5]GPIO0_22 [IRQ6]GPIO0_23[PerCS6] MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 Ball AB32 AC33 AD34 AC32 AD33 AD32 AE33 AP27 AM26 AN27 AN28 AM28 AN29 AP30 AM29 AN30 AP31 AL29 AM30 AP32 AM27 AP28 SDRAM SDRAM Note: During cycle MemAddr00 least significant (lsb) this bus. Interrupts Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AM18 AN19 AP19 AP18 AN18 AN17 AP16 AN16 AM15 AP14 AM16 AN14 AM14 AP13 AN13 AL14 AM13 AN12 AP11 AM12 AN11 AN10 AP09 AM10 AL10 AP08 AM09 AN08 AP07 AM08 AN07 AL08 SDRAM Notes: MemData00 most significant (msb). MemData31 least significant (lsb) Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball Power AD04 AD31 AF04 AF31 AH04 AH31 AK04 AK31 Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball AL05 AL07 AL09 AL11 AL24 AL26 AL27 AL28 AL30 AM06 AM11 AM19 AM23 AN32 AP17 Power Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0[BE0] PCIC1[BE1] PCIC2[BE2] PCIC3[BE3] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel Ball Note: PCIAD31 most significant (msb) this bus. Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 Ball AD02 AC03 AD01 AC02 AB03 AC01 AA04 AB02 AB01 AA03 AA02 AA01 External Slave Peripheral Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PerBLast PerClk PerCS0 [PerCS1]GPIO0_28 [PerCS2]GPIO0_29 [PerCS3]GPIO0_30 [PerCS4]GPIO0_12[DMAReq3] [PerCS5]GPIO0_16[DMAAck3] [PerCS6]GPIO0_23[IRQ6] [PerCS7]GPIO0_27[EOT3/TC3] PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE Ball AG34 AF32 AG33 AA32 AC34 AE33 AE31 AM07 AN06 AP05 AN05 AP04 AN03 AL06 AM05 AN04 AM04 AL03 AL02 AM01 AK03 AJ04 AM02 AK02 AJ03 AK01 AJ02 AH03 AG04 AH02 AG03 AG02 AF03 AG01 AE04 AF02 AE03 AF01 AE02 External Slave Peripheral External Slave Peripheral External Slave Peripheral Note: PerData00 most significant (msb) this bus. External Slave Peripheral Interface Group External Slave Peripheral External Slave Peripheral Page
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PerPar0 PerPar1 PerPar2 PerPar3 PerR/W PerReady PerWBE0 PerWBE1 PerWBE2 PerWBE3 [PerWE]PCIINT PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] [PHY0CrS0DV]PHY0CrS [PHY0CrS1DV]PHY0RxDV [PHY0RefClk]PHY0TxClk PHY0RxClk PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] PHY0RxD2[PHY0Rx1D0][PHY0Rx2D] PHY0RxD3[PHY0Rx1D1][PHY0Rx3D] PHY0RxDV[PHY0CrS1DV] PHY0RxErr[PHY0Rx0Er] [PHY0Rx0Er]PHY0RxErr [PHY0Rx1Er]PHY0Col PHY0TxClk[PHY0RefClk] [Req]PCIGnt0 Reserved SysClk SysErr SysReset Ball AP03 AL01 AH01 AD03 AP22 Ethernet Ethernet Ethernet SDRAM Other System System System Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet External Slave Peripheral Ethernet Ethernet Ethernet Ethernet Ethernet External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral Interface Group Page
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [TC0/EOT0]GPIO0_24 [TC1/EOT1]GPIO0_25 [TC2/EOT2]GPIO0_26 [TC3/EOT3]GPIO0_27 TestEn TmrClk [TrcClk]GPIO0_31 TRST [TS1E]GPIO0_01 [TS2E]GPIO0_02 [TS1O]GPIO0_03 [TS2O]GPIO0_04 [TS3]GPIO0_05 [TS4]GPIO0_06 [TS5]GPIO0_07 [TS6]GPIO0_08 [UART0_CTS]GPIO1_26 [UART0_DCD]GPIO1_28 [UART0_DSR]GPIO1_27 [UART0_DTR]GPIO1_31 [UART0_RI]GPIO1_29 [UART0_RTS]GPIO1_30 UART0_Rx UART0_Tx [UART1_RI]GPIO1_23[HDLCMPTxEn3] UART1_Rx UART1_Tx UARTSerClk Ball AF34 AE32 AF33 AE31 AH34 AG32 AH33 AH32 AJ33 AG31 Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Trace JTAG JTAG System System JTAG Trace JTAG Trace Trace External Slave Peripheral JTAG Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power AB04 AB31 AL13 AL15 AL16 AL19 AL20 AL22 AM21 SDRAM Interface Group Page
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
SIGNALS LISTED BALL ASSIGNMENT
Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball PCIAD11 PCIAD13 PCIAD14 PCIPErr PCIDevSel PCIReq5 OVDD PCIAD19 PCIAD20 PCIIDSel PCIAD26 PCIGnt1 PCIAD31 PCIReq0 PHY0CrS EMC0TxErr EMC0TxD3 EMC0TxD0 PHY0RxD2 GPIO1_01 GPIO1_04 GPIO1_10 GPIO1_13 GPIO1_17 Signal Name Ball PCIAD10 PCIReq3 OVDD PCIC1[BE1] PCIParity PCIStop PCIIRDY PCIC2[BE2] PCIClk PCIAD18 PCIAD21 PCIAD23 PCIAD24 PCIAD25 PCIAD28 PCIAD30 PCIGnt0[Req] PCIReset EMC0MDIO OVDD EMC0TxD1 PHY0RxClk PHY0RxD3 Signal Name Ball Signal Name PCIAD08 PCIAD09 PCIAD12 PCIINT[PerWE] PCIAD15 PCIReq4 OVDD PCITRDY PCIFrame PCIAD16 PCIAD17 PCIGnt4 PCIAD22 PCIC3[BE3] OVDD PCIAD27 PCIAD29 PHY0TxClk PHY0Col EMC0MDClk EMC0TxD2 PHY0RxDV PHY0RxErr PHY0RxD1 GPIO1_02 GPIO1_05 GPIO1_08 GPIO1_11 GPIO1_16 GPIO1_19 GPIO1_24 GPIO1_21 Ball Signal Name PCIC0[BE0] PCIReq1 PCIAD07 OVDD PCIGnt2 OVDD PCISErr OVDD PCIGnt3 OVDD PCIGnt5 EMC0TxEn OVDD GPIO1_00 OVDD GPIO1_07 OVDD GPIO1_15 OVDD TmrClk GPIO1_20 GPIO1_25
PHY0RxD0 GPIO1_03 GPIO1_06 GPIO1_09 GPIO1_12 GPIO1_18 GPIO1_14
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball Signal Name PCIAD06 PCIReq2 OVDD OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD GPIO1_22 GPIO1_26 GPIO1_28 Ball PCIAD04 OVDD PCIAD05 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO1_23 GPIO1_27 GPIO1_29 Signal Name Ball Signal Name PCIAD01 PCIAD02 PCIAD03 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD GPIO1_30 HDLCMPRxClk0 HDLCMPRxData0 Ball Signal Name HoldAck ExtAck BusReq PCIAD00 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO1_31 HDLCMPRxClk1 HDLCMPRxClk2
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball Signal Name PerErr HoldReq ExtReq OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD HDLCMPRxData1 SysReset Ball PerClk ExtReset HoldPri ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball HDLCMPRxData2 SysErr Signal Name Ball Signal Name PerOE PerReady PerBLast OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD OVDD SysClk TRST Ball Signal Name PerWBE2 PerCS0 PerR/W ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD TestEn OVDD
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball Signal Name PerAddr31 PerWBE0 PerWBE3 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Halt HDLCMPRxClk3 Ball Signal Name PerAddr27 PerAddr29 PerAddr30 PerWBE1 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball AVDD HDLCMPRxData3 HDLCMPTxClk0 HDLCMPTxClk1 Ball PerAddr25 PerAddr26 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball HDLCMPTxData1 HDLCMPTxClk2 Signal Name Ball Signal Name PerAddr22 PerAddr23 PerAddr28 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball HDLCMPTxData0 HDLCMPTxClk3 HDLCMPTxData3
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball Signal Name PerAddr21 PerAddr20 PerAddr24 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball HDLCMPTxData2 GPIO0_01 GPIO0_00 Ball Signal Name PerAddr18 PerAddr19 PerAddr15 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO0_06 GPIO0_02 GPIO0_03 Ball Signal Name PerAddr17 PerAddr16 PerAddr11 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO0_10 GPIO0_05 GPIO0_04 Ball PerAddr14 PerAddr13 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO0_08 GPIO0_07 Signal Name
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Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 Signal Name PerAddr12 PerAddr10 PerAddr09 PerAddr06 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO0_15 GPIO0_12 GPIO0_11 GPIO0_09 Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 Signal Name PerAddr08 PerAddr07 PerAddr04 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO0_17 GPIO0_14 GPIO0_13 Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 Signal Name PerAddr05 PerAddr03 PerAddr01 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO0_20 GPIO0_18 GPIO0_16 Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 Signal Name PerAddr02 PerAddr00 PerPar3 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD GPIO0_22 GPIO0_21 GPIO0_19
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 PerData31 PerData29 PerData27 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO0_27 GPIO0_25 GPIO0_23 Signal Name Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 Signal Name PerData30 PerData28 PerData25 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD GPIO0_29 GPIO0_26 GPIO0_24 Ball AG01 AG02 AG03 AG04 AG05 AG06 AG07 AG08 AG09 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 Signal Name PerData26 PerData24 PerData23 PerData21 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball UARTSerClk UART0_Rx GPIO0_30 GPIO0_28 Ball AH01 AH02 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 Signal Name PerPar2 PerData22 PerData20 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD UART1_Rx UART0_Tx GPIO0_31
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball AJ01 AJ02 AJ03 AJ04 AJ05 AJ06 AJ07 AJ08 AJ09 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 PerData19 PerData17 PerData14 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball HDLCEXRxClk IICSDA[IECSDA] UART1_Tx Signal Name Ball AK01 AK02 AK03 AK04 AK05 AK06 AK07 AK08 AK09 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 Signal Name PerData18 PerData16 PerData13 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD HDLCEXTxDataA HDLCEXRxDataA IICSCL[IECSCL] Ball AL01 AL02 AL03 AL04 AL05 AL06 AL07 AL08 AL09 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 Signal Name PerPar1 PerData11 PerData10 OVDD PerData06 OVDD MemData31 OVDD MemData24 OVDD MemData15 BankSel0 OVDD ECC7 OVDD OVDD OVDD MemAddr10 OVDD HDLCEXTxClk HDLCEXTxFS HDLCEXRxDataB Ball AM01 AM02 AM03 AM04 AM05 AM06 AM07 AM08 AM09 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 Signal Name PerData12 PerData15 PerData09 PerData07 OVDD PerData00 MemData29 MemData26 MemData23 OVDD MemData19 MemData16 MemData12 MemData08 MemData10 MemData00 OVDD DQMCB BankSel2 OVDD ECC2 ECC5 MemAddr01 MemClkOut0 MemAddr04 MemAddr07 MemAddr11 HDLCEXRxFS HDLCEXTxDataB
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NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Signals Listed Ball Assignment (Sheet
Signal names followed asterisk multiplexed. Look name shown "Signals Listed Alphabetically" page indication signals pin.
Ball AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 PerData05 PerData08 PerData03 PerData01 MemData30 MemData27 DQM3 MemData21 MemData20 MemData17 MemData14 MemData11 DQM1 MemData07 MemData05 MemData04 MemData01 DQM0 ClkEn1 BankSel3 ECC1 ECC3 ECC6 MemAddr02 MemAddr03 MemAddr05 MemAddr08 OVDD Signal Name Ball AP01 AP02 AP03 AP04 AP05 AP06 AP07 AP08 AP09 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 PerPar0 PerData04 PerData02 MemData28 MemData25 MemData22 MemData18 DQM2 MemData13 MemData09 MemData06 OVDD MemData03 MemData02 ClkEn0 BankSel1 ECC0 ECC4 MemAddr00 MemClkOut1 MemAddr06 MemAddr09 MemAddr12 Signal Name Ball Signal Name Ball Signal Name
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SIGNAL DESCRIPTION
following table provides summary number package pins (balls) associated with each functional interface group.
SUMMARY
Table Summary
Group
Nonmultiplexed Signals Multiplexed Signals Total Signal Pins AVDD OVDD (and thermal) Reserved Total Pins
Pins
Multiplexed Pins table "Signal Functional Description" page each external signal listed along with short description signal function. signals grouped together according their function. Some signals multiplexed same package (ball) that used different functions. most cases, signal name shown this table unaccompanied multiplexed signal names that associated with cases where multiplexed signals same functional group, names appear default signal followed secondary signals square brackets (for example, EMC0TxErr[EMC0Tx1En]). Active-low signals (for example, RAS) marked with overline. signal that primary (default) signal multiplexed shown square brackets. active signal multiplexed controlled programming. expected that single application, particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. Multipurpose Pins addition multiplexing, pins also multipurpose. example multi-purpose occurs when peripheral controller address pins used outputs NPe405H broadcast address external slave devices when NPe405H control external bus. However, when external master gains ownership external bus, these same pins used inputs which driven external master received NPe405H. this example, pins also bidirectional, serving both inputs outputs. Initialization Strapping group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Initialization" page 68). Note that these pins strapping considered multiplexing since strapping function programmable.
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NPe405H PowerNP NPe405H Embedded Processor
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Pull-up Pull-down Resistors Pull-up pull-down resistors used strapping during reset retain unused undriven inputs appropriate state. recommended pull-up value +3.3V (10k used tolerant I/Os) pull-down value GND, applies only individually terminated signals. prevent possible damage device, I/Os capable becoming outputs must never tied together terminated through common resistor. your system-level test methodology permits, input-only signals connected together terminated through either common resistor directly +3.3V GND. When resistor used, value must ensure that grouped I/Os reach valid logic zero logic state when accounting total input current into NPe405H. Unused I/Os Strapping some pins necessary when they unused. Although NPe405H requires only pull-up pull-down terminations specified "Signal Functional Description" page good design practice terminate unused inputs configure I/Os such that they always drive. unused, peripheral, SDRAM, buses should configured terminated follows: Peripheral interface-PerAddr00:31, PerData00:31, control signals driven default. Terminate PerReady high PerError low. SDRAM-Program SDRAM0_CFG[EMDULR]=1 SDRAM0_CFG[DCE]=1. This causes NPe405H actively drive SDRAM address, data, control signals. PCI-Configure controller park actively drive PCIAD31:0, PCIC3:0[BE3:0], remaining control signals doing following: Strap NPe405H disable internal arbiter. Individually connect PCISErr, PCIPErr, PCITRDY, PCIStop through 3.3k resistors +3.3V. Terminate PCIReq1:5 +3.3V. Terminate PCIReq0[Gnt] GND.
External Peripheral Control Signals external peripheral control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck) high-impedance state when ExtReset=0. addition, detailed PowerNP NPe405H Embedded Processor User's Manual, peripheral controller programmed EBC0_CFG float some these control signals between transactions when external master owns peripheral bus. result, pull-up resistor should added those control signals where undriven state affect devices receiving that particular signal. following table lists signals provided NPe405H. Please "Signals Listed Alphabetically" page number which each signal assigned. cases where multiplexed signal (indicated square brackets) shown without other signals that assigned that pin, what other signals referring same table.
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
SIGNAL FUNCTIONAL DESCRIPTION
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name Description Type
Notes
Interface
PCIAD0:31 PCIC3:0[BE3:0] Address/Data bus. Multiplexed address data command Byte Enable Parity. Parity even across PCIAD0:31 PCIC0:3[BE0:3]. PCIParity valid cycle after either address data phase. device that drove PCIAD0:31 responsible driving PCIParity next clock. Driven current master indicate beginning duration access. Driven current master. Assertion PCIIRDY indicates that initiator ready transfer data. target current transaction drives PCITRDY. Assertion PCITRDY indicates that target ready transfer data. target current transaction assert PCIStop indicate requesting master that wants current transaction. Driven target current transaction. target asserts PCIDevSel when decoded address command encoding claims transaction. Used during configuration cycles select slave interface configuration Used reporting address parity errors catastrophic failures detected target. Used reporting data parity errors transactions. PCIPErr driven active device receiving PCIAD0:31, PCIC0:3[BE0:3], PCIParity, clocks following data which parity detected. Used asynchronous clock. specific reset Interrupt. Open-drain output (two states; open circuit). Req0 when internal arbiter used, when external arbiter used. used, pull this signal otherwise, pull down. Used PCIReq1:5 input when internal arbiter used Gnt0 when internal arbiter used, when external arbiter used tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V
PCIParity
PCIFrame PCIIRDY
PCITRDY
PCIStop
PCIDevSel
PCIIDSel PCISErr
PCIPErr
PCIClk PCIReset PCIINT
PCIReq0[Gnt]
PCIReq1:5 PCIGnt0[Req]
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NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name PCIGnt1:5 Description PCIGnt1:5 output when internal arbiter used. Type tolerant 3.3V
Notes
HDLCEX Interface
HDLCEXTxClk HDLCEXTxFS HDLCEXTxDataA HDLCEXTxDataB HDLCEXRxClk HDLCEXRxFS HDLCEXRxDataA HDLCEXRxDataB [HDLCEXTxEnA] [HDLCEXTxEnB] Transmit Clock Transmit Frame Synchronization Transmit Data port Transmit Data port Receive Clock Receive Frame Synchronization Receive Data port Receive Data port Transmit Enable port Transmit Enable port 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
HDLCMP Interface
HDLCMPTxClk0:3 [HDLCMPTxClk4:7] HDLCMPTxData0:3 [HDLCMPTxData4:7] [HDLCMPTxEn0:7] HDLCMPRxClk0:3 [HDLCMPRxClk4:7] HDLCMPRxData0:3 [HDLCMPRxData4:7] Transmit Clock signal that controls transmit rate Transmit Clock signal that controls transmit rate Transmit Data signal Transmit Data signal Transmit Data Enable signal that controls when external buffer tri-stated Receive Clock signal that controls receive rate Receive Clock signal that controls receive rate Receive Data signal Receive Data signal 3.3V LVTTL tolerant 3.3V LVTTL 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL 3.3V LVTTL tolerant 3.3V LVTTL 3.3V LVTTL tolerant 3.3V LVTTL
Ethernet Interface
EMC0MDClk Management Data Clock. MDClk sourced PHY. Management information transferred synchronously with respect this clock (MII, RMII, SMII). Management Data Input/Output bidirectional signal between Ethernet controller PHY. used transfer control status information (MII, RMII, SMII). 3.3V LVTTL
EMC0MDIO
tolerant 3.3V LVTTL
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Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name Description Type
Notes
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] Transmit Data. nibble wide data towards net. EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] data synchronous with PHY0TxClk (MII 0[RMII 1][SMII EMC0TxD2[EMC0Tx1D0][EMC0Tx2D] 3]). EMC0TxD3[EMC0Tx1D1][EMC0Tx3D] [EMC1TxD0][EMC1Tx2D0] [EMC1TxD1][EMC1Tx2D1] [EMC1TxD2][EMC1Tx3D0] [EMC1TxD3][EMC1Tx3D1]
3.3V LVTTL
RMII Transmit Data (MII 1[RMII 3]).
tolerant 3.3V LVTTL
EMC0TxEn[EMC0Tx0En][EMC0Sync]
Transmit Enable. This signal driven EMAC2 PHY. Data valid during active state this signal. Deassertion this signal indicates frame transmission. This signal synchronous with PHYTxClk (MII 0[RMII 0]). SMII Sync. Transmit Error. This signal generated Ethernet controller, connected synchronous with PHY0TxClk. informs that error detected (MII Transmit Enable [RMII Transmit Enable ([MII 1][RMII 2]). Transmit Error. This signal generated Ethernet controller, connected synchronous with PHY1TxClk. informs that error detected ([MII 1]). Transmit Enable [RMII Collision [receive error] signal from PHY. This asynchronous signal (MII Receive Error ([RMII 1]). Carrier Sense signal from PHY. This asynchronous signal (MII Carrier sense data valid ([RMII 0]). Receiver medium clock. This signal generated (MII Received Data. This nibble wide from PHY. data synchronous with PHY0RxClk (MII 0[RMII 1][SMII 3]).
3.3V LVTTL
EMC0TxErr[EMC0Tx1En]
3.3V LVTTL
[EMC1TxEn][EMC1Tx2En]
tolerant 3.3V LVTTL
[EMC1TxErr][EMC1Tx3En]
tolerant 3.3V LVTTL
PHY0Col[PHY0Rx1Er]l
tolerant 3.3V LVTTL
PHY0CrS[PHY0CrS0DV]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PHY0RxClk PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] PHY0RxD2[PHY0Rx1D0][PHY0Rx2D] PHY0RxD3[PHY0Rx1D1][PHY0Rx3D] [PHY1RxD0][PHY1Rx2D0] [PHY1RxD1][PHY1Rx2D1] [PHY1RxD2][PHY1Rx3D0] [PHY1RxD3][PHY1Rx3D1]
Receive Data (MII 1[RMII 3]).
tolerant 3.3V LVTTL
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name Description Receive Data Valid. Data Data valid when this signal activated. Deassertion this signal indicates frame reception (MII Carrier sense data valid ([RMII Receive Error. This signal comes from synchronous with PHY0RxClk (MII [RMII 0]). Transmit medium clock. This signal generated ([MII 0]). Reference Clock [RMII SMII]. Collision [receive error] signal from PHY. This asynchronous signal ([MII 1]). Receive Error. This signal comes from synchronous with PHY1RxClk ([RMII 3]). Carrier Sense signal from PHY. This asynchronous signal ([MII 1]). Carrier Sense Data Valid ([RMII 2]). Receiver medium clock. This signal generated ([MII 1]). Receive Data Valid ([MII 1]). Carrier Sense Data Valid ([RMII 3]). Receive Error. This signal comes from synchronous with PHY1RxClk ([MII 1][RMII 2]). Transmit medium clock. This signal generated ([MII 1]). Type
Notes
PHY0RxDV[PHY0CrS1DV]
tolerant 3.3V LVTTL
PHY0RxErr[PHY0Rx0Er]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PHY0TxClk[PHY0RefClk]
[PHY1Col][PHY1Rx3Er]
tolerant 3.3V LVTTL
[PHY1CrS][PHY1CrS2DV]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
[PHY1RxClk]
[PHY1RxDV][PHY1CrS3DV]
[PHY1RxErr][PHY1Rx2Er] [PHY1TxClk] SDRAM Interface
MemAddr00:31
Memory Data Notes: MemAddr00 most significant (msb). MemData31 least significant (lsb). Memory Address bus. Notes: MemAddr12 most significant (msb). MemAddr00 least significant (lsb). Bank Address supporting internal banks Address Strobe. Column Address Strobe. byte lane (MemAddr00:7), (MemAddr08:15), (MemData16:23), (MemData24:31)
3.3V LVTTL
MemAddr12:00
3.3V LVTTL
BA1:0
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
3.3V LVTTL
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name DQMCB ECC0:7 BankSel0:3 ClkEn0:1 MemClkOut0:1 External Slave Peripheral Interface PerData00:31 External peripheral data when external master mode, otherwise used external master. Note: PerData00 most significant (msb) this bus. External peripheral address when external master mode, otherwise used external master. External peripheral byte parity signals. Peripheral write-byte enable. Byte-enables which valid entire cycle write-byte-enables which valid each byte each data transfer, allowing partial word transactions. Used either external controller controller depending upon type transfer involved. Used inputs when external master owns external interface. Peripheral write enable. when four PerWBE signals low. Peripheral Chip Selects Peripheral output enable. Used either external controller controller depending upon type transfer involved. When NPe405H master, enables peripherals drive bus. Peripheral read/write. Used when external master mode either external controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. Otherwise used external master input indicate direction transfer. Indicates peripheral ready transfer data. Peripheral burst last. Used indicate last transfer memory access. Peripheral Clock. Used external master synchronous peripheral slaves. Used indicate errors from peripherals. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL Description check bits. check bits 0:7. Select four external SDRAM banks. Write Enable. SDRAM Clock Enable. copies SDRAM clock allows, some cases, glueless SDRAM attachment without requiring this signal repowered zero-delay buffer. Type 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Notes
PerAddr00:31 PerPar0:3
PerWBE0:3
tolerant 3.3V LVTTL
[PerWE] PerCS0 [PerCS1:7]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerOE
PerR/W
tolerant 3.3V LVTTL
PerReady PerBLast PerClk PerErr
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name Description request. Used peripheral slaves request data transfer. Following system reset, default mode signals active-low. They programmed active-high using DMA0_POL register. acknowledge. Used indicate peripherals that data transfer complete. Following system reset, default mode signals active-low. They programmed active-high using DMA0_POL register. Transfer/Terminal Count. Indication peripherals that data been transferred, controller that programmed amount data been transferred. Following system reset, default mode signals active-low. They programmed active-high using DMA0_POL register. Type tolerant 3.3V LVTTL
Notes
[DMAReq0:3]
[DMAAck0:3]
tolerant 3.3V LVTTL
[EOT0:3/TC0:3]
tolerant 3.3V LVTTL
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name External Master Peripheral Interface ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq Internal Peripheral Interface Serial Clock used provide alternative clock internally generated serial clock. Used cases where allowable internally generated baud rates satisfactory. This input individually connected either both UART0 UART1. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Ready. UART0 Clear Send. UART0 Data Terminal Ready. UART0 Request Send. UART0 Ring Indicator. Peripheral Reset. Used external master synchronous peripheral slaves. Hold Request. Used external master request ownership peripheral bus. Hold Acknowledge. Used NPe405H transfer ownership peripheral external master. External Request. Used external master indicate prepared transfer data. External Acknowledgement. Used NPe405H indicate that data transfer occurred. Hold Primary. Used external master indicate priority given transfer high, low). Request. Used when NPe405H needs regain control peripheral interface from external Master. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL Description Type
Notes
UARTSerClk
tolerant 3.3V LVTTL
UART0_Rx UART0_Tx [UART0_DCD] [UART0_DSR] [UART0_CTS] [UART0_DTR] [UART0_RTS] [UART0_RI]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name UART1_Rx UART1_Tx [UART1_DCD] [UART1_DSR] [UART1_CTS] [UART1_DTR] [UART1_RTS] [UART1_RI] IICSCL[IECSCL] IICSDA[IECSDA] Interrupts Interface [IRQ0:6] JTAG Interface TRST Test Data Test Mode Select. Test Data Out. Test Clock. Test Reset. TRST must power-on reset JTAG boundary scan state machine. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL Interrupt Requests. tolerant 3.3V LVTTL UART1 Receive data. UART1 Transmit data. UART1 Data Carrier Detect. UART1 Data Ready. UART1 Clear Send. UART1 Data Terminal Ready. UART1 Request Send. UART1 Ring Indicator. [Initilization PROM] Serial Clock. [Initilization PROM] Serial Data. Description Type tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Notes
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name System Interface SysClk SysReset SysErr Halt GPIO0_00:31 GPIO1_00:31 TestEn Main System Clock input. Main System Reset. when Machine Check generated. Halt from external debugger. System General Purpose I/O. Communications General Purpose I/O. Test Enable. Used only manufacturing tests. Pull down normal operation. This input must toggle rate less than half core frequency (less than 100MHz most cases). most cases this input toggles much slower 1MHz 10MHz range). 3.3V Analog Wire w/ESD tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL 3.3V LVTTL Rcvr w/PD tolerant 3.3V LVTTL Description Type
Notes
TmrClk
Trace Interface [TS1E] [TS2E] [TS1O] [TS2O] [TS3:6] Even Trace execution status.To access this function, software must toggle bit. Trace execution status. access this function, software must toggle bit. Trace Status. access this function, software must toggle bit. Trace interface clock. toggling signal that always half core frequency. access this function, software must toggle bit. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
[TrcClk] Power Pins OVDD AVDD Other Pins Reserved
Ground Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14, P09-P14 also thermal balls. Logic voltage-2.5V Output driver voltage-3.3V Filtered voltage-2.5V
Hardwire Hardwire Hardwire 3.3V Wire w/ESD
connect signals, voltage, ground these pins.
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) Supply Voltage Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias
Notes: voltages specified with respect ground (GND). AVDD should derived from using following circuit:
Symbol OVDD AVDD TSTG
Value +2.7 +3.6 +2.7 -0.6 (OVDD 0.6) -0.6 (OVDD 2.4) +150 +120
Unit
AVDD inductor (equivalent MuRata LQH3C2R2M34) chip ferrite bead (equivalent MuRata BLM31A700S)
tantalum monolithic ceramic capacitor with dielectric equivalent 0.01 monolithic ceramic capacitor with dielectric equivalent
PACKAGE THERMAL SPECIFICATIONS
Table Package Thermal Specifications
NPe405H designed operate within case temperature range -40°C 85°C. Thermal resistance values EPBGA packages convection environment follows:
Package-Thermal Resistance
35mm, 580-balls-Junction-to-Case 35mm, 580-balls-Case-to-Ambient
Symbol
Airflow ft/min (m/sec)
(0.51) (1.02)
Unit
°C/W °C/W
Notes:
chip mounted JEDEC 2S2P card without heat sink. chip mounted card with least signal power planes, following relationships exist: Case temperature, measured center case surface with device soldered circuit board. where ambient temperature power consumption. TCMax TJMax where TJMax maximum junction temperature power consumption.
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
RECOMMENDED OPERATING CONDITIONS
Table Recommended Operating Conditions
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability. Notes: drivers meet specifications.
Parameter Logic Supply Voltage Supply Voltage Supply Voltage Input Logic High (3.3V LVTTL receivers) Input Logic High (2.5V CMOS receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Output Logic High Output Logic 3.3V input current pull-up pull-down) Input Current (with internal pull-down) Input Current (with internal pull-up) Input Allowable Overshoot (2.5V CMOS receivers) Input Allowable Overshoot (3.3V LVTTL receivers) Input Allowable Overshoot (5.0V LVTTL receivers) Input Allowable Undershoot (3.3V 5.0V receivers) Output Allowable Overshoot (3.3V 5.0V receivers) Output Allowable Undershoot (3.3V 5.0V receivers) Case Temperature
Notes: page
Symbol OVDD AVDD IIL1 IIL2 IIL3 VIMAO25 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3
Minimum +2.3 +3.0 +2.3 +2.0 +1.7 +2.0 +2.4
Typical +2.5 +3.3 +2.5
Maximum +2.7 +3.6 +2.7 OVDD +5.5 +0.8 OVDD +0.4
Unit
Notes
-250
3.6V) 3.6V) OVDD +5.5
OVDD
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
V-TOLERANT INPUT CURRENT
Figure 5V-Tolerant Input Current
-100 Input Current (µA)
-200 -300
-400
-500
-600 -700 Input Voltage
INPUT CAPACITANCE
Table Input Capacitance
Parameter 3.3V LVTTL I/O) tolerant LVTTL only pins Symbol CIN1 CIN2 CIN3 CIN4 Maximum 0.75 Unit Notes
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics
Parameter Active Operating Current 133MHz Active Operating Current 200MHz Active Operating Current 266MHz Active Operating Current OVDD 133MHz Active Operating Current OVDD 200MHz Active Operating Current OVDD 266MHz Active Operating Current AVDD Active Operating Power 133MHz Active Operating Power 200MHz Active Operating Power 266MHz Symbol IODD IODD IODD IADD Minimum Typical 1074 Maximum 1183 Unit
2.91
Notes: Maximum power characterized VDD=2.7V, OVDD=3.6V, across silicon process (worse case best case), while running application designed maximize power consumption. maximum power values measured with following clock rate combinations: CPU=133.33MHz, PLB=66.66MHz, OPB=66.66MHz, EBC=33.33MHz, PCI=33.33MHz CPU=200 MHz, PLB=100MHz, OPB=50MHz, EBC=50MHz, PCI=33.33MHz CPU=266.66MHz, PLB=133.33MHz, OPB=66.66MHz, EBC=66.66MHz, PCI=33.33MHz
TEST CONDITIONS
Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized OVDD 3.00V 85°C with 50pF test load shown figure right.
Output 50pF
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
CLOCKING SPECIFICATIONS
Table Clocking Specifications
Symbol SysClk Input SysClk clock input frequency SysClk clock period Clock edge stability (phase jitter, cycle cycle) Clock input high time Clock input time nominal period nominal period 66.66 0.15 nominal period nominal period Parameter Units
Note: Input slew rate 2V/ns
MemClkOut Output Other Clocks frequency frequency-133MHz frequency-200MHz frequency-266MHz frequency-133MHz frequency-200MHz frequency-266MHz 66.66 133.33
MemClkOut clock output frequency-133MHz MemClkOut clock period-133MHz MemClkOut clock output frequency-200MHz MemClkOut clock period-200MHz MemClkOut clock output frequency-266MHz MemClkOut clock period-266MHz Clock output high time Clock output time nominal period nominal period
66.66
133.33
nominal period nominal period
Notes: HDLCEX used, maximum frequency 66.66MHz.
CLOCKING WAVEFORM
Figure Clocking Waveform
2.0V 1.5V 0.8V
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
SPREAD SPECTRUM CLOCKING
Care must taken when using spread spectrum clock generator (SSCG) with NPe405H. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with NPe405H following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating NPe405H with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board NPe405H peripherals impose more stringent requirements (see Note peripheral clock (PerClk) logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation.
Please refer application note Using Spread Spectrum Clock Generator with PowerPC 405GP additional details. This application note available AMCC site http://www.amcc.com. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. external serial clock used baud rate unaffected modulation. Ethernet operation unaffected. operation unaffected. clock specification 66MHz allows maximum frequency deviation modulation between 30kHz 33kHz. asynchronous mode unaffected. Caution: system designer ensure that SSCG used with NPe405H meets above requirements does adversely affect other aspects system.
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
PERIPHERAL INTERFACE CLOCK TIMINGS
Table Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk input high time PCIClk input time EMC0MDClk output frequency EMC0MDClk period EMC0MDClk output high time EMC0MDClk output time PHY0TxClk input frequency PHY0TxClk period PHY0TxClk input high time PHY0TxClk input time PHY0RxClk input frequency PHY0RxClk period PHY0RxClk input high time PHY0RxClk input time PerClk output frequency-133MHz PerClk period-133MHz PerClk output frequency-200MHz PerClk period-200MHz PerClk output frequency-266MHz) PerClk period-266MHz PerClk output high time PerClk output time UARTSerClk input frequency (Note UARTSerClk period UARTSerClk input high time UARTSerClk input time TmrClk input frequency-133MHz TmrClk period-133MHz TmrClk input frequency-200MHz TmrClk period-200MHz TmrClk input frequency-266MHz TmrClk period-266MHz TmrClk input high time TmrClk input time HDLCEXTxClk, HDLCEXRxClk HDLCMPTxClk, HDLCMPRxClk Note nominal period nominal period nominal period nominal period nominal period nominal period nominal period nominal period 2TOPB TOPB TOPB nominal period nominal period Note nominal period nominal period 33.33 66.66 nominal period nominal period 1000/(2TOPB 2ns) 33.33 66.66 nominal period nominal period 8.192 2.048 Units
Notes: TOPB period clock. maximum clock frequency 33.33 133MHz parts, 200MHz parts, 66.66MHz 266MHz parts. asynchronous mode minimum PCIClk frequency Clock. Refer NPe405H User's Manual more information.
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
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Data Sheet
INPUT SETUP HOLD WAVEFORM
Figure Input Setup Hold Waveform
Clock
Inputs Valid
OUTPUT DELAY FLOAT TIMING WAVEFORM
Figure Output Delay Float Timing Waveform
Clock
Outputs
High (Drive) Float (High-Z) Valid (Drive) Valid
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
SPECIFICATIONS-ALL
Table Specifications-All (Sheet
Notes: timings asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz.
Input (ns) Signal Setup Time (TIS min) async async async async async async async async async async async async async async Hold Time (TIH min) async async async async async async async async async async async async async async Output (ns) Valid Delay (TOV max) async async async async async async async async Hold Time (TOH min) async async async async async async async async Output Current (mA) (maximum) (minimum) PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk Clock Notes
Interface
PCIAD00:31 PCIC0:3[BE3:0] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1:5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY PCIClk PCIClk async async
Internal Peripheral Interface
IICSCL IICSDA [UART0_CTS] [UART0_DCD] [UART0_DSR] [UART0_DTR] [UART0_RI] [UART0_RTS] UART0_Rx UART0_Tx [UART1_CTS] [UART1_DCD] [UART1_DSR] [UART1_DTR] [UART1_RI] [UART1_RTS] UART1_Rx UART1_Tx UARTSerClk
Interrupts Interface
[IRQ0:6]
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Specifications-All (Sheet
Notes: timings asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz.
Input (ns) Signal JTAG Interface TRST async async async async async async async async async async async async async async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (maximum) (minimum) Clock Notes
System Interface
GPIO0:1 Halt SysClk SysErr SysReset TestEn TmrClk
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
SPECIFICATIONS(A)-133
Table Specifications-133 200MHz (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative MemClkOut terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405H package pin. System designers must NPe405H IBIS model (available from www.amcc.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Ethernet Interface EMC0MDClk EMC0MDIO EMC0TxD0:3 [EMC0Tx0:1D0:1] [EMC0Tx0:3D] EMC0TxEn [EMC0Tx0En] [EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC1TxD0][EMC1Tx2D0] [EMC1TxD1][EMC1Tx2D1] [EMC1TxD2][EMC1Tx3D0] [EMC1TxD3][EMC1Tx3D1] [EMC1TxEn][EMC1Tx2En] [EMC1TxErr][EMC1Tx3En] PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] PHY0RxClk PHY0RxD0:3 [PHY0Rx0:1D0:1] [PHY0Rx0:3D] PHY0RxDV[PHY0CRS1DV] PHY0RxErr[PHY0Rx0Er] PHY0TxClk[PHY0RefClk] [PHY1RxD0][PHY1Rx2D0] [PHY1RxD1][PHY1Rx2D1] [PHY1RxD2][PHY1Rx3D0] [PHY1RxD3][PHY1Rx3D1] [PHY1Col][PHY1Rx3Er] [PHY1CrS][PHY1CrS2DV] [PHY1RxClk] [PHY1RxDV] [PHY1CrS3DV] [PHY1RxErr][PHY1Rx2Er] [PHY1TxClk] HDLCEX Interface HDLCEXRxClk HDLCEXRxDataA:B HDLCEXRxFS 27.7 24.2 EMC0MDClk PHYTX async clock Clock period 10ns period 12.4 14.4 13.6[7.1] [15.0][8.2] [15.0][8.3] [15.1][8.2] [15.0][8.2] [16.4][8.2] [16.5][8.3] 4.0[2.4] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (maximum) (minimum) Clock Notes
async[1.1] async[1.0] 1.5[1.0] 1.5[1.1] [1.0][1.8] [1.3][2.2] [1.1][2.2] [1.0][1.9] [1.4][2.2] [1.3][2.1] [1.0] [2.1] [1.0][1.9]
async[0.9] async[1.3] 1.7[1.1] 1.6[1.0] [3.5][0.7] [3.0][0.3] [3.0][0.3] [3.3][0.7] [2.2][0.3] [2.6][0.8] [2.6] [0.0] [3.2][0.6]
PHYTX PHYTX
async PHYRX PHYRX PHYRX async
DS2011
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NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Specifications-133 200MHz (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative MemClkOut terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405H package pin. System designers must NPe405H IBIS model (available from www.amcc.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal HDLCEXTxClk HDLCEXTxDataA:B HDLCEXTxFS [HDLCEXTxEnA:B] HDLCMP Interface HDLCMPTxClk0:3 [HDLCMPTxClk4:7] HDLCMPTxData0:3 [HDLCMPTxData4] [HDLCMPTxData5] [HDLCMPTxData6] [HDLCMPTxData7] [HDLCMPTxEn0] [HDLCMPTxEn1] [HDLCMPTxEn2] [HDLCMPTxEn3] [HDLCMPTxEn4] [HDLCMPTxEn5] [HDLCMPTxEn6] [HDLCMPTxEn7] HDLCMPRxClk0:3 [HDLCMPRxClk4:7] HDLCMPRxData0:3 [HDLCMPRxData4] [HDLCMPRxData5] [HDLCMPRxData6] [HDLCMPRxData7] Trace Interface [TrcClk] [TS1E] [TS2E] [TS1O] [TS2O] [TS3:4] [12.2] [7.2] [7.2] [7.2] [7.2] [7.2] [2.5] [2.0] [2.0] [2.0] [2.0] [2.0] 22.8 [24.9] [24.7] [24.6] [24.8] [0.1] [0.1] [0.1] [0.1] [9.9] [9.8] [9.8] [9.8] [10.0] [9.9] [9.4] [9.5] [9.9] [9.8] [9.8] [9.9] [3.3] [2.8] [3.0] [3.0] [2.9] [2.9] [2.9] [2.9] [3.3] [2.8] [3.0] [3.0] Setup Time (TIS min) 24.4 Hold Time (TIH min) Output (ns) Valid Delay (TOV max) 10.5 Hold Time (TOH min) Output Current (mA) (maximum) (minimum) Clock Notes
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Specifications-133 200MHz (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative MemClkOut terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405H package pin. System designers must NPe405H IBIS model (available from www.amcc.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal SDRAM Interface BA1:0 BankSel3:0 ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:00 MemData00:31 [DMAReq0:3] [DMAAck0:3] [EOT0:3/TC0:3] PerAddr04:31 PerBLast PerCS0 [PerCS1:7] PerData00:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 PerClk PerErr BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq EEPROM Controller IECSCL IECSDA async async async async async async async async [4.7] [4.5] [0.0] [0.0] [8.5] [8.6] [8.7] -0.6 [1.0] [1.0] [1.0] -0.7 MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (maximum) (minimum) Clock Notes
External Slave Peripheral Interface
External Master Peripheral Interface
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
SPECIFICATIONS(A)-266
Table Specifications-266MHz (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative MemClkOut terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405H package pin. System designers must NPe405H IBIS model (available from www.amcc.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (maximum) (minimum) EMC0MDClk PHYTX Clock Notes
Ethernet Interface
EMC0MDClk EMC0MDIO EMC0TxD0:3 [EMC0Tx0:1D0:1] [EMC0Tx0:3D] EMC0TxEn [EMC0Tx0En] [EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC1TxD0][EMC1Tx2D0] [EMC1TxD1][EMC1Tx2D1] [EMC1TxD2][EMC1Tx3D0] [EMC1TxD3][EMC1Tx3D1] [EMC1TxEn][EMC1Tx2En] [EMC1TxErr][EMC1Tx3En] PHY0Col[PHY0Rx1Er]l PHY0CrS[PHY0CrS0DV] PHY0RxClk PHY0RxD0:3 [PHY0Rx0:1D0:1] [PHY0Rx0:3D] PHY0RxDV[PHY0CRS1DV] PHY0RxErr[PHY0Rx0Er] PHY0TxClk[PHY0RefClk] [PHY1RxD0][PHY1Rx2D0] [PHY1RxD1][PHY1Rx2D1] [PHY1RxD2][PHY1Rx3D0] [PHY1RxD3][PHY1Rx3D1] [PHY1Col][PHY1Rx3Er] [PHY1CrS][PHY1CrS2DV] [PHY1RxClk] [PHY1RxDV] [PHY1CrS3DV] [PHY1RxErr][PHY1Rx2Er] [PHY1TxClk] async clock clock period +10ns period [5.3] [4.6] 11.4 [5.2] [4.6] 10.8[5.4] [11.3[6.5] [10.9][6.1] [10.9][6.1] [11.4][6.5] [12.7][6.2] [12.7][6.0] [2.3] [1.5] [2.3] [1.5] 4.0[2.3] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5] [4.8][2.5]]
async[1.0] async[1.0] [1.1] [1.1] 1.5[1.1] 1.5[1.1] [1.0][1.5] [1.2][1.8] [1.1][1.8] [0.9][1.5] [1.4[2.0] [1.3][1.9] [1.8] [1.0][1.6] 25.6 24.2
async[0.7] async[0.9] [0.7] [0.1] 1.2[0.8] 1.2[0.8] [2.6][0.5] [2.2][0.3] [2.2][0.3] [2.5][0.5] [1.5][0.2] [1.8][0.5] [0.1] [2.4][0.4]
PHYTX PHYTX
async PHYRX PHYRX PHYRX async
HDLCEX Interface
HDLCEXRxClk HDLCEXRxDataA:B HDLCEXRxFS AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Specifications-266MHz (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative MemClkOut terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405H package pin. System designers must NPe405H IBIS model (available from www.amcc.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal HDLCEXTxClk HDLCEXTxDataA:B HDLCEXTxFS [HDLCEXTxEnA:B] Setup Time (TIS min) 24.3 21.1 [24.8] [24.7] [24.7] [24.8] Hold Time (TIH min) [0.1] [0.1] [0.1] [0.1] Output (ns) Valid Delay (TOV max) [7.4] [7.5] [7.4] [7.3] [7.4] [7.4] [7.5] [7.8] [7.4] [7.4] [9.5] [5.9] [5.9] [5.9] [5.9] [5.9] Hold Time (TOH min) [3.2] [3.2] [2.9] [3.0] [3.0] [2.8] [3.2] [3.1] [3.0] [3.0] [2.5] [2.0] [2.0] [2.0] [2.0] [2.0] Output Current (mA) (maximum) (minimum) Clock Notes
HDLCMP Interface
HDLCMPTxClk0:3 [HDLCMPTxClk4:7] HDLCMPTxData0:3 [HDLCMPTxData4] [HDLCMPTxData5] [HDLCMPTxData6] [HDLCMPTxData7] [HDLCMPTxEn0:3] [HDLCMPTxEn4] [HDLCMPTxEn5] [HDLCMPTxEn6] [HDLCMPTxEn7] HDLCMPRxClk0:3 [HDLCMPRxClk4:7] HDLCMPRxData0:3 [HDLCMPRxData4] [HDLCMPRxData5] [HDLCMPRxData6] [HDLCMPRxData7]
Trace Interface
[TrcClk] [TS1E] [TS2E] [TS1O] [TS2O] [TS3:6]
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Table Specifications-266MHz (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative MemClkOut terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405H package pin. System designers must NPe405H IBIS model (available from www.amcc.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Setup Time (TIS min) [3.8] [3.5] async async Hold Time (TIH min) [0.0] [0.0] async async Output (ns) Valid Delay (TOV max) [6.1] [6.4] [7.1] async async Hold Time (TOH min) [1.0] [1.0] [1.0] async async Output Current (mA) (maximum) (minimum) Clock Notes
SDRAM Interface
BA1:0 BankSel3:0 ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:00 MemData00:31 [DMAReq0:3] [DMAAck0:3] [EOT0:3/TC0:3] PerAddr04:31 PerBLast PerCS0 [PerCS1:7] PerData00:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 PerClk PerErr BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
External Slave Peripheral Interface
External Master Peripheral Interface
EEPROM Controller
IECSCL IECSDA
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
INITIALIZATION
following describes method which initial chip settings established when system reset occurs. Strapping While SysReset input (system reset), state certain pins read enable default initial conditions prior NPe405H start-up. actual capture instant nearest SysClk edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. recommended pull-up +3.3V recommended pulldown GND.These pins used strap functions only during reset. They used other signals during normal operation. following table lists strapping pins along with their functions strapping options.
STRAPPING ASSIGNMENTS
Table Strapping Assignments
Function SEPROMPresent Serial EEPROM connection interface connected Connected Option Ball Strapping AJ33 (UART1_Tx) (HoldAck) (ExtAck)
When SEPROMPresent these pins highorder bits EEPROM base address. When SEPROMPresent these pins indicated width boot ROM.
High order EEPROM base address bits bits bits bits reserved
EEPROM During reset, configuration values other than those obtained from strapping pins read from serial EEPROM connected port. association bits EEPROM with configuration values their default values covered detail PowerNP NPe405H Network Processor User's Manual. Caution: SEPROMPresent strapped EEPROM connected defective, NPe405H will boot
DS2011
AMCC Proprietary
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
DOCUMENT REVISION HISTORY
Revision 1.02 1.01 1.00 Date 11/16/07 04/18/07 07/29/04 Description Page Updated Ordering, PVR, JTAG Information Table, also included update footnote. Page Updated AMCC Part Number Block. Updated SDRAM MDIO timing Tables Initial Release
AMCC Proprietary
DS2011
NPe405H PowerNP NPe405H Embedded Processor
Revision 1.02 November 2007
Data Sheet
Applied Micro Circuits Corporation 6310 Sequence Dr., Diego, 92121 Main Phone: (858) 450-9333 Technical Support Phone: (858) 535-6517 (800) 840-6055 http://www.amcc.com (support@amcc.com)
AMCC reserves right make changes products, datasheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available datasheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered Trademark Applied Micro Circuits Corporation. Copyright 2007 Applied Micro Circuits Corporation.
DS2011
AMCC Proprietary
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