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APC58120 COMPRESS VOICE Introduction APC58120 speech-melody


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INTEGRATED CIRCUITS INC.-APC58120
APC58120 COMPRESS VOICE
Introduction
APC58120 speech-melody chip. APC58120 provides 10-bit converter driving speaker directly. only function active same time. Besides, general voice music decompression rate provided embedded decompression engine 14.4k bit/sec maximum 3.6k bit/sec minimum, while high-quality music decompression rate given engine bit/sec maximum bit/sec minimum.
Features
Power supply 2.4V~3.6V(For battery application) 24bit instruction Data Built-in Built-in oscillator Timer Timer Watchdog Timer Port Port 8-level stacks program counter 24-bit instructions 16-bit data interrupt Timer_ Timer_ Timer_ Timer_ PA_INT
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Memory mapping
Address 30H~3FFH
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Register INDirect addressing register IND0 Memory Index Register (MIR0) INDirect addressing register IND1 Memory Index Register (MIR1) Program register(PC) Status Flag Register Timer_A Timer_B Timer_C Timer_D register register register register Port data Register Port Control register Port data Register Port Control register Watchdog Timer Control Register Interrupt Flag Register(IFR) Control register PortA Interrupt control register PortA Pull High register PortB Pull High register PortA Pull Down register PortB Pull Down register PortA edge Control register Table Pointer Register High Word Table Pointer Register Word Data Pointer Register High Word Data Pointer Register Word Other register register PLLSEL register
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assignment
Symbol IO_VSS CORE_VSS CORE_VDD IO_VDD PA0~PA15 PB0~PB7 IO_VDD CORE_VDD CORE_VSS IO_VSS OSC1 OSC2 TESTMODE ERSTB XT_RC_SEL DAC_VDD DAC_VSS DACO PWMVDD PWM1O PWMVSS PWM2O PWMVDD ANA_VDD ANA_VSS PLLCAP Description Oscillator resistor input Ground Ground CORE LOGIC Power CORE LOGIC Power port port Power Power CORE LOGIC Ground CORE LOGIC Ground Crystal input Crystal Output test only Chip Reset Crystal oscillator select Power Ground output Output Output Power Analog Circuit Ground Analog Circuit input
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5.Function Control Registers:
Address Name IND0[9:0] MIR0[9:0] IND1[9:0] MIR1[9:0] SFR[7:0] Timer_A Timer_B Timer_C Timer_D TCA[7:0] TCB[7:0] TCC[7:0] TCD[7:0] RPA[15:0] CPA[15:0] RPB[7:0] CPB[7:0] WTC[7:0] IFR[7:0] IFR[15:8] PLLC[5:0] IPA[7:0] PADC TDPTRH[16] TDPTRL DPTRH DPTRL Bit15/ Bit14/ Bit13/ Bit12/ Bit11/ Bit10/ Bit9/ Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 contents MIR0 address data memory (not physical register) Indirect data memory address pointer contents MIR1 address data memory (not physical register) Indirect data memory address pointer Program Counter register Ponrst bits real timer clock/counter bits real timer clock/counter bits real timer clock/counter Timer TACK TAPRE TAEI TAEN TAPS2 TAPS1 TBCK TBPRE TBEI TBEN TBPS2 TBPS1 TCCK TCPRE TCEI TCEN TCPS2 TCPS1 TDEI TDEN TDPS2 TDPS1 Port data Register Port Control register Port data Register Port Control register WTPS WTPS Timer_ Timer_ Timer_ PortA7 PortA6 PortA5 PortA4 PortA3 PortA2 PortA1 PWME DACE PLLCl PLLEN ksel1 PortA Interrupt control register PortA Pull High register PortB Pull High register PortA Pull Down register PortB Pull Down register PortA Edge Control register Table Pointer Register High Word Table Pointer Register Word Data Pointer Register High Word Data Pointer Register Word Result multiplier high word Result multiplier word Channel register Channel register Bit8/ Bit0
TAPS0 TBPS0 TCPS0 TDPS0
WTPS Timer_ PortA0 PLLCl ksel0
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23h[7:0] 23h[11:8] PLLSEL
TMRB TMRA C1ALP C0ALP LVDSE OVPA OVPA ASSEN ASSEN SSEN SSEN LVDE Config _wtc1 Config _wtc0
pwmdo PWMD DACD MIX1s MIX0s REG1 REG2 usel atasel atasel Index Register pllbypa PLLsel sssel
Special registers
1)00H [9:0] <IND0> Indirect address register 0{RW}
Description: serving physical register,the register used indirect address register. Reading writing this address will have access register address defined 01H(MIR0).
2)01H [9:0] <MIR0> Memory Index register 0{RW}
[9:0] indicate that this register used indirect addressing mode defines which register will select during instruction read/write
3)02H [9:0] <IND1> Indirect address register 1{RW}
Description: serving physical register,the register used indirect address register. Reading writing this address will have access register address defined 03H(MIR1).
4)03H [9:0] <MIR1> Memory Index register 1{RW}
[9:0] indicate that this register used indirect addressing mode defines which register will select during instruction read/write
<PC> Program Counter register 6)05H [5:0] <SFR> Status Flag register
Carry Flag <AC>Auxiliary Flag Zero Flag <SP> Sleep Flag <WT> Watchdog Flag <Ponrst> ponrst Flag
7)06H [15:0] <Timer_ Timer/Counter register {RW} 8)07H [15:0] <Timer_ Timer/Counter register {RW} 9)08H [15:0] <Timer_ Timer/Counter register {RW} 10)09H [15:0] <Timer_ Timer
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11)0AH [7:0] <TCA> Timer/Counter Control register{RW}
[2:0] TAPS2, TAPS1, TAPS0> Timer prescaler TAPS2 TAPS1 TAPS0 rate 1:16 1:32 1:64 1:128 1:256
<TAPREEN> 0:Timer Prescaler Disable Prescale Rate 1:Timer Prescaler Enable(default) <TACKSEL> select system clock(default) select crystal clock(32768) [6]< TAEN> Timer/Counter Enable control Timer/Counter disable(default) Timer/Counter enable [7]<TAEI> Timer/Counter Interrupt Enable control Timer/Counter interrupt disable(default) Timer/Counter interrupt enable
12)0BH [7:0] <TCB> Timer/Counter Control register{RW}
[2:0] TBPS2, TBPS1, TBPS0> Timer prescaler TBS2 TBS1 TBS0 rate 1:16 1:32 1:64 1:128 1:256
<TBPREEN> 0:Timer Prescaler Disable Prescale Rate 1:Timer BPrescaler Enable(default) <TBCKSEL> select system clock(default) select crystal clock(32768) [6]< TBEN> Timer/Couner Enable control Timer/Counter disable(default) Timer/Counter enable [7]<TBEI> Timer/Counter Interrupt Enable control Timer/Counter interrupt disable(default) Timer/Counter interrupt enable
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[7:0] <TCC> Timer/Counter Control register{RW}
[2:0] TCPS2, TCPS1, TCPS0> Timer prescaler TCS2 TCS1 TCS0 rate 1:16 1:32 1:64 1:128 1:256
<TCPREEN> 0:Timer Prescaler Disable Prescale Rate 1:Timer Prescaler Enable(default) <TCCKSEL> select system clock(default) select crystal clock(32768) [6]< TCEN> Timer/Counter Enable control Timer/Counter disable(default) Timer/Counter enable [7]<TCEI> Timer/Counter Interrupt Enable control Timer/Counter interrupt disable(default) Timer/Counter interrupt enable
[7:0] <TCD> Timer/Counter Control register{RW}
[2:0] TDPS2, TDPS1, TDPS0> Timer prescaler TDS2 TDS1 TDS0 rate 0.5Hz 16Hz 32Hz 64Hz
[6]< TDEN> Timer/Counter Enable control Timer/Counter disable(default) Timer/Counter enable [7]<TDEI> Timer/Counter Interrupt Enable control Timer/Counter interrupt disable(default) Timer/Counter interrupt enable
[15:0] <RPA> Port data Register{RW}
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[15:0] <CPA> Port Control register{RW}
output input(default)
[7:0] <RPB> Port data Register{RW} [7:0] <CPB> Port Control register{RW}
output input(default)
[2:0] <WTC> Watchdog control register{RW}
[2:0] WTPSC2,WTPSC1,WTPSC0> WTPSC2 WTPSC2 WTPSC1 WTPSC1 WTPSC0 WTPSC0 rate 1:16 1:32 1:64 1:128 Rate 22ms 44ms 88ms 176ms 352ms 704ms 1408ms 2816ms
<IFR> Interrupt Flag register{RW}
[0]< Timer_ Timer/Counter Flag register [1]< Timer_ Timer/Counter Flag register [2]< Timer_ Timer/Counter Flag register [3]< Timer_ Timer/Counter Flag register PortA0F> Port Flag register PortA1F> Port Flag register [10] PortA2F> Port Flag register [11] PortA3F> Port Flag register [12] PortA4F> Port Flag register [13] PortA5F> Port Flag register [15] PortA7F> Port Flag register
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<PLLC> Control register
[1:0] PLLClksel1, PLLClksel0> 24Mhz(default) 32Mhz 40Mhz 48MHz <PLLEN> disable enable (default) <DACEN> enable register 0:disable (default) 1:enable <PWMEN> enable register 0:disable (default) 1:enable
[7:0] <IPA> Port Interrupt control register {RW}
disable Port Interrupt(default) 1:enable Port Interrupt
[15:0] <PHA> Port Pull High register {RW}
pull high (default) pull high
[7:0] <PHB> Port Pull High register {RW}
pull high (default) pull high
[15:0] <PDA> Port Pull Down register {RW}
pull down (default) pull down
[7:0] <PDB> Port Pull Down register {RW}
pull down (default) pull down
[15:0] <PADC>Port Edge Control register{RW}
[7:0] Port interrupt happen when positive edge occur [15:8] Port interrupt happen when negative edge occur
<TDPTRH> Table Pointer Register High Word {RW} <TDPTRL> Table Pointer Register Word {RW} [15:0] <DPTRH> Data Pointer Register High Word {RW} [15:0] <DPTRL> Data Pointer Register Word {RW} [15:0] <M1> Result multiplier high word {RW} [15:0] <M0> Result multiplier word {RW} [15:6] <C1> Channel data register {RW}
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[15:6] <C0> Channel data register {RW} [11:0] OTHER register
[1:0] <CONFIG_wtc1,CONFIG_wtc0> watchdog timer disabled time watchdog timer disabled during sleep stand-by mode watchdog timer enabled time (default) [2]<LVDEN> Voltage reset enable disable(default) enable [3]<LVDSEL> Voltage reset voltage select Lower 1.4~1.8V(default) Higher 2.1~2.8V [4]<C0ALPASSEN> register Pass temp0 register {see figure 0:whether pass controlled Timer (default) 1:always pass [5]< TMRAOVPASSEN Timer overflow signal pass enable 0:disable (default) 1:enable [6]<C1PASSEN> register Pass temp1 register {see figure 0:whether pass controlled Timer (default) 1:always pass [7]<TMRBOVPASSEN>Timer overflow signal pass enable 0:disable (default) 1:enable [8]<MIX0sel> select channel data mixed data 0:select channel Data (default) select Data [9]<MIX1sel> select channel data mixed data 0:select channel Data(default) select Data [10]<DACDatasel> select MUX0 data MUX1 data 0:select MUX0 Data(default) select MUX1 Data [11]<PWMDatasel> select MUX0 data MUX1 data 0:select MUX0 Data(default) select MUX1 Data [13:12] REG[1:0] They unused [14] pwmdousel 0:select order modulator 1:select order modulator(default)
24H[10:0] Index Register 25H[0]
<PLLsel> System Clock PLL(default) System Clock 32768Hz [1]< pllbypasssel> select clock(default) select clock
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Special Register Condition
Registers 01H(MIR0) 03H(MIR1) 04H(PC) 05H(SFR) 06H(TIMER_A) 07H(TIMER_B) 08H(TIMER_C) 09H(TIMER_D) 0AH(TCA) 0BH(TCB) 0CH(TCC) 0DH(TCD) 0EH(RPA) 0FH(CPA) 10H(RPB) 11H(CPB) 12H(WTC) 13H(IFR) 14H(PLLC) 15H(IPA) 16H(PHA) 17H(PHB) 18H(PDA) 19H(PDB) 1AH(PADC) 1BH(TDPTRH) 1CH(TDPTRL) 1DH(DPTRH) 1EH(DPTRL) 1FH(M1) 20H(M0) 21H(C1) 22H(C0) 23H(OTH) 24H(PIR) 25H(PLLSEL) Power-on/External Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1xxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 -111 0001 -111 0001 -111 -111 xxxx xxxx xxxx xxxx 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 1111 1111 -111 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -0000 0000 1000 0000 0011 0000 0000 0000 0000 Watchdog reset uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 1uuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 -111 0001 -111 0001 -111 -111 uuuu uuuu uuuu uuuu 1111 1111 1111 1111 uuuu uuuu uuuu uuuu 1111 1111 -111 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -0000 0000 1000 0000 0011 0000 0000 0000 0000
x:unknown u:unchanged ?:conditional color means only controlled power reset
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Figure system
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Instruction
Binary Code 00000000 0000000000000000 00001111 11111110 000nnnnn 00001111 11111111 000nnnnn 00001111 11111110 001nnnnn Syntax SHLM Operation None M1M0 bitM1M0 sign M1M0[31] M1M0[n-1:0] M1M0 bitM1M0 sign M1M0[31] sign M1M0[31:31-n] M1M0 bitM1M0 {SATURATION} sign M1M0[31] M1M0[n-1:0] M1M0 bitM1M0 {SATURATION} sign M1M0[31] signM1M0[31:31-n] Stop Clock Stop StackPC StackPC PC+A (TDPTR[31:0])(Byte mode)A (TDPTR[31:0])(Byte mode)A tdptr+=1 (TDPTR[31:0])A (TDPTR[31:0])A,tdptr+=1 (DPTR[31:0])A (DPTR[31:0])A,dptr+=1 i*AM1M0 M1M0 SP=0 SP=0 None None None None None Status Affected None None
SHRM
None
SHSLM
None
00001111 11111111 001nnnnn 00001111 11111111 11110110 00001111 11111111 11110111 00001111 11111111 11111000 00001111 11111111 11111001 00001111 11111111 11111010 00001111 11111111 11111011 00001111 11111111 11110100 00001111 11111111 11110101 00001111 11111111 11111100 00001111 11111111 11111101 00001111 11111111 11111110 00001111 11111111 11111111 00010000 iiiiiiii iiiiiiii 00010001 rrrrrrrr rrrrrrrr
SHSRM
None
CLRWT STDBY SLEEP RETI SKIPA TLBDA TLBPA TLDDA TLDPA LDDA LDPA MULIA MULAR
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00010010 rrrrrrrr rrrrrrrr 00010011 rrrrrrrr rrrrrrrr 00010100 rrrrrrrr rrrrrrrr 00010101 rrrrrrrr rrrrrrrr 00010110 rrrrrrrr rrrrrrrr 00010111 iiiiiiii iiiiiiii 00011000 rrrrrrrr rrrrrrrr 0001101d rrrrrrrr rrrrrrrr 0001110d rrrrrrrr rrrrrrrr 0010dnnn nrrrrrrr rrrrrrrr 0011dnnn nrrrrrrr rrrrrrrr 0100dnnn nrrrrrrr rrrrrrrr 0101dnnn nrrrrrrr rrrrrrrr 1000bbbb rrrrrrrr rrrrrrrr 1001bbbb rrrrrrrr rrrrrrrr 1010bbbb rrrrrrrr rrrrrrrr 1011bbbb rrrrrrrr rrrrrrrr 1100000d rrrrrrrr rrrrrrrr 1100001d rrrrrrrr rrrrrrrr 1100010d rrrrrrrr rrrrrrrr 1100011d rrrrrrrr rrrrrrrr 1100100d rrrrrrrr rrrrrrrr 1100101d rrrrrrrr rrrrrrrr 1100110d
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MULSAR CMPAR STAR CLRR MULMR MULMI STARO LDRO SSHL r,n,d
M1M0{SATURATION} r*M1M0 ->M1M0 i*M1M0 ->M1M0 (r+PIR) (r+PIR) sign r[15] r[n-1:0] signr[15] signr[15:15-n] r[n-1:0] r[15:16-n] r[b] r[b] Skip r[b]=0 Skip r[b]=1 r+A+C r-A-/C .OR. .XOR.A .AND.A
None None None None
None
SSHR r,n,d r,n,d r,n,d BTRSC BTRSS ADDAR ADCAR SUBAR SBCAR IORAR XORAR ANDAR
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None None None None None None None C,AC,Z C,AC,Z C,AC,Z C,AC,Z
VER1.0
INTEGRATED CIRCUITS INC.-APC58120
rrrrrrrr rrrrrrrr 1100111d rrrrrrrr rrrrrrrr 1101000d rrrrrrrr rrrrrrrr 1101001d rrrrrrrr rrrrrrrr 1101010d rrrrrrrr rrrrrrrr 1101011d rrrrrrrr rrrrrrrr 1101100d rrrrrrrr rrrrrrrr 1101101d rrrrrrrr rrrrrrrr 1101110d rrrrrrrr rrrrrrrr 1101111d rrrrrrrr rrrrrrrr 11100010 rrrrrrrr rrrrrrrr 11101100 iiiiiiii iiiiiiii 11101101 iiiiiiii iiiiiiii 11110010 iiiiiiii iiiiiiii 11110100 iiiiiiii iiiiiiii 11110101 iiiiiiii iiiiiiii 11110110 iiiiiiii iiiiiiii 11110111 iiiiiiii iiiiiiii 11111000 iiiiiiii iiiiiiii 11111001 iiiiiiii iiiiiiii 11111010 iiiiiiii iiiiiiii 11111011 iiiiiiii iiiiiiii 11111100 iiiiiiii iiiiiiii 11111101 iiiiiiii iiiiiiii 11111110 iiiiiiii iiiiiiii COMR ADDSAR ADCSAR SUBSAR SBCSAR DECR DRSZ INCR IRSZ XCHAR CALL JUMP LDIA ADDSIA ADCSIA SUBSIA SBCSIA ADDIA ADCIA SUBIA SBCIA CMPIA IORIA XORIA d{SATURATION} r+A+C d{SATURATION} d{SATURATION} r-A-/Cd{SATURATION} d,skip Zero d,skip Zero stack,i A{SATURATION} i+A+CA{SATURATION} i-AA{SATURATION} i-A-/CA{SATURATION} i+A+C i-A-/CA .OR. .XOR.A C,AC,Z C,AC,Z C,AC,Z C,AC,Z None None None None None None C,AC,Z C,AC,Z C,AC,Z C,AC,Z C,AC,Z C,AC,Z C,AC,Z C,AC,Z
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11111111 iiiiiiii iiiiiiii Notes syntax: General register address Accumulator position Number Immediate data Destination General register Accumulator Zero flag Carry flag Auxiliary Sleep flag Reg: General register watchdog timer OR.: Inclusive XOR.: Exclusive Complement M1M0 register ANDIA .AND.A
PWM:A 10-bit built APC58120.The drive speaker directly. DAC: 10-bit current mode converter built APC58120.The input data mapping current follows. Input data(Code) Current (mA) 3/1024 3*2/1024 3*3/1024 3*4/1204 1024 3*1024/1024
Electrical Parameter
Characteristic Test Condition: 2.4V 3.6V (3.3V), (max) 75°C Parameter Operating Voltage Operating Current Power down Current Symbol IDWN Specification Unit 3.35 7.85 Test Condition 3.3V 3.3V
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INTEGRATED CIRCUITS INC.-APC58120
Characteristic Conditions 75°C, 3.3V, Name Oscillator Frequency Symbol Fcry Conditions Min. Typ. Max. Unit
APPLICATION CIRCUIT Output application
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INTEGRATED CIRCUITS INC.-APC58120
Output application
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VER1.0

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