Part APC5800M4 APC5800M2 Module size 32.8 45.6 4.5V Speaker outpu

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Part APC5800M4 APC5800M2 Module size 32.8 45.6 4.5V Speaker outpu

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COMPRESS VOICE APC5800M MODULE
Part APC5800M4 APC5800M2
Module size 32.8 45.6 4.5V Speaker output bits Compress 14.4K VOICE MUSIC
Part
7.2K
8.4K
9.6K
10.8K
13.2K
14.4K
APC5800M2 min. min. min. min. min. min. min. min. APC5800M4 min. min. min. min. min. min. min. min. 14.4 VOICE compress Part
APC5800M2 min. min. min. min. min. min. min. min. APC5800M4 min. min. min. min. min. min. min. min. MUSIC compress
http://www.aplusinc.com.tw
PAGE
VER1.3
PWM1
VDD4V5 Reset
VDD3V PWM2
PIN-19 output drive OP-AMP,but Q1,R5& must delete
ADDRESS ARRANGEMENT
0000-07FF: Internal 1Kx16 0000-1FFF: External, Non-Bank (Extramcs=1) 4Kx16
4000-7FFF: Data area bank select, BANK BANK RAM, sized with even 64M-bit C000-FFFF: system program user program 16Kx16 FFF0, FFF1: executed vector copressor FFF2, FFF3: vector FFF4, FFF5: used FFF6, FFF7: vector Timer (IRQ vector Fix_Timer Timer_A) FFF8, FFF9: vector PA[7:0] FFFA, FFFB: vector Timer_B FFFC, FFFD: vector. FFFE, FFFF: vector According priority, RES, NMI, OK_INT, ADC_INT, TIMER_INT, PA_INT, EXT_IRQ arranged.
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PAGE
VER1.3
Memory Mapping
3FE0 System Flag. Read only
used used error error Timer_A flag Timer Timer_A flag Timer_A Fix_Timer Timer (not used) (executed flag Coprocessor) (coprocessor's carry) (tone0 tone1 enabled)
3FE0 System control Write only
must -PA14 PA15 pins (default). EXTIRQ pin. (default). EXTRAMCS. (default). enabled; PA13 pin. 0-ADC disabled;PA13 pin(default). used (must used (must (PWM enabled) -(PWM disabled (default)) 1-(DAC enabled) -(DAC disabled (default))
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PAGE
VER1.3
3FE1 System Control Write only 3FE2 System control Write only
-(Timer clock selects system clock.) (Entry stand-by mode) (Timer clock selects 32.768k Hz.) (Default) stand-by mode, held. used (must will wake CPU. (Timer enabled) -(Entry sleep mode) -(Timer disabled) (Default) sleep mode, both main system clock (Timer enabled) 32768Hz will stopped, functions stopped only external interrupt (Timer disabled) (Default) 1-(Timer interrupt enabled) wake this chip. 3-2: (system clock Fxosc/2 (4.19MHz)) (Default) (Timer interrupt disabled) (Default) (system clock Fxosc/2 (8.38MHz)) (Timer enabled) (system clock Fxosc/2 (12.58MHz)) -(Timer disabled) (Default) 7-4: 0xxx (Fix-timer disabled) (System clock 32768Hz) 1000 (Fix-timer 64Hz) (System clock clock) (Default) 1001 (Fix-timer 32Hz) (Watchdog timer enabled) (Default) 1010 (Fix-timer 16Hz) (Watchdog timer disabled) 1011 (Fix-timer 8Hz) 1100 (Fix-timer 4Hz) 1101 (Fix-timer 2Hz) 1110 (Fix-timer 1Hz) 1111 (Fix-timer 0.5Hz)
3FE3 interrupt enable register Port_a[7.0]. Write only
this register will interrupt function corresponding port_a enabled. default value each `1'.
3FE4 3FE5 3FE6 3FE7 3FE8
data register Port_a[7.0]. Read write direction register Port_a[7.0]. Write only this register will corresponding port_a output. default value each zero. data register Port_b[7.0]. Write only
Clear watchdog timer. Write only watchdog timer reset will happen programmer does clear watchdog timer before watchdog timer time-out occurs.
byte voice channel Write only
2-0: Reserved. used (must 7-4: nibble byte voice channel
3FE9
high byte voice channel Write only resolution voice channel bits ($3FE9,$3FE8 bit7_4). Bank register coprocessor. Write only
3FEA 3FEB
Bank register coprocessor. Write only
Bank register 9-bit register ($3FEB bit0 $3FEA bit7-0). memory range bank from $4000 $7FFF. 7-1: Reserved.
3FEC, 3FED
Timer data tone0 generator. Read write. After timer_a enabled, timer will start count down. When timer counts zero, timer will count from initial value timer_a will happen. time elapsing (($3FED,$3FEC)+1) (Timer input clock)
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PAGE
VER1.3
3FEE 3FEF
byte data Timer Read write high byte data Timer Read write After timer_b enabled, timer will start count down. When timer counts zero, timer will count from initial value timer_b will happen. time elapsing (($3FEF,$3FEE)+1) (Timer input clock) direction register Port_a[15.8]. Write only this register will corresponding port_a output. default value each zero. data register Port_a[15.8]. Read write data register Port_b[11.8]. Write only 3-0: Port_b Reserved Bank register CPU. Write only
3FF0 3FF1 3FF2
3FF4 3FF5
bank register CPU. Write only Bank register 9-bit register ($3FF5 bit0 $3FF4 bit7-0). memory range bank from $4000 $7FFF. Reserved. (Voice0 buffer transferred port directly.) (Default) (Voice0 buffer will transferred port when timer_b happen.) Reserved. data register Port_c[7.0]. Read write data register Port_c[15.8]. Read write
3FF6 3FF7 3FF8 3FF9
direction register Port_c[7.0]. Write only this register will corresponding port_c output. default value each zero. direction register Port_c[15.8]. Write only this register will corresponding port_c output. default value each zero.
3FFA
register. Read only When timer occurs, conversion process starts circuit stops sampling begins holding until process finished. interrupt will generated when process finished.
3FFB, 3FFC, 3FFD.not used 3FFE byte Voice channel system control Write only
(Mix mode output) (Separate mode output) (Default) (Mix mode output) (Separate mode output) (Default) used (must used (must 7-4: nibble byte voice channel
3FFF
high byte voice channel Write only resolution voice channel bits ($3FFF $3FFE bit7_4). This register will transferred port while timer_b happen separate mode.
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PAGE
VER1.3

Part APC5800M4 APC5800M2 Module size 32.8 45.6 4.5V Speaker outpu

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