Divider v1.DS530 January 2006 Product Specification Introduc

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Divider v1.DS530 January 2006 Product Specification Introduc

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Divider v1.DS530 January 2006
Product Specification
Introduction
LogiCOREDivider core creates circuit fixed-point floating-point division based radix-2 non-restoring division, division repeated multiplications, respectively. Divider core supersedes Serial Divider core version 3.0, which been incorporated into this core forms fixed-point solution.
LogiCOREFacts Core Specifics
Supported Device Family
VirtexTM, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, SpartanTM-II, Spartan-IIE, Spartan-3, Spartan-3E FPGAs
LUTs Block RAMs
Resources Used
Features
Generates arithmetic division algorithms fixed-point floating-point division with operands bits wide, respectively Performs radix-2 integer division division repeated multiplications floating-point numbers Supports IEEE-754 format floating-point numbers Optional operand widths, synchronous controls, selectable latency with Xilinx CORE Generatortool v8.1i. Incorporates Xilinx Smart-IPtechnology maximum parameterization optimum implementation
Fixed point Floating point
Table Fixed-point Performance Characteristics Table Floating-point Performance Characteristics
Provided with Core
Documentation Design File Formats Constraints File Verification Data Sheet VHDL none VHDL Behavioral Model VHDL Structural (UniSim) Model Verilog Structural (UniSim) Model VHDL Wrapper Verilog Wrapper
Instantiation Template
Design Tool Requirements
Xilinx Implementation Tools Verification Simulation Synthesis 8.1i later ModelSim® 6.1a ModelSim 6.1a v8.1i higher
Support
Provided Xilinx, Inc. www.xilinx.com/support.
2006 Xilinx, Inc. rights reserved. XILINX, Xilinx logo, other designated brands included herein trademarks Xilinx, Inc. other trademarks property their respective owners. Xilinx providing this design, code, information is." providing design, code, information possible implementation this feature, application, standard, Xilinx makes representation that this implementation free from claims infringement. responsible obtaining rights require your implementation. Xilinx expressly disclaims warranty whatsoever with respect adequacy implementation, including limited warranties representations that this implementation free from claims infringement implied warranties merchantability fitness particular purpose.
DS530 January 2006 Product Specification
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Overview
Divider core selects implementation depending algorithm_type parameter. Currently, following division implementations supported: Fixed-point. Radix-2, non-restoring integer division using fixed-point operands, allowing remainder generated. Floating-point. Division repeated multiplications. Works normalized operands; effect, floating-point implementation. detailed explanation each implementation provided later section this data sheet.
Applications
Division most complex four basic arithmetic operations. Because hardware solutions correspondingly larger more complex than solutions other operations, best minimize number divisions algorithm. There many forms division implementation, which separated into broad categories: fixed-point algorithms floating-point algorithms. This core provides example each category. radix-2 non-restoring algorithm solves quotient cycle using addition subtraction. this reason, achieve very high clock speeds expense relatively high latency. However, design fully pipelined, achieve throughput division clock cycle. resulting circuit relatively large, however, throughput smaller, divisions clock parameter allows compromises throughput resource use. This algorithm naturally generates remainder, choice applications requiring remainders modulus results. repeated multiplications algorithm iterative method using successive approximations reciprocal denominator. number bits quotient solved doubles iteration, this algorithm well suited applications requiring precise results. Also, because this core makes embedded multipliers, overall resource less than that radix-2 algorithm. Again, design fully pipelined allow throughput division clock cycle. This algorithm does naturally yield remainder.
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DS530 January 2006 Product Specification
Generic VHDL Parameters
descriptions below refer generic VHDL parameters. Table defines parameters, legal values, meaning parameters VHDL generics, which broadly equivalent. c_family (string) c_xdevicefamily (string): Together, these generics identify specific FPGA device family core targeting. Table values each supported families.
Table Relationship between Target FPGA Family, c_family c_xdevicefamily
Target FPGA Family
Virtex/Virtex-E Spartan-II/Spartan-II Virtex-II Virtex-II Spartan-3 Spartan-3E Virtex-4
c_family
"virtex" "virtex" "virtex2" "virtex2p" "spartan3" "spartan3" "virtex4"
c_xdevicefamily
"virtex" "spartan2" "virtex2" "virtex2p" "spartan3" "spartan3e" "virtex4"
algorithm_type (integer): Specifies division algorithm use. choice radix-2 (fixed-point notation) division repeated multiplications (floating-point notation). signed_b (integer): unsigned operands, signed (2's complement) operands. Applies fixed-point notation only. fractional_b (integer): remainder) (has remainder). Applies fixed-point only. dividend_width (integer): (fixed). Specifies width both dividend quotient. fractional_width (integer): (fixed-point only). c_has_ce (integer): ce), (has ce). c_has_aclr (integer): ce), (has ce). c_has_sclr (integer): ce), (has ce). divclk_sel (integer): Specifies number clocks between division results fixed-point case only. higher number results lower-circuit area cost lower throughput. latency (integer): 99(float only). Specifies circuit latency terms enabled clock (ce) cycles. divisor_width (integer):2 (fixed) bias (integer): Specifies bias exponent, according IEEE-754 format. value results bias value mid-point exponent range. mantissa_width (integer): Specifies width mantissae operands (floating-point only). exponent_width (integer): Specifies width exponents operands (floating-point only).
DS530 January 2006 Product Specification
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Table Common Generic Parameters Parameter Values Generic VHDL Parameter Common Generics fixed-point division (radix-2) floating-point division ACLR ACLR SCLR SCLR SCLR overrides overrides SCLR Generic Values Description
Algorithm Type
Fixed, Float
algorithm_type
(1),2
ACLR SCLR
false, true false, true false, true SCLR_overrides _CE, CE_overrides _SCLR
c_has_ce c_has_aclr c_has_sclr
(0),1 (0),1 (0),1
SCLR/CE Priority
c_sync_enable
(0),1
Serial-divider Generics (Fixed-point) Dividend Quotient width Divisor width Remainder type Fractional width Operand sign (16) (16) remainder, fractional (16) unsigned, signed dividend_width divisor_width fractional_b fractional_width signed_b 32(16) (16) (16) Width dividend quotient (fixed only) Width divisor (fixed only) remainder, fractional Width fraction (fractional only) unsigned signed Throughput (interval between input opportunities)
Clocks division
1,2,4,8
divclk_sel
(1),2,4,8
Low-latency Generics (Floating-point) Mantissa width Exponent width Latency Bias 2^Exponent _width mantissa_width exponent_width latency bias (16) 99(1) 2^exponent_width-1 Width mantissa Width exponent Latency division Exponent bias
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DS530 January 2006 Product Specification
Feature Summary Fixed-point Solution
Divides dividend divisor provide quotient with integer fractional remainder Pipelined architecture increased throughput Pipeline reduction size versus throughput selections Dividend width from bits Divisor width from bits Fractional remainder width from bits Independent dividend, divisor fractional widths Fully synchronous design using single clock Supports unsigned two's complement signed numbers implement (reciprocal) function Fully registered outputs
Overview Fixed-point Solution
This parameterized module divides M-bit-wide variable dividend N-bit-wide variable divisor. output consists quotient either integer remainder fractional result (quotient continued past binary point). integer remainder case, result division M-bit-wide quotient with N-bit-wide integer remainder (Equation fractional case, result M-bit-wide quotient with F-bit-wide fractional remainder (Equation When both fractional signed selected, fractional result two's complement sign bit, resulting less magnitude result (Equation efficient, high-speed, parallel implementation. core configured unsigned signed data.
Dividend quotient divisor remainder Equation Integer remainder case.
FractRmd=
IntRmd*2F Divisor
Equation F-bit-wide fractional remainder unsigned case
FractRmd=
IntRmd*2( F-1) Divisor
Equation F-bit-wide fractional remainder signed case
Note that signed mode with integer remainder, sign quotient remainder correspond exactly Equation
DS530 January 2006 Product Specification
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Thus 6/-4 REMD whereas -6/4 REMD signed mode with fractional remainder, sign present both quotient remainder. example, four-bit dividend, divisor fractional remainder have: -9/4 9/-4 1/4) This corresponds (1)0111 0100 1001/1100 Giving result: Quotient 1110 Remainder 1110 -1/4) division zero, quotient, remainder, fractional results undefined. design highly pipelined. amount pipelining reduced decrease area design expense throughput. fully pipelined mode design outputs result division operation clock cycle after initial latency. design also supports options clock cycles division after initial latency, shown Table dividend divisor widths independently. width quotient equal width dividend. width integer remainder equal width divisor. fractional output, remainder width also independent dividend divisor. core will handle data ranges bits dividend, divisor fractional output. divider used implement function; that reciprocal variable this, dividend width unsigned signed data fractional mode selected. dividend input tied high within user's design.
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DS530 January 2006 Product Specification
Pinout Fixed-point Solution
fixed-point core pinout signal names shown Figure defined Table
Figure x-ref
Figure Core Pinout Diagram
Table Fixed-point Signal Pinout Signal
DIVIDEND[Dividend Width-1:0] DIVISOR[Divisor Width -1:0]
Direction
Input Input
Description
Dividend (parallel data in). Data width determined Dividend width generic parameter. Divisor (parallel data in). Data width determined Divisor width generic parameter. Clock. With exception ACLR, control data inputs captured output data formed rising clock transitions. Asynchronous Clear (ACLR). Optional input pin. control signals synchronous rising edge except ACLR. When ACLR asserted (High), core flip-flops asynchronously initialized. core remain this state until ACLR negated. Synchronous Clear (SCLR). Optional input pin. When asserted (high), core flip-flops synchronously initialized (synchronous clock). core remains this state until SCLR deasserted. When both SCLR exist, sync_enable parameter determines whether SCLR qualified whether SCLR overrides (that will clear module clock edge even deasserted). Clock Enable (CE). Optional input pin. When deasserted (low), synchronous inputs ignored core remains current state.
Input
ACLR
Input (optional)
SCLR
Input (optional)
Input (optional)
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Table Fixed-point Signal Pinout (Continued) Signal Direction Description
Ready Data (RFD). output that indicates cycle which input data sampled core. This only applicable cores where divclk_sel case divclk_sel core fully pipelined samples inputs every enabled clock rising edge; hence, will always high. Output When divclk_sel core only samples data every 2nd, enabled clock rising edge respectively. cycle which data sampled important definition latency, shown figure3. will only change enabled input) clock rising edges core that input (has_ce True). Quotient. result integer division dividend divisor (dividend divisor). width quotient equal dividend. signed operation, quotient two's complement form. Parallel data out. Data width determined dividend width generic parameter. Remainder. integer remainder integer division dividend divisor (dividend divisor) when core fractional. fractional core, this output fractional part division result. either case, core signed, output two's complement form. Integer Remainder. Result data width determined divisor width generic parameter. Fractional Remainder. Result data width determined Fractional Width generic parameter.
QUOTIENT[Dividend width-1:0]
Output
REMAINDER[n:0] REMAINDER[f:0]
Output
Following power-on reset, SCLR, ACLR, outputs QUOTIENT REMAINDER output zeroes until results appear.
Waveforms Fixed-point Solution
total latency (number clocks required first output) function width dividend. fractional output required, latency also function fractional width. clock enable selected, latency terms enabled clock cycles. When `clocks division' output indicates cycle which input data sampled (Figure therefore from when latency measured. Ready data should qualified clock enable used externally. general: Latency order integer remainder dividers Latency order fractional remainder dividers
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DS530 January 2006 Product Specification
Table provides list latency formula divider selections Figure illustrates latency defined. Latency expressed clock cycles dividers with clock enable input otherwise enabled clock cycles.
Figure x-ref
dividend divisor quot remd
latency
Figure Latency Example (Clocks Division
Table Latency Fixed-point Solution Based Divider Parameters
Signed
False False False False True True True True
Fractional
False False True True False False True True
Clks/Div
Latency
M+F+2 M+F+3 M+F+4 M+F+5
Note: M=dividend width, F=fractional remainder width.
divclk_sel parameter allows range choices throughput versus area. With divclk_sel core fully pipelined, will have maximal throughput division clock cycle, will occupy most area. divclk_sel selections reduce throughput those respective factors smaller core sizes.
DS530 January 2006 Product Specification
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Performance Characteristics Fixed-point Solution
Table defines performance characteristics cases Virtex-4, speed grade device, intended provide indication resources used achievable clock speed. Generics specified their default values.
Table Fixed-point Performance Characteristics
Divisor Width
Dividend Width
Divclk_sel
Slices used
1666
Speed (MHz)
DSP48s used
Block Memories
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DS530 January 2006 Product Specification
Feature Summary Floating-point Solution
Performs division repeated multiplications floating-point numbers Supports IEEE-754 format floating-point numbers Optional operand widths, synchronous controls, selectable latency
Overview Floating-point Solution
floating-point implementation performs division repeated multiplications. design fully pipelined maximal throughput. operands, divisor dividend, entered sign-mantissa-exponent form. single sign operand determines sign mantissa. mantissa width configurable, exponent width. bias exponent also configurable. Following IEEE754, certain combinations exponent mantissa interpreted zero, infinity (not number). result expressed same form inputs. Overflow underflow outputs given those results whose magnitudes above below (respectively) range which expressed with specified mantissa exponent widths. format number representation follows IEEE754. mantissas, both input output have implicit leading '1.' mantissa describes number range 0.5(inclusive) 1.0(not inclusive). example, number 0.75 0.11000. binary. mantissa describe this would 10000. specified width). leading indicates number range just less than 1.0. Since number representation requires this normalization leading required input since carries information. underflow overflow outputs provided show result calculation resulted exponent outside range allowed width exponent, that >2^exponent_width. Table defines special values recognized core.
Table Special Values
Exponent
'1's '1's '0's
Mantissa
'0's '0's '0's
Special Value
Number (NaN) Infinity Zero
Table defines division results involving special values described Table
Table Division Results Involving Special Values
Dividend
Value Infinity Zero value
Divisor
Value Infinity Zero Infinity
Quotient
Zero
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Table Division Results Involving Special Values (Continued)
Dividend
Value Zero Infinity
Divisor
Zero Value Value
Quotient
Infinity Zero Infinity
Pinout Floating-point Solution
floating-point core pinout signal names displayed Figure defined Table
Figure x-ref
Figure x-ref
Figure Floating-point Schematic Symbol
Table Pinout Floating-point Solution Signal
ACLR SCLR DIVIDEND _MANTISSA [Mantissa Width-1:0] DIVISOR _MANTISSA [Mantissa Width-1:0] DIVISOR_SIGN
Direction
Input Input (optional) Input (optional) Input (optional) Input Input Input
Description
Clock. Rising edge clock signal Clock Enable Asynchronous Clear Synchronous Clear Dividend mantissa Divisor mantissa Sign Divisor mantissa +ve, -ve)
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DS530 January 2006 Product Specification
Table Pinout Floating-point Solution (Continued) Signal
DIVIDEND_SIGN DIVISOR _EXPONENT [Exponent Width-1:0] DIVIDEND _EXPONENT [Exponent Width-1:0] QUOTIENT _MANTISSA [Mantissa Width-1:0] QUOTIENT_SIGN QUOTIENT _EXPONENT [Exponent Width-1:0] OVERFLOW UNDERFLOW
Direction
Input Input Input Output Output Output Output Output
Description
Sign Dividend mantissa +ve, -ve) Exponent Divisor Exponent Dividend Quotient mantissa Sign Quotient Exponent Quotient Float overflow indication Float underflow indication
Note control inputs Active High. Active input required particular control pin, inverter must placed path pin. inverter will absorbed appropriately during synthesis and/or mapping.
Waveforms Floating-point Solution
functional timing characteristics floating-point solution very simple. Because design throughput division clock cycle, handshaking signals (Ready Data, Data, output Ready) required. Latency selectable defined same manner fixedpoint solution. this reason, outputs occur following enabled rising clock edge after inputs, where latency value.
Performance Characteristics Floating-point Solution
Table defines performance characteristics cases Virtex-4, speed grade device intended provide indication resources used achievable clock speed. Generics specified their default values. Note that when core does have asynchronous clear synchronous clear, made SRL16 primitives, leading substantial reduction circuit size. this reason, SCLR ACLR recommended.
Table Floating-point Performance Characteristics
Mantissa Width
Exponent Width
Latency
26(no SCLR)
Slices used
Speed (MHz)
DSP48s used
Block Memories
DS530 January 2006 Product Specification
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Table Floating-point Performance Characteristics (Continued)
Mantissa Width
Exponent Width
Latency
26(with SCLR)
Slices used
Speed (MHz)
DSP48s used
Block Memories
Generating Core
Divider core included your design ways: Using CORE Generator graphical user interface (GUI), using direct instantiation.
Method
CORE Generator system produces several files when core generated. Instructions about instantiate core using this method automatically produced .vho file. example section .vho file provided below: following code must appear VHDL architecture header:
Begin here COMPONENT Declaration COMP_TAG component div_gen_v1_0 port clk: std_logic; .(other ports) component;
COMP_TAG_END COMPONENT Declaration following code must appear VHDL architecture body. Substitute your instance name names.
Begin here INSTANTIATION Template INST_TAG your_instance_name div_gen_v1_0 port clk, INST_TAG_END INSTANTIATION Template must compile wrapper file counter.vhd when simulating
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DS530 January 2006 Product Specification
core, counter. When compiling wrapper file, sure reference XilinxCoreLib VHDL simulation library. detailed instructions, please CORE Generator User Guide.
Method Direct Instantiation
CORE Generator allows cores directly instantiated into user code. this, following lines head your VHDL file: Library Xilinxcorelib; instantiate Divider core with appropriate values generics your local signals:
i_instance: div_gen_v1_0 generic map( c_dividend_width c_has_ce etc. port map( sclr sclr
quotient output
Note that generics need specified default value suits your application.
CORE Generator Parameter Screens
Divider core provides three screens selecting core parameters. Main screen. Describes parameters common both implementations, such SCLR allows selection divider implementation. Fixed-point implementation options. Provides configuration options fixed-point divider configuration. Note that this screen displayed only Fixed-point selected main screen. Floating-point implementation options. Provides configuration options floating-point divider configuration. Note that this screen displayed only Floating-point selected main screen.
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Main Screen
Figure x-ref
Figure Main Screen
Component Name. base name output files generated core. Names must begin with letter composed following characters: "_".
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DS530 January 2006 Product Specification
Fixed-point Implementation Options
Figure x-ref
Figure Fixed-point Implementation Options
Floating-point Implementation Options
Figure x-ref
Figure Floating-Point Implementation Options
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Verification
Divider core supplied with VHDL functional behavioral model, CORE Generator also produce UniSim-based Verilog model desired.
Simulation
When Divider core generated using CORE Generator, VHDL functional behavioral model also generated. VHDL behavioral model pre-defined, parameterized model core, which copied project directory. Verilog wrapper also provided VHDL model mixed-language simulation. Verilog model selected, CORE Generator produces UniSim-based model core. Important Note: VHDL Behavioral model provided floating-point solution does exactly reproduce behavior synthesized core. models quotients differ least significant mantissa. exact match, structural (UniSim) behavioral model must used.
References
"Computer Arithmetic Algorithms Hardware Designs," Behrooz Parhami. Oxford Press 2000.
Licensing
Divider core does require license.
Ordering Information
This core downloaded from Xilinx Center with Xilinx CORE Generator system v8.1i higher. Xilinx CORE Generator system bundled with Foundation software additional charge. inquire about other Xilinx products, contact your local Xilinx sales representative.
Support
Xilinx provides technical support this LogiCORE product when used described product documentation. Xilinx cannot guarantee timing, functionality, support product implemented devices listed documentation, customized beyond that allowed product documentation, changes made sections design marked MODIFY.
Related Information
Xilinx products intended life-support appliances, devices, systems. Xilinx product such application without written consent appropriate Xilinx officer prohibited.
Revision History
Date
1/18/06
Version
Initial Xilinx release.
Revision
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DS530 January 2006 Product Specification

Divider v1.DS530 January 2006 Product Specification Introduc

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