3-in-1 Dual Buck Linear Power Controller Provide Synchronous Rect
|
|
|
Top Searches for this datasheet
APW7116
3-in-1 Dual Buck Linear Power Controller
Provide Synchronous Rectified Buck Controllers VDDQ VMCH Integrated Power FETs with Regulator Source/Sink 2.0A Drive Cost N-Channel Power MOSFETs Internal 0.8V Reference Voltage Adjustable VDDQ VMCH Thermal Shutdown Tracks Half Reference Voltage Fixed Switching Frequency 250kHz VDDQ VMCH Over Current Protection Under Voltage Protection VDDQ VMCH Fully Complies with ACPI Power Sequencing Specifications degrees Phase Shift between VDDQ VMCH Power Okay Function VDDQ VMCH Fast Transient Response Maximum Duty Cycle High-Bandwidth Error Amplifier
General Description
APW7116 integrates Dual buck controllers internal linear regulator memory power solution. synchronous buck controllers drive four N-channel MOSFETs memory supply voltage (VDDQ) regulator. internal regulator designed track half reference voltage with sourcing sinking current memory termination regulator (VTT). APW7116 uses latched BUF_Cut signal BOOT comply with ACPI power sequencing specifications. regulators also provide signals indicate regulators good. device also phase shift function between controllers. protection functions controllers include over current protection, under voltage protection external soft-start function. regulator provides sinking sourcing current limit function also thermal shutdown protection. TSSOP-24-P package with copper provides excellent thermal impedance available.
Simple single-Loop Control Design Voltage Mode Control External Compensation
External Soft-Start VDDQ VMCH Shutdown Function VDDQ/VTT VMCH Thermally Enhanced TSSOP-24 Package Lead Free Available (RoHS Compliant)
Applications
Memory Power Supply
ANPEC reserves right make changes improve reliability manufacturability without notice, advise customers obtain latest version relevant information verify before placing orders. Copyright ANPEC Electronics Corp. Rev. Jul., 2006 www.anpec.com.tw
APW7116
Pinout
COMP1 SS1/EN1 VTTGND VDDQ AGND VTTFB REFSEN SS2/EN2 POK2 BOTTOM SIDE PHASE1 LGATE1 UGATE1 BOOT COMP2 BUF_CUT UGATE2 LGATE2 PHASE2 POK1
TSSOP-24-P VIEW
Ordering Marking Information
APW7116 Lead Free Code Handling Code Temp. Range Package Code Package Code TSSOP-24-P Operating Ambient Temp. Range Handling Code Tube Tape Reel Tray Lead Free Device Lead Free Device Blank Original Device XXXXX Date Code
APW7116
APW7116 XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials 100% matte plate termination finish; which fully compliant with RoHS compatible with both SnPb lead-free soldiering operations. ANPEC lead-free products meet exceed lead-free requirements IPC/JEDEC STD-020C classification lead-free peak reflow temperature.
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Block Diagram
BUF_CUT BOOT
11uA
UGATE1 Power Reset Logic Control Gate Control Logic LGATE1 110uA
SS1/ 11uA
SS2/ 60%VREF1 COMP1 110uA VREF1 0.8V 0.2V 0.2V
PHASE1
Comparator
PHASE2
UGATE2 VREF2 0.8V Phase Shift COMP2 60%VREF2 POK1 Comparator REFSEN 83%~90%V REF1 VDDQ POK2 83%~90%VREF2 Oscillator LGATE2 Gate Control Logic
VTTFB
AGND
VTTGND
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Absolute Maximum Ratings
Symbol VBOOT UGate Drive AGND BOOT AGND UGATE1, UGATE2 Voltage <100ns pulse width LGATE1, LGATE2 Voltage <100ns pulse width PHASE1, PHASE2 Voltage <100ns pulse width Input/Output Pins AGND Pins 1-3, 5-6, 8-14, 18-19, Output Current GND, VTTGND AGND Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10sec) Rating (VHBM) +/-2A -0.3 +0.3 +150 +150 Parameter Rating -0.3 -0.3 -0.3 VBOOT+0.3 VBOOT+2 -0.3 VCC+0.3 -0.3 -0.3 Unit
LGate Drive
PHASE
IVTT TSTG VESD
Note: Absolute Maximum Ratings those values beyond which life device impaired. Exposure absolute maximum rating conditions extended periods affect device reliability.
Recommended Operating Conditions
Symbol VBOOT VDDQ VMCH VREFSEN IVTT AGND BOOT AGND Power Input Voltage Controllers AGND VDDQ AGND VMCH AGND VREFSEN AGND Output Current Operating Junction Temperature Operating Ambient Temperature Parameter 10.8 2.97 -1.8 13.2 Unit
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Electrical Characteristics
Operating Conditions: VCC=5V, BOOT=12V, -20°C 70°C, unless Otherwise Specified.
APW7116
Symbol
Parameter
Test Conditions
Unit
SUPPLY CURRENT supply Current Mode) supply Current Mode) supply Current Mode) BOOT supply Current Mode) BOOT supply Current Mode) Mode, UGATEs, LGATEs open Mode, UGATEs, LGATEs open Mode, UGATEs, LGATEs open Mode, UGATEs, LGATEs switching Mode, UGATEs, LGATEs switching
IVCC
IBOOT
POWER-ON RESET THRESHOLD VBOOT Power-On Reset Threshold BOOT Power-On Reset Threshold Rising Falling VBOOT Rising VBOOT Falling (Note1) (Note1) 10.0 10.2 10.4
THERMAL SHUTDOWN TSDHYS Thermal Shutdown Thermal Shutdown Hysteresis Oscillator Frequency Oscillator Ramp Amplitude Duty Cycle Range (Note1) Reference Voltage Reference Voltage Accuracy Load Regulation Reference Voltage Reference Voltage Accuracy Load Regulation (Note1) -1.0 IVDDQ -1.0 IGMCH +1.0 +1.0
OSCILLATOR (PWM1 PWM2) FOSC VOSC Duty
REFERENCE VOLTAGE
VREF1
VREF2
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Electrical Characteristics (Cont.)
Operating Conditions: VCC=5V, BOOT=12V, -20°C 70°C, unless Otherwise Specified.
APW7116 Symbol Parameter Test Conditions Unit
POWER OKAY (POK1 POK2) VPOKLT VPOKHT ILKG VPOKOL Threshold High Threshold Leakage Current Voltage Open Loop Gain(Note1) Open Loop Bandwidth (Note1) Slew Rate (Note1) Output High Source Current Output Sink Current Falls VREF Reaches VREF VPOK IPOK RL=10k RL=10k GND, CL=100pF RL=10k GND, CL=100pF COMP 2.5V COMP 2.5V 0.16 V/us
ERROR AMPLIFIER (PWM1 PWM2)
PROTECTION MONITOR (PWM1 PWM2) IOCSET VOCP PHASE Source Current Reference Voltage Under Voltage Level Soft-Start Charge Current SS/EN Shutdown Threshold REGULATOR Output Voltage Load Regulation Line Regulation RREFSEN REFSEN Input Resistance VTTFB Hysteresis (Note1) ILIMVTT RDS(ON) Source Current Limit Sink Current Limit Internal Power FETs RDS(ON) Internal Soft-Start Interval (Note1) IOUT -10mA 10mA VREFSEN= 2.5V IOUT -10mA 10mA VREFSEN= 1.8V IOUT VDDQ 1.8V 2.5V (Note1) REFSEN Output Falls VREF 0.17 0.23
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Electrical Characteristics (Cont.)
APW7116 Symbol Parameter Test Conditions Unit
BUF_CUT CONTROL VBUF_CUTH BUF_CUT Input Logic High VBUF_CUTL BUF_CUT Input Logic IBUF_CUT BUF_CUT Input Current
BOOT=12V, UGATE1=2V VCC=5V, UGATE1=2V BOOT=12V, LGATE1=2V VCC=5V, LGATE1=2V BOOT=12V, UGATE2=2V VCC=5V, UGATE2=2V BOOT=12V, LGATE2=2V VCC=5V, LGATE2=2V
Gate Drivers UGATE1 Source UGATE1 Sink LGATE1 Source LGATE1 Sink UGATE2 Source UGATE2 Sink LGATE2 Source LGATE2 Sink Dead Time (Note1)
Note1: Guaranteed design, tested production.
0.45 3.45 0.675
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Application Circuit
1N4148
COMP1 VDDQ 6.8nF 2.37k 1.13k 100nF UGATE1 6.2k APM2509N PHASE1 VMCH COMP2 6.8nF 2.2k LGATE1 APM2506N 0.1uF BOOT
1N4148 1N4148 1uH/10A Filtered 5VDUAL 1.8uH 1500uF VDDQ 5VDUAL
2200uF
2200uF
4.7nF
Filtered 5VDUAL 3.3V 2.5k 100nF UGATE2 Pull High Voltage PHASE2 POK2 REFSEN POK1 LGATE2 APM2014N 4.7nF 8.1k 1000uF 1000uF APW7116 APM2014N 1.8uH VMCH 1500uF
BUF_CUT
2N7002 2N7002
SS1/EN1
VDDQ 470uF 470uF 0.1uF
SS2/EN2 0.1uF 0.1uF AGND
VTTFB VTTGND
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Descriptions
COMP1 (Pin1), COMP2 (Pin19) These pins output error amplifiers their respective regulators. They used compensation components. (Pin2), (Pin10) These pins inverting input error amplifiers their respective regulators. They used output voltage compensation components. voltage under reference voltage, because short circuit other influence, will cause under voltage protection, turn regulators. Remove error condition restart voltage, device will enable again. (Pin3), (Pin11) Connect capacitor setting soft-start time. open drain logic signal pull SS/EN disable respective output, leave open enable respective output. VTTGND (Pin4) return. Connect copper plane carrying return current. trace connecting this must able carry BUF_CUT (Pin18) (Pin5) Active high control signal activate sleep state. regulator output. VDDQ (Pin6) Power input regulator. AGND (Pin7) Analog ground. Compensation Components Soft-Start capacitors connect this ground. VTTFB (Pin8) regulation closed loop regulation. REFSEN (Pin9) Reference voltage input regulator. will
Copyright ANPEC Electronics Corp. Rev. Jul., 2006 www.anpec.com.tw
regulated this voltage. Connect point load. POK1 (Pin13), POK2 (Pin12) These pins open-drain pull-down devices. When respective falls reference voltage, output pulled low. When respective reaches reference voltage, output pulled high, power okay. PHASE1 (Pin24), PHASE (Pin14) resistor (ROCSET) connected between this drain low-side MOSFET will determine over current limit conveter. (Pin15) This power ground gate drivers. UGATE1 (Pin22), UGATE2 (Pin17) These pins provide gate drivers upper MOSFETs VDDQ VMCH. LGATE (Pin23), LGATE (Pin16) These pins provide gate drivers lower MOSFETs VDDQ VMCH.
BUF_CUT pulled internal current source. (Pin20) Power supply input pin. Connect nominal power supply this control circuit lower gate drivers. BOOT (Pin21) Upper gate drivers input supply.
APW7116
Typical Characteristics
Source Current BOOT-UGATE1 Voltage
Sink Current UGATE1 Voltage
Source Current
Sink Current
BOOT-UGATE1 Voltage
UGATE1 Voltage
Source Current VCC-LGATE1 Voltage
Sink Current LGATE1 Voltage
Source Current
Sink Current
VCC-LGATE1 Voltage
LGATE1 Voltage
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Characteristics (Cont.)
Source Current BOOT-UGATE2 Voltage
Sink Current UGATE2 Voltage
Source Current
Sink Current
BOOT-UGATE2 Voltage
UGATE2 Voltage
Source Current VCC-LGATE2 Voltage
Sink Current LGATE2 Voltage
Source Current
Sink Current
VCC-LGATE2 Voltage
LGATE2 Voltage
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Characteristics (Cont.)
Voltage Load Current
-1.5 -0.5
Voltage Temperature
Voltage (mV)
Voltage
Load Current
Temperature
OCSET Current Temperature
Switching Frequency Temperature
OCSET Current (uA)
Switching Frequency (kHz)
Temperature
Temperature
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Characteristics (Cont.)
VDDQ VMCH Power
VDDQ Power
(2V/div)
(2V/div)
VDDQ (1V/div)
VDDQ (1V/div)
VDDQ pin= VDDQ output
(2V/div)
VMCH(1V/div)
(1V/div)
Time (10ms/div)
Time (10ms/div)
VDDQ Power
Phase Shift
(2V/div)
(10V/div)
VDDQ (2V/div)
(5V/div)
BOOT (5V/div)
VDDQ pin= external supply
(10V/div)
(1V/div)
(5V/div)
Time (10ms/div)
Time (1us/div)
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Characteristics (Cont.)
Enable VDDQ
Disable VDDQ
POK1 (5V/div)
POK1 (5V/div)
VDDQ (2V/div)
VDDQ (2V/div)
(2V/div)
(10V/div)
(2V/div)
(10V/div)
Time (10ms/div)
Time (10ms/div)
Enable VMCH
Disable VMCH
POK1 (5V/div)
POK1 (5V/div)
VMCH (2V/div)
VMCH (2V/div)
(2V/div)
(10V/div)
(2V/div)
(10V/div)
Time (10ms/div)
Time (10ms/div)
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Characteristics (Cont.)
Rising
Falling
(5V/div)
(5V/div)
PHASE1 (5V/div)
PHASE1 (5V/div)
(5V/div)
(5V/div)
Time (20ns/div)
Time (20ns/div)
Rising
Falling
(5V/div)
(5V/div)
PHASE2 (5V/div)
PHASE2 (5V/div)
(5V/div)
(5V/div)
Time (20ns/div)
Time (20ns/div)
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Characteristics (Cont.)
VDDQ (2V/div)
VDDQ (2V/div)
VMCH (1V/div)
VMCH (1V/div)
(1V/div)
(1V/div)
BUF_CUT (5V/div)
BUF_CUT (5V/div)
Time (5ms/div)
Time (5ms/div)
VDDQ
VMCH
COMP1 (2V/div)
COMP2 (2V/div)
(5V/div)
(5V/div)
VREF2 (0.5V/div)
VREF1 (0.5V/div)
(10V/div)
(10V/div)
Time (20us/div)
Time (20us/div)
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Characteristics (Cont.)
VDDQ
ROCSET=6k MOSFET=APW2014
(10V/div)
VMCH
ROCSET=4k MOSFET=APW2014
(10V/div)
(5V/div)
VDDQ (2V/div)
(5V/div)
VMCH (2V/div)
(10A/div)
(10A/div)
Time (10ms/div)
Time (10ms/div)
Load Transient
VDDQ (0.1V/div)
VDDQ Load Transient
VDDQ (0.2V/div) VMCH (0.1V/div)
VMCH (0.1V/div)
VTT(0.1V/div)
VTT(0.1V/div)
outout current (2A/div)
VDDQ outout current (10A/div)
Time (20us/div)
Time (0.1ms/div)
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Typical Characteristics (Cont.)
VMCH Load Transient
VDDQ (0.1V/div)
VMCH (0.2V/div)
VTT(0.1V/div)
VMCH outout current (10A/div)
Time (0.1ms/div)
Function Description
Soft-Start/Enable VDDQ VMCH regulators have independent soft-start control shundown function. Connect capacitor from each softstart interval VDDQ VMCH open drain logic signal each SS/EN enable disable respective output. Figure1 shows soft-start interval. Boot voltoge above their trip points, 11uA current source starts charge capacitor starts internal soft-start interval. softs start interval about 500us. When reaches internal reference voltage starts rise follows Until reaches about internal reference completes soft-start interval reaches 0.8V. soft-start VMCH same VDDQ. This method provides rapid controlled output voltage rise. Figure1. Soft-Start Interval
0.5ms
TIME FB1&2 VDDQ&VMCH VOLTAGE SS1&2
(11uA)
Where: Externnal Soft-Start capacitor Soft-Start charg currrent
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Function Description (Cont.)
Power Okay Power Okay function monitors VDDQ VMCH drives indicate fault. When fault condition such over-current, short-circuit, thermal shutdown occurred, VDDQ VMCH falls nominal voltage, pulled low. When VDDQ VMCH reaches nomis voltage, pulled high. Since open-drain device, connecting resistor pull high voltage necessary. over-current never occurred normal operating load range; variation parameters above equation should determined. MOSFET RDS(ON) varied temperature gate source voltage, user should determine maximum RDS(ON) manufacturer' datasheet. minimum IOCSET (90uA), maximum Vocp (230mV) minimum OCSET should used above equation. better resistor OCSET recommended.
Note that ILIMIT current flow through
upper MOSFET; ILIMIT must greater than maximum
VOLTAGE VDDQ
output current half inductor ripple current. over current condition will repeat soft-start function times over current condition removed during times soft-star interval then regulators will shut down, require either VBOOT restart Note that parastic capacitor from PHASE
TIME
POK1
will distort PHASE signal current limit will larger than value. Reduce parastic capacitance small possible make current limit meet value.
Figure2. Power Okay Function Over Current Protection resistor (ROCSET) connected between phase drain low-side MOSFET will determine over current limit. internally generated 110uA current source will flow through this resistor, creating voltage drop. When volatge across low-side MOSFET exceeds voltage across ROCSET minus VOCP detected. function will trip peak inductor current, threshold over current limit therefore given
LIMIT
VMCH
POK1
POK2
VDDQ
OCSET IOCSET DS(ON) lower MOSFET
TIME
Figure3. VDDQ Over-Current Protection Waveforms
Copyright ANPEC Electronics Corp. Rev. Jul., 2006 www.anpec.com.tw
APW7116
Function Description (Cont.)
O.C.P. Comparator 0.2V
UGATE2
OCSET 110uA
ROCSET
VOLTAGE
UGATE1
PHASE
RDS(ON)
Figure4. Low-side Over-Current Protection Circuit Regulator regulator internal N-Channel FETs provide current sink source capability regulator tracked half REFSEN voltage internal resistor divider. When both BOOT voltages reach their rising trip points, soft-start starts rising; soft-start interval about 0.5ms. regulator activated only mode; mode regulator needed turned off. regulator 2.5A sink source current limit protect internal FETs. When current limit occurred, regulator keeps load current device provides soft-start function when current limit condition released. Phase Shift APW7116 phase shift function between converters. phase difference relative falling edges UGATE1 UGATE2 phase shift fixed degrees (see figure However, phase shift between rising edge UGATE1 UGATE2 depending duty cycles, rising edges might overlap; user should check advantage phase shift avoid overlapping switching current spikes channels, interaction between channels; also reduces current input capacitors, allowing fewer caps employed.
Copyright ANPEC Electronics Corp. Rev. Jul., 2006 www.anpec.com.tw
Shift TIME
Figure Phase with respect falling edge Thermal Shutdown When junction temperature exceeds device shut down protect device from damage. After temperature decreases device starts again. ACPI Control Logic BUF_CUT signal Power-On Reset thresholds BOOT pins used determine operating mode. BOOT supplied external supplies 5VDUAL 12VATX. When BOOT voltage above their rising trip points, device enabled enters normal operating mode. BUF_CUT pulled internal current source. Pull BUF_CUT high mode, device enters sleep mode. mode output voltages VMCH disabled supply voltage 12VATX supplied device. When BUF_CUT pulled 12VATX enabled, operating mode will back mode. 12VATX supply voltage removed, device into shutdown mode, regulator will shut down. Note that transition from allowed. timing diagram shown Figure state transitions diagram shown Figure
APW7116
Function Description (Cont.)
5VSTBY 5VDUAL
High Threshold
Threshold
BUF_CUT High Threshold BUF_CUT Threshold
BUF_CUT
90%VDDQ 83%VDDQ
VDDQ
90%VMCH 83%VMCH 90%VMCH 83%VMCH
VMCH
POK1
POK2
Figur6. ACPI Timing Diagram
Regulators
VCC=L
BUF_CUT=L BOOT=H
BUF_CUT=L BOOT=L VCC=L VCC=H BOOT=H BUF_CUT=L VCC=L
BUF_CUT=H Regulators
BUF_CUT=L BOOT=H
VMCH
Figure7. State Transitions Diagram
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Application Information
Output Voltage Setting output voltage converter adjusted with resistive divider. internal reference voltage 0.8V. following equation used calculate output voltage: VOUT 0.8V Note that part compensation. should conformed feedback compensation. chosen, should changed adjust output voltage; only change instead. Using better resistors resistor divider recommended.
COMP
Higher capacitor value lower reduce output ripple load transiene drop. addition, capacitor chosen based voltage rating. recommended value output capacitor between 100uF (min. rating 1000uF (min. rating 2m), maximum rating 300m. low-ESR aluminum electrolytic capacitor works well provides good transient response stability. Compensation output filter step down converter introduces double pole, which contributes with -40dB/decade gain slope degrees phase shift control loop. compensation network between COMP, VOUT should added compensate double pole. compensation network shown Fig.
VOUT
0.8V
output filter consists output inductor output capacitors. transfer function filter given GAINLC
Figure8. Resistor Divider VDDQ VMCH regulator voltage determined REFSEN voltage, internal fixed resistive divider from REFSEN ground divides REFSEN voltage ratio 1:1. following equation used calculate output voltage:
COUT COUT COUT
poles zero this transfer function are:
FESR
COUT
COUT
VREFSEN x0.495 source current VREFSEN x0.505 sink current
Regulator Input/Output Capacitor Selection input capacitor chosen based voltage rating. Under load transient condition, input capacitor will momentarily supply required transient current. output capacitor regulator chosen minimize drop during load transient condition.
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
double poles filter, FESR zero introduced output capacitor.
PHASE COUT Output
Figure Output Filter
www.anpec.com.tw
APW7116
Application Information (Cont.)
Compensation (Cont.)
-40dB/dec
COMP GAINAMP
FESR
-20dB/dec
(R1+
poles zeros transfer function are:
Frequency
Figure Filter Gain Frequency modulator shown Figure. input output error amplifier output PHASE node. transfer function modulator given GAINPWM
(R1+
Driver Comparator
VOUT
VCOMP
VOSC
VREF
PHASE
Vcomp
Figure Compensation Network closed loop gain converter written
Driver
GAINLC GAINPWM GAINAMP Figure shows asymptotic plot closed
Figure Modulator compensation circuit shown Figure Design appropriate compensation circuit desired zero crossover frequency sufficient phase margin. transfer function error amplifier given loop converter gain following guidelines will help design compensation network. Using below guidelines should give compensation similar curve plotted. stable closed loop -20dB/ decade slope phase margin greater than degree.
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Application Information (Cont.)
Compensation (Cont.) 1.Choose value usually between 2.Select desired zero crossover frequency (1/5 1/10) >FO>FESR following equation calculate 0.75 3.Place first zero before output filter double pole frequency FLC. 0.75 Calculate equation: 4.Set pole zero frequency FESR: FESR Calculate equation: Figure Converter Gain Frequency Output Inductor Selection inductor value determines inductor ripple current affects load transient response. Higher inductor value reduces inductor' ripple current induces lower output ripple voltage. ripple current ripple voltage approximated VOUT VOUT IRIPPLE VOUT IRIPPLE where switching frequency regulator. Although increase inductor value reduce ripple current voltage, there tradeoff exists between inductor' ripple current regulator load transient response time. smaller inductor will give regulator faster load transient response expense higher ripple current. maximum ripple current occurs maximum input voltage. good starting point choose ripple current approximately maximum output current.
20log (R2/R1) Gain Open Loop Error Gain FZ1=0.75FLC FP1=FESR FZ2=FLC FP2=0.5FS
FESR Filter Gain
20log (VIN/ VOSC) Compensation Gain
Converter Gain Frequency
FESR
5.Set second pole half switching frequency also second zero output filter double pole FLC. compensation gain should exceed error amplifier open loop gain, check compensation gain with capabilities error amplifier. 0.5xFS Combine equations will following component calculations: 2xFLC
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Application Information (Cont.)
Output Inductor Selection (Cont.) Once inductance value been chosen, select inductor that capable carrying required peak current without going into saturation. some type inductors, especially core that make ferrite, ripple current will increase abruptly when saturates. This will result larger output ripple voltage. Output Capacitor Selection Higher Capacitor value lower reduce output ripple load transient drop. Therefore, select high performance capacitors that intended switching regulator applications. some applications, multiple capacitors have parallel achieve desired value. small decoupling capacitor parallel bypassing noise also recommended, voltage rating output capacitors also must considered. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. Input Capacitor Selection input capacitor chosen based voltage rating current rating. reliable operation, select capacitor voltage rating least times higher than maximum input voltage. maximum current rating requirement approximately IOUT/2, where IOUT load current. During power input capacitors have handle large amount surge current. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. high frequency decoupling, ceramic capacitor connected between drain upper MOSFET source lower MOSFET. MOSFET Selection selection N-channel power MOSFETs determined RDS(ON), reverse transfer capacitance (CRSS) maximum output current requirement. losses MOSFETs have components: conduction loss transition loss. upper lower MOSFET, losses approximately given following: PUPPER IOUT 2(1+ TC)(RDS(ON))D (0.5)(IOUT)(VIN)(tSW)FS PLOWER IOUT 2(1+ TC)(RDS(ON))(1-D) where IOUT load current temperature dependency RDS(ON) switching frequency switching interval duty cycle Note that both MOSFETs have conduction losses while upper MOSFET include additional transition loss. switching internal, function reverse transfer capacitance CRSS. (1+TC) term factor temperature dependency RDS(ON) extracted from "RDS(ON) Temperature" curve power MOSFET. Layout Considerations high power switching regulator, correct layout important ensure proper operation regulator. general, interconnecting impedances should minimized using short, wide printed circuit traces. Signal power grounds kept separate finally combined using ground plane construction single point grounding. Figure illustrates layout, with bold lines indicating high current paths; these traces must short wide. Components along bold lines should placed close together.
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Application Information (Cont.)
Layout Considerations (Cont.) Below checklist your layout:
traces from gate drivers MOSFETs
(UG1, LG1, UG2, LG2) should short wide.
metal plate bottom packages
(TSSOP-24-P) must soldered connect plane backside through several thermal vias. More vias better heatsink.
Decoupling capacitor, compensation component,
resistor dividers, boot capacitors, capacitors should close their pins.
Keep switching nodes (UGATE, LGATE
PHASE) away from sensitive small signal nodes since these nodes fast moving signals. Therefore keep traces these nodes short possible.
input capacitor should near drain
upper MOSFET; output capacitor should near loads.
input capacitor should close
output capacitor lower MOSFET GND.
Connet VTTFB point load
REFSEN should connected point load VDDQ output.
drain MOSFETs (VIN phase nodes)
should large plane heat sinking.
APW7116 CBOOT PHASE BOOT CVCC AGND REFSEN BOTTOM SIDE VDDQ 5VDUAL COUT VDDQ
LOAD VTTGND VTTFB Island power plane connection ground plane
Figure?. Layout Guidelines
Figure Layout Guidelines
Copyright ANPEC Electronics Corp. Rev. Jul., 2006 www.anpec.com.tw
APW7116
Packaging Information
TSSOP/ TSSOP-P (Reference JEDEC Registration MO-153)
GAUGE PLANE
EXPOSED THERMAL ZONE
0.25
(L1)
BOTTOM VIEW (THERMALLY ENHANCED VARIATIONDS ONLY)
Millimeters Max. 0.00 0.15 0.80 1.05 0.19 0.30 (N=20PIN) (N=20PIN) (N=24PIN) (N=24PIN) (N=28PIN) (N=28PIN) (N=20PIN) (N=24PIN) (N=28PIN) 0.65 6.40 4.30 4.50 (N=20PIN) (N=24PIN) (N=28PIN) 0.45 0.75 0.09 0.09
Inches Max. 0.047 0.000 0.006 0.031 0.041 0.007 0.012 0.252 (N=20PIN) 0.260 (N=20PIN) 0.303 (N=24PIN) 0.311 (N=24PIN) 0.378 (N=28PIN) 0.386 (N=28PIN) 0.165 (N=20PIN) 0.188 (N=24PIN) 0.150 (N=28PIN) 0.026 0.252 0.169 0.177 0.118 (N=20PIN) 0.127 (N=24PIN) 0.110 (N=28PIN) 0.018 0.030 0.039REF 0.004 0.004 0.008
www.anpec.com.tw
Min.
Min.
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
APW7116
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material 90/10 63/37 SnPb), 100%Sn Meets Specification RSI86-91, ANSI/J-STD-002 Category
Reflow Condition
(IR/Convection Reflow)
Critical Zone
Ramp-up
Temperature
Tsmax
Tsmin Ramp-down Preheat
Peak
Classification Reflow Profiles
Profile Feature Average ramp-up rate Preheat Temperature (Tsmin) Temperature (Tsmax) Time (min max) (ts) Time maintained above: Temperature (TL) Time (tL) Peak/Classificatioon Temperature (Tp) Time within actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds table 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds table 20-40 seconds
6°C/second max. 6°C/second max. minutes max. minutes max. Time 25°C Peak Temperature Notes: temperatures refer topside package .Measured body surface.
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
(mm)
www.anpec.com.tw
APW7116
Classification Reflow Profiles(Cont.)
Table SnPb Entectic Process Package Peak Reflow Temperatures Package Thickness Volum Volume <350 <2.5 +0/-5°C +0/-5°C +0/-5°C +0/-5°C
Table Pb-free Process Package Classification Reflow Temperatures Package Thickness Volume Volume Volume <350 350-2000 >2000 <1.6 +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* *Tolerance: device manufacturer/supplier shall assure process compatibility including stated classification temperature (this means Peak reflow temperature +0°C. example 260°C+0°C) rated level.
Reliability Test Program
Test item SOLDERABILITY HOLT Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD Description 245°C, 1000 Bias @125°C Hrs, 100%RH, 121°C -65°C~150°C, Cycles VHBM 2KV, 200V 10ms, 100mA
Carrier Tape Reel Dimensions
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
APW7116
Carrier Tape Reel Dimensions(Cont.)
Application
+0.1
±0.5
±0.5 ±0.1
16.4 ±0.2 ±0.1
±0.2 ±0.1
±0.3 ±0.1
±0.1 ±0.1
1.75±0.1 0.3±0.05
TSSOP-
±0.1
(mm)
Cover Tape Dimensions
Application TSSOP- Carrier Width Cover Tape Width 21.3 Devices Reel 2000
Customer Service
Anpec Electronics Corp. Head Office No.6, Dusing Road, SBIP, Hsin-Chu, Taiwan, R.O.C. 886-3-5642000 886-3-5642050 Taipei Branch 137, Lane 235, Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, 886-2-89191368 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. Jul., 2006
www.anpec.com.tw
Other recent searches
TN-SFP-ELX1-AS - TN-SFP-ELX1-AS TN-SFP-ELX1-AS Datasheet
ML12061 - ML12061 ML12061 Datasheet
MC12061 - MC12061 MC12061 Datasheet
MDX-19-6-1-X-X - MDX-19-6-1-X-X MDX-19-6-1-X-X Datasheet
MCA1T-80MH+ - MCA1T-80MH+ MCA1T-80MH+ Datasheet
AN10365 - AN10365 AN10365 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
