Synchronous Buck Linear Controller with 0.8V Reference Voltage Re

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Synchronous Buck Linear Controller with 0.8V Reference Voltage Re

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APW7068
Synchronous Buck Linear Controller with 0.8V Reference Voltage
Regulated Voltages REF_OUT Synchronous Buck Converter Linear Regulator REF_OUT 0.8V±1% with source current Single Power Supply Required Excellent Both Output Voltage Regulation 0.8V Internal Reference Over Line Voltage Temperature Integrated Soft-Start Linear Outputs 300KHz Fixed Switching Frequency Voltage Mode Control Design (Typ.) Duty Cycle Under-Voltage Protection Monitoring Linear Output Over-Voltage Protection Monitoring Output Over-Current Protection Output Sense Low-side MOSFET' RDS(ON) SOP-14, QSOP-16 Compact QFN4x4-16 packages Lead Free Available (RoHS Compliant)
General Description
APW7068 integrates synchronous buck PWM, linear controller, 0.8V Reference Voltage, well monitoring protection functions into single package. fixed 300KHz switching frequency synchronous controller drives dual N-channel MOSFETs, which provides controlled power output with over-voltage over-current protections. Linear controller drives external N-channel MOSFET with under-voltage protection. APW7068 provides excellent regulation output load variation. internal 0.8V temperature-compensated reference voltage designed meet requirement output voltage applications. APW7068 with excellent protection functions: POR, OCP, UVP. Power-On Reset (POR) circuit monitor VCC12 supply voltage exceeds threshold voltage while controller running, built-in digital soft-start provides both outputs with controlled rising voltage. Over-Current Protection (OCP) monitors output current using voltage drop across lower MOSFET' RDS(ON), comparing with voltage OCSET pin, VOCSET. maximum VOCSET voltage limited internal default value 0.25V. addition, when OCSET floating ROCSET resistor), over current threshold will also internal default value, 0.25V. When output current reaches trip point, controller will shutdown directly, latch converter' output. Under-Voltage Protection (UVP) monitors voltage short-circuit protection. When VFBL less than VREF, controller will shutdown directly. Over-Voltage Protection (OVP) monitors voltage When over 135% VREF, controller will make Low-side gate signal fully turn until fault events removed.
Simplified Application Circuit
VIN2 VOUT2 Linear Controller Controller VIN1 VOUT1
Applications
Graphic Cards
ANPEC reserves right make changes improve reliability manufacturability without notice, advise customers obtain latest version relevant information verify before placing orders. Copyright ANPEC Electronics Corp. Rev. May, 2007 www.anpec.com.tw
APW7068
Ordering Marking Information
APW7068 Lead Free Code Handling Code Temp. Range Package Code APW7068 APW7068
APW7068 XXXXX APW7068 XXXXX
Package Code SOP-14 QSOP 4x4-16 Temp. Range Handling Code Tube Tape Reel Tray (for only) Lead Free Code Lead Free Device Blank Original Device XXXXX Date Code XXXXX Date Code
APW7068
APW7068 XXXXX
XXXXX Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials 100% matte plate termination finish; which fully compliant with RoHS compatible with both SnPb lead-free soldering operations. ANPEC lead-free products meet exceed leadfree requirements IPC/JEDEC STD-020C classification lead-free peak reflow temperature.
Configurations
FS_DIS UGATE BOOT PHASE Metal (Bottom) AGND DGND VCC12 VCC12
BOOT FS_DIS COMP DRIVE UGATE PHASE PGND LGATE OCSET REF_OUT VCC12 BOOT FS_DIS COMP DRIVE UGATE PHASE PGND LGATE OCSET REF_OUT VCC12 VCC12 DRIVE COMP
PGND LGATE OCSET REF_OUT
SOP-14 VIEW
QSOP-16 VIEW
4x4-16 VIEW
Absolute Maximum Ratings
Symbol VCC12 VBOOT VUGATE VLGATE VPHASE VDRIVE VCC12 BOOT PHASE UGATE PHASE <400ns pulse width >400ns pulse width LGATE PGND PHASE DRIVE <400ns pulse width >400ns pulse width <200ns pulse width >200ns pulse width Parameter Rating -0.3 -0.3 VBOOT -0.3 VBOOT +0.3 VCC12+5 -0.3 VCC12+0.3 -0.3 -0.3 Unit
VFB, VFBL, VCOMP, VFS_DIS FBL, COMP, FS_DIS
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Absolute Maximum Ratings (Cont.)
Symbol VPGND TSTG TSDR VESD PGND Junction Temperature Range Storage Temperature Soldering Temperature Seconds) Minimum Rating Parameter Rating -0.3 +0.3 +150 Unit
Note Absolute Maximum Ratings those values beyond which life device impaired. Exposure absolute maximum rating conditions extended periods affect device reliability. Note device sensitive. Handling precautions recommended.
Recommended Operating Conditions
Symbol VCC12 VIN1 VOUT1 IOUT1 IOUT2 Supply Voltage Converter Input Voltage Converter Output Voltage Converter Output Current Linear Output Current Ambient Temperature Range Junction Temperature Range Parameter Rating 10.8 13.2 13.2 Unit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC12 12V, =-20 70°C. Typical values 25°C.
Symbol
Parameter
Test Conditions
APW7068
Unit
INPUT SUPPLY CURRENT ICC12 VCC12 Supply Current (Shutdown mode) VCC12 Supply Current POWER-ON RESET Rising VCC12 Threshold Falling VCC12 Threshold OSCILLATOR Accuracy FOSC VOSC Duty VREF Oscillator Frequency Ramp Amplitude Maximum Duty Cycle Reference Voltage Reference Voltage Tolerance Load Regulation Linear Load Regulation ERROR AMPLIFIER Gain GBWP Open Loop Gain Open Loop Bandwidth 10k, 10pF (Note 10k, 10pF
(Note
UGATE, LGATE DRIVE open; FS_DIS UGATE, LGATE DRIVE open (nominal 1.2V 2.7V) (Note
REFERENCE Error Amp1 Amp2 IOUT1 IOUT2 0.792 0.80 0.808
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12 12V, =-20 70°C. Typical values 25°C. Symbol Parameter Test Conditions APW7068 VCOMP VCOMP 2.25 2.25 10k, 10pF (Note 10k, 10pF VFBL= 0.8V
(Note
Unit
ERROR AMPLIFIER (Cont.) VCOMP VCOMP ICOMP ICOMP IUGATE IUGATE ILGATE ILGATE RUGATE RUGATE RLGATE RLGATE Gain GBWP VDRIVE VDRIVE IDRIVE IDRIVE VFB-OV VFBL-UV IOCSET REF_OUT VREF_OUT IREF_OUT Output Voltage Offset Voltage Source Current Sink Current Output Capacitance
Note Guaranteed design.
Slew Rate Input Current COMP High Voltage COMP Voltage COMP Source Current COMP Sink Current Upper Gate Source Current Upper Gate Sink Current Lower Gate Source Current Lower Gate Sink Current Upper Gate Source Impedance Upper Gate Sink Impedance Lower Gate Source Impedance Lower Gate Sink Impedance Dead Time Open Loop Gain Open Loop Bandwidth Slew Rate Input Current DRIVE High Voltage DRIVE Voltage DRIVE Source Current DRIVE Sink Current
10k, 10pF (Note 0.8V
V/us 3.375 1.05 3.375 V/us 0.808
GATE DRIVERS VBOOT 12V, VUGATE VPHASE VCC12 12V, VLGATE VBOOT 12V, IUGATE 0.1A VBOOT 12V, IUGATE 0.1A VCC12 12V, ILGATE 0.1A VCC12 12V, ILGATE 0.1A
LINEAR REGULATOR VDRIVE VDRIVE FOSC=300kHz 0.792 0.25 0.800
10k, 10pF (Note
PROTECTION Over Voltage Protection Trip Point Percent VREF Under Voltage Protection Trip Point OCSET Current Source Internal Soft-Start Interval (NOTE3) Percent VREF
SOFT START
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Typical Operating Characteristics
UGATE Source Current UGATE Voltage
VBOOT =12V VPHASE=0V
UGATE Sink Current UGATE Voltage
VBOOT =12V VPHASE=0V
UGATE Source Current
UGATE Sink Current
UGATE Voltage
UGATE Voltage
LGATE Source Current LGATE Voltage
VCC12=12V
LGATE Sink Current LGATE Voltage
VCC12=12V
LGATE Source Current
LGATE Sink Current
LGATE Voltage
LGATE Voltage(V)
VREF Junction Temperature
0.804 0.8035
Reference Voltage(V)
0.803 0.8025 0.802 0.8015 0.801 0.8005
VREF
Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. May, 2007 www.anpec.com.tw
APW7068
Operating Waveforms
Power
VCC12=12V, VIN1=12V,VIN2=3.3V VOUT 1=1.2V,VOUT 2=2.5V L=1uH
Power
VCC12=12V, VIN1=12V,VIN2=3.3V VOUT1=1.2V,VOUT2=2.5V L=1uH
CH1: VCC12 (10V/div) CH2: VOUT1 (1V/div) CH3: VOUT2 (2V/div) Time: 10ms/div
CH1: VCC12 (10V/div) CH2: VOUT1 (1V/div) CH3: VOUT2 (2V/div) Time: 10ms/div
VCC12 =12V, L=1uH, VIN1 =12V, VIN2 =3.3V VOUT1 =1.2V, VOUT2=2.5V
Shutdown
VCC12 =12V, L=1uH, VIN1 =12V, VIN2 =3.3V VOUT1 =1.2V, VOUT2=2.5V
CH1: VFS_DIS (1V/div) CH2: VDRIVE (5V/div) CH3: VOUT1 (1V/div) CH4: VOUT2 (2V/div) Time: 10ms/div
CH1: VFS_DIS (1V/div) CH2: VDRIVE (5V/div) CH3: VOUT1 (1V/div) CH4: VOUT2 (2V/div) Time: 10ms/div
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Operating Waveforms (Cont.)
UGATE Rising
VCC12=12V, VIN1=12V VOUT1=1.2V
UGATE Falling
VCC12=12V, VIN1=12V VOUT1=1.2V
CH1: VUGATE (20V/div) CH2: VPHASE (10V/div) CH3: VLGATE (10V/div) Time: 50ns/div
CH1: VUGATE (20V/div) CH2: VPHASE (10V/div) CH3: VLGATE (10V/div) Time: 50ns/div
OVP_PWM Controller (VFB 135% VREF)
VCC12=12V, VIN1 =12V VOUT1=1.2V, VOUT 2=2.5V, L=1uH
UVP_Linear Regulator (VFBL< VREF)
VCC12=12V, VIN2 =3.3V VOUT2=2.5V, 2=3A
CH1: VCC12 (1V/div) CH2: VLGATE (1V/div) CH3: VOUT1 (500mV/div) CH4: VOUT2 (2V/div) Time: 10ms/div
CH1: VFBL (1V/div) CH2: VDRIVE (5V/div) CH3: VOUT2 (2V/div) Time: 100us/div
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Operating Waveforms (Cont.)
Load Transient Response (PWM Controller)
VCC12=12V, VIN1=12V, VOUT1=2V, FOSC=300KHz IOUT1 slew rate=±10 A/us
CH1: VOUT1 (100mV/div,AC) CH2: VUGATE (20V/div) CH3: IOUT1 (10A/div) Time: 20us/div
CH1: VOUT1 (100mV/div,AC) CH2: VUGATE (20V/div) CH3: IOUT1(10A/div) Time: 50us/div
CH1: VOUT1 (100mV/div,AC) CH2: VUGATE (20V/div) CH3: IOUT1(10A/div) Time: 20us/div
Load Transient Response (Linear Regulator)
VCC12=12V, VIN2=3.3V, VOUT2=2.5V IOUT2 slew rate=±3A/us
CH1: VOUT2 (100mV/div,AC) CH2: IOUT2 (2A/div) Time: 1us/div
CH1: VOUT2 (100mV/div,AC) CH2: IOUT2 (2A/div) Time: 10us/div
CH1: VOUT2 (100mV/div,AC) CH2: IOUT2 (2A/div) Time: 1us/div
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Operating Waveforms (Cont.)
Over Current Protection
VCC12=12V, VIN1=12V, VOUT1=1.2V, VIN2 =3.3V, VOUT2=2.5V, L=1uH
Short Test after Power Ready
VCC12=12V, VIN1=12V, VOUT 1=1.2V, VIN2=3.3V, VOUT 2=2.5V, L=1uH
=470uFx2, OCSET DS(ON)=4m
=470uFx2, OCSET DS(ON)=4m
CH1: VOUT1 (1V/div) CH2: VDRIVE (5V/div) CH3: VUGATE (20V/div) CH4: (10A/div) Time: 50us/div
CH1: VOUT1 (1V/div) CH2: VDRIVE (5V/div) CH3: VUGATE (20V/div) CH4: (10A/div) Time: 50us/div
Short Test before Power
VCC12=12V, VIN1=12V, VOUT1=1.2V, VIN2=3.3V, VOUT2=2.5V, L=1uH
CH1: VCC12 (10V/div) CH2: VOUT1 (1V/div) CH3: VUGATE (20V/div) CH4: (10A/div) Time: 2ms/div
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Function Descriptions
VCC12 Power supply input pin. Connect nominal power supply this pin. power-on reset function monitors input voltage this pin. recommended that decoupling capacitor 10µF) connected noise decoupling. BOOT This provides bootstrap voltage upper gate driver driving N-channel MOSFET. external capacitor from PHASE BOOT, internal diode, power supply valtage VCC12, generates bootstrap voltage upper gate diver (UGATE). PHASE This return path upper gate driver. Connect this upper MOSFET source, connect capacitor BOOT bootstrap voltage. This also used monitor voltage drop across lower MOSFET over-current protection. This signal ground pin. Connect good ground plane. PGND This power ground lower gate driver. should tied board. COMP This output error amplifier. used compensation components. This inverting input error amplifier. used output voltage compensation components. This also monitored undervoltage protection, when voltage under reference voltage (0.4V), both outputs will shutdowned immediately. UGATE This gate driver upper MOSFET output. LGATE This gate driver lower MOSFET output. DRIVE This drives gate external N-channel MOSFET linear regulator. also used compensation some specific applications, example, with values output capacitance ESR. This inverting input linear regulator error amplifier. used output voltage. This also monitored under-voltage protection, when voltage under reference volta (0.4V), both outputs will shutdown immediately. OCSET Connect resistor OCSET) from this GND, internal 40µA current source will flow through this resistor create voltage drop. When VCC12 reaches rising threshold voltage, voltage drop ROCSET will memoried compared with voltage across lower MOSFET. threshold over current limit therefore given
ILIMIT IOCSET ROCSET RDS(ON) (LOW Side)
APW7068 internal voltage source, value around 0.25V. When ROCSET IOCSET bigger than 0.25V OCSET floating ROCSET resistor), over current threshold will internal default value 0.25V. REF_OUT This provides buffed voltage, which from internal reference voltage. recommended that capacitor connected ground stability. When VOCSET above REF_OUT buffer will closed, VREF_OUT FS_DIS This provides shutdown function. When pulling FS_DIS near will shutdown both regulators; almost NFET other pull-down device impedance) should work. Upon release FS_DIS pin, will enable both outputs back into regulation.
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Block Diagram
VCC12 OCSET
IOCSET 40uA
REF_OUT
Reference Buffer
Regulator
Power-On Reset
BOOT
VREF (0.8V) 135%VREF X1.35 Soft Start Fault Logic
O.C.P Comparator VOCSET
UGATE
O.V.P Comparator
PHASE
Sense Side
Gate Control
LGATE PGND
Error
Comparator
U.V.P Comparator 50%VREF
VREF Oscillator Sawtooth Wave (300KHz) VREF Error
DRIVE
COMP
FS_DIS
Typical Application Circuits
2.2nF 3.9K VOUT1 VIN2 3.3V CIN2 470uF APM3055 1.5K 22nF RGND1 BOOT FS_DIS COMP DRIVE UGATE PHASE PGND APM2506 2.2nF OUT1 470uFx2 0.01uF ON/OFF 2N7002 0.1uF VIN1 APM2509 CIN1 470uFx2
VOUT1 1.2V
LGATE OCSET REF_OUT VCC12 APW7068
VOUT2 2.5V
2.5K COUT2 470uF
RGND2 1.17K *C5,R5forspecificapplication
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Functional Descriptions
Power Reset (POR) Power-On Reset (POR) function APW7068 continually monitors input supply voltage (VCC12), ensures supply voltage exceed rising threshold voltage. function initiates soft-start interval operation while VCC12 voltage exceeds threshold inhibits operation under disabled status. Soft-Start Figure shows soft-start interval. When VCC12 reaches rising threshold voltage, internal reference voltage controlled follow voltage proportional soft-start voltage. soft-start interval variable oscillator frequency. formulation given 2560 FOSC Figure shows more detail voltage ramps. voltage soft-start ramps formed with many small steps voltage. voltage step about 20mV VFBL, period step about 32/FOSC. This method provides controlled voltage rise prevents large peak current charge output capacitors. voltage compares voltage shift earlier time establishment Figure2. voltage estabilishment time difference variable oscillator. formulation given
Voltage
Voltage(V)
VFBL 20mV 32/FOSC
32/FOSC
20mV
Time
Figure Controlled Stepped Voltage during Soft-Start
Over-Current Protection Connect resistor (ROCSET) from this GND, internal 40µA current source will flow through this resistor create voltage drop, which will compared with voltage across lower MOSFET. When voltage across lower MOSFET exceeds voltage drop across ROCSET, over-current condition detected controller will shutdown directly, converter's output latched. APW7068 internal voltage source, value around 0.25V. When ROCSET IOCSET bigger than 0.25V OCSET floating ROCSET resistor), over current threshold will internal default value 0.25V. threshold over current limit therefore given
ILIMIT IOCSET OCSET RDS(ON) (LOW Side)
FOSC
VCC12
over-current never occurred normal operating load range; variation parameters above equation should determined. MOSFET' RDS(ON) varied temperature gate source voltage, user should determine maximum RDS(ON) manufacturer' datasheet. minimum OCSET (36uA) minimum OCSET should used above equation. Note that ILIMIT current flow through lower MOSFET; ILIMIT must greater than maximum output current half inductor ripple current.
VOUT1 VOUT2
Time
Figure Soft-Start Interval Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Functional Descriptions (Cont.)
Over-Current Protection (Cont.) When OCSET floating, VOCSET will pulled high over current threshold will internal default value 0.25V. When voltage drop across lower MOSFET' RDS(ON) larger than 0.25V, overs current condition detected, controller will shutdown directly, latch converter' output. Over Voltage Protection monitored during converter operation Over Voltage(OV) comparator. voltage over 135% reference voltage, controller will make Low-Side gate signal fully turn until fault events removed. Under Voltage Protection monitored during converter operation Under Voltage (UV) comparator. voltage drop below reference voltage (50% 0.8V 0.4V), fault signal internally generated, device turns both high-side low-side MOSFET converter' output latched floating. controller will shutdown directly. Shutdown Enable Pulling FS_DIS near open drain transistor other pull-down device impedance) will shutdown both regulators. Upon release FS_DIS pin, will enable both outputs back into regulation. shutdown mode, UGATE LGATE turn pull PHASE respectively.
Application Information
Output Voltage Selection output voltage converter programmed with resistive divider. better resistors resistive divider recommended. inverter input error amplifier, reference voltage 0.8V. output voltage determined VOUT1 GND1 Where resistor connected from VOUT1 RGND1 resistor connected from GND. linear regulator output voltage VOUT2 also means external resistor divider. inverter input error amplifier, reference voltage 0.8V. output voltage determined VOUT2 GND2 Where resistor connected from VOUT2 RGND2 resistor connected from GND. Linear Regulator Input/Output Capacitor Selection input capacitor chosen based voltage rating. Under load transient condition, input capacitor will momentarily supply required transient current. output capacitor linear regulator chosen minimize droop during load transient condition. addition, capacitor chosen based voltage rating.
Copyright ANPEC Electronics Corp. Rev. May, 2007
Linear Regulator Input/Output MOSFET Selection maximum DRIVE voltage about when VCC12 equal 12V. Since this drives external N-channel MOSFET, therefore maximum output voltage linear regulator dependent upon VGS. VOUT2MAX Another criterion efficiency heat removal. power dissipated MOSFET given IOUT2 (VIN2 OUT2) Where IOUT2 maximum load current, VOUT2 nominal output voltage. some applications, heatsink might required help maintain junction temperature MOSFET below maximum rating. Linear Regulator Compensation Selection linear regulator stable over loads current. However, transient response further enhanced connecting network between DRIVE pin. Depending output capacitance load current application, value this network then varied. Compensation output filter step down converter introduces double pole, which contributes with -40dB/decade gain slope degrees phase shift control loop.
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APW7068
Application Information (Cont.)
Compensation (Cont.) compensation network among COMP, OUT1 should added. compensation network shown Figure output filter consists output inductor output capacitors. transfer function filter given GAINLC COUT1 COUT1 COUT1
VOSC Comparator PHASE Output Error Amplifier
GAINPWM
VOSC
VIN1 Driver
poles zero this transfer functions are:
Driver
COUT1
COUT1
Figure Modulator
FESR
compensation network shown Figure provides close loop transfer function with highest zero crossover frequency sufficient phase margin. transfer function error amplifier given
double poles filter, FESR zero introduced output capacitor.
VPHASE VOUT1
COUT1
Figure Output Filter
VCOMP GAINAMP VOUT1 R1//
poles zeros transfer function are:
-40dB/dec
FESR
-20dB/dec
(R1+
VOUT1 VREF VCOMP
GAIN (dB)
Frequency(Hz)
Figure Filter GAIN Frequency
modulator shown Figure input output error amplifier output PHASE node. transfer function modulator given
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Figure Compensation Network
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APW7068
Application Information (Cont.)
Compensation (Cont.) closed loop gain converter written GAINLC GAINPWM GAINAMP Figure shows asymptotic plot closed loop converter gain, following guidelines will help design compensation network. Using below guidelines should give compensation similar curve plotted. stable closed loop -20dB/ decade slope phase margin greater than degree. Choose value usually between Select desired zero crossover frequency (1/5 1/10) >FO>FESR following equation calculate VOSC Place first zero before output filter double pole frequency FLC. 0.75 Calculate equation: 0.75 pole zero frequency FESR: FESR Calculate equation: FESR second pole half switching frequency also second zero output filter double pole FLC. compensation gain should exceed error amplifier open loop gain, check compensation gain with capabilities error amplifier. Combine equations will following component calculations:
FESR Filter Gain Converter Gain
GAIN (dB)
20log (R2/R1)
Compensation Gain 20log (VIN/VOSC)
Frequency(Hz)
Figure Converter Gain Frequency
Output Inductor Selection inductor value determines inductor ripple current affects load transient response. Higher inductor value reduces inductor' ripple current induces lower output ripple voltage. ripple current ripple voltage approximated IRIPPLE VIN1 VOUT1 VOUT1 VIN1
VOUT1 IRIPPLE where switching frequency regulator. Although increase inductor value frequency reduces ripple current voltage, tradeoff will exist between inductor' ripple current regulator load transient response time. smaller inductor will give regulator faster load transient response expense higher ripple current. Increasing switching frequency (FS) also reduces ripple current voltage, will increase switching loss MOSFET power dissipation converter. maximum ripple current occurs maximum input voltage. good starting point choose ripple current approximately maximum output current. Once inductance value been chosen, select inductor that capable carrying required peak current without going into
Copyright ANPEC Electronics Corp. Rev. May, 2007
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APW7068
Application Information (Cont.)
Output Inductor Selection (Cont.) saturation. some types inductors, especially core that made ferrite, ripple current will increase abruptly when saturates. This will result larger output ripple voltage. Output Capacitor Selection Higher capacitor value lower reduce output ripple load transient drop. Therefore, selecting high performance capacitors intended switching regulator applications. some applications, multiple capacitors have parallel achieve desired value. small decoupling capacitor parallel bypassing noise also recommended, voltage rating output capacitors also must considered. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. Input Capacitor Selection input capacitor chosen based voltage rating current rating. reliable operation, select capacitor voltage rating least times higher than maximum input voltage. maximum current rating requirement approximately IOUT1/2, where IOUT1 load current. During power input capacitors have handle large amount surge current. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. high frequency decoupling, ceramic capacitor connected between drain upper MOSFET source lower MOSFET. MOSFET Selection selection N-channel power MOSFETs determined RDS(ON), reverse transfer capacitance (CRSS) maximum output current requirement. There components loss MOSFETs: conduction loss transition loss. upper lower MOSFET, losses approximately given following: PUPPER IOUT1 TC)(RDS(ON))D (0.5)( IOUT1)(VIN1)( tSW)FS PLOWER IOUT1 TC)(RDS(ON))(1-D) Where IOUT1 load current temperature dependency RDS(ON) switching frequency switching interval duty cycle Note that both MOSFETs have conduction loss while upper MOSFET include additional transition loss. switching internal, tSW, function reverse transfer capacitance CRSS. (1+TC) term factor temperature dependency RDS(ON) extracted from "RDS(ON) Temperature" curve power MOSFET.
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APW7068
Layout Considerations
high switching frequency converter, correct layout important ensure proper operation regulator. With power devices switching 300KHz above, resulting current transient will cause voltage spike across interconnecting impedance parasitic circuit elements. example, consider turn-off transition MOSFET. Before turn-off, MOSFET carrying full load current. During turn-off, current stops flowing MOSFET free-wheeling lower MOSFET parasitic diode. parasitic inductance circuit generates large voltage spike during switching interval. general, using short, wide printed circuit traces should minimize interconnecting impedances magnitude voltage spike. signal power grounds kept separate till combined using ground plane construction single point grounding. Figure illustrates layout, with bold lines indicating high current paths; these traces must short wide. Components along bold lines should placed lose together. Below checklist your layout: metal plate bottom packages (QFN-16) must soldered connected plane backside through several thermal vias. Keep switching nodes (UGATE, LGATE PHASE) away from sensitive small signal nodes since these nodes fast moving signals. Therefore, keep traces these nodes short possible. traces from gate drivers MOSFETs (UG, DRIVE) should short wide. Place source high-side MOSFET drain low-side MOSFET close possible. Minimizing impedance with wide layout plane between pads reduces voltage bounce node. Decoupling capacitor, compensation component, resistor dividers boot capacitors should close their pins. decoupling ceramic capacitor near drain high-side MOSFET close possible. bulk capacitors also placed near drain).
Figure Layout Guidelines
VOUT2
input capacitor should near drain upper MOSFET; output capacitor should near loads. input capacitor should close output capacitor lower MOSFET GND. drain MOSFETs (VIN1 PHASE nodes) should large plane heat sinking.
APW7068 VIN1 VCC12 VIN2 BOOT DRIVE
UGATE PHASE LGATE VOUT1
REF_OUT
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APW7068
Package Information
SOP-14
VIEW
0.25 GAUGE PLANE SEATING PLANE VIEW
SOP-14 MILLIMETERS MIN. MAX. 1.75 0.10 1.25 0.31 0.17 8.65 6.00 3.90 1.27 0.25 0.40 0.50 1.27 0.010 0.016 0.51 0.25 0.25 0.004 0.049 0.012 0.007 0.341 0.236 0.154 0.050 0.020 0.050 0.020 0.010 MIN. INCHES MAX. 0.069 0.010
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APW7068
Package Information
QSOP-16
VIEW
0.25 GAUGE PLANE SEATING PLANE VIEW
QSOP-16 MILLIMETERS MIN. MAX. 1.75 0.10 1.24 0.20 0.15 4.90 5.99 3.91 0.635 0.40 0.25 1.27 0.50 0.016 0.010 0.30 0.25 0.25 0.004 0.049 0.008 0.006 0.193 0.236 0.154 0.025 0.050 0.020 0.012 0.010 MIN. INCHES MAX. 0.069 0.010
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APW7068
Package Information
QFN4x4-16
QFN4x4-16 MILLIMETERS MIN. 0.80 0.00 0.20 0.25 4.00 2.50 4.00 2.50 0.65 0.30 0.50 0.012 2.80 0.098 0.026 0.020 2.80 0.098 0.157 0.110 0.35 0.010 0.157 0.110 MAX. 1.00 0.05 MIN. 0.031 0.000 0.008 0.014 INCHES MAX. 0.039 0.002
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APW7068
Carrier Tape Reel Dimensions
Application SOP-14 (150mil) Application
330REF
100REF 0.50 +1.5 1.55 +0.1
13.0 1.50 (MIN) 12.75+ 0.15 1.55+ 0.25
16.5REF 12.4
16.0 2.10 5.2±
0.3±0.05 2.1±
1.75
1.75±0.1 0.3±0.013
QSOP-
5.5±
(mm)
Devices Reel
Package Type SOP- QSOP- Devices Reel 2500 2500
Copyright ANPEC Electronics Corp. Rev. May, 2007
www.anpec.com.tw
APW7068
Shipping Tray
Copyright ANPEC Electronics Corp. Rev. May, 2007
www.anpec.com.tw
APW7068
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material: 90/10 63/37 SnPb), 100%Sn Meets Specification RSI86-91, ANSI/J-STD-002 Category
Reflow Condition
(IR/Convection Reflow)
Critical Zone Ramp-up
Temperature
Tsmax
Tsmin Ramp-down Preheat
25°C Peak
Time
Classification Reflow Profiles
Profile Feature Average ramp-up rate Preheat Temperature (Tsmin) Temperature (Tsmax) Time (min max) (ts) Time maintained above: Temperature (TL) Time (tL) Peak/Classification Temperature (Tp) Time within actual Peak Temperature (tp) Ramp-down Rate Time 25°C Peak Temperature Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds table 10-30 seconds 6°C/second max. minutes max. Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds table 20-40 seconds 6°C/second max. minutes max.
Notes: temperatures refer topside package. Measured body surface.
Copyright ANPEC Electronics Corp. Rev. May, 2007 www.anpec.com.tw
APW7068
Classification Reflow Profiles (Cont.)
Table SnPb Eutectic Process Package Peak Reflow Temperatures Package Thickness <2.5 Volume <350 +0/-5°C +0/-5°C
Volume +0/-5°C +0/-5°C
Table Pb-free Process Package Classification Reflow Temperatures Volume Volume Volume <350 350-2000 >2000 <1.6 +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* Tolerance: device manufacturer/supplier shall assure process compatibility including stated classification temperature (this means Peak reflow temperature +0°C. example 260°C+0°C) rated level. Package Thickness
Reliability Test Program
Test item SOLDERABILITY HOLT Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD Description 245°C, 1000 Bias @125°C Hrs, 100%RH, 121°C -65°C~150°C, Cycles VHBM 2KV, 200V 10ms, 100mA
Customer Service
Anpec Electronics Corp. Head Office No.6, Dusing Road, SBIP, Hsin-Chu, Taiwan, R.O.C. 886-3-5642000 886-3-5642050 Taipei Branch 137, Lane 235, Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, 886-2-89191368 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. May, 2007
www.anpec.com.tw

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