Synchronous Buck Controller Single Power Supply Required Fast Tra
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APW7065
Synchronous Buck Controller
Single Power Supply Required Fast Transient Response 0~90% Duty Ratio 0.8V Reference with Accuracy Shutdown Function Controlling COMP Voltage Internal Soft-Start (3.4ms) Function Voltage Mode Control Design Under-Voltage Protection Over-Current Protection Sense Side MOSFET' RDS(ON) 300KHz Fixed Switching Frequency SOP-8 Packages Lead Free Available (RoHS Compliant)
General Description
APW7065 uses fixed 300KHz switching frequency, voltage mode, synchronous controller which drives dual N-channel MOSFETs. device integrates control, monitoring protection functions into single package, provides controlled power output with under-voltage over-current protections. APW7065 provides excellent regulation output load variation. internal 0.8V temperaturecompensated reference voltage designed meet requirement output voltage applications. built-in digital soft-start with fixed soft-start interval prevents output voltage from overshoot well limiting input current. APW7065 with excellent protection functions: POR, UVP. Power-On Reset (POR) circuit monitor supply voltage exceeds threshold voltage while controller running, built-in digital soft-start provides output with controlled voltage rise. Over-Current Protection (OCP) monitors output current using voltage drop across lower MOSFET' RDS(ON), comparing with internal VOCP (0.29V), when output current reaches trip point, controller will soft-start function until fault events removed. UnderVoltage Protection (UVP) monitors voltage short-circuit protection, when less than VREF (0.4V), controller will shutdown directly.
Applications
Graphics Card Mother Board
Pinouts
BOOT UGATE LGATE PHASE COMP
SOP-8 (APW7065)
ANPEC reserves right make changes improve reliability manufacturability without notice, advise customers obtain latest version relevant information verify before placing orders. Copyright ANPEC Electronics Corp. Rev. Mar., 2007 www.anpec.com.tw
APW7065
Ordering Marking Information
APW7065
Lead Free Code Handling Code Temp. Range Package Code APW7065 APW7065 XXXXX Package Code SOP-8 Operating Ambient Temp. Range Handling Code Tube Tape Reel Lead Free Code Lead Free Device Blank Original Device XXXXX Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials 100% matte plate termination finish; which fully compliant with RoHS compatible with both SnPb lead-free soldering operations. ANPEC lead-free products meet exceed lead-free requirements IPC/JEDEC STD-020C classification lead-free peak reflow temperature.
Block Diagram
BOOT Power-On Reset
UGATE
Sense Side O.C.P Comparator 0.29V 50%VREF Error Comparator U.V.P Comparator
Digital Soft Start
PHASE
Gate Control
LGATE
VREF Oscillator Sawtooth Wave FOSC 300KHz
COMP
Copyright ANPEC Electronics Corp. Rev. Mar., 2007
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APW7065
Application Circuit
2.2R BOOT UGATE PHASE LGATE 33nF 8.2nF 2.7K 0.1uF APM2509 APM2506 470uFx2 470uF 1N4148 (12V)
2N7002 ON/OFF COMP
VOUT (1.2V)
470uFx2
68nF
Absolute Maximum Ratings
Symbol BOOT UGATE LGATE PHASE COMP, TSTG TSDR VESD BOOT PHASE UGATE PHASE LGATE PHASE COMP, Junction Temperature Range Storage Temperature Maximum Soldering Temperature, Seconds Minimum Rating (Human Body Mode) (Note <400ns pulse width >400ns pulse width <400ns pulse width >400ns pulse width <200ns pulse width >200ns pulse width Parameter Rating -0.3 -0.3 BOOT+5 -0.3 BOOT+0.3 VCC+5 -0.3 VCC+0.3 -0.3 -0.3 Unit
Note Absolute Maximum Ratings those values beyond which life device impaired. Exposure absolute maximum rating conditions extended periods affect device reliability. Note device sensitive. Handling precautions recommended.
Thermal Characteristics
Symbol Parameter Junction-to-Ambient Thermal Resistance Free SOP-8 Junction-to-Case Thermal Resistance SOP-8 Value Unit
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APW7065
Recommended Operating Conditions
Symbol VOUT IOUT Parameter Supply Voltage Converter Output Voltage Converter Input Voltage Converter Output Current Ambient Temperature Range Junction Temperature Range Range 10.8 13.2 13.2 Unit
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC=12V, =-20~70oC. Typlcal values TA=25oC.
Symbol SUPPLY CURRENT IVCC
Parameter
Test Conditions
APW7065
Unit
Nominal Supply Current Shutdown Supply Current
UGATE LGATE Open UGATE, LGATE
VP-P
POWER-ON RESET Rising Threshold Falling Threshold COMP Shutdown Threshold COMP Shutdown Hysteresis OSCILLATOR FOSC Free Running Frequency VOSC Ramp Amplitude REFERENCE VOLTAGE VREF Reference Voltage Accuracy ERROR AMPLIFIER Gain VCOMP VCOMP Open Loop Gain Slew Rate Input Current COMP High Voltage COMP Voltage RL=10k, CL=10pF(Note3) RL=10k, CL=10pF(Note3) RL=10k, CL=10pF(Note3) 0.8V(Note3) Measured =-20~70°C
-1.0 +1.0
V/us
GBWP Open Loop Bandwidth
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APW7065
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC=12V =-20~70oC. Typlcal values TA=25oC.
Symbol
Parameter
Test Conditions
APW7065 1.05 0.27 0.29 0.31 1.95
Unit
ERROR AMPLIFIER (Cont.) ICOMP ICOMP COMP Source Current COMP Sink Current VCOMP=2V VCOMP=2V BOOT 12V, VUGATE -VPHASE BOOT 12V, VUGATE -VPHASE 12V, VLGATE 12V, VLGATE BOOT 12V, IUGATE 0.1A BOOT 12V, IUGATE 0.1A 12V, ILGATE 0.1A 12V, ILGATE 0.1A
GATE DRIVERS IUGATE Upper Gate Source Current IUGATE Upper Gate Sink Current ILGATE ILGATE Lower Gate Source Current Lower Gate Sink Current
RUGATE Upper Gate Source Impedance RUGATE Upper Gate Sink Impedance RLGATE Lower Gate Source Impedance RLGATE Lower Gate Sink Impedance VOCP VUVP Dead Time PROTECTIONS
1.25 1.88
Over-Current Reference Voltage =-20~70°C Under-Voltage Threshold Trip Point Soft-Start Interval Percent VREF
SOFT-START
Note Guaranteed design.
Functional Description
BOOT (Pin bootstrap circuit with diode connected used create voltage suitable drive logic-level N-channel MOSFET. UGATE (Pin Connect this high-side N-channel MOSFET' gate. This provides gate drive high-side MOSFET. (Pin terminal provides return path bias current low-side MOSFET driver' pull-low current. Connect system ground very impedance layout PCBs. LGATE (Pin Connect this low-side N-channel MOSFET' gate. This provides gate drive low-side MOSFET.
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APW7065
Functional Description (Cont.)
(Pin Connect this supply voltage. This provides bias supply control circuitry low-side MOSFET driver. voltage this monitored Power-On Reset (POR) purpose. recommended that decoupling capacitor 10uF) connected noise decoupling. (Pin This inverting input internal error amplifier. Connect this output (VOUT) converter external resistor divider closedloop operation. output voltage resistor divider determined using following formula
VOUT where resistor connected from VOUT
also monitored under voltage events. COMP (Pin This output error amplifier. used compensation components. addition, pulled below 1.2V, will disable device. PHASE (Pin This return path upper gate driver. Connect this upper MOSFET source. This also used monitor voltage drop across MOSFET over-current protection.
resistor connected from GND.
Typical Characteristics
Power
VCC=12V, Vin=12V Vo=1.2V, L=1uH
Power
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH1: (5V/div) CH2: (1V/div) CH3: (1V/div) CH4: (20/Vdiv) Time: 10ms/div
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CH1: (5V/div) CH2: (1V/div) CH3: (1V/div) CH4: (20/Vdiv) Time: 10ms/div
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APW7065
Typical Characteristics (Cont.)
VCC=12V, Vin=12V Vo=1.2V, L=1uH
Shutdown
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH1: VCOMP (2V/div) CH2: (1V/div) CH3: (20V/div) CH4: (10Vdiv) Time: 5ms/div
CH1: VCOMP (2V/div) CH2: (1V/div) CH3: (20V/div) CH4: (10Vdiv) Time: 20us/div
UGATE Rising
VCC=12V, Vin=12V Vo=1.2V, L=1uH Iout=5A
UGATE Falling
VCC=12V, Vin=12V Vo=1.2V, L=1uH Iout=5A
CH1: (20V/div) CH2: (5V/div) CH3: Phase (10V/div) Time: 50ns/div
CH1: (20V/div) CH2: (5V/div) CH3: Phase (10V/div) Time: 50ns/div
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APW7065
Typical Characteristics (Cont.)
Load Transient Response
VCC=12V, Vin=12V Vo=1.2V, L=1uH
Under Voltage Protection
VCC=12V, Vin=12V Vo=1.2V, L=4.7uH
CH1: (500mV/div,AC) CH2:Io (5A/div) Time: 1ms/div
CH1: (10A/div) CH2: (1V/div) CH3: (20V/div) CH4: (10V/div) Time: 100us/div
Over Current Protection
VCC=12V, Vin=12V,Vo=1.2V, L=1uH, L_side: APM2023, Rds(on)=17m
Short Test
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH1: (10A/div) CH2: (2V/div) CH3: (20V/div) CH4: (10V/div) Time: 2ms/div
CH1: (10A/div) CH2: (2V/div) CH3: (20V/div) CH4: (10V/div) Time: 5ms/div
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APW7065
Typical Characteristics (Cont.)
Switching Frequency Junction Temperature
VCC=12V
Reference Voltage Junction Temperature
0.804
Switching Frequency(KHz)
0.802
VCC=12V
Reference Voltage(V)
0.798
0.796
0.794
0.792
Junction Temperature
Junction Temperature
UGATE Source Current UGATE Voltage
UGATE Sink Current UGATE Voltage
VBOOT=12V
VBOOT=12V
UGATE Source Current
UGATE Sink Current
UGATE Voltage
UGATE Voltage
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APW7065
Typical Characteristics (Cont.)
LGATE Source Current LGATE Voltage
LGATE Sink Current LGATE Voltage
LGATE Source Current
LGATE Sink Current
VCC=12V
VCC=12V
LGATE Voltage
LGATE Voltage
Functional Description
Power Reset (POR) Power-On Reset (POR) function APW7065 continually monitors input supply voltage (VCC) COMP pin. supply voltage (VCC) must exceed rising threshold voltage. function initiates soft-start operation after COMP voltages exceed their thresholds. operation with single +12V power source, equivalent +12V power source must exceed rising threshold. function inhibits operation disabled status (VCOMP less than 1.2V). With both input supplies above their thresholds, device initiates soft-start interval. Soft-Start APW7065 built-in digital soft-start control output voltage rise limit current surge during start-up. Figure when exceeds rising threshold voltage, will delay 2048/Fosc
Copyright ANPEC Electronics Corp. Rev. Mar., 2007
seconds then begin soft start. During soft-start, internal ramp connected positive inputs amplifier rises from replace reference voltage (0.8V) until ramp voltage reaches reference voltage. soft-start interval decided oscillator frequency (300kHz). formulation given
Tdelay 2048/FOSC 6.8ms
Tsoft start 1024/FOSC 3.4ms
Figure shows more detail voltage ramp. voltage soft-start ramp formed with many small steps voltage. voltage step about 12.5mV period step about FOSC. This method provides controlled voltage rise
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APW7065
Functional Description (Cont.)
Soft-Start (Cont.) prevents large peak current charge output capacitor.
Voltage(V)
MOSFET' RDS(ON) varied temperature gate source voltage, user should determine maximum RDS(ON) manufacturer' datasheet. minimum Vocset should used above equation.
Note that ILIMIT current flow through lower MOSFET; ILIMIT must greater than maximum output current half inductor ripple
current. Shutdown Enable
Time
Pulling COMP voltage open drain transistor, shown typical application circuit, shutdown APW7065 controller. shutdown
Figure 1.Soft Start Interval
Voltage(V)
mode, UGATE LGATE turn pull PHASE respectively. Under Voltage Protection
12.5mV
monitored during converter operation internal Under Voltage (UV) comparator.
16/Fosc
voltage drops below reference voltage (50% 0.8V 0.4V), fault signal internally generated,
Time
Figure 2.The Controlled Stepped Voltage during Soft Start Over-Current Protection over-current protection monitors output current using voltage drop across lower MOSFET' RDS(ON) this voltage drop will compared with internal 0.29V reference voltage. voltage drop across lower MOSFET' RDS(ON) larger than 0.29V, over-current condition detected. threshold over current limit given 0.29 ILimit over-current never occurred normal operating load range; variation parameters above equation should determined.
Copyright ANPEC Electronics Corp. Rev. Mar., 2007
device turns both high-side low-side MOSFET converter' output latched floating.
Application Information
Output Voltage Selection output voltage programmed with resistive divider. better resistors resistive divider recommended. inverter input error amplifier, reference voltage 0.8V. output voltage determined
Where ROUT resistor connected from VOUT RGND resistor connected from GND.
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APW7065
Application Information (Cont.)
Output Inductor Selection inductor value determines inductor ripple current affects load transient response. Higher inductor value reduces inductor' ripple current induces lower output ripple voltage. ripple current ripple voltage approximated
IRIPPLE VOUT
capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. Input Capacitor Selection input capacitor chosen based voltage rating current rating. reliable operation, select capacitor voltage rating least times higher than maximum input voltage. maximum current rating requirement approximately IOUT/2, where IOUT load current. During power input capacitors have handle large amount surge current. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. high frequency decoupling, ceramic capacitor connected between drain upper MOSFET source lower MOSFET. MOSFET Selection selection N-channel power MOSFETs determined RDS(ON), reverse transfer capacitance (CRSS) maximum output current requirement. There components loss MOSFETs: conduction loss transition loss. upper lower MOSFET, losses approximately given following: PUPPER IOUT TC)(RDS(ON))D (0.5)( IOUT)(VIN)( tSW)FS PLOWER IOUT TC)(RDS(ON))(1-D) Where IOUT load current temperature dependency RDS(ON) switching frequency switching interval duty cycle Note that both MOSFETs have conduction loss while upper MOSFET include additional transition loss. switching internal, function reverse transfer capacitance RSS. (1+TC) term
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VOUT IRIPPLE
where switching frequency regulator. Although increase inductor value reduces ripple current voltage, tradeoff will exist between inductor' ripple current regulator load transient response time. smaller inductor will give regulator faster load transient response expense higher ripple current. maximum ripple current occurs maximum input voltage. good starting point choose ripple current approximately maximum output current. Once inductance value been chosen, select inductor that capable carrying required peak current without going into saturation. some types inductors, especially core that made ferrite, ripple current will increase abruptly when saturates. This will result larger output ripple voltage. Output Capacitor Selection Higher capacitor value lower reduce output ripple load transient drop. Therefore, selecting high performance capacitors intended switching regulator applications. some applications, multiple capacitors have parallel achieve desired value. small decoupling capacitor parallel bypassing noise also recommended, voltage rating output capacitors also must considered. tantalum
Copyright ANPEC Electronics Corp. Rev. Mar., 2007
APW7065
Application Information (Cont.)
MOSFET Selection (Cont.) factor temperature dependency RDS(ON) extracted from "RDS(ON) Temperature" Compensation output filter step down converter introduces double pole, which contributes with -40dB/decade gain slope degrees phase shift control loop. compensation network among COMP, VOUT should added. compensation network shown Figure output filter consists output inductor output capacitors. transfer function filter given
Frequency(Hz) GAIN (dB) -40dB/dec
curve power MOSFET.
-20dB/dec
Figure Filter GAIN Frequency modulator shown Figure input output error amplifier output PHASE node. transfer function modulator given GAIN
Driver Comparator PHASE
GAIN
poles zero this transfer functions are:
FESR
Output Error Amplifier Driver
double poles filter, FESR zero introduced output capacitor.
Figure Modulator compensation network shown Figure provides close loop transfer function with highest zero crossover frequency sufficient phase margin. transfer function error amplifier given
PHASE
OUTPUT
COUT
Figure Output Filter
GAIN R1// COMP
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Copyright ANPEC Electronics Corp. Rev. Mar., 2007
APW7065
Application Information (Cont.)
Compensation (Cont.) poles zeros transfer function are:
Calculate equation: 0.75 4.Set pole zero frequency FESR: FESR Calculate equation:
FESR
5.Set second pole half switching frequency also second zero output filter double pole FLC. compensation gain should exceed error amplifier open loop gain, check compensation gain with capabilities error amplifier.
COMP
Combine equations will following component calculations:
Figure Compensation Network closed loop gain converter written GAINLC GAINPWM GAINAMP Figure shows asymptotic plot closed loop converter gain, following guidelines will help design compensation network. Using below guidelines should give compensation similar curve plotted. stable closed loop -20dB/ decade slope phase margin greater than degree.
GAIN (dB)
1.Choose value usually between 2.Select desired zero crossover frequency (1/5 1/10) >FO>FESR following equation calculate
20log (R2/R1)
20log
Compensation Gain
VOSC
3.Place first zero before output filter double pole frequency FLC. 0.75
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Filter Gain Frequency(Hz) Converter Gain
Figure Converter Gain Frequency
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APW7065
Application Information (Cont.)
Layout Considerations high switching frequency converter, correct layout important ensure proper operation regulator. With power devices switching 300KHz, resulting current transient will cause voltage spike across interconnecting impedance parasitic circuit elements. example, consider turn-off transition MOSFET. Before turn-off, MOSFET carrying full load current. During turn-off, current stops flowing MOSFET free-wheeling lower MOSFET parasitic diode. parasitic inductance circuit generates large voltage spike during switching interval. general, using short, wide printed circuit traces should minimize interconnecting impedances magnitude voltage spike. signal power grounds kept separate till combined using ground plane construction single point grounding. Figure illustrates layout, with bold lines indicating high current paths; these traces must short wide. Components along bold lines should placed lose together. Below checklist your layout: Figure 8.Layout Guidelines Keep switching nodes (UGATE, LGATE PHASE) away from sensitive small signal nodes since these nodes fast moving signals. Therefore, keep traces these nodes short possible. traces from gate drivers MOSFETs (UG, should short wide. Place source high-side MOSFET drain low-side MOSFET close possible. Minimizing impedance with wide layout plane between pads reduces voltage bounce node. Decoupling capacitor, compensation component,
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resistor dividers, boot capacitors should close their pins. (For example, place decoupling ceramic capacitor near drain high-side MOSFET close possible. bulk capacitors also placed near drain). input capacitor should near drain upper MOSFET; output capacitor should near loads. input capacitor should close output capacitor lower MOSFET GND. drain MOSFETs (VIN PHASE nodes) should large plane heat sinking.
APW7065 BOOT UGATE PHASE LGATE
VOUT
APW7065
Package Information
SOP-8 (Reference JEDEC Registration MS-012)
0.015X45
0.004max.
Millimeters Min. 1.35 0.10 4.80 3.80 5.80 0.40 0.33 1.27BSC Max. 1.75 0.25 5.00 4.00 6.20 1.27 0.51 Min. 0.053 0.004 0.189 0.150 0.228 0.016 0.013
Inches Max. 0.069 0.010 0.197 0.157 0.244 0.050 0.020 0.50BSC
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APW7065
Carrier Tape Reel Dimensions
Reel Dimensions
Application SOP-8 5.5± 12.4 2.1± 1.75±0.1 0.3±0.013
+1.5 12.75+ 0.15
1.55 +0.1 1.55+ 0.25
5.2±
(mm)
Cover Tape Dimensions
Application SOP- Carrier Width Cover Tape Width Devices Reel 2500
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APW7065
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material 90/10 63/37 SnPb), 100%Sn Meets Specification RSI86-91, ANSI/J-STD-002 Category
Reflow Condition
(IR/Convection Reflow)
Critical Zone
Ramp-up
Temperature
Tsmax
Ramp-down Preheat
Peak
Classification Reflow Profiles
Profile Feature Average ramp-up rate Preheat Temperature (Tsmin) Temperature (Tsmax) Time (min max) (ts) Time maintained above: Temperature (TL) Time (tL) Peak/Classification Temperature (Tp) Time within actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds table 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds table 20-40 seconds
6°C/second max. 6°C/second max. minutes max. minutes max. Time 25°C Peak Temperature Notes: temperatures refer topside package .Measured body surface.
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Copyright ANPEC Electronics Corp. Rev. Mar., 2007
APW7065
Classification Reflow Profiles (Cont.)
Table SnPb Entectic Process Package Peak Reflow Temperatures Package Thickness Volum Volum <350 <2.5 +0/-5°C +0/-5°C +0/-5°C +0/-5°C
Table Pb-free Process Package Classification Reflow Temperatures Package Thickness Volum Volum Volum <350 350-2000 >2000 <1.6 +0°C* +0°C* +0°C +0°C* +0°C* +0°C +0°C* +0°C* +0°C *Tolerance: device manufacturer/supplier shall assure process compatibility including stated classification temperature (this means Peak reflow temperature +0°C exam 260°C+0 rated level.
Reliability Test Program
Test item SOLDERABILITY HOLT Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD Description 245°C, 1000 Bias @125°C Hrs, 100%RH, 121°C -65°C~150°C, Cycles VHBM 2KV, 200V 10ms, 100mA
Customer Service
Anpec Electronics Corp. Head Office No.6, Dusing Road, SBIP, Hsin-Chu, Taiwan, R.O.C. 886-3-5642000 886-3-5642050 Taipei Branch 137, Lane 235, Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, 886-2-89191368 886-2-89191369
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