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APA2065

NoteBook PC LCD Monitor or TV

APA2065
Features
Low Operating Current with 14mA Improved Depop Circuitry to Eliminate Turn-on and Turn-off Transients in Outputs High PSRR 32 Steps Volume Adjustable by DC Voltage with Hysteresis 2W per Channel Output Power into 4 Load at 5V, BTL Mode Two Output Modes Allowable with BTL and SE Modes Selected by SE / BTL pin Low Current Consumption in Shutdown Mode (50µA) Short Circuit Protection Power Off Depop Circuit Integration DIP-16A Package Available Lead Free Available (RoHS Compliant)
General Description
Applications
NoteBook PC LCD Monitor or TV
APA2065
Ordering and Marking Information
APA2065 Lead Free Code Handling Code Temp. Range Package Code Package Code J : DIP-16A Temp. Range I : - 40 to 85 ° C Handling Code TU : Tube TR : Tape & Reel TY : Tray Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code
APA2065 J :
APA2065 XXXXX
Block Diagram
LOUT+ LIN-
RINVolume Control
LOUT-
BYPASS
ROUT+ VOLUME
ROUTSHUTDOWN
Shutdown ckt POW ER and Depop circuit
VDD GND
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APA2065
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol VDD VIN TA TJ TSTG TS VESD PD
Note :
Parameter Supply Voltage Range Input Voltage Range, SE / BTL, SHUTDOWN Operating Ambient Temperature Range Maximum Junction Temperature Storage Temperature Range Soldering Temperature, 10 seconds Electrostatic Discharge Power Dissipation
Rating -0.3 to 6 -0.3 to VDD+0.3 -40 to 85 Intermal Limited -65 to +150 260 -3000 to 3000 3 -200 to 200
Intermal Limited
Recommended Operating Conditions
Min. Supply Voltage, VDD High level threshold voltage, VIH Low level threshold voltage, VIL Common mode input voltage, VICM SHUTDOWN SE / BTL SHUTDOWN SE / BTL VDD-1.0 4.5 2 4 1.0 3 Max. 5.5 Unit V V V V
Thermal Characteristics
Symbol Parameter Thermal Resistance from Junction to Ambient in Free Air DIP-16A 45 ° C / W Value Unit
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APA2065
Electrical Characteristics
Maximum Output Power
THD+N Total Harmonic Distortion Plus Noise PSRR Power Ripple Rejection Ratio Xtalk S / N Channel Separation Signal to Noise Ratio
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APA2065
Pin Description
ROUT+ SHUTDOWN RINGND GND VOLUME LOUT+ LIN-
APA2065 DIP-16A
16 VDD 15 ROUT14 SE / BTL 13 GND 12 11 10 9 GND BYPASS LOUTVDD
Pin Function Description
Pin No 1 2 3 4, 5, 12, 13 6 7 8 9, 16 10 11 14 15 Name ROUT+ SHUTDOWN RINGND VOLUME LOUT+ LINVDD LOUTBYPASS SE / BTL ROUTI / P O / P O / P I / P O / P I / P O / P I / P I / P Right channel positive output in BTL mode and SE mode. It will be into shutdown mode when pull low. Right channel input terminal Ground connection, Connected to thermal pad. Input signal for internal volume gain setting. Left channel positive output in BTL mode and SE mode. Left channel input terminal Supply voltage for internal circuit excepting power amplifier. Left channel negative output in BTL mode and high impedance in SE mode. Bias voltage generator Output mode control input, high for SE output mode and low for BTL mode. Right channel negative output in BTL mode and high impedance in SE mode. Config. Description
Control Input Table
SE / BTL X L H SHUTDOWN L H H Operating mode Shutdown mode BTL out SE out
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APA2065
Typical Application Circuit
0.1µF VDD GND
100µF
1µF L-Ch input 1µF R-Ch input VDD
LOUT+ LIN220µF 1k RINVolume Control 4 LOUTSE / BTL Sleeve Control Pin Ring
2.2µF 50k BYPASS BYPASS
Tip ROUT+
Headphone Jack VDD 100k 100k Shutdown Signal SHUTDOWN Shutdown ckt VOLUME
220µF 1k
SE / BTL 4 ROUT-
Hysteresis(mV) 52 51 50 49 47 46 45 44 43 41 40 39 38 37
Recommended Voltage(V) 0 0.20 0.31 0.43 0.54 0.65 0.77 0.88 0.99 1.10 1.22 1.33 1.44 1.56 1.67
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APA2065
Typical Characteristics
THD+N vs. Frequency
THD+N vs. Output Power
0.01 10m 100m 1 2 3
Frequency (Hz)
Output Power (W)
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APA2065
Typical Characteristics
THD+N vs. Frequency
THD+N vs. Output Power
500 1k
0.01 100m
500m 800m
Frequency (W)
Output Power (W)
THD+N vs. Frequency
THD+N vs. Output Power
0.01 10m
Frequency (Hz)
Output Power (W)
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APA2065
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
0.01 10m
Frequency (Hz)
Output Power (W)
THD+N vs. Frequency
THD+N vs. Output Power
500 1k
0.01 10m
Frequency (Hz)
Output Power (W)
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APA2065
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
0.01 10m
Frequency (Hz)
Output Power (W)
THD+N vs. Frequency
THD+N vs. Output Swing
0.01 20 100 1k 20k
0.01 100m
Frequency (Hz)
Output Swing (VRMS)
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APA2065
Typical Characteristics (Cont.)
Crosstalk vs. Frequency
Crosstalk (dB)
R-ch to L-ch L-ch to R-ch
Frequency (Hz)
Noise Floor vs. Frequency
100u 50u
Noise Floor vs. Frequency
Noise Floor (µVRMS)
No Filter
A-Weight
10u 5u
No Filter
10u 5u
A-Weight
100 1k 20k
Frequency (Hz)
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APA2065
Typical Characteristics (Cont.)
Noise Floor vs. Frequency
Power Dissipation vs. Output Power
Power Dissipation (W)
Noise Floor (µVRMS)
20u 10u
No Filter
A-Weight
100 1k 20k
Frequency (Hz)
Output Power (W)
Power Dissipation vs. Output Power
Supply Current vs. Supply Voltage
Power Dissipation (W)
Suuply Current (mA)
No Load
Output Power (W)
Supply Voltage (V)
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APA2065
Typical Characteristics (Cont.)
Output Power vs. Supply Voltage
Output Power (mW)
Output Power (W)
Supply Voltage (V)
Output Power vs. Load Resistance
Output Power (W)
Load Resistance ()
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APA2065
Typical Characteristics (Cont.)
Close Loop Response
Loop Gain (dB)
Frequency (Hz)
PSRR vs. Frequency
Ripple Rejection Ratio (dB)
Frequency (Hz)
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APA2065
Application Descriptions
BTL Operation The APA2065 output stage (power amplifier) has two pairs of operational amplifiers internally, allowed for different amplifier configurations. Four times the output power same conditions. A BTL configuration, such as the one used in APA2065, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, no need DC voltage
Volume Control amplifier output signal
exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Single-Ended Operation
OUTOP2
Vbias Circuit
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APA2065
Application Descriptions (Cont.)
Output SE / BTL Operation (Cont.) · When SE / BTL is held high, the OP2 is in a high output impedance state, which configures the APA2065 as SE driver from OUT+. IDD is reduced by approximately one-half in SE mode. Control of the SE / BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application Circuit. VOLUME input pin. The APA2065 volume control consists of 32 steps that are individually selected by a variable DC voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from 20dB to -80dB. Each gain step corresponds to a specific input voltage range, as shown in table. To minimize the effect of noise on the volume control pin, which can affect the selected gain level, hysteresis and clock delay are implemented. The amount of hysteresis corresponds to half of the step width, as shown in volume control graph.
1k VDD 100k SE / BTL
Sleeve Control Pin Ring
Headphone Jack
Figure 2: SE / BTL input selection by phonejack plug In Figure 2, input SE / BTL operates as follows : When the phonejack plug is inserted, the 1k resistor is disconnected and the SE / BTL input is pulled high and enables the SE mode. When the input goes high, the OUT- amplifier is shutdown causing the speaker to mute. The OUT+ amplifier then drives through the output capacitor (CC) into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100k and 1k. Resistor 1k then pulls low the SE / BTL pin, enabling the BTL function. Volume Control Function APA2065 has an internal stereo volume control whose setting is a function of the DC voltage applied to the
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APA2065
Application Descriptions (Cont.)
Ri(k) 120 100 80 60 40 20
1 2x10kxFC
Consider to input resistance variation, the Ci is 0.16µF so one would likely choose a value in the range of 0.22µF to 1.0µF. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD / 2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor, Cbypass
Ri vs Gain(BTL)
0 -40 -30 -20 -10 0 10 20 Gain(dB)
As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitors located on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger bypass capacitor will improve PSRR due to increased supply stability. Typical applications employ a 5V regulator with 1.0µF and a 0.1µF bypass capacitor as supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2065. The selection of bypass capacitors, especially Cbypass, is thus dependent upon desired PSRR requirements, click and pop performance.
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APA2065
Application Descriptions (Cont.)
The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads.
For example, a 330µF capacitor with an 8 speaker would attenuate low frequencies below 60.6Hz.The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of C C are required to pass low frequencies into the load.
can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the
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APA2065
Application Descriptions (Cont.)
Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8 loads and a 5V supply, the maximum draw on the power supply is almost 3W. A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation, V DD is in the
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APA2065
Application Descriptions (Cont.)
For DIP-16A package with thermal pad, the thermal resistance (JA) is equal to 45C / W. Since the maximum junction temperature (TJ, MAX) of APA2065 is 150C and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation15. Once the power dissipation is greater than the maximum limit (P D, MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced.
Since the APA2065 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2065 does not require extra heatsink. The power dissipation from equation14,
APA2065
Packaging Information
DIP-16A ( Reference JEDEC Registration MS-001)
Millimeters Min. 0. 0.38 2.92 0.36 1.14 0.20 19.81 0.13 7.62 6.10 2.54 BSC 7.62 BSC 2.92 10.92 3.81 0.115 Max. 5.33 4.95 0.56 1.78 0.35 20.31 8.26 7.11 Min. 0.015 0.115 0.014 0.045 0.008 0.780 0.005 0.300 0.240
Inches Max. 0.210 0.195 0.022 0.070 0.014 0.800 0.325 0.280 0.100 BSC 0.300 BSC 0.430 0.150
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APA2065
Physical Specifications
Reflow Condition
(IR / Convection or VPR Reflow)
TP Ramp-up
tp Critical Zone T L to T P
Temperature
TL Tsmax
Tsmin Ramp-down ts Preheat
t 25 °C to Peak
Classificatin Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak / Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C / second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3°C / second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds See table 2 20-40 seconds
6°C / second max. 6°C / second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
APA2065
Classificatin Reflow Profiles(Cont.)
Reliability Test Program
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
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