-48V Programmable Swap Sequencing Power Controller FEATURES APPLI
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SMH4804
-48V Programmable Swap Sequencing Power Controller
FEATURES APPLICATIONS
INTRODUCTION
SMH4804 user-programmable -48V power supply controller designed control hot-swapping plug-in cards sequence supplies distributed power environment. SMH4804 drives external power MOSFET switch that connects side supply card side load controls in-rush current while providing both current regulation over-current protection. When source drain voltages external MOSFET within specification, SMH4804 asserts four PG[4:1]# power-good logic outputs either simultaneously sequenced programmable intervals enable DC-DC converters distribute card side power. Additional features device include: monitor, master enable temperature sense input (EN/ TS), 2.5V reference outputs expanding monitor functions, Pin-Detect enable inputs (PD1# PD2#) card insertion verification, duty-cycle latched over-current protection modes. features programmed nonvolatile registers through interface which simplified with SMX3200 interface adapter Windows software available from Summit Microelectronics. Engineers program device directly in-circuit with units voltage, current time, allowing fast design cycles.
Features:
Soft Starts Main Power Supply Card Insertion System Power In-Rush Current Limiting Master Enable Allow System Control Power Down Programmable Independent Control DC/DC Converters Power Good Signals, PG[4:1]# Highly Programmable Circuit Breaker Level Mode Programmable Quick-TripValue, Current Limiting, Duty Cycle Times, Over-Current Filter Programmable Host Voltage Fault Monitoring Programmable UV/OV Filter Hysteresis Programmable Fault Mode: Latched Duty Cycle Internal Shunt Regulator Allows Wide Supply Range (typically Volts) 2-Wire Serial Interface Programming, Power On/Off Operational Status
Applications:
Telecom Hot-Swap Card Distributed Power Architectures Power-on LAN, IEEE 802.3
SIMPLIFIED APPLICATION DRAWING
-48V (0V) Dual MMBD1401 -48V2 (Short Pins) -48V1 -48V 267K, 10K, 10K, 10K, 1/2W PD2# PD1# 5VREF 2.5VREF Vin+ Vout+ On/Off Vout- Vin5.0V
PG#1
SMH4804
DrainSense CBSense
PG#2
Vin+ Vout+ On/Off Vout- Vin3.3V
PG#3 VGate
PG#4
Note Vin+ Vout+ On/Off VoutVin2.5V
100nF
10nF
100K
-48V1 -48V2 100nF 0.02
100nF
MMBD1401 IRF1310N
Vin+ Vout+ On/Off VinVout-
1.8V
Note Safety isolation interface required. Apps Section.
Figure SMH4804 Simplified Application Diagram
SUMMIT Microelectronics, Inc. 2005 1717 Drive Jose 95131 Phone 436-9890 436-9897 www.summitmicro.com
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Functional Block Diagram
SMH4804
FUNCTIONAL BLOCK DIAGRAM
2.5VREF
ENPGA ENPGB ENPGC
PG4#
12VREF
PROGRAMMING STEERING LOGIC
PROGRAMMABLE DELAY
PG3#
200k 10µA PROG FILTER PROGRAMMABLE DELAY
EN/TS PD1# PD2#
PROGRAMMABLE DELAY
PG2#
PG1#
DRAIN SENSE
2.5V
MODE RESET#
PROGRAMMABLE DELAY 50mV
CBSENSE
Programmable Quick Response Ref. Voltage
Three DEVICE ADDRESS DECODE FILTER
OV/UV FILTER
5.0VREF
VGATE SENSE
VGATE
FAULT LATCH DUTY CYCLE TIMER
FAULT#
Programmable Shutdown Timer
2050
Figure SMH4804 Block Diagram 2050 10/13/05 Summit Microelectronics
SMH4804
Functional Description
FUNCTIONAL DESCRIPTION
SMH4804 integrated swap power controller operates within wide supply range, typically volts, generates signals necessary drive isolatedoutput DC/DC converters. general start-up procedure follows: physical connection must first made with chassis discharge electrostatic voltage potentials when typical add-in board inserted into powered backplane. board then contacts long pins backplane that provide power ground. soon power applied device starts does immediately apply power output load. Under-voltage over-voltage circuits inside controller verify that input voltage within userspecified range. SMH4804 senses PD1# PD2# detection signals indicate card seated properly. These requirements must Detect Delay period tPDD. Once this time elapsed, hot-swap controller enables VGATE turn external power MOSFET switch. VGATE output current limited IVGATE, allowing slew rate easily modified using external passive components. During controlled turn-on period MOSFET monitored drain sense input. When DRAIN SENSE drops below 2.5V, VGATE rises above VGT, SMH4804 asserts PG1# through PG4# power good outputs enable controllers. ENPGA, ENPGB, ENPGC Power Good Enable inputs used activate deactivate specific output loads. Steady-state operation maintained long conditions normal. following events cause device disable DC/DC controllers shutting down power MOSFET: under-voltage over-voltage condition host power supply. over-current event detected CBSENSE input failure power MOSFET sensed DRAIN SENSE pin. PD1#/PD2# detect signals becoming invalid. master enable (EN/TS) falls below 2.5V. input driven events secondary side DC/DC controllers. SMH4804 configured that after these events occurs, VGATE output shuts either latches into state, recycles power after cooling down period, tCYC. Summit Microelectronics
Powering
SMH4804 contains internal shunt regulator that prevents voltage from exceeding 12V. necessary dropper resistor (RD) between host power supply order limit current into device prevent possible damage. dropper resistor allows device operate across wide range system supply voltages, typically -72V, also helps protect device against common-mode power surges. Refer Applications Section help calculating resistance value.
Hot-Swap Verification
There several enabling inputs that allow host control SMH4804. Detect signals (PD1# PD2#) active enables that generally used indicate that add-in circuit card properly seated. These inputs must held pin-detect delay period tPDD before power-up sequence initiated. This typically done clamping inputs through implementation ejector switch, alternatively through staggered pins card-cage interface. detect delay (tPDD) timing parameter controlled bits register Refer Register Address 1001 page more information. shorter pins, arranged opposite ends connector, force card fully seated before both detects enabled. Care must taken exceed maximum voltage rating these pins during insertion process. Refer details Applications Section proper circuit implementation. Note that PD1# PD2# inputs enabled disabled using Register Refer Register Address 0011 page more information. EN/TS input provides active high comparator input that used master enable temperature sense input. This input signal must exceed 2.5V (nominal) proper operation. Refer Descriptions page more information.
Under-/Over-Voltage Sensing
Under-Voltage (UV) Over-Voltage (OV) inputs provide comparators that conjunction with external resistive divider ladder sense whether host supply voltage within user-defined limits. power-up sequence initiated when input rises above 2.5V input falls below
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Functional Description
2.5V period least tPDD (Pin Detect Delay time). tPDD filter helps prevent spurious start-up sequences while card being inserted. falls below 2.5V rises above 2.5V, PG[4:1]# VGATE outputs disabled immediately.
SMH4804
falling voltage compare level steps 62.5mV below 2.5V. rising voltage compare level fixed 2.5V. default under-voltage hysteresis level 62.5mV. default conditions SMH4804 under-voltage state once voltage rises above 2.5V; after that under-voltage occurrence recognized until voltage falls below 2.4375V (2.5V 62.5mV).
Under-/Over-Voltage Filtering
SMH4804 configured that out-oftolerance condition UV/OV does shut output immediately. Instead, filter delay inserted that only sustained under-voltage over-voltage conditions shut output. out-of-tolerance condition UV/OV longer than filter delay time (tUOFLTR Figure causes VGATE PG[4:1]# outputs shut when UV/OV filter option enabled using bits Register under-/over-voltage filtering feature disabled (bits default configuration. Refer Register Address 0100 page more information filter delay options. filters enabled disabled programming bits Register respectively. Refer Register Address 0110 page more information. Note that delay values Register only valid corresponding over under voltage filtering enabled using bits Register Figure shows timing under-/over-voltage filter.
Soft Start Slew Rate Control
Once preconditions powering DC/DC controllers have been explained previous sections, SMH4804 provides means soft start external power MOSFET. important limit in-rush current prevent damage add-in card disruptions host power supply. example, charging filter capacitance quickly (normally required input DC/DC controllers) generate very high current. VGATE output SMH4804 current limited IVGATE, allowing slew rate easily modified using external passive components. slew rate found dividing IVGATE gate-to-drain capacitance placed external FET.
Load Control Sequencing Secondary Supplies
PG1# through PG4# output pins used enable external DC/DC controllers. Once card inserted, SMH4804 samples PD1# PD2# detect input pins determine card been inserted properly. then monitors state input pins assure there under-voltage over-voltage condition present. Once these conditions met, EN/TS greater than 2.5V, SMH4804 asserts VGATE output turn external MOSFET. During time takes turn MOSFET SMH4804 monitors system over-current condition CBSENSE input pin. addition, device internally monitors voltage level VGATE output pin. This shown `VGATE Sense' block Figure Once power been ramped DC/DC controllers, conditions must before PG[4:1]# outputs enabled: DRAIN SENSE input voltage must below 2.5V. VGATE voltage must greater than VGT, where gate threshold. DRAIN SENSE input helps ensure that power MOSFET absorbing much steady state power from operating high VDS. This sensor remains active times (except when current regulation enabled). Summit Microelectronics
2.5V
tUOFLTR
FAULT#
2050 Fig07
Figure Under-/Over-Voltage Filter Timing
Under-/Over-Voltage Latching
additional option out-of-tolerance condition latch VGATE PG[4:1]# outputs such that return normal UV/OV operation does turn them back this case FAULT# output asserted.
Under-Voltage Hysteresis
Under-Voltage comparator input configured with programmable level hysteresis using Register
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SMH4804
VGATE sensor makes sure that power MOSFET operating well into saturation region before allowing loads switched Once VGATE reaches this sensor latched.
PG1#
Functional Description
tPGD
When external MOSFET properly switched PG[4:1]# outputs enabled. Output PG1# activated first, followed PG2# after delay tPGD, PG3# after another tPGD delay, PG4# after final tPGD delay. delays built into SMH4804 allow timed sequencing power loads. delay times programmable from 50µs 160ms using bits Register Register Refer Register Address 0011 page Register Address 1001 page more information. ENPGA, ENPGB, ENPGC input pins Figure used enabled PG[4:1]# outputs. ENPGA controls PG[4:2]# outputs. ENPGA deasserted external logic, SMH4804 disables PG[4:2]# outputs they enter high-impedance state. ENPGA input must asserted order PG[4:2]# driven SMH4804. ENPGB controls PG[4:3]# outputs. ENPGB deasserted external logic, SMH4804 disables PG[4:3]# outputs they enter high-impedance state. ENPGB input must asserted order PG[4:3]# driven SMH4804. ENPGC controls PG[4]# output. ENPGC deasserted external logic, SMH4804 disables PG[4]# outputs output enters high-impedance state. ENPGC input must asserted order PG[4]# driven SMH4804. This cascaded control mechanism useful enabling supplies that have dependencies based other voltages system. PG[4:1]# outputs have withstand capability, high voltages must connected these pins. Bipolar transistors opto-isolators used boost withstand voltage that host supply. Refer Figure connectivity information. Figure shows relationship between PG[4:1]# ENPG[C:A] signals.
ENPGA tPGD PG2#
ENPGB tPGD PG3#
ENPGC
PG4#
2050 Fig02
Figure Output ENPG Input Relationship
Forced Shutdown Secondary Feedback
Forced Shutdown signal (FS#) active input that provides method receiving feedback from secondary side DC/DC controllers. built-in shutdown timer allows SMH4804 ignore state input until timer period expires. timer period defined bits Register input must driven high this timer period. level this input causes Fault condition, driving FAULT# shutting VGATE PG[4:1]# outputs. purpose shutdown timer allow enough time devices secondary side DC/DC controllers power stabilize. This feature allows supervisory circuits such SMS44 control shutdown primary side soft start circuit, even though secondary side initially power. Alternatively, input programmed fourth ENPG input controlling PG1# output. This combined with option independently enable PG1# with affect other PG[4:2]# outputs, programmed PG1# enabling output other outputs.
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Functional Description
Circuit Breaker Operation
SMH4804 provides number circuit breaker functions protect against over-current conditions. sustained over-current event could damage host supply and/or load circuitry. board's load current passes through series resistor (RS) connected between MOSFET source (which tied CBSENSE) VSS. breaker trips whenever voltage drop across greater than 50mV more than tCBD programmable filter delay ranging from 10µs 500µs). circuit breaker cycle time controlled Register
RESET# TCBD CBSENSE
SMH4804
50mV
TPDD VGATE
TCBRST
Figure shows circuit breaker duty cycle operation with RESET# high.
2050 Fig04
Figure Circuit Breaker Reset with RESET#
Quick-TripCircuit Breaker
TCBD CBSENSE 50mV TCBD
TCYC VGATE
SMH4804 provides Quick-Tripfeature that causes circuit breaker trip immediately voltage drop across exceeds VQCB. Quick-Trip level 60mV, 100mV (default), 200mV, feature disabled. Refer bits Register Address 0010 page more information. Figure shows circuit breaker `Quick Trip' response.In this figure, voltage rises above VQCB, causing VGATE deasserted.
2050 Fig03
Figure Circuit Breaker Duty Cycle Operation with RESET# High Figure shows behavior VGATE CBSENSE immediately after RESET# deasserted. circuit breaker cycle time programmed value either seconds seconds depending system configuration. Refer Register Address 0100 page more information selecting circuit breaker cycle time.
<TCBD
VQCB 50mV
CBSENSE
TFSTSHTDN VGATE
2050 Fig05
Figure Circuit Breaker Quick Trip Response
Current Regulation
current regulation mode optional feature that provides means regulate current through MOSFET programmable period time using bits Register
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SMH4804
Current regulation generally enabled applications that have switched dual distributed power sources. using current regulation function, unwarranted shutdowns avoided dual supplies switched when more negative potential currently operating supply. When current regulation selected programming bits Register binary value ms), ms), (160 ms), enabled during soft-start (power period) during normal operation after PG[4:1]# outputs enabled. voltage monitored CBSENSE greater than 50mV, less than 60mV, SMH4804 reduces VGATE voltage order maintain CBSENSE potential less than 60mV, effectively regulating current through MOSFET. Figure Figure illustrate current regulation function. time period tPCR selectable maximum time during which regulation enforced. either VQCB tPCR exceeded VGATE PG[4:1]# outputs immediately deasserted. However, CBSENSE drops below 50mV before timer period ends, timer reset VGATE resumes normal operation (see Current Regulation With Recovery page Quick-Trip level exceeded, device bypasses current regulation timer shuts down immediately. current regulation feature disabled default configuration.
Functional Description
VQCB CBSENSE
tPCR
50mV VGATE
2050 Fig06b
Figure Current Regulation Without Recovery
Nonvolatile Fault Latch
SMH4804 provides optional nonvolatile fault latch (NVFL) circuit breaker feature. nonvolatile fault latch essentially provides programmable fuse circuit breaker. When latch enabled setting Register nonvolatile fault latch whenever circuit breaker trips. Once set, cannot reset cycling power through RESET# pin. Note: device remains disabled until Register reprogrammed. Refer Register Address 1100 page more information. long NVFL set, FAULT# output remains asserted. Nonvolatile Fault Latch feature disabled default configuration.
VQCB CBSENSE
<tPCR tPCR
50mV tCRD VGATE
Resetting FAULT#
When circuit breaker trips, VGATE output turned SMH4804 drives FAULT# low. There methods reset circuit breaker which selectable with MODE pin: When MODE held high left floating, circuit breaker duty-cycle mode. this case breaker resets automatically after time tCYC. When MODE held disabled Configuration Register) FAULT# reset bringing RESET# low. VGATE output attempts restart MOSFET slew control circuitry tPDD after bringing RESET# back high again. either case, cycling power board resets circuit breaker. over current condition still exists after MOSFET switches back circuit breaker will re-trip.
2050 Fig06a
Figure Current Regulation With Recovery
Summit Microelectronics
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Functional Description
Serial Interface
SMT4804 uses industry standard I2C, 2-wire serial data interface. This interface provides access configuration registers nonvolatile fault latch. interface three address inputs allowing eight devices same bus. This allows multiple devices same board multiple boards system controlled with signals; SCL. Device configuration utilizing Windows based SMT4804 graphical user interface (GUI) highly recommended. software available from Summit website (www.summitmicro.com). Using conjunction with this datasheet, simplifies process device prototyping interaction various functional blocks. programming Dongle (SMX3200) available from Summit communicate with SMT4804. Dongle connects directly parallel port programs device through cable using protocol.
SMH4804
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Summit Microelectronics
SMH4804
Package Configurations
PACKAGE CONFIGURATIONS PACKAGE CONFIGURATIONS
28-Pin SOIC
DRAIN SENSE VGATE EN/TS PD1# PD2# FAULT# RESET# MODE CBSENSE
PG4# PG2# PG1# PG3# ENPGA ENPGB ENPGC 2.5VREF 5VREF
2050 SOIC PCon
Figure 28-Pin SOIC Package Pinout
48-Pin TQFP
DRAIN SENSE
VGATE
PG4#
PG2#
EN/TS PD1# PD2# FAULT# RESET# MODE
PG1# PG3# ENPGA ENPGB ENPGC 2.5VREF 5VREF
CBSENSE
2050 TQFP PCon
Figure 48-Pin TQFP Package Pinout1
unnamed pins this package no-connects.
Summit Microelectronics 2050 10/13/05
Descriptions
SMH4804
DESCRIPTIONS Table provides type, name, description SMH4804 pins. numbers provided both 28-pin SOIC 48-pin TQFP packages.
Number (28-Pin SOIC) Number (48-Pin TQFP) Type (I/O) Name Description
DRAIN SENSE
DRAIN SENSE input monitors voltage drain external power MOSFET switch with respect VSS. internal 10µA source pulls DRAIN SENSE signal towards reference level. DRAIN SENSE must held below 2.5V enable PG[4:1] outputs. input works conjunction with inputs. Together these inputs used decoding multiple devices serial bus. input internal pull-up VGATE output activates external power MOSFET switch. This signal supplies constant current output (100µA typical), which allows easy adjustment MOSFET turn slew rate. Enable/Temperature Sense input master enable input. EN/TS less than 2.5V, VGATE disabled. This internal 200K pull-up PD1# works conjunction with PD2# optionally enable VGATE PG[4:1]outputs when they VSS. This internal pull-up PD2# works conjunction with PD1# optionally enable VGATE PG[4:1]# outputs when they VSS. This internal pull-up FAULT# open-drain, active-low output that indicates fault status device. RESET# used clear latched fault conditions. When this asserted, VGATE PG[4:1]# outputs disabled. Refer section Circuit Breaker Operation more information. This internal pull-up bidirectional serial data port. This internal pull-up state MODE signal determines fault conditions cleared. device latched mode when this low, cycle mode when high floating.
VGATE
EN/TS
PD1#
PD2#
FAULT# RESET#
MODE
Table SMH4804 Descriptions 2050 10/13/05 Summit Microelectronics
SMH4804
Number (28-Pin SOIC) Number (48-Pin TQFP) Type (I/O) Name
Descriptions
Description
CBSENSE
serial clock input. This internal pull-up circuit breaker sense input used detect overcurrent conditions across external, value sense resistor (RS) tied series with Power MOSFET. voltage drop greater than 50mV across resistor longer than tCBD trips circuit breaker. programmable Quick-Tripsense point also available. input works conjunction with inputs. Together these inputs used decoding multiple devices serial bus. input internal pull-up This connected negative side supply. used under-voltage supply monitor, typically conjunction with external resistor ladder. VGATE disabled less than 2.5V. Programmable internal hysteresis available input, adjustable increments 62.5mV. Also available filter delay input. input works conjunction with inputs. Together these inputs used decoding multiple devices serial bus. input internal pull-up used over-voltage supply monitor, typically conjunction with external resistor ladder. VGATE disabled greater than 2.5V. filter delay available input. Forced Shutdown (FS#) active input that causes VGATE PG[4:1]# outputs shut down time after internal shutdown timer expired. shutdown timer allows supervisory circuits secondary side (which powered initially) control shut down SMH4804 opto-isolator. This input pull-up resistor. This precision output reference voltage that used expand logic input functions SMH4804. output reference voltage with respect VSS. This precision 2.5V output reference voltage that used expand logic input functions SMH4804. output reference voltage with respect VSS.
5VREF
2.5VREF
Table SMH4804 Descriptions (Continued)
Summit Microelectronics
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Descriptions
Number (28-Pin SOIC) Number (48-Pin TQFP) Type (I/O) Name Description
SMH4804
ENPGC
active-high ENPGC input controls PG4# output. When ENPGC low, PG4# output immediately placed high-impedance state. When ENPGC high, left floating, PG4# driven time period tPGD after PG3# asserted. This internal pull-up active-high ENPGB input controls PG3# PG4# outputs. When ENPGB low, PG3#, PG4# outputs immediately placed highimpedance state. When ENPGB high, left floating, PG3# driven time period tPGD after PG2# asserted. This internal pull-up active-high ENPGA input controls PG2#, PG3#, PG4# outputs. When ENPGA low, PG2#, PG3#, PG4# outputs immediately placed high-impedance state. When ENPGA high, left floating, PG2# driven time period tPGD after PG1# asserted. This internal pull-up PG3# output open-drain, active signal with internal pull-up resistor. This used switch load enable DC/DC converter. PG1# enabled immediately after VGATE reaches DRAIN SENSE voltage less than 2.5V. Each successive PGn# output (PG2# PG3# PG4#) enabled tPGD after predecessor, provided that ENPGx inputs high. voltage this cannot exceed relative VSS. ENPGx refers ENPGA, ENPGB, ENPGC inputs. PG1# output open-drain, active signal with internal pull-up resistor. This used switch load enable DC/DC converter. PG1# enabled immediately after VGATE reaches DRAIN SENSE voltage less than 2.5V. Each successive PGn# output (PG2# PG3# PG4#) enabled tPGD after predecessor, provided that ENPGx inputs high. voltage this cannot exceed relative VSS. ENPGx refers ENPGA, ENPGB, ENPGC inputs.
ENPGB
ENPGA
PG3#
PG1#
Table SMH4804 Descriptions (Continued)
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SMH4804
Number (28-Pin SOIC) Number (48-Pin TQFP) Type (I/O) Name
Descriptions
Description
PG2#
PG2# output open-drain, active signal with internal pull-up resistor. This used switch load enable DC/DC converter. PG1# enabled immediately after VGATE reaches DRAIN SENSE voltage less than 2.5V. Each successive PGn# output (PG2# PG3# PG4#) enabled tPGD after predecessor, provided that ENPGx inputs high. voltage this cannot exceed relative VSS. ENPGx refers ENPGA, ENPGB, ENPGC inputs. PG4# output open-drain, active signal with internal pull-up resistor. This used switch load enable DC/DC converter. PG1# enabled immediately after VGATE reaches DRAIN SENSE voltage less than 2.5V. Each successive PGn# output (PG2# PG3# PG4#) enabled tPGD after predecessor, provided that ENPGx inputs high. voltage this cannot exceed relative VSS. ENPGx refers ENPGA, ENPGB, ENPGC inputs. This positive supply input. internal shunt regulator limits voltage this approximately with respect VSS. resistor must placed series with limit regulator current application illustrations).
PG4#
Table SMH4804 Descriptions (Continued)
Summit Microelectronics
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Absolute Maximum Ratings
SMH4804
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Ambient) -40o +85o Supply Voltage(VDD) (IDD mA). Package Thermal Resistance (JA) 28-pin SOIC 79oC/W Package Thermal Resistance (JA) 48-pin TQFP. 80oC/W Moisture Classification Level (MSL J-STD-020 Reliability Characteristics Data Retention. Years Endurance1 100,000 Cycles
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias. -55°C 125°C Power Supply Current (IDD) Storage Temperature -65°C 150°C Lead Solder Temperature seconds) Terminal Voltage with Respect VSS: VGATE 0.3V MODE, RESET, ENPGA, ENPGB, ENPGC, FS#, SDA, SCL. -0.3 PD1#, PD2#, VDD, CBSENSE, DRAIN SENSE, EN/TS, FAULT#, PG1#, PG2#, PG3#, PG4# -0.3 +15V Open Drain Output Short Circuit Current.100 Junction Temperature .150o Rating JEDEC .2000V Latch-Up testing JEDEC.± 100mA Stresses listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
Guaranteed Design
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SMH4804
Operating Characteristics
OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise notes. voltages relative GND.)
Symbol Parameter Conditions Unit
5VREF ILOAD5 2.5VREF ILOAD2.5 IDD1 VUVHYST VOVHYST VGATE IGATE VSENSE ISENSE VQCB
Supply voltage reference output voltage reference output current 2.5V reference output voltage 2.5V reference output current Power supply current Under-voltage threshold Under-voltage hysteresis Over-voltage threshold Over-voltage hysteresis VGATE output voltage VGATE output current DRAIN SENSE threshold DRAIN SENSE current output Circuit breaker threshold Programmable Quick Trip circuit breaker threshold voltage
2.45 -0.5
5.00
5.25
2.50
2.55
IGATE VGATE VSENSE
2.45
2.50
2.55
2.45
2.50
2.55
2.45 2.40 2.50 2.45 -0.1
2.55 2.50
VENTS VENTSHYST
EN/TS threshold voltage EN/TS threshold hysteresis voltage Input voltages: ENPGA/B/C, MODE, RESET#, PD1#, PD2# Output voltage: FAULT# Output voltage: PG1#/2#/3#/
5VREF
Input current: PD1#, PD2#, Gate threshold
This value resistor. Table listing programmable under-voltage hysteresis settings.
Summit Microelectronics
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Operating Characteristics
SMH4804
OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise notes. voltages relative GND.)
Symbol Description Conditions Unit Comment
tCBD tCBD Programmable Over-Current Filter tCBD tCBD tCBD tPGD tPGD tPGD tPGD Programmable power good delay (PG1 PG2, PG3, PG4) tPGD 1000 tPGD tPGD tCBD
Figure Figure Figure Figure Figure Figure Figure Figure
tPGD tPGD tPGD tQTSD tCYC tCBRST Quick-Trip shutdown Circuit breaker cycle mode cycle time CBRESET pulse width tPUVF tPUVF Programmable under-voltage filter
tCYC tCYC
tCYC
tPUVF tPUVF tPUVF tPDD
tPUVF
tPDD
Programmable detect
tPDD tPDD
tPDD
Figure Figure
tPDD
Indicates default value
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SMH4804
Characteristics
2-Wire Serial Interface Operating
2-WIRE SERIAL INTERFACE OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise notes. voltages relative GND.)
Symbol Parameter Conditions Units
fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT
clock frequency Clock period Clock period high free time1 Before transmission Start condition setup time Start condition hold time Stop condition setup time Clock edge valid output Data hold time rise time1 fall Data setup time Data hold time Noise filter Write cycle time SDA1 Noise suppression time1 valid (cycle (cycle n+1) change
1000
Values guaranteed design.
TIMING DIAGRAM Figure shows timing diagram Interface Memory timing. table above lists timing parameters Figure data transferred during each clock pulse. Note that data must remain stable when clock high.
tHIGH
tLOW
tSU:SDA tHD:DAT tSU:DAT tSU:STO
tHD:SDA
tBUF
2050 Fig09
Figure Interface Memory Timing Summit Microelectronics 2050 10/13/05
Timing Diagram
Power-on Timing
SMH4804
Figure illustrates some power sequences, including differentials their reference, Power Good cascading. Refer table page more information tPDD tCBD timings.
<tPUVF
2.5VREF
PD1#/ PD2#
tPDD
VGATE Note 'Fault' condition
caused Drain Sense high.
DRAIN SENSE
2.5VREF
50mVREF CBSENSE <tCBD tPGD PG1# tPGD PG2# tPGD PG3#
PG4#
2050 Fig01
Figure SMH4804 Power-On Sequences
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SMH4804
Timing Diagram
SMH4804 Power-On Waveforms -48V
Tektronix TDS3054: Time/Horizontal division 40mS
(2V/Div) 3.3V DC-DC converter output (Yellow trace) (50V/Div) PG#2 output (Blue trace) Note (50V/Div) Switched supply voltage (Purple trace) (2A/Div) Inrush input current (Green)
Note After initial swap conditions met, outputs first drop -43V until ready sequence DC-DC converter. When ready sequence, outputs then drop additional enable converters.
SMH4804 Sequencing waveforms
Four DC/DC converters sequenced 160ms intervals
Tektronix TDS3054: Time/Horizontal division 100mS
(1V/Div) 5.0V DC-DC converter output (Yellow trace) (1V/Div) 3.3V DC-DC converter output (Yellow trace) (1V/Div) 2.5V DC-DC converter output (Yellow trace) (1V/Div) 1.8V DC-DC converter output (Yellow trace)
SMH4804 with 0.1uF 0.01uF Soft-Start Capacitors
Tektronix TDS3054: Time/Horizontal division 40mS
(50V/Div) MOSFET Drain (Yellow trace) (5V/Div) SMH4804 (Blue trace) (10V/Div) MOSFET Gate (Purple trace) (2A/Div) -48V Inrush input current (Green)
SMH4804 with 0.1uF Soft-Start Capacitors
Tektronix TDS3054: Time/Horizontal division 200mS
(50V/Div) MOSFET Drain (Yellow trace) (5V/Div) SMH4804 (Blue trace) (10V/Div) MOSFET Gate (Purple trace) (2A/Div) -48V Inrush input current (Green)
Summit Microelectronics
2050 10/13/05
Timing Diagram
Operating High Voltages
breakdown voltage external active passive components limits maximum operating voltage SMH4804 hot-swap controller. Components that must able withstand full supply voltage are: input output decoupling capacitors, protection diode series with DRAIN SENSE pin, power MOSFET switch capacitor connected between drain gate, high-voltage transistors connected power good outputs, dropper resistor connected controller's pin.
SMH4804
Next minimum current that flows through resistive divider, IDMIN, calculated from ratio minimum maximum supply voltage levels:
IDMIN
Substituting:
IDMAX VSMIN VSMAX
IDMIN
250µA
Over-Voltage Under-Voltage Resistors
Figures three resistors (R1, connected inputs must capable withstanding maximum supply voltage several hundred volts. trip voltage inputs 2.5V relative VSS. input impedance very high, large value resistors used resistive divider. divider resistors should high stability, metal-film resistors keep under-voltage over-voltage trip points accurate.
value calculated from IDMIN:
VSMIN IDMIN
under-voltage trip point, also 2.5V. Substituting:
2.5V
Telecom Design Example
hot-swap telecom application power supply with -25% +50% tolerance (i.e., supply vary from 72V). formula calculating follows. First, peak current, IDMAX, must specified resistive network. value current arbitrary, cannot high (self-heating becomes problem), (the value becomes very large, leakage currents reduce accuracy trip points). value IDMAX should 200µA best accuracy trip points. value 250µA IDMAX used illustrate following calculations. With (2.5V) being over-voltage trip point, calculated formula:
closest standard resistor value Then calculated:
Substituting:
2.5V
Excel spread sheet available Summit's website (www.summitmicro.com) simplify resistor value calculations tolerance analysis
IDMAX
Substituting:
Dropper Resistor Selection 2.5V 250µA
SMH4804 powered from high-voltage supply dropper resistor, dropper resistor must provide SMH4804 (and loads) with sufficient operating current under minimum supply voltage conditions, must
2050 10/13/05
Summit Microelectronics
SMH4804
allow maximum supply current exceeded under maximum supply voltage conditions. dropper resistor value calculated from:
Timing Diagram
worst case condition 85°C ambient. Using resistor gives: VDS(ON)THRESHOLD 2.5V (15µA 68k) 0.5V
VSMIN VDDMAX ILOAD
where VSMIN lowest operating supply voltage, VDDMAX upper limit SMH4804 supply voltage, minimum current required SMH4804 operate, ILOAD additional load current from 2.5V outputs between VSS. Calculate minimum wattage required from:
voltage drop across MOSFET switch sense resistor, VDSS, calculated from: VDSS RON)
where MOSFET drain current, circuit breaker sense resistor MOSFET resistance. dropper resistor value should chosen such that minimum maximum specifications SMH4804 maintained across host supply's valid operating voltage range. First, subtract minimum SMH4804 from voltage, divide minimum value. Using this value resistance find operating current that would result from running high supply voltage verify that resulting current less than maximum current allowed. some range supply voltage chosen that would cause maximum specification violated, then external zener diode with breakdown voltage ~12V should used across VDD. example choosing proper value, assume host supply voltage ranges from 72V. largest dropper resistor that used (36V-11V)/3mA 8.3k. Next, confirm that this value also works high end: (72V-13V)/8.3k 7.08mA, which less than 8mA. input also used conjunction with secondary-side supervisory circuit providing positive feedback loop during power sequence. example, assume SMH4804 configured turn -48V three DC/DC converters then sequentially turn converters with 1.6ms delay. Further assume enable inputs true PG4# just been sequenced option (100BIN register been selected, then must driven high within 1.6ms after PG4# goes low, otherwise PG[4:1]# outputs disabled. Ideally, there would secondary-side supervisor similar SMS44 that would have reset time-out period programmed less than 1.6ms. After last supply turns RESET# output SMS44 would released pulled high. However, reason
(VSMAX VDDMIN)2
where VDDMIN lower limit SMH4804 supply voltage, VSMAX highest operating supply voltage. circumstances where input voltage swing over wide range (e.g., from 100V) maximum current exceeded. these circumstances necessary Zener diode between handle wide current range. Zener voltage should below nominal regulation voltage SMH4804 that becomes primary regulator.
MOSFET VDS(ON) Threshold
drain sense input SMH4804 monitors voltage drain external power MOSFET switch with respect VSS. When MOSFET's below userdefined threshold MOSFET switch considered VDS(ON)THRESHOLD adjusted using resistor, series with drain sense protection diode. This protection, blocking, diode prevents high voltage breakdown drain sense input when MOSFET switch OFF. leakage MMBD1401 diode offers protection 100V. high voltage applications 500V) Central Semiconductor CMR1F-10M diode should used. VDS(ON)THRESHOLD calculated from: VDS(ON)THRESHOLD VSENSE (ISENSE VDIODE
where VDIODE forward voltage drop protection diode. VDS(ON)THRESHOLD varies over temperature temperature dependence VDIODE ISENSE. calculation below gives VDS(ON)THRESHOLD under
Summit Microelectronics
2050 10/13/05
Timing Diagram
supplies turn RESET# released SMH4804 disables PG[4:1]# outputs. This termination timer function programmed abort sequence after PG1#, PG2#, PG3# PG4#.
SMH4804
secondary-side voltages. SMH4804 Quad Swap Controller easily configured independent on/off control individual DC-DC converters. simplified schematic displaying SMH4804 enable pins together with their respective output enabling pins shown Figure SMH4804 asserts each output enabling pins (PG[4:1]#) independently another shown Figure Applying logic high (3.5V `ENABLE_PGx#' nodes forces corresponding output logic low. example, turn first DC-DC converter (assuming Enable requires turn on), `ENABLE_PG1#' must high. Taking this node forces SMH4804 output high impedance (open-drain) state. Please refer Application Brief AB-01 more details.
Soft Start Slew Rate Control
-48V turn time controlled SMH4804 values Figures turn time approximately 10ms with component values shown Figure Increasing capacitance reduces output slew rate increases turn time. capacitors prevent MOSFET from turning simultaneously with application -48V. Resistor specified limit current into rate charge ratio (10:1) limits MOSFET's approximately once -48V supply connected fully charged.
Configuring SMH4804 Independent Control DC-DC Converters Power-onLAN IEEE 802.3
Certain systems employing live card insertion `hotswapping' require independent control individual
PG1# ENPGA PG2#
SMH4804
ENABLE PG1# DC-DC ENABLE PG1# DC-DC ENABLE PG1# DC-DC ENABLE PG1# DC-DC
ENPGA PG3# ENPGA PG4#
Figure Configuring SMH4804 Quad Independent Hot-Swap Controller.
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Summit Microelectronics
SMH4804
Timing Diagram
-48V (0V)
-48V (0V)
6.8k
2.5VREF
ENPGA
ENPGB
ENPGC
MMBTA06LT1
EN/TS
PG4#
100k PG3# PD1# PD2# FAULT# RESET# MODE
MMBTA06LT1
100k
SMH4804
PG2#
MMBTA06LT1
5VREF
100k
MMBTA06LT1
DRAIN SENSE
CBSENSE
PG1# MMBD1401
100nF 3.3nF
100nF
VGATE
10nF 100V
100nF
100µF 100V
MMBD1401
-48V
2050 Fig16
-48V
Figure Changing Polarity Power Good Output PG1# Notes: resistor must located close possible MOSFET. Optional bypass capacitor. larger value required zener must connected parallel. Optional interface circuit. PG[4:1]# outputs directly connected power module input voltage module within tolerance voltage PG[4:1]# outputs doesn't exceed 15V. DRAIN Sense function cause nuisance tripping voltage transients -48V line when using multiple lines. This avoided following methods: Disable function connecting DRAIN Sense directly. components eliminated. capacitor from DRAIN Sense VSS. exact capacitance value depends upon magnitude duration voltage transient appearing drain MOSFET.
Summit Microelectronics
2050 10/13/05
Timing Diagram
SMH4804
-48V (0V)
-48V (0V)
@TMAX
6.8k
100k
2.5VREF
ENPGA
ENPGB
ENPGC
LMV331
EN/TS
MMBTA06LT1
PG4#
100k PG3# PD1# PD2# FAULT# RESET# MODE 5VREF PG1# 100k MMBTA06LT1 100k MMBTA06LT1
SMH4804
PG2#
MMBTA06LT1
100k
DRAIN SENSE
CBSENSE
VGATE
100nF 3.3nF
100nF 10nF 100V
100nF
100µF 100V 100nF
MMBD1401
-48V
2050 Fig17
-48V
Figure Over-temperature Shutdown Notes: resistor (RG) must located close possible MOSFET. Optional bypass capacitor. larger value required Zener must connected parallel. Optional interface circuit. PG[4:1]# outputs directly connected power module input voltage module within tolerance voltage PG[4:1]# outputs doesn't exceed 15V. DRAIN Sense function cause nuisance tripping voltage transients -48V line when using multiple lines. This avoided following methods: Disable function connecting DRAIN Sense directly. components eliminated. capacitor from Drain Sense VSS. exact capacitance value depends upon magnitude duration voltage transient appearing drain MOSFET.
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Summit Microelectronics
SMH4804
Timing Diagram
-48V (0V)
6.8k
100k
ENPGA
ENPGB
ENPGC
EN/TS
PG4# MMBTA06LT1
+VIN +VOUT -VIN -VOUT ON/OFF
100k PG3# MMBTA06LT1
+VIN +VOUT -VIN -VOUT ON/OFF
ISOLATED OUTPUTS
SMH4804
PD1# PD2#
DRAIN SENSE CBSENSE
100k PG2# MMBTA06LT1
+VIN +VOUT -VIN -VOUT ON/OFF
VGATE
FAULT# RESET# MODE
5VREF PG1#
100k MMBTA06LT1
+VIN +VOUT -VIN -VOUT ON/OFF Converters with Active On/Off Control
100k
100nF 10nF 100V MMBD1401 100nF 100µF 100V
100nF 3.3nF
-48V
2050 Fig18
Figure Typical Application Sequencing Four DC/DC Converter Notes: resistor (RG) must located close possible MOSFET. Optional bypass capacitor. larger value required Zener must connected parallel. Optional interface circuit. PG[4:1]# outputs directly connected power module input voltage module within tolerance voltage PG[4:1]# outputs doesn't exceed 15V. DRAIN Sense function cause nuisance tripping voltage transients -48V line when using multiple lines. This avoided following methods: Disable function connecting DRAIN Sense directly. components eliminated. capacitor from DRAIN Sense VSS. exact capacitance value depends upon magnitude duration voltage transient appearing drain MOSFET.
Summit Microelectronics
2050 10/13/05
Timing Diagram
SMH4804
IRQ#
-48V (0V)
SMS44
5VREF
PGx#
DRAIN SENSE
SMH4804
CBSENSE VGATE
DC/DC
2050 Fig19
-48V
Figure Controlling with Secondary Feedback
CHASSIS CARD
-48V RTNRet -48V (0V)
PD1#
-48V1 (Short Pins) -48V2
PD1# PD2#
SMH4804
-48V
PD2#
-48V
-48V
Short Pins
2050 Fig20
Figure PD1# PD2# Inputs, Physical Offset
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Summit Microelectronics
SMH4804
Programming Information
PROGRAMMING INFORMATION I2CBus Interface
two-way, two-line serial communication between different integrated circuits. lines are: serial data line (SDA) serial clock line (SCL). SMH4804 supports clock rate. line must connected positive supply pull-up resistor located bus. SMH4804 contains Schmitt input both signals. Start Stop Conditions Both pins remain high when busy. Data transfers between devices initiated with Start condition only when high. highto-low transition while high defined Start condition. low-to-high transition while high defined Stop condition. Figure shows timing diagram start stop conditions. When last byte been transferred Master during read SMH4804, Master leaves high Acknowledge (NACK) cycle. This causes SMH4804 part stop sending data, Master issues Stop clock pulse following NACK. Figure shows Acknowledge timing.
Trans
2050 Fig11
Figure Acknowledge Timing Read Write first byte from Master always made 7-bit Slave address Read/Write (R/W) bit. tells Slave whether Master reading data from writing data Read, Write). first four seven address bits called Device Type Identifier (DTI). SMH4804 1010BIN. next three bits Address values multiple devices used). SMH4804 issues Acknowledge after recognizing Start condition DTI. Figure shows example typical master address byte transmission.
START Condition
STOP Condition
2050 Fig10
Figure Start Stop Conditions Master/Slave Protocol master/slave protocol defines device that sends data onto transmitter, device that receives data receiver. device controlling data transmission called Master, controlled device called Slave. cases SMH4804 referred Slave device since never initiates data transfers. Acknowledge Data always transferred bytes. Acknowledge (ACK) used indicate successful data transfer. transmitting device releases after transmitting eight bits. During ninth clock cycle Receiver pulls line acknowledge that received eight bits data. This shown callout Figure
2050 Fig12
Figure Typical Master Address Byte Transmission During read Master device, SMH4804 transmits eight bits data, then releases line, monitors line Acknowledge signal. Acknowledge detected, Stop condition generated Master, SMH4804 continues transmit data. Acknowledge detected (NACK), SMH4804 terminates subsequent data transmission. read transfer protocol shown Figure
Summit Microelectronics
2050 10/13/05
Programming Information
SMH4804
followed address word read. This procedure sets internal address counter SMH4804 desired address.
Master Slave
2050 Fig13
Figure Read Protocol During Master write, SMH4804 receives eight bits data, then generates Acknowledge signal. device continues generate condition until Stop condition generated Master. write transfer protocol shown Figure
After word address Acknowledge received Master, immediately reissues Start condition followed another Slave address field with Read. SMH4804 responds with Acknowledge then transmits data bits stored addressed location. this point, Master sets line NACK generates Stop condition. SMH4804 discontinues data transmission reverts standby power mode.
Sequential Reads
Master Slave
Sequential reads initiated either current address read random access read. first word transmitted with other byte Read modes (current address byte Read random address byte Read). However, Master responds with Acknowledge, indicating that requires additional data from SMH4804. SMH4804 continues output data each Acknowledge received. Master sets line NACK generates Stop condition. During sequential Read operation internal address counter automatically incremented with each Acknowledge signal. Read operations address bits incremented, allowing entire array read using single Read command. After count last memory address address counter rolls over memory continues output data.
2050 Fig14
Figure Write Protocol
Random Access Read
Random address read operations allow Master access memory location random fashion. This operation involves two-step process. First, Master issues Write command which includes Start condition Slave address field (with Write)
Master Slave
DEVICE IDENTIFIER
Typical Write Operation
ADDRESS
Master Slave
DEVICE IDENTIFIER
Typical Read Operation
ADDRESS
2050 Fig15
Figure Sequential Cycles
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Summit Microelectronics
SMH4804
Register Access
SMH4804 contains 2-wire interface register access explained previous section. This highly configurable, while maintaining industry standard protocol. SMH4804 responds selectable Device Type Addresses: 1010BIN, generally assigned NVmemories, 1011BIN, which default address SMH4804. Device Type Address assigned programming Register Register accesses also programmable using bits Register Accesses denied reads writes), read only, read/write (default state). SMH4804 three address pins, A[2:0], associated with 2-wire bus. SMH4804 configured respond only proper serial data string Device Type Address specific addresses (Register set). Device Type Address address (Register cleared).
-48V
Programming Information
view straight 0.1" 0.1" closed side connector SMX3200 interface Reserved Reserved Reserved Pin5, Reserved Pin3,
-48V (0V)
SMH4804
0.01µF
2050 Fig08
Figure SMH4804 Programming Connection Caution: Damage occur when connecting dongle system utilizing earth-connected positive terminal. Master/Slave Protocol master/slave protocol defines device that sends data onto transmitter device that receives data receiver. device controlling data transmission called Master controlled device called Slave. SMH4804 always Slave device, since never initiates data transfers. data transferred during each clock pulse. data line must remain stable during clock high time, because change data line while high interpreted either Start Stop condition.
Development Hardware Software
user Summit SMX3200 programming cable software connect board containing SMH4804 personal computer. Figure board connections. programming cable interfaces directly between PC's parallel port 10-pin connector shown Figure application's values entered intuitive graphical user interface employing drop-down menus. After desired settings application determined software generates file that written SMH4804. This file contains customer part number used customize devices during final electrical test operations. Figure shows diagram SMH4804 programming connections.
Register Maps
SMH4804 eight user programmable, nonvolatile, configuration registers. Although 8-bit data transfers used reading writing registers, only lease significant bits each register utilized device. Therefore, each following registers, bits left blank. Bits used shown each register.
Summit Microelectronics
2050 10/13/05
Default Configuration Register Settings SMH4804F-019
SMH4804
DEFAULT CONFIGURATION REGISTER SETTINGS SMH4804F-019
Register
Contents
Description
Over-current delay Quick-Trip over-current reference level. Power-good sequencing delay, mode enable, PD[2:1]# pin-detect enable. PG[4:1]# Power-good sequence enable, over/under voltage filter delay, circuit breaker cycle time. Non-volatile fault latch enable, forced shutdown function control. Under-voltage filter enable, over-voltage filter enable, VGATE current regulation control 320ms. Under-voltage hysteresis control. control, including device type address, configuration register status, slave address response control. Power-good sequence speed, PD[2:1]# detect delay time. Non-volatile fault latch. hardware when fault detected. Table SMH4804 Default Register Settings
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Summit Microelectronics
SMH4804
Registers
REGISTERS
Register Address 0010
This register used select both over-current delay quick trip threshold electronic circuit breaker.
Bits Default Description
0b01 0b10
Over-current delay Over-current delay Over-current delay Over-current delay Quick Trip reference voltage Quick Trip reference voltage Quick Trip reference voltage Quick Trip reference voltage off. Table Register Bitmap
Summit Microelectronics
2050 10/13/05
Registers
Register Address 0011
SMH4804
This register used control sequencing delays from PG1# PG2#, PG2# PG3#, PG3# PG4#. SMH4804 provides levels sequencing delay: fast slow, which selected programming Register These bits effectively concatenated with providing programmable delay periods. Refer Register more information. NOTE controls effect MODE pin. When (high) functions described descriptions. cleared (low) state ignored circuit breaker enters latch mode. enables disables function PD[4:1]# inputs.
Bits
Default
Description
Register 0b00 PG[4:1]# Sequencing delay: 1500 PG[4:1]# Sequencing delay: PG[4:1]# Sequencing delay: PG[4:1]# Sequencing delay: Register 0b00 PG[4:1]# Sequencing delay: PG[4:1]# Sequencing delay: PG[4:1]# Sequencing delay: PG[4:1]# Sequencing delay: Register When cleared (0), MODE MODE disabled (see NOTE above). When (1), MODE enabled (see NOTE above). When cleared, PD1# PD2# signals disabled. When set, PD1# PD2# signals enabled. Table Register Bitmap
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Summit Microelectronics
SMH4804
Register Address 0100
Registers
Register enables PG[4:1]# signal sequencing, sets voltage filter timing, selects circuit breaker cycle time. this register enables disables PG[4:1]# sequence delays. When set, delays defined registers cleared, delay incurred sequencing based solely state ENPGA#, ENPGB#, ENPGC# inputs. ENPGx# inputs tied high, PG[4:1]# outputs turn simultaneously.
Bits Default Description
0b00
When cleared, PG[4:1]# signal sequencing simultaneous. When set, PG[4:1]# signal sequencing enabled. When bits 0b00, over/under voltage filter off. When bits 0b01, over/under voltage delay When bits 0b10, over/under voltage delay When bits 0b11, over/under voltage delay
When cleared, circuit breaker cycle time sec. When set, circuit breaker cycle time sec. Table Register Bitmap
Summit Microelectronics
2050 10/13/05
Registers
Register Address 0101
SMH4804
Register controls function nonvolatile fault latch provides general control input. controls enabling non-volatile latch. Bits configure input. basic functions: programmed auxiliary enable input controlling PG1# output, programmed event monitor during power-up sequence. These bits also control interrelationship PG[4:1]# outputs. cascade operating mode PG1# must true before PG2# true, etc. This interrelationship disabled that each PG[4:1]# output effectively controlled corresponding ENGPx# input, long primary supply, VGATE DRAIN SENSE pins within their operating limits. When programmed enable PG1# there options: 010BIN disables cascade mode (the PG[4:1]# outputs independently) effectively becomes enable input PG1#; 011BIN enables cascade mode makes enable input PG1#. this mode, PG1# must active before PG2# activated, followed PG3#, then PG4#. event monitor mode generally implemented conjunction with monitoring device secondary side DC/DC converters, such SMS44, SMT4004 SMS64. pulled high before programmed condition then PG[4:1]# VGATE outputs shut down. example, binary value 111BIN, VGATE PG1# shut down pulled high before tPGD elapsed after PG1# true. None other PG[4:1]# outputs activated. failure occurs lapse event monitor timer, cycling power resets device.
Bits
Default
Description
When cleared, non-volatile latch enabled. When set, non-volatile latch disabled. When bits 0b000, function: tPGD cascade disabled simultaneous assertion PG[4:1]# pins. When bits 0b001, function disabled (=1). When bits 0b010, function active (=1) before enabled. Cascade disabled simultaneous assertion PG[4:1]# pins.
0b100
When bits 0b011, function must high (deasserted) before enabled. function: tPGD Delay) function: tPGD Delay) function: tPGD Delay) function: tPGD Delay) Table Register Bitmap
2050 10/13/05
Summit Microelectronics
SMH4804
Registers
last event mode, 000BIN, disables cascade effect sets PG4# going true trigger event. must pulled high before tPGD elapses, VGATE PG[4:1]# outputs disabled. Cascade enabled: ENPGA enables PG2#, PG3# PG4#; ENPGB enables PG3# PG4#; ENPGC enables PG4#. Cascade disabled: ENPGA enables PG2#; ENPGB enables PG3#; ENPGC enables PG4#. Simultaneous: PG1#, PG2#, PG3# PG4# operate independently from another. Sequenced: PG1#, PG2#, PG3# PG4# dependent upon activation PG(N-1) plus programmable delay.p=On
Summit Microelectronics
2050 10/13/05
Registers
Register Address 0110
SMH4804
This register enables what events recorded nonvolatile fault latch cleared. high order bits this register control whether under over voltage pins filtered, order bits program current regulation time period.
Bits Default Description
When cleared, under voltage filtered. When set, under voltage filtered. When cleared, over voltage filtered. When set, over voltage filtered. When bits 0b00, current regulation turned off.
0b00
When bits 0b01, current regulation When bits 0b10, current regulation When bits 0b11, current regulation Table Register Bitmap
Register Address 0111
This register controls hysteresis. values shown with respect VSS.
Bits Default Description
this register, always set. When bits 0b000, hysteresis volts. When bits 0b001, hysteresis 0.0625 volts. When bits 0b010, hysteresis 0.125 volts.
0b001
When bits 0b011, hysteresis 0.1785 volts. When bits 0b100, hysteresis 0.250 volts. When bits 0b101, hysteresis 0.3125 volts. When bits 0b110, hysteresis 0.375 volts. When bits 0b111, hysteresis 0.4375 volts. Table Register Bitmap
2050 10/13/05
Summit Microelectronics
Register Address 1000
This register used control interface activity. determines Device Type Address, bits select register access capability, determines whether device must receive address that corresponds biasing address pins. Note: fault latch option selected write access denied SMH4804 cannot cleared fault condition.
Bits Default Description
When cleared, device type address 1011. When set, device type address 1010. When bits 0b00, Configuration registers read/write (R/W).
0b00
When bits 0b01, Configuration registers read-only (RO). When bits 0b10 0b11, access Configuration registers disabled. When cleared, SMH4804 responds address pins. When set, SMH4804 responds address address polarities (A0,A1 A2). Table Register Bitmap
Summit Microelectronics
Registers
Register Address 1001
SMH4804
this register, works conjunction with Register bits Refer Register description details. sets UV/OV conditions either latched latched. Bits select delay from point where both PD[2:1]# inputs initial power conditions) when sequencing commence.
Bits Default Description
When cleared, power good sequence Fast. When set, power good sequence Slow. When cleared, UV/OV conditions latched. When set, UV/OV conditions latched. When bits 0b00, delay
0b01
When bits 0b01, delay When bits 0b10, delay When bits 0b11, delay Table Register Bitmap
Register Address 1100
This register configuration register, rather nonvolatile fault latch (NVFL). circuit breaker fault condition detected NVFL enabled (Register cleared), Register automatically (written with logic `1') when circuit breaker trips. long remains set, SMH4804 able drive VGATE PG[4:1]# outputs. host service center must access register clear (write `0') once fault condition been resolved. also used nonvolatile Power on/off control power SMH4804 system through bus.
Bits Default Description
When cleared, fault latch cleared. This cleared software once fault condition resolved.
outputs will power system
When cleared command, VGATE PG[4:1]#
When set, fault latch set. This automatically hardware when fault detected.
outputs will power system off.
Table Register Bitmap
When command, VGATE PG[4:1]#
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Summit Microelectronics
SMH4804
Packaging
PACKAGING Figure shows package dimensions 28-pin SOIC package.
0.701 0.711* (17.01 18.06)
Jedec MS-013
0.394 0.419 (10.00 10.65)
0.291 0.299 (7.391 7.595) 0.010 0.029 (0.254 0.737) 0.093 0.104 (2.362 2.642) 0.037 0.045 (0.940 1.143 0.050 (1.270) 0.014 0.019 (0.356 0.482) 0.004 0.012 (0.102 0.305)
0.009 0.013 (0.229 0.330)
0.016 0.050 (0.406 1.270)
Figure 28-Pin SOIC Package
Summit Microelectronics
2050 10/13/05
Packaging
Figure shows package dimensions 48-pin TQFP package.
SMH4804
0.354 (9.00) 0.276 (7.00)
Inches (Millimeters)
0.02 (0.5)
0.007 0.011 (0.17 0.27)
DETAIL Jedec S-026
0.037 0.041 0.95 1.05 0.039 (1.00) Indicator
0.047 MAX. (1.2)
0.002 0.006 (0.05-0.15)
0.018 0.030 (0.45 0.75)
DETAIL
Figure 48-Pin TQFP Package
2050 10/13/05
Summit Microelectronics
SMH4804
Ordering Information
ORDERING INFORMATION
Summit SMH4804 Part Number Package F=48TQFP S=28SOIC
PART MARKING
Environmental Attribute 100% RoHS compliant Part Number Suffix
Specific requirements contained suffix
SUMMIT SMH4804F Annn AYYWW
Summit Part Number Status Tracking Code (01, 03.) (Summit Use)
Date Code (YYWW) tracking code (Summit use)
Drawing scale
100% RoHS compliant, Green Part Number suffix (Contains Customer specific ordering requirements) Product Tracking Code (Summit use)
NOTICE
SUMMIT Microelectronics, Inc. reserves right make changes products contained this publication order improve design, performance reliability. SUMMIT Microelectronics, Inc. assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained herein reflect representative operating parameters, vary depending upon user's specific application. While information this publication been carefully checked, SUMMIT Microelectronics, Inc. shall liable damages arising result error omission. SUMMIT Microelectronics, Inc. does recommend products life support aviation applications where failure malfunction product reasonably expected cause failure either system significantly affect their safety effectiveness. Products authorized such applications unless SUMMIT Microelectronics, Inc. receives written assurances, satisfaction, that: risk injury damage been minimized; user assumes such risks; potential liability SUMMIT Microelectronics, Inc. adequately protected under circumstances. Revision This document supersedes previous versions. Please check Summit Microelectronics, Inc. site www.summitmicro.com data sheet updates. Copyright 2005 SUMMIT MICROELECTRONICS, Inc. trademark Philips Corporation. PROGRAMMABLE POWER DIGITAL WORLD
Summit Microelectronics
2050 10/13/05
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