Turbo Plus Series Fast Turbo 8032 with Programmable Logic Figure
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uPSD34xx
Turbo Plus Series Fast Turbo 8032 with Programmable Logic
Figure
Packages
Fast 8-bit Turbo 8032 MCU, Advanced core, 4-clocks instruction MIPs peak performance 40MHz (5V) JTAG Debug In-System Programming 16-bit internal instruction path fetches double-byte instruction single memory cycle Branch Cache instruction Prefetch Queue Dual XDATA pointers with automatic increment decrement Compatible with party 8051 tools Dual Flash memories with memory management Place either memory into 8032 program address space data address space READ-while-WRITE operation InApplication Programming EEPROM emulation Single voltage program erase 100K guaranteed erase cycles, 15-year retention Clock, reset, power supply management SRAM Battery Backup capable Flexible 8-level clock divider register Normal, Idle, Power Down Modes Power-on Voltage reset supervisor Programmable Watchdog Timer Programmable logic, general purpose macrocells logic applications (e.g., shifters, state machines, chip-selects, gluelogic keypads, LCDs) converter Eight Channels, 10-bit resolution,
TQFP52 (T), 52-lead, Thin, Quad, Flat
TQFP80 (U), 80-lead, Thin, Quad, Flat
Communication interfaces v2.0 Full Speed (12Mbps) endpoint pairs (In/Out), each endpoint with 64-byte FIFO (supports Control, Intr, Bulk transfer types) Master/Slave controller, 833kHz Master controller, 10MHz UARTs with independent baud rate IrDA Potocol: kbaud I/O, tolerant uPSD34xxV Timers interrupts Three 8032 standard 16-bit timers Programmable Counter Array (PCA), 16-bit modules PWM, CAPCOM, timers 8/10/16-bit operation Interrupt sources with external interrupt pins Operating voltage source (±10%) Devices: 5.0V 3.3V sources 3.3V Devices: 3.3V source
July 2006
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www.st.com
uPSD34xx Table Device Summary
Flash Flash (bytes) uPSD3422E-40T6 uPSD3422EV-40T6 uPSD3422E-40U6 uPSD3422EV-40U6 uPSD3433E-40T6 uPSD3433EV-40T6 uPSD3433E-40U6 uPSD3433EV-40U6 uPSD3434E-40T6 uPSD3434EV-40T6 uPSD3434E-40U6 uPSD3434EV-40U6 uPSD3454E-40T6 uPSD3454EV-40T6 uPSD3454E-40U6 uPSD3454EV-40U6 uPSD3422EB40T6 uPSD3422EVB40T6 uPSD3422EB40U6 uPSD3422EVB40U6 uPSD3433EB40T6 uPSD3433EVB40T6 uPSD3433EB40U6 uPSD3433EVB40U6 uPSD3434EB40T6 uPSD3434EVB40T6 uPSD3434EB40U6 uPSD3434EVB40U6 uPSD3454EB40T6 uPSD3454EVB40T6 uPSD3454EB40U6 uPSD3454EVB40U6 128K 128K 128K 128K 256K 256K 256K 256K 256K 256K 256K 256K 128K 128K 128K 128K 256K 256K 256K 256K 256K 256K 256K 256K 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 SRAM GPIO 8032 Pkg.
Part Number
Note:
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Operating temperature Industrial range (-40°C 85°C).
uPSD34xx
Contents
Contents
Summary description descriptions Hardware description Memory organization
Internal memory (MCU module, standard 8032 memory: DATA, IDATA, SFR) External memory (PSD module: program memory, data memory)
8032 core performance enhancements
Pre-fetch queue (PFQ) branch cache (BC) example, multi-cycle instructions Aggregate performance
module description 8032 registers
Stack pointer (SP) Data pointer (DPTR) Program counter (PC) Accumulator (ACC) register General purpose registers Program status word (PSW)
Special function registers (SFR) 8032 addressing modes
Register Addressing Direct Addressing Register Indirect Addressing Immediate Addressing
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Contents
uPSD34xx
9.10 9.11
External Direct Addressing External Indirect Addressing Indexed Addressing Relative Addressing Absolute Addressing Long Addressing Addressing
uPSD34xx instruction summary Dual data pointers
11.1 11.2 Data pointer control register, DPTC (85h) Data pointer mode register, DP(86h)
Debug unit Interrupt system
13.1 Individual interrupt sources
clock generation
14.1 14.2 MCU_CLK PERIPH_CLK
Power saving modes
15.1 15.2 15.3 Idle Mode Power-down Mode Reduced Frequency Mode
Oscillator external components ports module
17.1 port operating modes
interface
18.1 18.2 PSEN cycles READ WRITE cycles
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uPSD34xx
Contents
18.3 18.4 18.5
Connecting external devices Programmable timing Controlling
Supervisory functions
19.1 19.2 19.3 19.4 19.5 External reset input pin, RESET_IN voltage detect, Power-up reset JTAG debug reset Watchdog timer,
Standard 8032 timer/counters
20.1 20.2 20.3 20.4 20.5 20.6 Standard timer SFRs Clock sources SFR, TCON SFR, TMOD Timer Timer operating modes Timer
Serial UART interfaces
21.1 21.2 21.3 21.4 21.5 21.6 UART operation modes Serial port control registers UART baud rates More about UART mode More about UART mode More About UART Modes
IrDA interface
22.1 22.2 Baud rate selection Pulse width selection
interface
23.1 23.2 23.3 interface main features Communication flow Operating modes
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Contents
uPSD34xx
23.4 23.5 23.6 23.7 23.8 23.9
arbitration Clock synchronization General call address Serial engine (SIOE) interface control register (S1CON) interface status register (S1STA)
23.10 data shift register (S1DAT) 23.11 address register (S1ADR) 23.12 START sample setting (S1SETUP) 23.13 operating sequences
(synchronous peripheral interface)
24.1 24.2 24.3 24.4 24.5 24.6 features communication flow Full-duplex operation Bus-level activity registers configuration Dynamic control
interface
25.1 25.2 25.3 25.4 25.5 Basic concepts Types transfers Endpoint FIFOs registers Typical connection
Analog-to-digital convertor (ADC)
26.1 Port channel selects
Programmable counter array (PCA) with
27.1 27.2 27.3 27.4 block Clock Selection Operation modes Capture mode
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uPSD34xx
Contents
27.5 27.6 27.7 27.8 27.9
Timer mode Toggle mode mode (x8), fixed frequency mode (x8), programmable frequency mode fixed frequency, 16-bit
27.10 mode fixed frequency, 10-bit 27.11 Writing capture/compare registers 27.12 Control register definition 27.13 interrupts
module
28.1 28.2 28.3 28.4 28.5 28.6 module functional description Memory mapping module data width Runtime control register definitions (csiop) module detailed operation module reset conditions
AC/DC parameters Maximum rating parameters Package mechanical information Part numbering Important notes
34.1 34.2 34.3 34.4 34.5 34.6 interrupts with idle mode Reset Interrupt Reset Data Toggle FIFO Accessibility Erroneous Resend Data Packet
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Contents
uPSD34xx
34.7 34.8 34.9
FIFO Pairing Operation FIFO Pairing Operation Missing host retransmission SETUP packet
34.10 JTAG 34.11 PORT 5-volt Tolerant 34.12 Incorrect Code Execution when Code Banks Switched 34.13 Received Data Corrupted UART Modes
Revision history
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uPSD34xx
Summary description
Summary description
Turbo Plus uPSD34xx Series combines powerful 8051-based microcontroller with flexible memory structure, programmable logic, rich peripheral form ideal embedded controller. core fast 4-cycle 8032 with 4-byte instruction prefetch queue (PFQ) 4-entry fully associative branching cache (BC). connected 16-bit internal instruction path maximize performance, enabling loops code smaller localities execute extremely fast. 16-bit wide instruction path Turbo Plus Series allows double-byte instructions fetched from memory single memory cycle. This keeps average performance near peak performance (peak performance 40MHz Turbo Plus uPSD34xx MIPS single-byte instructions, average performance will approximately MIPS single- multi-byte instructions). (full speed, 12Mbps) included, providing endpoints, each with 64-byte FIFO maintain high data throughput. Endpoint (Control Endpoint) uses endpoints directions, remaining eight endpoints allocated either type transfers: Bulk Interrupt. Code development easily managed without hardware In-Circuit Emulator using serial JTAG debug interface. JTAG also used In-System Programming (ISP) little seconds, perfect manufacturing development. 8032 core coupled Programmable System Device (PSD) architecture optimize 8032 memory structure, offering independent banks Flash memory that placed virtually address within 8032 program data address space, easily paged beyond bytes using onchip programmable decode logic. Dual Flash memory banks provide robust solution remote product updates field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating need external EEPROM chips. General purpose programmable logic (PLD) included build endless variety gluelogic, saving external logic devices. configured using software development tool, PSDsoft Express, available from www.st.com/psm, charge. uPSD34xx also includes supervisor functions such programmable watchdog timer low-voltage reset.
Note:
list known limitations uPSD34xx devices, please refer Section Important notes.
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Summary description Figure Block Diagram
uPSD34xx
16-bit Timer/ Counters External Interrupts Turbo 8032 Core
uPSD34xx
Programmable Decode Page Logic
Flash Memory: 64K, 128K, 256K Bytes Flash Memory: Bytes SRAM: Bytes
P3.0:7
UART0 GPIO, Port (80-pin only) GPIO, Port General Purpose Programmable Logic, Macrocells GPIO, Port GPIO, Port GPIO, Port
PA0:7 PB0:7 PD1:2
10-bit Optional IrDA Encoder/Decoder
SYSTEM
P1.0:7
GPIO, Port
PC0:7
JTAG 8032 Address/Data/Control (80-pin device only) Supervisor: Watchdog Low-Voltage Reset VCC, VDD, GND, Reset, Crystal
UART1
16-bit PWM, CAPCOM, TIMER
P4.0:7 USB+, USB-
GPIO, Port
Dedicated Pins
v2.0, Full Speed
FIFOs
AI09695b
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uPSD34xx
descriptions
descriptions
Figure TQFP52 connections
P1.6/SPITXD(2)/ADC6 P1.7/SPISEL(2)/ADC7
AVCC/AVREF(3)
RESET_IN
PD1/CLKIN JTAG JTAG DEBUG 3.3V USB+ VDD(1) USB- PC2/VSTBY JTAG JTAG
P1.5/SPIRXD(2)/ADC5 P1.4/SPICLK(2)/ADC4 P1.3/TXD1(IrDA)(2)/ADC3 P1.2/RXD1(IrDA)(2)/ADC2 P1.1/T2X(2)/ADC1 P1.0/T2(2)/ADC0 VDD(1) XTAL2 XTAL1 P3.7/SCL P3.6/SDA P3.5/C1 P3.4/C0
SPISEL(2)/PCACLK1/P4.7
SPITXD(2)/TCM5/P4.6
SPIRXD(2)/TCM4/P4.5
SPICLK(2)/TCM3/P4.4
TXD1(IrDA)(2)/PCACLK0/P4.3
RXD1(IrDA)(2)/TCM2/P4.2
T2X(2)/TCM1/P4.1
T2(2)/TCM0/P4.0
RXD0/P3.0
TXD0/P3.1
EXTINT0/TG0/P3.2
EXTINT1/TG1/P3.3
AI09696b
Note:
applications, must connected 5.0V source. 3.3V applications, must connected 3.3V source. These signals used different ports (Port Port flexibility. Default Port1. AVREF 3.3V AVCC shared 52-pin package only. channels must 3.3V AVREF 52-pin package.
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descriptions Figure TQFP80 connections
P1.6/SPITXD(3)/ADC6 P1.7/SPISEL(3)/ADC7 P3.2/EXINT0/TG0
uPSD34xx
P3.0/RXD0
P3.1/TXD0
RESET_IN
AVREF
PSEN
AVCC
PD2/CSI P3.3/TG1/EXINT1 PD1/CLKIN JTAG JTAG DEBUG PC4/TERR 3.3V USB+(1) VDD(2) USB- PC3/TSTAT PC2/VSTBY JTAG SPISEL(2)/PCACLK1/P4.7 SPITXD(2)/TCM5/P4.6 JTAG
P1.5/SPIRXD(3)/ADC5 P1.4/SPICLK(3)/ADC4 P1.3/TXD1(IrDA)(3)/ADC3 P1.2/RXD1(IrDA)(3)/ADC2 P1.1/T2X(3)/ADC1 P1.0/T2(3)/ADC0 VDD(1) XTAL2 XTAL1 P3.7/SCL P3.6/SDA P3.5/C1
SPIRXD(2)/TCM4/P4.5
SPICLK(2)/TCM3/P4.4
TXD1(IrDA)(2)/PCACLK0/P4.3
RXD1(IrDA)(2)/TCM2/P4.2
T2X(2)/TCM1/P4.1
T2(2)/TCM0/P4.0
P3.4/C0
AI09697b
Note: Note:
Connected USB+ needs 1.5k pull-up resistor. applications, must connected 5.0V source. 3.3V applications, must connected 3.3V source. These signals used different ports (Port Port flexibility. Default Port1.
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uPSD34xx Table
Port
descriptions definitions
Signal Name 80-Pin 52-Pin In/Out No.(1) Function Basic External Multiplexed Address/Data A0/D0 Multiplexed Address/Data A1/D1 Multiplexed Address/Data A2/D2 Multiplexed Address/Data A3/D3 Multiplexed Address/Data A4/D4 Multiplexed Address/Data A5/D5 Multiplexed Address/Data A6/D6 Multiplexed Address/Data A7/D7 General port General port General port General port General port General port General port General port Timer Count input Channel (T2) input (ADC0) Timer Trigger input (T2X) UART1 IrDA Receive (RxD1) UART IrDA Transmit (TxD1) Clock (SPICLK) Receive (SPIRxD) Transmit (SPITxD) Slave Select (SPISEL) Channel input (ADC1) Channel input (ADC2) Channel input (ADC3) Channel input (ADC4) Channel input (ADC5) Channel input (ADC6) Channel input (ADC7) Alternate Alternate
MCUAD0
MCUAD1
MCUAD2
MCUAD3
MCUAD4
MCUAD5
MCUAD6
MCUAD7
ADC0 ADC1 RxD1 ADC2 TXD1 ADC3 SPICLK ADC4 SPIRxD ADC5 SPITXD ADC6 SPISEL ADC7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
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descriptions Table
Port
uPSD34xx
definitions
Signal Name RxD0 TXD0 EXINT0 80-Pin 52-Pin In/Out No.(1) Function Basic General port General port Alternate UART0 Receive (RxD0) UART0 Transmit (TxD0) Alternate
P3.0 P3.1
P3.2
Interrupt input General port (EXTINT0)/Timer gate control (TG0) Interrupt input General port (EXTINT1)/Timer gate control (TG1) General port Counter input (C0) General port Counter input (C1) General port General port General port serial data (I2CSDA) clock (I2CSCL) Program Counter Timer Count input Array0 PCA0-TCM0 (T2) Timer Trigger input (T2X) UART1 IrDA Receive (RxD1) UART1 IrDA Transmit (TxD1)
P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7
INT1 TCM0 TCM1 RXD1 TCM2 TXD1 PCACLK0 SPICLK TCM3 SPIRXD TCM4 SPITXD SPISEL PCACLK1
General port PCA0-TCM1 General port PCA0-TCM2 General port PCACLK0 General port
Program Counter Clock Array1 PCA1-TCM3 (SPICLK) Receive (SPIRxD) Transmit (SPITxD) Slave Select (SPISEL)
General port PCA1-TCM4 General port PCA1-TCM5 General port PCACLK1 Reference Voltage input ADC. Connect AVREF used. READ Signal, external WRITE Signal, external
AVREF
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uPSD34xx Table
Port
descriptions definitions
Signal Name 80-Pin 52-Pin In/Out No.(1) VSTBY Function Basic PSEN Signal, external Address Latch signal, external Active reset input Oscillator input system clock Oscillator output system clock Debug Unit General port General port General port General port General port General port General port General port General port General port General port General port General port General port General port General port JTAG (TMS) JTAG (TCK) General port SRAM Standby voltage input (VSTBY) Optional JTAG Status (TSTAT) Optional JTAG Status (TERR) Macrocell output, input PLD, Macrocell output, input PLD, Macrocell output, input Port pins support: Macrocell outputs, inputs, Latched Address (A0-A7 A8-A15) Port pins support: Macrocell outputs, inputs, Latched Address (A0-A7), Peripheral Mode Alternate Alternate
PSEN RESET_IN XTAL1 XTAL2 DEBUG JTAGTMS JTAGTCK
TSTAT TERR
General port General port
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descriptions Table
Port JTAGTDI JTAGTDO
uPSD34xx
definitions
Signal Name 80-Pin 52-Pin In/Out No.(1) Function Basic JTAG (TDI) JTAG (TDO) General port PLD, Macrocell output, input Clock input Chip select Module Alternate Alternate
CLKIN
General port
General port pin; 1.5k pull-up resistor required. Module. Connect AVCC used. Analog Input Module 3.3V Module 3.3V
USB+ USB-
3.3V-VCC
AVCC 3.3V 3.3V
Note:
Signal Available 52-pin package.
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uPSD34xx
Hardware description
Hardware description
uPSD34xx modular architecture built from stacked process. There die, designated "MCU Module" this document, other designated "PSD Module" (see Figure page 18). cases, Module operates 3.3V with tolerant I/O. Module either 3.3V die, depending uPSD34xx device described below. Module consists fast 8032 core, that operates with clocks instruction cycle, many peripheral system supervisor functions. Module provides 8032 with multiple memories (two Flash SRAM) program data, programmable logic address decoding general-purpose logic, additional I/O. Module communicates with Module through internal address data busses (AD0 AD15) control signals (RD, PSEN, ALE, RESET). There slightly different characteristics each module. I/Os module designated Ports I/Os Module designated Ports uPSD34xx devices, 3.3V Module stacked with Module. this case, uPSD34xx device must supplied with 3.3VCC Module 5.0VDD Module. Ports Module 3.3V ports with tolerance devices (they directly driven external devices they directly drive external devices while producing 2.4V max). Ports Module true ports. 3.3V uPSD34xxV devices, 3.3V Module stacked with 3.3V Module. this case, 3.3V uPSD34xx device needs supplied with single 3.3V voltage source both VDD. pins Ports tolerant connected external peripherals devices desired. Ports Module 3.3V ports, which tolerant external devices. Refer Table port type voltage source requirements. 80-pin uPSD34xx devices provide access 8032 address, data, control signals external pins connect external peripheral memory devices. 52-pin uPSD34xx devices provide access 8032 system bus. non-volatile memory configuration portions uPSD34xx device programmed through JTAG interface special programming voltage needed. This same JTAG port also used debugging 8032 core runtime providing breakpoint, single-step, display, trace features. non-volatile security programmed block access JTAG interface security. security defeated only erasing entire device, leaving device blank ready again. Table
Device Type uPSD34xx 3.3V: uPSD34xxV
Port type voltage source combinations
Module 3.3V 3.3V Module 5.0V 3.3V Ports Module 3.3V (Ports tolerant) 3.3V (Ports tolerant) Ports Module 3.3V. tolerant
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Hardware description Figure Functional modules
Port UART0, Intr, Timers Port imer, ADC, Port PCA, PWM, UART1 Port pins
uPSD34xx
Module
Port Port urbo 8032 Core Dual UARTs Interrupt imer Counters Byte SRAM
Clock Unit
10-bit
Counters
Unit
Transceiver
Pins 3.3V
Dedicated Memory Interface Prefetch, Branch Cache 8-Bit/16-Bit Die-to-Die Enhanced Interface
Page Register
8032 Internal
Ext. Reset Input
DEBUG
Internal Reset
Reset Logic
Reset
Main Flash
Decode
Secondary Flash
Reset SRAM
Module
Internal
CPLD MACROCELLS
Pins 3.3V
uPSD34xx
Port JTAG GPIO
Port A,B,C GPIO
Port GPIO
AI10409
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uPSD34xx
Memory organization
Memory organization
8032 core views memory module "internal" memory views memory module "external" memory, Figure Internal memory Module consists DATA, IDATA, SFRs. These standard 8032 memories reside bytes SRAM located fixed address space starting address 0x0000. External memory Module consists four types: main Flash (64K, 128K, 256K bytes), smaller secondary Flash (32K), SRAM (4K, 32Kbytes), block Module control registers called csiop (256 bytes). These external memories reside programmable address ranges, specified using software tool PSDsoft Express. Module section this document more details these memories. External memory accessed 8032 separate byte address spaces. address space program memory other address space data memory. Program memory accessed using 8032 signal, PSEN. Data memory accessed using 8032 signals, 8032 needs access more than bytes external program data memory, must paging banking) techniques provided Page Register Module.
Note:
When referencing program data memory spaces, nothing with 8032 internal SRAM areas DATA, IDATA, Module. Program data memory spaces only relate external memories Module. External memory Module overlap internal SRAM memory Module same physical address range (starting 0x0000) without interference because 8032 core does assert signals when accessing internal SRAM. Figure uPSD34xx memories
Internal SRAM Module External Memory Module
Fixed Addresses Indirect Addressing
Main Flash Bytes SRAM Bytes
External memories placed virtually address using software tool PSDsoft Express. SRAM Flash memories placed 8032 Program Space Data Space using PSDsoft Express. memory 8032 Data Space XDATA.
IDATA
Bytes
Direct Addressing
Bytes
64KB 128KB 256KB
Secondary Flash
SRAM 32KB
AI10410b
DATA
Direct Indirect Addressing
32KB
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Memory organization
uPSD34xx
4.1.1
Internal memory (MCU module, standard 8032 memory: DATA, IDATA, SFR)
DATA memory
first bytes internal SRAM ranging from address 0x0000 0x007F called DATA, which accessed using 8032 direct indirect addressing schemes typically used store variables stack. Four register banks, each with registers R7), occupy addresses 0x0000 0x001F. Only these four banks enabled time. next locations 0x0020 0x002F contain directly addressable locations that used software flags. SRAM locations 0x0030 above used variables stack.
4.1.2
IDATA memory
next bytes internal SRAM named IDATA range from address 0x0080 0x00FF. IDATA accessed only through 8032 indirect addressing typically used hold stack well data variables. stack reside both DATA IDATA memories reach size limited only available space combined bytes these memories (since stack accesses always done using indirect addressing, boundary between DATA IDATA does exist with regard stack).
4.1.3
memory
Special Function Registers (Table page occupy separate physical memory, they logically overlap same bytes IDATA, ranging from address 0x0080 0x00FF. SFRs accessed only using direct addressing. There active registers used many functions: changing operating mode 8032 core, controlling 8032 peripherals, controlling I/O, managing interrupt functions. remaining unused SFRs reserved should accessed. SFRs both byte- bit-addressable. Bit-addressable SFRs those whose address ends hex.
External memory (PSD module: program memory, data memory)
Module four memories: main Flash, secondary Flash, SRAM, csiop. MODULE section more detailed information these memories. Memory mapping Module implemented with Decode (DPLD) optionally Page Register. user specifies decode equations individual segments each memories using software tool PSDsoft Express. This very easy pointand-click process allowing total flexibility mapping memories. Additionally, each memories placed various combinations 8032 program address space 8032 data address space using software tool PSDsoft Express.
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uPSD34xx
Memory organization
4.2.1
Program memory
External program memory addressed 8032 using 16-bit Program Counter (PC) accessed with 8032 signal, PSEN. Program memory present address program space between 0x0000 0xFFFF. After power-up reset, 8032 begins program execution from location 0x0000 where reset vector stored, causing jump initialization routine firmware. address 0x0003, just following reset vector interrupt service locations. Each interrupt assigned fixed interrupt service location program memory. interrupt causes 8032 jump that service location, where commences execution service routine. External Interrupt (EXINT0), example, assigned service location 0x0003. EXINT0 going used, service routine must begin location 0x0003. Interrupt service locations spaced 8-byte intervals: 0x0003 EXINT0, 0x000B Timer 0x0013 EXINT1, forth. interrupt service routine short enough, reside entirely within 8-byte interval. Longer service routines jump instruction somewhere else program memory.
4.2.2
Data memory
External data referred XDATA addressed 8032 using Indirect Addressing 16-bit Data Pointer Register (DPTR) accessed 8032 signals, XDATA present address data space between 0x0000 0xFFFF.
Note:
uPSD34xx dual data pointers (source destination) making XDATA transfers much more efficient.
4.2.3
Memory placement
Module architecture allows placement external memories into different combinations program memory data memory spaces. This means main Flash, secondary Flash, SRAM viewed 8032 various combinations program memory data memory defined PSDsoft Express. example this flexibility, applications that require great deal Flash memory data space (large lookup tables extended data recording), larger main Flash memory placed data space smaller secondary Flash memory placed program space. opposite realized different application more Flash memory needed code less Flash memory data. default, SRAM csiop memories Module must always reside data memory space they treated 8032 XDATA. main Flash secondary Flash memories reside program space, data space, both. These memory placement choices specified PSDsoft Express programmed into non-volatile sections uPSD34xx, active power-up after reset. possible override these initial settings during runtime In-Application Programming (IAP). Standard 8032 architecture cannot write program memory space prevent accidental corruption firmware. However, this becomes obstacle typical 8032 systems when remote update firmware Flash memory required using IAP. module provides solution remote updates allowing 8032 firmware temporarily "reclassify" Flash memory reside data space during remote update, then returning
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Memory organization
uPSD34xx
Flash memory back program space when finished. Register (Table page 197) Module section this document more details.
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uPSD34xx
8032 core performance enhancements
8032 core performance enhancements
Before describing performance features uPSD34xx, first look standard 8032 architecture. clock source 8032 creates basic unit timing called machine-cycle, which period clocks standard 8032 MCUs. instruction traditional 8032 MCUs consists byte instructions that execute different combinations machine-cycles. example, there one-byte instructions that execute machine-cycle clocks), one-byte instructions that execute four machine-cycles clocks), two-byte, two-cycle instructions clocks), addition, standard 8032 architecture will fetch bytes from program memory almost every machine-cycle, regardless needs them (dummy fetch). This means onebyte, one-cycle instructions, second byte ignored. These one-byte, one-cycle instructions account half 8032's instructions (126 opcodes). There inefficiencies wasted cycles idle times that eliminated. uPSD34xx 8032 core offers increased performance number ways, while keeping exact same instruction standard 8032 (all opcodes, number bytes instruction, native number machine-cycles instruction identical original 8032). first performance boosted reducing machine-cycle period just clocks compared clocks standard 8032. This shortened machine-cycle improves instruction rate one- two-byte, one-cycle instructions factor three (Figure page compared standard 8051 architectures, significantly improves performance multiple-cycle instruction types. example Figure page shows continuous execution stream one- twobyte, one-cycle instructions. uPSD34xx will yield MIPS peak performance this case while operating 40MHz clock rate. typical application however, effective performance will lower since programs only one-cycle instructions, special techniques implemented uPSD34xx keep effective MIPS rate close possible peak MIPS rate times. This accomplished with instruction PreFetch Queue (PFQ), Branch Cache (BC), 16-bit program memory shown Figure page Figure Comparison uPSD34xx with Standard 8032 Performance
2-byte, 1-cycle Instructions Instruction Turbo uPSD34xx
Execute Instruction Pre-Fetch Next Instruction
Instruction
Execute Instruction Pre-Fetch Next Instruction
Instruction
Execute Instruction Pre-Fetch Next Instruction
clocks (one machine cycle)
machine cycle
machine cycle
Clock
clocks (one machine cycle)
Instruction Standard 8032
Fetch Byte Instruction Execute Instruction Fetch Second Dummy Byte
Dummy Byte Ignored (wasted access)
Turbo uPSD34xx executes instructions same amount time that standard 8032 executes only Instruction
AI10411
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8032 core performance enhancements Figure Instruction Pre-Fetch Queue Branch Cache
Branch Code Branch Cache (BC) Branch Code Compare
uPSD34xx
Branch Branch Code Code Branch Branch Code Code Branch Code Branch Code
Load Branch Address Match
Instruction Byte 16-bit Program Memory Module
Current Branch Address Instruction Byte
Instruction Byte
Address Bytes Instruction Wait
8032
Address
Wait
Instruction Pre-Fetch Queue (PFQ)
AI10431
Pre-fetch queue (PFQ) branch cache (BC)
always working minimize idle time inherent 8032 architecture, eliminate wasted memory fetches, maximize memory bandwidth MCU. does this running asynchronously relation MCU, looking ahead pre-fetch bytes (word) code from program memory during idle periods. Only necessary word will fetched dummy fetches like standard 8032). will queue four code bytes advance execution, which significantly optimizes sequential program performance. However, when program execution becomes non-sequential (program branch), typical pre-fetch queue will empty itself reload code, causing stall. Turbo uPSD34xx diminishes this problem using Branch Cache with PFQ. four-way, fully associative cache, meaning that when program branch occurs, branch destination address compared simultaneously with four recent previous branch destinations stored Each four cache entries contain four bytes code related branch. there match), then four code bytes matching program branch transferred immediately simultaneously from PFQ, execution that branch continues with minimal delay. This greatly reduces chance that will stall from empty PFQ, improves performance embedded control systems where quite common branch loop relatively small code localities. default, enabled after power-up reset. 8032 disable runtime desired writing specific (BUSCON). memory module operates with variable wait states depending value specified named BUSCON. example, uPSD34xx device operating 40MHz crystal frequency requires four memory wait states (equal four clocks). this example, once word code, wait states become transparent full MIPS achieved when program stream consists sequential one- two-byte, machine-cycle instructions shown Figure page (transparent because machine-cycle four clocks which equals memory pre-fetch wait time that also
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uPSD34xx
8032 core performance enhancements four clocks). also important understand operation multi-cycle instructions.
example, multi-cycle instructions
look string two-byte, two-cycle instructions Figure page There three instructions executed sequentially this example, instructions Each time divisions figure machine-cycle four clocks, there phases reference this discussion. Each instruction pre-fetched into advance execution MCU. Prior Phase pre-fetched instruction bytes Instruction During Phase one, both bytes loaded into execution unit. Also Phase pre-fetching Instruction (bytes from program memory. Phase processing Instruction internally while pre-fetching Instruction Phase both bytes instruction loaded into execution unit begins pre-fetch bytes next instruction. Phase Instruction processed. uPSD34xx instructions exact scale standard 8032 instructions with regard number cycles instruction. Figure page shows equivalent instruction sequence from example above standard 8032 comparison.
Aggregate performance
stream two-byte, two-cycle instructions Figure page running 40MHz, uPSD34xx will yield MIPs. stream one- two-byte, one-cycle instructions Figure page same yield MIPs. Effective performance will depend number things: clock frequency; mixture instructions types (bytes cycles) application; amount time empty stalls (mix instruction types misses Branch Cache); operating voltage. uPSD34xx device operates with four memory wait states, 3.3V device operates with five memory wait states yielding MIPS peak compared MIPs peak device. same number wait states will apply both program fetches data READ/WRITEs unless otherwise specified named BUSCON. general, aggregate performance increase expected over standard 8032 application running same clock frequency. Figure operation multi-cycle instructions
Three 2-byte, 2-cycle Instructions uPSD34xx
Pre-Fetch Inst Pre-Fetch Inst Pre-Fetch next Inst
Inst Byte Inst Byte Inst Byte
Next Inst
Continue Pre-Fetch
4-clock Macine Cycle
Phase Phase Process Phase Phase Process Phase Phase Process Next Inst
Execution
Previous Instruction
Instruction
Instruction
Instruction AI10432
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8032 core performance enhancements Figure uPSD34xx multi-cycle instructions compared standard 8032
Three 2-byte, 2-cycle Instructions, uPSD34xx Standard 8032 Clocks Total clocks cycle) uPSD34xx Inst Inst Inst
uPSD34xx
Cycle Clocks clocks cycle) 8032 Byte Byte Process Inst Cycle
AI10412
Byte
Byte
Process Inst
Byte
Byte
Process Inst
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uPSD34xx
module description
module description
This following sections provide detailed description Module system functions peripherals, including:
8032 Registers Special Function Registers 8032 Addressing Modes uPSD34xx Instruction Summary Dual Data Pointers Debug Unit Interrupt System Clock Generation Power Saving Modes Oscillator External Components Ports Interface Supervisory Functions Standard 8032 Timer/Counters Serial UART Interfaces IrDA Interface Interface Interface Analog Digital Converter Programmable Counter Array (PCA) Interface
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8032 registers
uPSD34xx
8032 registers
uPSD34xx following 8032 core registers, also shown Figure Figure 8032 registers
R0-R7 DPTR(DPH)
AI06636
Accumulator Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3) Data Pointer Register
DPTR(DPL)
Stack pointer (SP)
8-bit register which holds current location stack. incremented before value pushed onto stack, decremented after value popped stack. initialized after reset. This causes stack begin location (top stack). avoid overlapping conflicts, user must initialize stack four banks registers used, well stack 8032 memory locations used.
Data pointer (DPTR)
DPTR 16-bit register consisting 8-bit registers, DPH. DPTR Register used base register create address indirect jumps, table look-up operations, external data transfers (XDATA). When used addressing, DPTR Register used general purpose 16-bit data register. Very frequently, DPTR Register used access XDATA using External Direct addressing mode. uPSD34xx special registers (DPTC, DPTM) control secondary DPTR Register speed memory-to-memory XDATA transfers. Having dual DPTR Registers allows rapid switching between source destination addresses (see details Section Dual data pointers page 47).
Program counter (PC)
16-bit register consisting 8-bit registers, PCH. This counter indicates address next instruction program memory fetched executed. reset forces location 0000h, which where reset jump vector stored.
Accumulator (ACC)
This 8-bit general purpose register which holds source operand receives result arithmetic operations. Register also source destination logic data movement operations. instructions, combined with
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uPSD34xx
8032 registers Register hold 16-bit operands. referred instruction set.
register
Register general purpose 8-bit register temporary data storage also used 16-bit register when concatenated with Register with instructions.
General purpose registers
There four banks eight general purpose 8-bit registers R7), only bank eight registers active given time depending setting word (described next). generally used assist manipulating values moving data from memory location another. These register banks physically reside first locations 8032 internal DATA SRAM, starting address 00h. reset, only first bank eight registers active (addresses 07h), stack begins address 08h.
Program status word (PSW)
8-bit register which stores several important bits, flags, that cleared many 8032 instructions, reflecting current state core. Figure page shows individual flags.
7.7.1
Carry flag (CY)
This flag when last arithmetic operation that executed results carry (addition) borrow (subtraction). cleared other arithmetic operations. flag also affected Shift Rotate Instructions.
7.7.2
Auxiliary carry flag (AC)
This flag when last arithmetic operation that executed results carry into (addition) borrow from (subtraction) high-order nibble. cleared other arithmetic operations.
7.7.3
General purpose flag (F0)
This bit-addressable, general-purpose flag under software control.
7.7.4
Register bank select flags (RS1, RS0)
These bits select which bank eight registers used during register accesses (see Table
7.7.5
Overflow flag (OV)
flag when: ADD, ADDC, SUBB instruction causes sign change; instruction results overflow (result greater than 255); instruction causes divide-
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8032 registers
uPSD34xx
by-zero condition. flag cleared ADD, ADDC, SUBB, MUL, instructions other cases. CLRV instruction will clear flag time.
7.7.6
Parity flag
flag eight bits Accumulator odd, cleared even. Table
.Register bank select addresses
Register Bank 8032 Internal DATA Address
Figure Program status word (PSW) register
Carry Flag Auxillary Carry Flag General Purpose Flag Register Bank Select Flags select Bank0-3)
AI06639
Reset Value Parity Flag assigned Overflow Flag
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uPSD34xx
Special function registers (SFR)
Special function registers (SFR)
group registers designated Special Function Register (SFR) shown Table page SFRs control operating modes core also control peripheral interfaces pins Module. SFRs accessed only using Direct Addressing method within address range from internal 8032 SRAM. Sixteen addresses address space both byte- bit-addressable. bitaddressable SFRs noted Table possible addresses occupied. remaining unoccupied addresses (designated "RESERVED" Table should written. Reading unoccupied locations will return undefined value.
Note:
There separate control registers Module, designated csiop, they described Section module page 185. pins, PLD, other functions Module controlled SFRs. SFRs categorized follows:
core registers: PSW, DPTL, DPTH, DPTC, DPMCU Module Port registers: P1SFS0, P1SFS1, P3SFS, P4SFS0, P4SFS1 Standard 8032 Timer registers TCON, TMOD, T2CON, TH0, TH1, TH2, TL0, TL1, TL2, RCAP2L, RCAP2H Standard Serial Interfaces (UART) SCON0, SBUF0, SCON1, SBUF1 Power, clock, timing registers PCON, CCON0, CCON1, BUSCON Hardware watchdog timer registers WDKEY, WDRST Interrupt system registers IPA, Prog. Counter Array (PCA) control registers PCACL0, PCACH0, PCACON0, PCASTA, PCACL1, PCACH1, PCACON1, CCON2, CCON3
capture/compare registers CAPCOML0, CAPCOMH0, TCMMODE0, CAPCOML1, CAPCOMH1, TCMMODE2, CAPCOML2, CAPCOMH2, TCMMODE2, CAPCOML3, CAPCOMH3, TCMMODE3,
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Special function registers (SFR)
uPSD34xx
CAPCOML4, CAPCOMH4, TCMMODE4, CAPCOML5, CAPCOMH5, TCMMODE5, PWMF0, PMWF1
interface registers SPICLKD, SPISTAT, SPITDR, SPIRDR, SPICON0, SPICON1 interface registers S1SETUP, S1CON, S1STA, S1DAT, S1ADR Analog Digital Converter registers ACON, ADCPS, ADAT0, ADAT1 IrDA interface register IRDACON interface registers
Table
Addr
UADDR, UPAIR, WE0-3, UIF0-3, UCTL, USTA, USEL, UCON, USIZE, UBASEH, UBASEL, USCI, USCV memory with direct address reset value
Name <Bit Address> Reset Value (hex)
P1.2 <92h> P1.1 <91h> P1.0 <90h> Table Table Table Table Table Table Section 20.1
88(1) 90(1) DPTC DPPCON TCON TMOD P1SFS0 P1SFS1 P3SFS P4SFS0 P4SFS1 P1.7 <97h> P1.6 <96h> P1.5 <95h> SMOD0 <8Fh> GATE SMOD1 <8Eh> <8Dh>
RESERVED SP[7:0] DPL[7:0] DPH[7:0] RESERVED MD1[1:0] RCLK1 <8Bh> GATE TCLK1 <8Ah> DPSEL[2:0] MD0[1:0] <89h> IDLE <88h> Table Table Table Table Table Section Section
<8Ch>
TL0[7:0] TL1[7:0] TH0[7:0] TH1[7:0] P1SFS0[7:0] P1SFS1[7:0] P1.4 <94h> P1.3 <93h>
P3SFS[7:0] P4SFS0[7:0] P4SFS1[7:0]
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Reg. Descr. with Link
Name
uPSD34xx Table
Addr
Special function registers (SFR) memory with direct address reset value
Name <Bit Address> Reset Value (hex)
ADS[2:0] <9Ch> <9Bh> <9Ah> ADATA[9:8] ADST <99h> ADSF <9h8> INTF2 CLK_SEL[1:0] INTF1 INTF0 <ABh> MATCH MATCH MATCH <AAh> TOGGLE TOGGLE TOGGLE EI2C <A9h> <A8h> Table Table Table
98(1) A8(1)
ADCPS ADAT0 ADAT1 ACON SCON0 SBUF0
ADCCE
ADCPS[2:0]
Table Table Table Table Table Section
ADATA[7:0] AINTF <9Fh> AINTEN <9Eh> ADEN <9Dh>
SBUF0[7:0] RESERVED RESERVED RESERVED
BUSCO
EPFQ
WRW1
WRW0
RDW1
RDW0
Table
RESERVED RESERVED RESERVED RESERVED PCACL0 PCACH0 PCACO PCASTA WDRST TCMMO TCMMO TCMMO CAPCO CAPCO WDKEY EADC <AFh> EINTF EINTF EINTF ESPI E_COMP E_COMP E_COMP EPCA <ADh> CAP_PE CAP_PE CAP_PE EN_ALL OVF1 EN_PCA INTF5 EOVF1 INTF4 PCACL0[7:0] PCACH0[7:0] PCA_IDL INTF3 OVF0 Table Table Table Table Table Table Table
WDRST[7:0] <ACh> CAP_NE CAP_NE CAP_NE
PWM[1:0] PWM[1:0] PWM[1:0]
CAPCOML0[7:0] CAPCOMH0[7:0] WDKEY[7:0]
Reg. Descr. with Link 33/293
Name
Special function registers (SFR) Table
Addr
uPSD34xx
memory with direct address reset value
Name <Bit Address> Reset Value (hex)
P3.2 <B2h> P3.1 <B1h> P3.0 <B0h> Table CAPCOMH2[7:0] PWMF0[7:0] RESERVED RESERVED PADC PSPI PPCA <BDh> <BCh> <BBh> <BAh> PI2C <B9h> <B8h> Table Table Table TOGGLE TOGGLE TOGGLE P4.2 <C2h> CLK_SEL[1:0] PWM[1:0] PWM[1:0] PWM[1:0] P4.1 <C1h> P4.0 <C0h> Table Table Table
B0(1) B8(1) C0(1)
CAPCO CAPCO CAPCO CAPCO PWMF0 P3.7 <B7h> P3.6 <B6h> P3.5 <B5h>
CAPCOML1[7:0] P3.4 <B4h> P3.3 <B3h>
Table Table
CAPCOMH1[7:0] CAPCOML2[7:0]
RESERVED PCACL1 PCACH1 PCACO TCMMO TCMMO TCMMO EINTF EINTF EINTF P4.7 <C7h> EN_PCA E_COMP E_COMP E_COMP P4.6 <C6h> EOVF1 CAP_PE CAP_PE CAP_PE P4.5 <C5h> PCACL1[7:0] PCACH1[7:0] PCA_IDL CAP_NE CAP_NE CAP_NE P4.4 <C4h> MATCH MATCH MATCH P4.3 <C3h>
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Reg. Descr. with Link
Name
uPSD34xx Table
Addr
Special function registers (SFR) memory with direct address reset value
Name <Bit Address> Reset Value (hex)
<CAh> C/T2 <C9h> CP/RL2 <C8h> Table Table CDIV2 <D2h> CDIV1 CDIV0 <D0> Table Section Section 20.1 Table FLSB RORIE <DA> <D9> <D8> Table Table Table Section
C8(1) D0(1) D8(1)
CAPCO CAPCO CAPCO CAPCO CAPCO CAPCO PWMF1 T2CON <CFh> EXF2 <CEh> RCLK <CDh>
CAPCOML3[7:0] CAPCOMH3[7:0] CAPCOML4[7:0] CAPCOMH4[7:0] CAPCOML5[7:0] CAPCOMH5[7:0] PWMF1[7:0] TCLK <CCh> EXEN2 <CBh>
RESERVED RCAP2L RCAP2H IRDACO <D7h> IRDA_EN <D6h> BIT_PULS <D5h> RCAP2L[7:0] RCAP2H[7:0] TL2[7:0] TH2[7:0] CDIV4 CDIV3
RS[1:0] <D4h, D3h> RESERVED
SPICLK SPISTAT SPITDR SPIRDR SPICON SPICON SCON1 SBUF1 <DE>
SPICLKD[5:0] BUSY TEISF RORISF
TISF
RISF
Table Table
SPITDR[7:0] SPIRDR[7:0] <DD> SPIEN <DC> SSEL TEIE <DB>
SBUF1[7:0]
Reg. Descr. with Link 35/293
Name
Special function registers (SFR) Table
Addr
uPSD34xx
memory with direct address reset value
Name <Bit Address> Reset Value (hex)
B_LOST ACK_R PR1OUT SUSPND IN2IE OUT2IE NAK2IE SUSPND IN2F OUT2F NAK2F USBEN SETUP PR3IN EOPIE IN1IE OUT1IE NAK1IE EOPF IN1F OUT1F NAK1F VISIBLE PR1IN UMIE IN0IE OUT0IE NAK0IE RESUM IN0F OUT0F NAK0F WAKEU USCI[2:0] Section
E0(1) F0(1) USEL UCON USIZE UBASEH UBASEL USCI USCV BASEADDR[7:6] UADDR UPAIR UIE0 UIE1 UIE2 UIE3 UIF0 UIF1 UIF2 UIF3 UCTL USTA OUTF S1SETU S1CON S1STA S1DAT S1ADR SS_EN STOP INTR
RESERVED SMPL_SET[6:0] TX_MD ADDR B_BUSY Table Table Table Table Table Section
S1DAT[7:0] S1ADR[7:0] A[7:0] <bit addresses: E7h, E6h, E5h, E4h, E3h, E2h, E1h, E0h> RESERVED USBADDR[6:0] PR3OUT RSTIE IN3IE OUT3IE NAK3IE RSTF IN3F OUT3F NAK3F RCVT
IN4IE OUT4IE NAK4IE NAKF IN4F OUT4F NAK4F RESERVED
EP[2:0]
B[7:0] <bit addresses: F7h, F6h, F5h, F4h, F3h, F2h, F1h, F0h> ENABLE SIZE[6:0] BASEADDR[15:8] USCV[7:0] STALL TOGGLE
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Reg. Descr. with Link
Name
uPSD34xx Table
Addr
Special function registers (SFR) memory with direct address reset value
Name <Bit Address> Reset Value (hex)
Table Table
CCON0 CCON1 CCON2 CCON3 PLLM[4] PLLEN UPLLCE
RESERVED RESERVED DBGCE CPU_ CPUPS[2:0] PLLD[3:0] PCA0CE PCA1CE RESERVED RESERVED RESERVED RESERVED RESERVED PCA0PS[3:0] PCA1PS[3:0] Table
PLLM[3:0]
Note:
This addressed individual bits (Bit Address mode) addressed entire byte (Direct Address mode).
Reg. Descr. with Link 37/293
Name
8032 addressing modes
uPSD34xx
8032 addressing modes
8032 uses different addressing modes listed below:
Register Direct Register Indirect Immediate External Direct External Indirect Indexed Relative Absolute Long
Register Addressing
This mode uses contents registers (selected last three bits instruction opcode) operand source destination. This mode very efficient since additional instruction byte needed identify operand. example:
Move contents accumulator
Direct Addressing
This mode uses 8-bit address, which contained second byte instruction, directly address operand which resides either 8032 DATA SRAM (internal address range 00h-07Fh) resides 8032 (internal address range 80h-FFh). This mode quite fast since range limit bytes internal 8032 SRAM. example:
Move contents DATA SRAM location into accumulator
Register Indirect Addressing
This mode uses 8-bit address contained either Register indirectly address operand which resides 8032 IDATA SRAM (internal address range 80h-FFh). Although 8032 registers also occupy same physical address range IDATA, SFRs will accessed Register Indirect mode. SFRs only accesses using Direct address mode. example:
Move into accumulator contents IDATA SRAM that pointed address contained
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uPSD34xx
8032 addressing modes
Immediate Addressing
This mode uses 8-bits data constant) contained second byte instruction, stores into memory location register indicated first byte instruction. Thus, data immediately available within instruction. This mode commonly used initialize registers SFRs perform mask operations. There also 16-bit version this mode loading DPTR Register. this case, bytes following instruction byte contain 16-bit value. example:
DPTR, 1234# Move constant, 40h, into accumulator Move constant, 1234h, into DPTR
External Direct Addressing
This mode will access external memory (XDATA) using 16-bit address stored DPTR Register. There only instructions using this mode both accumulator either receive byte from external memory addressed DPTR send byte from accumulator address DPTR. uPSD34xx special feature alternate contents (source destination) DPTR rapidly implement very efficient memory-to-memory transfers. example:
MOVX @DPTR Move contents accumulator XDATA address contained DPTR Move XDATA accumulator
MOVX @DPTR,
Note:
details Section Dual data pointers page
External Indirect Addressing
This mode will access external memory (XDATA) using 8-bit address stored either Register This fastest access XDATA (least cycles), because only 8-bits available address, this mode limits XDATA size only bytes (the traditional Port 8032 available uPSD34xx, possible write upper address byte). example:
MOVX @R0,A Move into accumulator XDATA that pointed address contained
Note:
This mode supported uPSD34xx.
Indexed Addressing
This mode used MOVC instruction which allows 8032 read constant from program memory (not data memory). MOVC often used read look-up tables that embedded program memory. final address produced this mode result
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8032 addressing modes
uPSD34xx
adding either 16-bit DPTR value contents accumulator. value accumulator referred index. data fetched from final location program memory stored into accumulator, overwriting index value that previously stored there. example:
MOVC @A+DPTR MOVC @A+PC Move code byte relative DPTR into accumulator Move code byte relative into accumulator
Relative Addressing
This mode will two's-compliment number stored second byte instruction program counter short jumps within +128 -127 addresses relative program counter. This commonly used looping very efficient since additional cycle needed fetch jump destination address. example:
SJMP Jump bytes ahead program memory) address which SJMP instruction stored. SJMP 1000h, program execution jumps 1034h.
Absolute Addressing
This mode will append high-order bits address next instruction low-order bits ACALL AJUMP instruction produce 16-bit jump address. jump will within same byte page program memory first byte following instruction. example:
AJMP 0500h next instruction located address 4000h, resulting jump will made 4500h.
9.10
Long Addressing
This mode will 16-bits contained bytes following instruction byte jump destination address LCALL LJMP instructions. example:
LJMP 0500h Unconditionally jump address 0500h program memory
9.11
Addressing
This mode allows setting clearing individual without disturbing other bits within 8-bit value internal SRAM. Addressing only available certain locations 8032 DATA memory. Valid locations DATA addresses addresses whose base address ends with (Example: SFR, base
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uPSD34xx
8032 addressing modes address A8h, each eight bits addressed individually address A8h, A9h, AFh.) example:
SETB individual (Enable Interrupts) inside Register,
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uPSD34xx instruction summary
uPSD34xx
uPSD34xx instruction summary
Tables through list instructions supported uPSD34xx, including number bytes number machine cycles required implement each instruction. This standard 8051 instruction set. meaning "machine cycles" many 8032 core machine cycles required execute instruction. "native" duration machine cycles memory wait state settings SFR, BUSCON, clock divider selections SFR, CCON0 (i.e. machine cycle typically clocks uPSD34xx). However, individual machine cycle grow duration when either things happen: stall imposed while loading 8032 Pre-Fetch Queue (PFQ); occurrence cache miss Branch Cache (BC) during branch program execution flow.
Section 8032 core performance enhancements page more details. generally speaking, during typical program execution, empty misses, producing very good performance without extending duration machine cycles. Table Arithmetic instruction
Description register direct byte indirect SRAM immediate data register with carry direct byte with carry indirect SRAM with carry immediate data with carry Subtract register from with borrow Subtract direct byte from with borrow Subtract indirect SRAM from with borrow Subtract immediate data from with borrow Increment Increment register Increment direct byte Increment indirect SRAM Decrement Decrement register Decrement direct byte Decrement indirect SRAM Length/Cycles byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle
Mnemonic(1) ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB Direct #data direct #data direct #data direct direct
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uPSD34xx
uPSD34xx instruction summary
Mnemonic(1) DPTR
Description Increment Data Pointer Multiply Divide Decimal adjust
Length/Cycles byte/2 cycle byte/4 cycle byte/4 cycle byte/1 cycle
Note:
mnemonics copyrighted ©Intel Corporation 1980. Table Logical instruction
Description Logical Instructions SWAP direct #data direct, direct, #data direct #data direct, direct, #data direct #data direct, direct, #data register direct byte indirect SRAM immediate data direct byte immediate data direct byte register direct byte indirect SRAM immediate data direct byte immediate data direct byte Swap nibbles within Exclusive-OR register Exclusive-OR direct byte Exclusive-OR indirect SRAM Exclusive-OR immediate data Exclusive-OR direct byte Exclusive-OR immediate data direct byte Clear Compliment Rotate left Rotate left through carry Rotate right Rotate right through carry byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle Length/Cycles
Mnemonic(1)
Note:
mnemonics copyrighted ©Intel Corporation 1980.
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uPSD34xx instruction summary Table Data transfer instruction
Description Move register Move direct byte Move indirect SRAM Move immediate data Move register Move direct byte register Move immediate data register Move direct byte Move register direct byte Move direct byte direct Move indirect SRAM direct byte Move immediate data direct byte Move indirect SRAM Move direct byte indirect SRAM Move immediate data indirect SRAM Load Data Pointer with 16-bit constant
uPSD34xx
Mnemonic(1) MOVC MOVC MOVX MOVX MOVX MOVX PUSH XCHD direct #data direct #data direct, direct, direct, direct direct, direct, #data @Ri, @Ri, direct @Ri, #data DPTR, #data16
Length/Cycles byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/1 cycle
@A+DPTR Move code byte relative DPTR @A+PC
Move code byte relative Move XDATA (8-bit addr) Move XDATA (16-bit addr) Move XDATA (8-bit addr) Move XDATA (16-bit addr) Exchange register with Push direct byte onto stack direct byte from stack Exchange direct byte with Exchange indirect SRAM with Exchange low-order digit indirect SRAM with
@DPTR @Ri,
@DPTR, direct direct direct
Note:
mnemonics copyrighted ©Intel Corporation 1980. This instruction supported uPSD34xx. Section 9.6: External Indirect Addressing page
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uPSD34xx Table
uPSD34xx instruction summary Boolean variable manipulation instruction
Description Clear carry Clear direct carry direct Compliment carry Compliment direct direct carry compliment direct carry direct carry compliment direct carry Move direct carry Move carry direct Jump carry Jump carry Jump direct Jump direct Jump direct clear Length/Cycles byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle
Mnemonic(1) SETB SETB /bit /bit bit, bit,
Note:
mnemonics copyrighted ©Intel Corporation 1980. Table Program branching instruction
Description Program Branching Instructions ACALL LCALL RETI AJMP LJMP SJMP CJNE CJNE CJNE addr11 addr16 @A+DPTR direct, #data, addr11 addr16 Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative addr) Jump indirect relative DPTR Jump zero Jump zero Compare direct byte ACC, jump equal Compare immediate ACC, jump equal byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle Length/Cycles
Mnemonic(1)
#data, Compare immediate register, jump equal
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uPSD34xx instruction summary
uPSD34xx
Mnemonic(1) CJNE DJNZ DJNZ @Ri, #data, direct,
Description Compare immediate indirect, jump equal Decrement register jump zero Decrement direct byte jump zero
Length/Cycles byte/2 cycle byte/2 cycle byte/2 cycle
Note:
mnemonics copyrighted ©Intel Corporation 1980. Table Miscellaneous instruction
Description Miscellaneous Operation byte/1 cycle Length/Cycles
Mnemonic(1)
Note:
mnemonics copyrighted ©Intel Corporation 1980. Table
direct #data
Notes instruction addressing modes
Register currently selected register bank. 8-bit address internal 8032 DATA SRAM (locations 7Fh) registers (locations FFh). 8-bit internal 8032 SRAM (locations FFh) addressed indirectly through contents 8-bit constant included within instruction.
#data16 16-bit constant included within instruction. addr16 addr11 16-bit destination address used LCALL LJMP. 11-bit destination address used ACALL AJMP. Signed (two-s compliment) 8-bit offset byte. Direct addressed internal 8032 DATA SRAM (locations 2Fh) registers (88h, 90h, 98h, A8h, B8h, C0h, C8h, D0h, D8h, E0h, F0h).
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uPSD34xx
Dual data pointers
Dual data pointers
XDATA accessed External Direct addressing mode, which uses 16-bit address stored DPTR Register. Traditional 8032 architecture only DPTR Register. This burden when transferring data between XDATA locations because requires heavy working registers manipulate source destination pointers. However, uPSD34xx data pointers, storing source address other storing destination address. These pointers configured automatically increment decrement after each data transfer, further reducing burden 8032 making this kind data movement very efficient.
11.1
Data pointer control register, DPTC (85h)
default, DPTR Register uPSD34xx will behave different than standard 8032 MCU. DPSEL0 register DPTC shown Table selects which "background" data pointer registers (DPTR0 DPTR1) will function traditional DPTR Register given time. After reset, DPSEL0 cleared, enabling DPTR0 function DPTR, firmware access DPTR0 reading writing traditional DPTR Register addresses 83h. When DPSEL0 set, then DPTR1 Register functions DPTR, firmware access DPTR1 through registers 83h. pointer which selected DPSEL0 remains background accessible 8032. DPSEL0 never set, then uPSD34xx will behave like traditional 8032 having only DPTR Register. further speed XDATA XDATA transfers, bit, automatically toggle data pointers, DPTR0 DPTR1, each time standard DPTR Register accessed MOVX instruction. This eliminates need firmware manually manipulate DPSEL0 between each data transfer. Detailed description register DPTC shown Table Table
DPTC: data pointer control register (SFR 85h, reset value 00h)
DPSEL0
Symbol DPSE0
Reserved
Definition
Manually Select Data Pointer Auto Toggle between DPTR0 DPTR1 Reserved DPTR0 Selected DPTR DPTR1 Selected DPTR
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Dual data pointers
uPSD34xx
11.2
Data pointer mode register, DP(86h)
"background" data pointers, DPTR0 DPTR1, configured automatically increment, decrement, stay same after MOVX instruction accesses DPTR Register. Only currently selected pointer will affected increment decrement. This feature controlled DPRegister defined Table automatic increment decrement function effective only MOVX instruction, MOVC other instruction that uses DTPR Register.
11.2.1
Firmware example
8051 assembly code illustrated Table shows transfer block data bytes from XDATA address region another XDATA address region. Auto-address incrementing auto-pointer toggling will used. Table
DPTM: data pointer mode register (SFR 86h, reset value 00h)
MD11 MD10 MD01 MD00
Symbol
DPTR1 Mode Bits DPTR1 Change Reserved Auto Increment Auto Decrement DPTR0 Mode Bits DPTR0 Change Reserved Auto Increment Auto Decrement
Definition Reserved
MD[11:10]
MD[01:00]
Table
8051 assembly code example
#COUNT DPTR, #SOURCE_ADDR 85h, #01h 85h, #40h 86h, #0Ah initialize size data block transfer load XDATA source address base into DPTR0 load DPTC access DPTR1 pointer load DPTC access DPTR0 pointer auto toggle load DPto auto-increment both pointers
DPTR, #DEST_ADDR load XDATA destination address base into DPTR1
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uPSD34xx
MOVX(1)
Dual data pointers
LOOP:
@DPTR
load XDATA byte from source into ACC. after load completes, DPTR0 increments DPTR switches DPTR1 store XDATA byte from destination. after store completes, DPTR1 increments DPTR switches DPTR0 continue until done disable auto-increment disable auto-toggle, back single DPTR mode
MOVX(1)
@DPTR,
DJNZ(1)
LOOP 86h, 85h,
Note:
code loop where data transfer takes place only lines code.
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Debug unit
uPSD34xx
Debug unit
8032 Module supports run-time debugging through JTAG interface. This same JTAG interface also used In-System Programming (ISP) physical connections described Module section, Section 28.6.1: JTAG JTAG debug page 251. Debugging with serial interface such JTAG non-intrusive gain access internal state 8032 core various memories. traditional external hardware emulator cannot completely effective uPSD34xx because Pre-Fetch Queue Branch Cache. nature hide visibility actual program flow through traditional external connections, thus requiring on-chip serial debugging instead. Debugging supported Windows based software tools used 8051 code development from party vendors listed www.st.com/psm. Debug capabilities include:
Halt Start execution Reset Single Step Match Breakpoints Range Breakpoint (inside outside range) Program Tracing Read Modify core registers, DATA, IDATA, SFR, XDATA, Code External Debug Event Pin, Input Output JTAG Debugger access registers, data memory, code memory while executing full speed cycle-stealing. This means "watch windows" displayed periodically updated during full speed operation. Registers data content also modified during full speed operation. There on-chip storage Program Trace data, instead this data scanned from uPSD34xx through JTAG channel run-time host proccessing. such, full speed program tracing possible only when 8032 operating below approximately MIPS performance. Above MIPS, program will real-time while tracing. MIPS performance determined combination choice clock frequency, settings registers BUSCON CCON0. Breakpoints optionally halt MCU, and/or assert external Debug Event pin. Breakpoint definitions qualified with read write operations, also qualified with address code, SFR, DATA, IDATA, XDATA memories. Three breakpoints will compare address, fourth breakpoint compare address also data content. Additionally, fouth breakpoint logically combined (AND/OR) with other three breakpoints. Debug Event configured host generate output pulse external triggering when break condition met. also configured event input breakpoint logic, causing break fallingedge external event signal. used, Debug Event should pulled
Some points regarding JTAG Debugger.
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uPSD34xx
Debug unit described section, Section 28.6.8: Debugging 8032 module page 257. duration pulse, generated when Event configured output, clock cycle. This active-low signal, first edge when event occurs high-to-low. clock Watchdog Timer, ADC, interface stopped breakpoint halt. Watchdog Timer should disabled while debugging with JTAG, else reset will generated upon watchdog time-out.
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Interrupt system
uPSD34xx
Interrupt system
uPSD34xx 12-source, priority level interrupt structure summarized Table Firmware assign each interrupt source either high priority writing bits SFRs named, IPA, shown Table interrupt will serviced long interrupt equal higher priority already being serviced. interrupt equal higher priority being serviced, interrupt will wait until finished before being serviced. lower priority interrupt being serviced, will stopped interrupt serviced. When interrupt finished, lower priority interrupt that stopped will completed. interrupt requests same priority level received simultaneously, internal polling sequence determines which request selected service. Thus, within each priority levels, there second priority structure determined polling sequence. Firmware individually enable disable interrupt sources writing bits SFRs named, IEA, shown Table page named contains global disable (EA), which cleared disable interrupts once, shown Table page Figure page illustrates interrupt priority, polling, enabling process. Each interrupt source least interrupt flag that indicates whether interrupt pending. These flags reside bits various SFRs shown Table page interrupt flags latched into interrupt control system beginning each machine cycle, they polled beginning following machine cycle. polling determines flags set, interrupt control system automatically generates LCALL user's Interrupt Service Routine (ISR) firmware stored program memory appropriate vector address.
specific vector address each interrupt sources listed Table page However, this LCALL jump blocked following conditions: interrupt equal higher priority already progress current machine cycle final cycle execution instruction progress current instruction involves write SFRs: IEA, current instruction RETI
Note:
Interrupt flags polled based sample taken previous machine cycle. interrupt flag active cycle denied serviced conditions above, then later active when conditions above finally satisfied, previously denied interrupt will serviced. This means that active interrupts remembered. Every poling cycle new. Assuming listed conditions satisfied, executes hardware generated LCALL appropriate ISR. This LCALL pushes contents onto stack (but does save PSW) loads with appropriate interrupt vector address. Program execution then jumps vector address. Execution precedes ISR. necessary firmware clear pending interrupt flag some interrupt sources, because interrupt flags automatically cleared hardware when called, shown Table page
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uPSD34xx
Interrupt system interrupt flag cleared after servicing interrupt, unwanted interrupt will occur upon exiting ISR. After interrupt serviced, last instruction executed RETI. RETI informs that longer progress pops bytes from stack loads them into Execution interrupted program continues where left off.
Note:
must with RETI instruction, RET. will inform interrupt control system that complete, leaving think still progress, making future interrupts impossible. Table Interrupt summary
Flag Name (SFR.bit position) Intr Pending Interrupt Reserved (high) 0063h External Interrupt INT0 Timer Overflow External Interrupt INT1 Timer Overflow UART0 Timer Overflow 0003h (TCON.1) Flag AutoCleared Hardware? Enable Name (SFR.bit position) Intr Enabled Intr Disabled (IE.0) Priority Name (SFR.bit position) High Priority Priority (IP.0)
Interrupt Polling Vecto Source Priority Addr
Edge Level Edge Level
000Bh
(TCON.5)
(IE.1)
(IP.1)
0013h
(TCON.3
(IE.2)
(IP.2)
001Bh 0023h
(TCON.7) (SCON0.0) (SCON0.1) (T2CON.7) EXF2 (T2CON.6) TEISF, RORISF, TISF, RISF (SPISTAT[3:0])
(IE.3) (IE.4)
(IP.3) (IP.4)
002Bh
(IE.5)
(IP.5)
0053h 0033h
ESPI (IEA.6) EUSB (IEA.0) EI2C (IEA.1) EADC (IEA.7)
PSPI (IPA.6) PUSB (IPA.0) PI2C (IPA.1) PADC (IPA.7)
0043h INTR (S1STA.5) 003Bh AINTF (ACON.7)
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Interrupt system
uPSD34xx
Flag Name (SFR.bit position) Intr Pending Interrupt UART1 005Bh OFVx, INTFx (PCASTA[0:7]) (SCON1.0) (SCON1.1) Flag AutoCleared Hardware? Enable Name (SFR.bit position) Intr Enabled Intr Disabled
Priority Name (SFR.bit position) High Priority Priority PPCA (IPA.5) (IPA.4)
Interrupt Polling Vecto Source Priority Addr
EPCA (IEA.5) (IEA.4)
(low) 004Bh
Note:
interrupt flag registers UIF0-3. Figure Enabling polling interrupts
Interrupt Sources Reserved Priority IE/IEA IP/IPA High
INT0 Timer INT1
Timer
UART0 Interrupt Polling Sequence
Timer
UART1
Global Enable
AI07844
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uPSD34xx
Interrupt system
13.1
13.1.1
Individual interrupt sources
External interrupts Int0 Int1
External interrupt inputs pins EXTINT0 EXTINT1 (pins 3.3) either edgetriggered level-triggered, depending bits named TCON. When external interrupt generated from edge-triggered (falling-edge) source, appropriate flag (IE0 IE1) automatically cleared hardware upon entering ISR. When external interrupt generated from level-triggered (low-level) source, appropriate flag (IE0 IE1) automatically cleared hardware.
13.1.2
Timer overflow interrupt
Timer Timer interrupts generated flag bits when there overflow condition respective Timer/Counter register (except Timer Mode
13.1.3
Timer overflow interrupt
This interrupt generated logical flag bits, EXE2. must read flag bits determine cause interrupt.
overflow Timer EXE2 generated falling edge signal external pin, (pin P1.1).
13.1.4
UART0 UART1 interrupt
Each UARTs have identical interrupt structure. each UART, single interrupt generated logical flag bits, (byte received) (byte transmitted). must read flag bits named SCON0 UART0, SCON1 UART1 determine cause interrupt.
13.1.5
interrupt
interrupt four interrupt sources, which logically ORed together when interrupting MCU. must read flag bits determine cause interrupt. flag for: data transmit (TEISF); data receive overrun (RORISF); transmit buffer empty (TISF); receive buffer full (RISF).
13.1.6
interrupt
flag INTR variety conditions occurring interface: received slave address (ADDR flag); received general call address flag); received STOP condition (STOP flag); successful transmission reception data byte.The must read flag bits determine cause interrupt.
13.1.7
interrupt
flag AINTF when A-to-D conversion completed.
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Interrupt system
uPSD34xx
13.1.8
interrupt
eight interrupt sources, which logically ORed together when interrupting MCU.The must read flag bits determine cause interrupt.
Each TCMs generate "match capture" interrupt flag bits OFV5.0 respectively. Each 16-bit counters generate overflow interrupt flag bits INTF1 INTF0 respectively.
Tables through Table page have detailed definitions interrupt system SFRs.
13.1.9
Interrupt
interrupt multiple sources. must read Interrupt Flag Registers (UIF0-3) determine source interrupt. interrupt activated following four group interrupt sources:
Global: interrupt flag when following events occurs: Reset, Suspend, Resume, Packet; FIFO: interrupt flag when Point FIFO becomes empty; FIFO: interrupt flag when Point FIFO becomes full; FIFO NAK: interrupt flag when Point FIFO ready (in-bound) packet. interrupt enable register (SFR A8h, reset value 00h)
Table
Symbol
Function Global disable bit. interrupts disabled. Each interrupt source individually enabled disabled setting clearing enable bit. modify this bit. used JTAG debugger instruction tracing. Always read write back same value when writing this SFR. Enable Timer Interrupt Enable UART0 Interrupt Enable Timer Interrupt Enable External Interrupt INT1 Enable Timer Interrupt Enable External Interrupt INT0
5(1)
3(1)
0(1)
Note:
Enable Interrupt, Disable Interrupt
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uPSD34xx Table
EADC
Interrupt system IEA: Interrupt Enable Addition Register (SFR A7h, reset value 00h)
ESPI EPCA EI2C EUSB
7(1) 6(1) 5(1)
Symbol EADC ESPI EPCA EI2C EUSB
Enable Interrupt Enable Interrupt
Function
Enable Programmable Counter Array Interrupt Enable UART1 Interrupt Reserved, logic '1.' Reserved, logic '1.' Enable Interrupt Enable Interrupt
1(1)
Note:
Enable Interrupt, Disable Interrupt Table
Interrupt Priority Register (SFR B8h, reset value 00h)
Symbol
Reserved Reserved
Function
Timer Interrupt priority level UART0 Interrupt priority level Timer Interrupt priority level External Interrupt INT1 priority level Timer Interrupt priority level External Interrupt INT0 priority level
3(1) 2(1)
0(1)
Note:
Assigns high priority level, Assigns priority level
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Interrupt system Table
PADC
uPSD34xx IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h)
PSPI PPCA PI2C PUSB
7(1) 6(1) 5(1)
Symbol PADC PSPI PPCA PI2C PUSB
Function Interrupt priority level Interrupt priority level Interrupt level UART1 Interrupt priority level Reserved Reserved Interrupt priority level Interrupt priority level
1(1)
Note:
Assigns high priority level, Assigns priority level
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uPSD34xx
clock generation
clock generation
Internal system clocks generated clock generation unit derived from signal, XTAL1, shown Figure XTAL1 frequency fOSC, which comes directly from external crystal oscillator device. named CCON0 (Table page controls clock generation unit. There clock signals produced clock generation unit:
MCU_CLK PERIPH_CLK
14.1
MCU_CLK
This clock drives 8032 core Watchdog Timer (WDT). frequency MCU_CLK equal fOSC default, divided much 2048, shown Figure bits CPUPS[2:0] select eight different divisors, ranging from 2048. frequency available immediately after CPUPS[2:0] bits written. final frequency MCU_CLK fMCU. MCU_CLK blocked either bit, IDL, named PCON during Powerdown Mode Idle Mode respectively. MCU_CLK clock further divided required WDT. details Section Supervisory functions page
14.2
PERIPH_CLK
This clock drives uPSD34xx peripherals except WDT. Frequency PERIPH_CLK always fOSC. Each peripherals independently divide PERIPH_CLK scale appropriately use. PERIPH_CLK runs times except when blocked named PCON during Power-down Mode.
14.2.1
JTAG Interface Clock
JTAG interface Debugging uses externally supplied JTAG clock, coming TCK. This means JTAG interface always available, JTAG Debug interface available when enabled, even during Idle mode Power-down Mode. However, since participates JTAG debug process, MCU_CLK halted during Idle Power-down Modes, majority debug functions available during these power modes. JTAG debug interface capable executing reset command while these power modes, which will exit back normal operating mode where debug commands available again. CCON0 contains bit, DBGCE, which enables breakpoint comparators inside JTAG Debug Unit when set. DBGCE default after reset, firmware clear this run-time. Disabling these comparators will reduce current consumption Module, recommended Debug Unit will used (such production version end-product).
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clock generation
uPSD34xx
14.2.2
USB_CLK
uPSD34xx dedicated analog phase locked loop (PLL) that configured generate 48MHz USB_CLK clock wide range fOSC frequencies. USB_CLK must 48MHz function properly. enabled after power power lock time clock about 200µs, firmware should wait that much time before enabling USB_CLK setting UPLLCE CCON0 Register '1.' disabled Power-down mode, also disabled enabled writing PLLEN CCON0 Register. output clock frequency (fUSB_CLK) determined using following formula:
USBCLK PLLM PLLD
where PLLM PLLD multiplier divisor that specified CCON1 Register. fOSC, PLLM PLLD range must meet following conditions generate stable USB_CLK: PLLM (binary: [11111] PLLM[4:0] [11110]), PLLD (binary: [1111] PLLD[3:0] [1110]), fOSC/(PLLD+2) must equal greater than 3MHz.
requires 48MHz clock operate correctly. PLLM[4:0] PLLD[3:0] values must selected generate USB_CLK that close 48MHz possible different oscillator frequencies (fOSC). Table lists some PLLM PLLD values that used common fOSC frequencies. Table
fOSC (MHz) 40.0 36.0 33.0 30.0 24.0 16.0 12.0
PLLM PLLD Values Different fOSC Frequencies
PLLM[4:0] decimal binary 10110 00110 11110 01110 10010 11100 11110 10110 11110 11110 PLLD[3:0] decimal binary 1000 0001 1001 0011 0011 0011 0010 0000 0000 1111 fUSB_CLK (MHz) 48.0 48.0 48.0 48.0 48.0 48.0 48.0 48.0 48.0 48.0
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uPSD34xx Figure Clock Generation Logic
PCON[1]: Power-Down Mode CCON[2:0], Clock Pre-Scaler Select
XTAL1 (default)
clock generation
PCON[0]: IDL, Idle Mode
XTAL1 (fOSC)
XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 /1024 XTAL1 /2048
MCU_CLK (fMCU) (to: 8032, WDT)
Clock Divider PERIPH_CLK (fOSC) (to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC)
USB_CLK
PCON[1] CCON0[6]
AI10433b
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clock generation Table
PLLM[4]
uPSD34xx CCON0: Clock Control Register (SFR F9h, reset value 50h)
PLLEN UPLLCE DBGCE CPUAR CPUPS[2:0]
Symbol PLLM[4]
Definition Upper 5-bit PLLM[4:0] Multiplier (Default: PLLM 00h) Enable Disable operation Enable operation (Default condition after reset) Clock Enable clock disabled (Default condition after reset) clock enabled Debug Unit Breakpoint Comparator Enable
PLLEN
UPLLCE
DBGCE
JTAG Debug Unit comparators disabled JTAG Debug Unit comparators enabled (Default condition after reset) Automatic Clock Recovery
CPUAR
There change CPUPS[2:0] when interrupt occurs. Contents CPUPS[2:0] automatically become 000b whenever interrupt occurs. MCUCLK Pre-Scaler 000b: fMCU fOSC (Default after reset) 001b: fMCU fOSC/2 010b: fMCU fOSC/4 011b: fMCU fOSC/8 100b: fMCU fOSC/16 101b: fMCU fOSC/32 110b: fMCU fOSC/1024 111b: fMCU fOSC/2048
CPUPS
Table
CCON1 Control Register (SFR FAh, reset value 00h)
PLLM[3:0]
PLLD[3:0]
Symbol
Definition Lower bits 5-bit PLLM[4:0] Multiplier (Default after reset: PLLM 00h) PLLM[4] CCON0 Register. 4-bit Divider (Default after reset: PLLD
PLLM[3:0] PLLD[3:0]
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uPSD34xx
Power saving modes
Power saving modes
uPSD34xx combination die, modules, each module having current consumption characteristics. This section describes reduced power modes Module. Section 28.1.16: Power management page reduced power modes Module. Total current consumption combined modules determined specifications this document. Module three software-selectable modes reduced power operation.
Idle Mode Power-down Mode Reduced Frequency Mode
15.1
Idle Mode
Idle Mode will halt 8032 core while leaving peripherals active (Idle Mode blocks MCU_CLK only). lowest current consumption this mode, recommended disable unused peripherals, before entering Idle mode (such Debug Unit breakpoint comparators). following functions remain fully active during Idle Mode (except disabled settings).
External Interrupts INT0 INT1 Timer Timer Timer Supervisor reset from: LVD, JTAG Debug, External RESET_IN_, Interface UART0 UART1 Interfaces Interface Programmable Counter Array Interface
interrupt generated these peripherals, reset generated from supervisor, will cause Idle Mode exit 8032 will resume normal operation. output state pins ports remain unchanged during Idle Mode. enter Idle Mode, 8032 executes instruction named PCON, shown Table page This last instruction executed normal operating mode before Idle Mode activated. Once Idle Mode, status entirely preserved, there changes PSW, ACC, SFRs, DATA, IDATA, XDATA. following factors related Idle Mode exit:
Activation enabled interrupt will cause cleared hardware, terminating Idle Mode. interrupt serviced, following Return from Interrupt instruction (RETI), next instruction executed will which follows instruction that PCON SFR. After reset from supervisor, cleared, Idle Mode terminated, restarts after three machine cycles.
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Power saving modes
uPSD34xx
15.2
Power-down Mode
Power-down Mode will halt 8032 core peripherals (Power-down Mode blocks MCU_CLK, USB_CLK, PERIPH_CLK). This lowest power state Module. When Module also placed Power-down mode, lowest total current consumption combined achieved uPSD34xx. Section 28.1.16: Power management page Module section details also place Module Power-down mode. sequence 8032 instructions important when placing both modules into Power-down Mode. instruction that sets named PCON (Table page last instruction executed prior Module going into Power-down Mode. Once Power-down Mode, on-chip oscillator circuitry clocks stopped. SFRs, DATA, IDATA, XDATA preserved. Power-down Mode terminated only reset from supervisor, originating from RESET_IN_ pin, Low-Voltage Detect circuit (LVD), JTAG Debug reset command. Since clock active during Power-down mode, possible supervisor generate reset. Table page summarizes status pins peripherals during Idle Power-down Modes Module. Table page shows state 8032 address, data, control signals during these modes.
15.3
Reduced Frequency Mode
8032 consumes less current when operating lower clock frequency. reduce clock frequency run-time writing three bits, CPUPS[2:0], named CCON0 described Table page These bits effectively divide clock frequency (fOSC) coming from external crystal oscillator device. clock division range from 1/2048, resulting frequency fMCU. This clock division does affect peripherals, except WTD. clock driving same clock driving 8032 core shown Figure page firmware reduce clock frequency run-time consume less current when performing tasks that time critical, then restore full clock frequency required perform urgent tasks. Returning full clock frequency done automatically upon interrupt, CPUAR named CCON0 (the interrupt will force CPUPS[2:0] 000). This excellent conserve power using frequency clock until event occurs that requires full performance. Table page details CPUAR. Specifications this document estimate current consumption based clock frequency.
Note:
Some bits PCON shown Table page related power control.
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uPSD34xx Table
Mode
Power saving modes Module Port Peripheral Status during Reduced Power Modes
Ports Maintain Data Maintain Data SPI, I2C, UART0,1 Active Disabled PCA, TIMER 0,1,2 Active Disabled INT0,1 Active Disabled SUPERVISORY Active(1) Disabled
Idle Powerdown
Active Disabled
Active Disabled
Note:
Watchdog Timer active during Idle Mode. Other supervisor functions active: LVD, external reset, JTAG Debug reset. Table
Mode Idle Power-down
State 8032 Signals during Power-down Idle Modes
PSEN_ AD0-7 A8-15
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Power saving modes Table
SMOD0
uPSD34xx PCON: Power Control Register (SFR 87h, reset value 00h)
SMOD1 RCLK1 TCLK1
Symbol
Function Baud Rate Double (UART0) Doubling Doubling (See Section 21.3: UART baud rates page details.) Baud Rate Double UART (UART1) Doubling Doubling (See Section 21.3: UART baud rates page details.) Reserved Only power-on reset sets this (cold reset). Warm reset will this bit. Cleared zero with firmware only power-on reset generated Supervisory circuit (see Section 19.3: Power-up reset page details). Received Clock Flag (UART1) (See Table page flag description.) Transmit Clock Flag (UART1) (See Table page flag description) Activate Power-down Mode Power-down Mode Enter Power-down Mode Activate Idle Mode Idle Mode Enter Idle Mode
SMOD0
SMOD1
RCLK1 TCLK1
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uPSD34xx
Oscillator external components
Oscillator external components
oscillator circuit uPSD34xx devices single stage, inverting amplifier Pierce oscillator configuration. internal circuitry between pins XTAL1 XTAL2 basically inverter biased transfer point. Either external quartz crystal ceramic resonator used feedback element complete oscillator circuit. Both operated parallel resonance. Ceramic resonators lower cost, typically have wider frequency tolerance than quartz crystals. Alternatively, external clock source from oscillator other active device drive uPSD34xx oscillator circuit input directly, instead using crystal resonator. minimum frequency quartz crystal, ceramic resonator, external clock source 3MHz used. minimum 8MHz used. maximum 40MHz cases. This frequency fOSC, which divided internally described Section clock generation page XTAL1 high gain amplifier input, XTAL2 output. drive uPSD34xx device externally from oscillator other active device, XTAL1 driven XTAL2 left open-circuit. This external source should drive logic voltage level below, logic high 0.7V above, 5.5V VCC. XTAL1 input tolerant. Most quartz crystals range 25MHz 40MHz operate third overtone frequency mode. external tank circuit XTAL2 output oscillator circuit needed achieve third overtone frequency, shown Figure page Without this circuit, crystal will oscillate fundamental frequency mode that about desired overtone frequency.
Note:
Figure page crystals which specified operate fundamental mode (not overtone mode) need circuit components. Since quartz crystals ceramic resonators have their characteristics based their manufacturer, wise also consult manufacturer's recommended values external components.
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Oscillator external components Figure Oscillator clock connections
XTAL1 (in) XTAL2 (out) Crystal Resonator Usage
uPSD34xx
XTAL (fOSC)
XTAL (fOSC) Ceramic Resonator Crystal, fundamental mode (3-40MHz) Crystal, overtone mode (25-40MHz)
50pF 15-33pF 20pF
None None 10nF
None None 2.2µH
Direct Drive
XTAL1 (in)
XTAL2 (out)
External Ocsillator Active Clock Source
Connect
AI09198
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uPSD34xx
ports module
ports module
Module three 8-bit ports: Port Port Port Module four other ports: Port This section describes only ports Module. ports will function bi-directional General Purpose (GPIO), port pins have alternate functions assigned run-time writing specific SFRs. default operating mode (during after reset) three ports GPIO input mode. Port pins that have external connection will float because each internal weak pull-up (~150K ohms) VCC. ports tolerant, meaning they driven/pulled externally 5.5V without damage. pins Port have higher current capability than pins Ports Three additional ports (only 80-pin uPSD34xx devices) dedicated bring 8032 address, data, control signals external pins. port, named MCUAD[7:0], eight multiplexed address/data bidirectional signals. third port control outputs: read, write, program fetch, address latch. These ports typically used connect external parallel peripherals memory devices, they used GPIO. Notice that eight upper address signals come pins port. high-order address signals required external pins (MCU addresses A[15:8]), then these address signals brought needed output pins Address mode pins Module ports. Module section, "Section 28.5.39: Latched address output mode page details. Figure page represents flexibility function routing controlled SFRs. Each pins three ports, individually routed pin-bypin basis desired function.
17.1
port operating modes
port pins operate GPIO alternate functions (see Figure page through Figure page 72). Depending selected function, particular operating mode will automatically used:
GPIO Quasi-bidirectional mode UART0, UART1 Quasi-bidirectional mode Quasi-bidirectional mode Open drain mode Analog input mode output Push-Pull mode input Input only (Quasi-bidirectional) Timer 0,1,2 Input only (Quasi-bidirectional)
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ports module
uPSD34xx
17.1.1
GPIO function
Ports GPIO mode operate quasi-bidirectional pins, consistent with standard 8051 architecture. GPIO pins individually controlled three SFRs:
SFR, (Table page SFR, (Table page SFR, (Table page
These SFRs accessed using Addressing mode, efficient control individual port pins.
17.1.2
GPIO output
Simply stated, when logic written these port SFRs while GPIO mode, corresponding port will enable low-side driver, which pulls ground, same time releases high-side driver pull-ups, resulting logic output. When logic written SFR, low-side driver released, high-side driver enabled just MCU_CLK period rapidly make 0-to1 transition pin, while weak active pull-ups (total ~150K) enabled. This structure consistent with standard 8051 architecture. high side driver momentarily enabled only 0-to-1 transitions, which implemented with delay function latch output pictured Figure page Figure page Figure page After high-side driver disabled, weak pull-ups remain enabled resulting logic output pin, sourcing external device. Optionally, external pull-up resistor added additional source current needed while outputting logic '1.'
17.1.3
GPIO input
GPIO port input, low-side driver ground must disabled, else true logic level being driven external device will masked (always reads logic '0'). make port "input ready", corresponding must have been logic prior reading that input. reset condition forces SFRs FFh, thus three ports input ready after reset. When used input, stronger pull-up maintains solid logic until external device drives input low. this time, pull-up automatically disabled, only pull-up will source external device consistent with standard 8051 architecture. GPIO Bi-Directional. possible operate individual port pins bi-directional mode. output, firmware would simply write corresponding logic needed. before using input, firmware must first ensure that logic last value written corresponding prior reading that input. GPIO Current Capability. GPIO Port sink twice much current than either Port Port when low-side driver outputting logic (IOL). specifications this document full details. Reading Port Reading Port Latch. When firmware reads GPIO ports, sometimes actual port sampled hardware, sometimes port latch read actual pin, depending type instruction used. These data paths shown Figure page through Figure page latches read (and pins) only when read part read-modify-write instruction write destination bits port SFR. These instructions are: ANL, ORL, XRL, JBC,
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uPSD34xx
ports module CPL, INC, DEC, DJNZ, MOV, CLR, SETB. other types reads port SFRs will read actual logic level port latch. This consistent with 8051 architecture. Figure module port function routing
Module Ports
GPIO UART0 TIMER0/1
GPIO
TIMER2 UART1
GPIO
8032 CORE
Addr Data[7:0]
Address [15:8]
80-pin Devices Only
(Available Module Pins) PSEN,
AI09199b
Figure cell block diagram port
Select_Alternate_Func DELAY, MCU_CLK Digital_Alt_Func_Data_Out P1.X Read Latch (for R-M-W instructions) MCU_Reset 8032 Data GPIO P1.X Write Latch P1.X Latch DELAY, MCU_CLK
SIDE HIGH SIDE
WEAK PULL-UP,
STONGER PULL-UP,
P1.X
P1.X Read Analog_Alt_Func_En Digital_Pin_Data_In Analog_Pin_In
AI09600
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ports module Figure cell block diagram port
Enable_I Select_Alternate_Func DELAY, MCU_CLK Digital_Alt_Func_Data_Out P3.X Read Latch (for R-M-W instructions) MCU_Reset 8032 Data GPIO P3.X Write Latch P3.X Latch DELAY, MCU_CLK
SIDE Disables High-Side Driver
uPSD34xx
WEAK PULL-UP,
STONGER PULL-UP,
HIGH SIDE
P3.X
P3.X Read Digital_Pin_Data_In
AI09601
Figure cell block diagram port
Enable_Push_Pull Select_Alternate_Func DELAY, MCU_CLK Digital_Alt_Func_Data_Out P4.X Read Latch (for R-M-W instructions) MCU_Reset 8032 Data GPIO P4.X Write Latch P4.X Latch DELAY, MCU_CLK
SIDE Alternate Function
WEAK PULL-UP,
STONGER PULL-UP,
HIGH SIDE
P4.X
P4.X Read Digital_Pin_Data_In
AI09602
72/293
uPSD34xx Table
P1.7
ports module port register (SFR 90h, reset value FFh)
P1.6 P1.5 P1.4 P1.3 P1.2 Function(1) Port Port Port Port Port Port Port Port P1.1 P1.0
Symbol P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
Note:
Write output. Read input, prior READ, this must have been firmware reset event. Table
P3.7
Port Register (SFR B0h, reset value FFh)
P3.6 P3.5 P3.4 P3.3 P3.2 Function(1) Port Port Port Port Port Port Port Port P3.1 P3.0
Symbol P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
Note:
Write output. Read input, prior READ, this must have been firmware reset event.
73/293
ports module Table
P4.7
uPSD34xx
Port Register (SFR C0h, reset value FFh)
P4.6 P4.5 P4.4 P4.3 P4.2 Function(1) Port Port Port Port Port Port Port Port P4.1 P4.0
Symbol P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
Note:
Write output. Read input, prior READ, this must have been firmware reset event.
17.1.4
Alternate Functions
There five SFRs used control mapping alternate functions onto port pins, these SFRs depicted switches Figure page
Port uses SFR, P3SFS (Table page 75). Port uses SFRs, P1SFS0 (Table page P1SFS1 (Table page 76). Port uses SFRs, P4SFS0 (Table page P4SFS1 (Table page 76).
Since these SFRs cleared reset, then default port pins function GPIO (not alternate function) until firmware initializes these SFRs. Each each three ports independently assigned different function pin-by-pin basis. peripheral functions Timer UART1, split independently between Port Port additional flexibility giving wider choice peripheral usage limited number device pins. When selected alternate function UART0, UART1, SPI, then related pins quasi-bidirectional mode, including high-side driver rapid 0-to-1 output transitions. high-side driver enabled just MCU_CLK period 0-to-1 transitions delay function "digital_alt_func_data_out" signal pictured Figure page through Figure page alternate function Timer Timer Timer input, then related pins quasi-bidirectional mode, input only. alternate function ADC, then each pull-ups, high-side driver, low-side driver disabled. analog input routed directly unit. Only Port supports analog functions (Figure page 71). Port tolerant. alternate function I2C, related pins will open drain mode, which just like quasi-bidirectional mode high-side driver enabled cycle when
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uPSD34xx
ports module outputting 0-to-1 transition. Only low-side driver internal weak pull-ups used. Only Port supports open-drain mode (Figure page 72). requires external pull-up resistor each signal, typically 4.7K VCC. alternate function output, then related pins push-pull mode, meaning pins actively driven held logic high-side driver, actively driven held logic low-side driver. Only Port supports push-pull mode (Figure page 72). Port push-pull pins source current when driving logic '1,' sink current when driving logic '0.' This current significantly more than capability pins Port Port (see Table page 265). example, assign these port functions:
Port UART1, ADC[1:0], P1[7:4] GPIO Port UART0, I2C, P3[5:2] GPIO Port TCM0, SPI, P4[3:1] GPIO P1SFS0 00001111b, P1SFS1 00000011b P3SFS 11000011b, P4SFS0 11110001b, P4SFS1 11110000b,
following values need written SFRs:
Table
P3SFS7
P3SFS: Port Special Function Select Register (SFR 91h, reset value 00h)
P3SFS6 P3SFS5 P3SFS4 P3SFS3 P3SFS2 P3SFS1 P3SFS0
Default Port Function Port P3SFS[i] Port Pin, GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Alternate Port Function P3SFS[i] Port Pin, UART0 Receive, RXD0 UART0 Transmit, TXD0 Intr 0/Timer Gate, EXT0INT/TG0 Intr 1/Timer Gate, EXT1INT/TG1 Counter Input, Counter Input, Data, I2CSDA Clock, I2CCL
Table
P1SF07
P1SFS0: Port Special Function Select Register (SFR 8Eh, reset value 00h)
P1SF06 P1SF05 P1SF04 P1SF03 P1SF02 P1SF01 P1SF00
75/293
ports module Table
P1SF17
uPSD34xx
P1SFS1: Port Special Function Select Register (SFR 8Fh, reset value 00h)
P1SF16 P1SF15 P1SF14 P1SF13 P1SF12 P1SF11 P1SF10
Table
P1SFS0 P1SFS1 Details
Default Port Function Alternate Port Function P1SFS0[i] P1SFS1[i] Port Pin, Timer Count Input, Timer Trigger Input, UART1 Receive, RXD1 UART1 Transmit, TXD1 Clock, SPICLK Receive, SPIRXD Transmit, SPITXD Select, SPISEL_ Alternate Port Function P1SFS0[i] P1SFS1[i] Port Pin, Input, ADC0 Input, ADC1 Input, ADC2 Input, ADC3 Input, ADC4 Input, ADC5 Input, ADC6 Input, ADC7
Port
P1SFS0[i] P1SFS1[i] Port Pin,
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Table
P4SF07
P4SFS0: Port Special Function Select Register (SFR 92h, reset value 00h)
P4SF06 P4SF05 P4SF04 P4SF03 P4SF02 P4SF01 P4SF00
Table
P4SF17
P4SFS1: Port Special Function Select Register (SFR 93h, reset value 00h)
P4SF16 P4SF15 P4SF14 P4SF13 P4SF12 P4SF11 P4SF10
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uPSD34xx Table P4SFS0 P4SFS1 Details
Default Port Function Port P4SFS0[i] P4SFS1[i] Port Pin, GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Alternate Port Function P4SFS0[i] P4SFS1[i]
ports module
Alternate Port Function P4SFS0[i] P4SFS1[i] Port Pin,
Port Pin,
PCA0 Module TCM0 Timer Count Input, PCA0 Module TCM1 Timer Trigger Input,
PCA0 Module TCM2 UART1 Receive, RXD1 PCA0 Clock, PCACLK0 PCA1 Module TCM3 PCA1 Module TCM4 PCA1 Module TCM5 PCA1 Clock, PCACLK1 UART1 Transmit, TXD1 Clock, SPICLK Receive, SPIRXD Transmit, SPITXD Select, SPISEL_
77/293
interface
uPSD34xx
interface
Module programmable interface which modified 8032 with multiplexed address data lines. supports four types data transfer (16- 8bit), each transfer to/from memory location external Module:
Code Fetch cycle using PSEN signal: fetch 16-bit code word filling prefetch queue. fetches code byte from execution; Code Read cycle using PSEN: read 16-bit code word using MOVC (Move Constant) instruction. code word routed directly by-pass PFQ; XDATA Read cycle using signal: read data byte using MOVX (Move eXternal) instruction; XDATA Write cycle using signal: write data byte using MOVX instruction
18.1
PSEN cycles
PSEN cycle, module fetches instruction from 16-bit program memory module. multiplexed address/data AD[15:0] connected module 16-bit data transfer. uPSD34xx does support external PSEN cycles cannot fetch instruction from other external program memory devices.
18.2
READ WRITE cycles
XDATA READ WRITE cycle, MCU's multiplexed AD[15:0] connected module, only lower bytes AD[7:0] used 8-bit data transfer. AD[7:0] lines also connected pins 80-pin package accessing external devices. high address byte A[15:8] needed external devices, Port Module configured provide latched A[15:8] address outputs.
18.3
Connecting external devices
uPSD34xx supports 8-bit only external Data memory devices. READ WRITE data transfer carried AD[7:0] which available 80-pin package. address lines brought external devices three ways: Configure Ports Module Address Output mode, shown Figure Port together with external latch, shown Figure page external latch latches address byte from AD[7:0] with signal.This configuration design where Port needed CPLD functions; Configure microcell CPLD output address line CPLD output pins. This most flexible implementation requires CPLD resources.
Ports Module configured PSDsoft provide latched address A[7:0] A[15:8] (see Section 28.5: module detailed operation page details enable Address Output mode). latched address outputs ports configurable. example, Port pins PB[2:0] enabled provide
78/293
uPSD34xx
interface A[10:8] remaining pins configured other functions such generating chip selects external devices. Figure Connecting external devices using ports address AD[15:0]
uPSD34xx
Module
AD[7:0] AD[15:8] PSEN
Module A8-15 A0-7
Port Port
D[7:0]
AI10434
External 8-bit Device
Figure Connecting external devices using port external latch address AD[15:0]
uPSD34xx
Module
AD[7:0] AD[15:8] PSEN
Module
Port
A8-15
D[7:0]
AI10435
A7-0
External 8-bit Device
18.4
Programmable timing
length cycles user programmable time. number MCU_CLK periods cycle specified register named BUSCON (see Table page 81). default, BUSCON Register loaded with long cycle times MCU_CLK periods) after reset condition. important that post-reset initialization firmware sets cycle times appropriately most performance, according Table page Keep mind that Module faster Turbo Mode (default) slower less power consuming Non-Turbo Mode. cycle times must programmed BUSCON optimize each mode shown Table Section 28.5: module detailed operation page more details.
79/293
interface
uPSD34xx
possible specify BUSCON Register different number MCU_CLK periods various address ranges. example, user cannot specify MCU_CLK periods read cycles address range Module, MCU_CLK periods read cycles different address range external device. However, user specify number clock periods PSEN read cycles different number clock periods cycles (see Figure page 80).
18.5
Controlling
BUSCON Register allows firmware enable disable run-time. Sometimes desired disable ensure deterministic execution. dynamic action cause varying program execution times depending events that happen prior particular section code interest. this reason, recommended implement timing loops firmware, instead many hardware timers uPSD34xx. default, enabled after reset condition. Important note: Disabling will seriously reduce performance. Figure PSEN cycle MCU_CLK
Clock
D0-D15(1)
AD0-AD15
A0-A15
RD/PSEN(2,3) 5-Clock Cycle
AI10436
Note:
PSEN cycle 16-bit, while cycle 8-bit only. PSEN cycle progress aborted before completion Branch Cache (BC) determines current code fetch cycle needed. Whenever same number MCU_CLK periods specified BUSCON both PSEN cycles, cycle timing typically identical each these types cycles. this case, only time PSEN read cycles longer than read cycles when issues stall while reloading. stalls affect read cycles. comparison, many traditional 8051 architectures, cycles always longer than PSEN cycles.
80/293
uPSD34xx Table
EPFQ
interface BUSCON: control register (SFR 9Dh, reset value EBh)
WRW[1:0]
RDW[1:0]
CW[1:0]
Symbol
Definition Enable Pre-Fetch Queue disabled enabled (default) Enable Branch Cache disabled enabled (default) Wait, number MCU_CLK periods write cycle during MOVX instruction 00b: clock periods 01b: clock periods 10b: clock periods (default) 11b: clock periods Wait, number MCU_CLK periods read cycle during MOVX instruction 00b: clock periods 01b: clock periods 10b: clock periods (default) 11b: clock periods Code Wait, number MCU_CLK periods PSEN read cycle during code byte fetch during MOVC code byte read instruction. Periods will increase with stall 00b: clock periods exception, MOVC instructions this setting results clock periods 01b: clock periods 10b: clock periods 11b: clock periods (default)
EPFQ
WRW[1:0]
RDW[1:0]
CW[1:0]
81/293
interface Table
uPSD34xx Number MCU_CLK Periods Required Optimize Transfer Rate
CW[1:0] Periods 3.3V(1) 5V(1) RDW[1:0] Periods 3.3V(1) 5V(1) WRW[1:0] Periods 3.3V(1) 5V(1)
Clock Frequency, MCU_CLK (fMCU) 40MHz, Turbo mode PSD(2) 40MHz, Non-Turbo mode 36MHz, Turbo mode 36MHz, Non-Turbo mode 32MHz, Turbo mode 32MHz, Non-Turbo mode 28MHz, Turbo mode 28MHz, Non-Turbo mode 24MHz, Turbo mode 24MHz, Non-Turbo mode 20MHz below, Turbo mode 20MHz below, Non-Turbo mode
Note:
Module "Turbo mode PSD" means that Module faster, Turbo mode (default condition). Module Non-Turbo mode slower, consumes less current. Module section, titled "PLD Non-Turbo Mode" details.
82/293
uPSD34xx
Supervisory functions
Supervisory functions
Supervisory circuitry Module will issue internal reset signal Module simultaneously Module result following four events:
external RESET_IN asserted Voltage Detect (LVD) circuitry detected voltage below specific threshold (power-on voltage sags) JTAG Debug interface issued reset command Watch Timer (WDT) timed
resulting internal reset signal, MCU_RESET, will force 8032 into known reset state while asserted, then 8032 program execution will jump reset vector program address 0000h just after MCU_RESET deasserted. Module will also assert active internal reset signal, RESET, Module. needed, signal RESET driven external system components through output Module. When driving this "RESET_OUT" signal from output, user choose make either active-high active-low logic, depending equation.
19.1
External reset input pin, RESET_IN
RESET_IN connected directly mechanical reset switch other device which pulls signal ground invoke reset. RESET_IN pulled internally enters Schmitt trigger input buffer with voltage hysteresis VRST_HYS immunity effects slow signal rise fall times, shown Figure RESET_IN also filtered reject voltage spike less than duration tRST_FIL. RESET_IN signal must maintained logic least duration tRST_LO_IN while oscillator running. resulting MCU_RESET signal will last only long RESET_IN signal active stretched). Refer Supervisor specifications Table page this document these parameter values. Figure Supervisor reset generation
PULL-UP
RESET_IN
Noise Filter
Clock Sync
JTAG Debug DELAY, tRST_ACTV
MCU_RESET Peripherals
RESET Module
AI09603
83/293
Supervisory functions
uPSD34xx
19.2
voltage detect,
internal reset generated circuit when drops below reset threshold, VLV_THRESH. After returns reset threshold, MCU_RESET signal will remain asserted tRST_ACTV before released. circuit always enabled (cannot disabled SFR), even Idle Mode Power-down Mode. input voltage hysteresis VRST_HYS will reject voltage spikes less than duration tRST_FIL. Important note: voltage threshold VLV_THRESH, suitable monitoring both 3.3V supply Module 3.3V supply Module 3.3V uPSD34xxV devices, since these supplies same circuit board. However, uPSD34xx devices, VLV_THRESH suitable monitoring voltage supply (VLV_THRESH low), good monitoring 3.3V supply. case uPSD34xx devices, external means required monitor separate supply, desired.
19.3
Power-up reset
power internal reset generated circuit latched logic named PCON (Table page 66). Software read this determine whether last reset result power (cold reset) reset from some other condition (warm reset). This must cleared with software.
19.4
JTAG debug reset
JTAG Debug Unit generate reset debugging purposes. This reset source also available when Idle Mode Power-Down Mode (the user JTAG debugger exit these modes).
19.5
Watchdog timer,
When enabled, will generate reset whenever overflows. Firmware that behaving correctly will periodically clear before overflows. Run-away firmware will able clear WDT, reset will generated. default, disabled after each reset.
Note:
active during Idle mode Power-down Mode. There SFRs that control WDT, they WDKEY (Table page WDRST (Table page 86). WDKEY contains 55h, disabled. value other than WDKEY will enable WDT. default, after reset condition, WDKEY automatically loaded with 55h, disabling WDT. responsibility initialization firmware write some value other than WDKEY after each reset used. consists 24-bit up-counter (Figure 24), whose initial count 000000h default after every reset. most significant byte this counter controlled SFR, WDRST. After being enabled WDKEY, 24-bit count increased each machine cycle. When count overflows beyond FFFFFh (224 machine cycles), reset issued automatically disabled (WDKEY again).
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uPSD34xx
Supervisory functions prevent from timing generating reset, firmware must repeatedly write some value WDRST before count reaches FFFFFh. Whenever WDRST written, upper bits 24-bit counter loaded with written value, lower bits counter cleared 0000h. time-out period adjusted writing value other that WDRST. example, WDRST written with 04h, then will start counting 040000h, 040001h, 040002h, each machine cycle. this example, time-out period shorter than WDRST written with 00h, because up-counter. value WDRST should never written that results time-out period shorter than time required complete longest code task application, else unwanted overflows will occur. Figure Watchdog counter
8-bits 8-bits 8-bits
SFR, WDRST
AI09604
formula determine time-out period WDTPERIOD tMACH_CYC NOVERFLOW NOVERFLOW number up-counts required reach FFFFFFh. This determined value written SFR, WDRST. tMACH_CYC average duration machine cycle. default, machine cycle always MCU_CLK periods uPSD34xx, following factors sometimes more MCU_CLK periods machine cycle:
number MCU_CLK periods assigned memory cycles determined SFR, BUSCON. this setting greater than then machine cycles have additional MCU_CLK periods during memory transfers. Whether PFQ/BC circuitry issues stall during particular machine cycle. stall adds more MCU_CLK periods machine cycle until stall removed.
tMACH_CYC also affected absolute time single MCU_CLK period. This number fixed following factors:
Frequency external crystal, resonator, oscillator: (fOSC) settings CCON0, which divide fO
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