Mobile video DENC analog outputs bits DAC) with: CVBS (Composite)

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Mobile video DENC analog outputs bits DAC) with: CVBS (Composite)

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STw8009 STw8019
Mobile video DENC
analog outputs bits DAC) with: CVBS (Composite) output (S-VHS) NTSC-J, 4.43 PAL-BDGHI, support current driver 8-bit digital interface input supporting both embedded external synchro CCIR YCbCr 4:2:2 format CCIR 656: pixel input clock Latest Macrovision (7.1.L1) (STw8019 only) 2-wire serial interface (I2C compatible) Master slave modes plug insertion detection Supply voltages 2.8V/3.3V analog 1.8V/2.8Vdigital 1.2V/1.4V core Power consumption Sleep mode: Standby mode: maximum CVBS: Y/C: Package TFBGA 4x4x1.2 height, pitch, VFBGA 3x3x1 height, pitch Full matrix:
STw8009
TFBGA VFBGA
Description
STw80x9 aimed mobile video Digital ENCoder (DENC). This device converts digital video signals into high quality analog signal compliant with standards, able encode interlaced standards) non-interlaced NTSC). Featuring ultra power consumption, suits perfectly mobile appliances that interface occasionally with sets VCRs. also ideal companion digital application processors such ST's Nomadik family. minimize space usage, STw80x9 features high level integration. STw80x9 drives directly video input, CVBS video input through optional protection devices. clock device power management controlled through digital processor interface [PORn, Suspend 2-wire compatible serial MPU]. This digital processor interface also controls STw80x9 operating modes (off, sleep, standby active).
Applications
Mobile video Digital ENCoder (DENC)
June 2007
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www.st.com
Contents
STw8009/STw8019
Contents
Overview Functional block diagram Ball/pin information Functional description
4.10 4.11 4.12 4.13 General Master slave modes Auto test mode Input demultiplexor Video timing Sub-carrier generation Luminance encoding Chrominance encoding Composite video signal generation Macrovisioncopy protection TV/VCR plug insertion detection Power management
4.13.1 4.13.2 Operating modes Mode transition diagram
4.14
JTAG interface
Control registers
Register addresses Description
5.2.1 5.2.2
DENC registers Control power management unit registers
interface
wire serial control interface (I2C compatible)
7-bit address mode
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STw8009/STw8019
Contents bits address mode.
YcbCr
Electrical characteristics
Absolute maximum rating Operating conditions Electrical timing characteristics
Application information Color test pattern waveforms Package mechanical data
10.1 10.2 TFBGA balls VFBGA balls
Ordering information Revision history
3/65
List tables
STw8009/STw8019
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Product name ball functions NTSC timings Register addresses std1, std0 sync2, sync1, sync0 Register valrst1 valrst0 selection syncin_ad[1:0]. syncout_ad[1:0] jump, dec_ninc, free_jump cfc[1:0]: color frequency control line ph_rst_mode[1:0]:sub-carrier phase reset dac2_mult[5:0]: multiplying factor dac2_c digital signal c_mult[3:0]: multiplying factor digital output Chroma main_coef_[8:0] main_del[3:0] Luma_coef_[0:9] dac12_conf dac1_multi[5:0] main_chr_del[3:0] STw80x9 addresses YcBCr data timing (Figure Absolute maximum ratings Operating conditions wire serial control interface timing (Figure Digital interface Power consumption/R load 37.5 Video output characteristics Rload 37.5 Rext kohm TFBGA 4x4x1.2 VFBGA 3x3x1.0 balls Pitch ball 0.25 Order codes Document revision history
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STw8009/STw8019
List figures
List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Application diagram STw8009 block diagram STw8019 block diagram Ball layout Input data format (ITU-R656/D1 4:2:2) PAL-BDGHI, PAL-N typical waveform, interlaced mode (ITU-R625 line numbering) NTSC-M typical waveforms, interlaced mode (SMTPE-524 line numbering PAL-M typical waveforms, interlaced mode (ITU-R/CCIR-525 line numbering) Horizontal blanked interval active video timings Luma filtering Luma filtering with 3.58 trap Luma filtering with 4.43 trap chroma filter chroma filter chroma filter chroma filter Mode transition diagram 2-wire serial control interface format (I2C compatible) 7-bit addresses. 2-wire serial control interface format (I2C compatible) 10-bit addresses. 2-wire serial control interface timing YcbCr format Data timing. Typical application schematic NTSC composite. NTSC S-video composite S-video TFBGA balls body size VFBGA balls body size
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Overview
STw8009/STw8019
Overview
STw80x9 aimed mobile video Digital ENCoder (DENC). This device converts digital video signals into high quality analog signal compliant with standards, able encode interlaced standards) non-interlaced NTSC). Featuring ultra power consumption, suits perfectly mobile appliances that interface occasionally with sets VCRs. also ideal companion digital application processors such ST's Nomadik family. minimize space usage, device features high level integration. high performance allows direct drive 37.5 load. STw80x9 drives directly video input, CVBS video input through optional protection devices. powered three voltage supplies, 2.8V/3.3V, 1.8V/2.8V 1.2V/1.4V (VccA, VI/O, Vdd). clock device power management controlled through digital processor interface [PORn, Suspend 2-wire compatible serial MPU]. This digital processor interface also controls operating modes (off, sleep, standby active). Figure Application diagram
STw80x9 Video YCbCr PORn C/CVBS protection
Digital processor
Suspend VccA VccA
Supply
Naming convention
Unless clearly specified document, STw80x9 stands both STw8009 STw8019.
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STw8009/STw8019
Functional block diagram
Figure
Functional block diagram
STw8009 block diagram
Figure
STw8019 block diagram
7/65
Ball/pin information
STw8009/STw8019
Table
Ball
Ball/pin information
Product name ball functions
Name Gndd VddIO1 VssIO1 VddIO2 VssIO2 VccA1 VccA2 VccA3 VccA4 GNDA1 GNDA2 GNDA3 GNDA4 GNDA5 Rext Type Power Power Power Power Power Power Power Analog Digital Input 1.8V/2.8V Voltage 1.2V/1.4V 1.8V/2.8V 1.8V/2.8V 2.8V/3.3V 2.8V/3.3V 2.8V/3.3V 2.8V/3.3V Description Digital core chip supply Digital core chip ground Digital supply Digital ground Digital supply Digital ground DAC2 matrix analog power supply DAC1 matrix analog power supply 2.8/3.3 digital feature supply /3.3 digital feature supply DAC2 ground DAC1 ground /3.3 digital feature ground Rext ground connection Analog ground current reference setting master pixel clock (pixclk) Time multiplexed 4:2:2 luminance chrominance data defined CCIR CCIR (excepted input signals) Horizontal synchronization signal: Input slave mode, except when sync extracted from YcbCr data Output master mode when sync extracted from YcbCr signal. Vertical Synchronization Odd/Even signal: Input slave mode, except when sync extracted from YcbCr data Output master mode when sync extracted from YcbCr signal. wire serial data line wire serial clock Device address selection Power Reset (Active low) Suspend input
YCbCr[0:7]
Digital Input
1.8V/2.8V
Hsync
Digital
1.8V/2.8V
Vsync Odd/Even
Digital
1.8V/2.8V
PORn Suspend
Digital Digital Input Digital input Digital input Digital input
1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V
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STw8009/STw8019 Table
Ball
Ball/pin information
Product name ball functions (continued)
Name C/CVBS Test tst_ana[0:2] PlugDet Type Analog output Analog output Digital input Digital output Digital input Digital input Digital input Digital input Digital input 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V Voltage Description output selected composite video chroma signal s-video. Luminance signal s-video JTAG test data used, connected JTAG test data used, left open JTAG test clock used, connected JTAG test mode select used, connected device test mode used, connected DENC test used, connected plug connection detection CMOS input
Figure
Ball layout
C/CVBS
VccA1
Rext
VccA2
VccA3
GNDA1
GNDA4
GNDA2
GNDA5
VccA4
Vdd_IO1
GNDA3
PORn
Vss_IO1
Gndd
tst_ana[0]
Test
YCbCr[7]
YCbCr[6]
tst_ana[2]
Vss_IO2
YCbCr[5]
YCbCr[4]
tst_ana[1]
Suspend
PlugDet
Vsync
YCbCr[3]
YCbCr[2]
Vdd_IO2
Hsync
YCbCr[1]
YCbCr[0]
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Functional description
STw8009/STw8019
Functional description
General
STw80x9 operates either master mode where supplies sync signal slave mode. digital input 8-bit carrying 13.5 MHz. Input samples latched rising edge clock input signal. STw80x9 able encode interlaced standards) interlaced NTSC) video. STw80x9 outputs interlaced non-interlaced video PAL-B,D,G,H,I,PAL-N,PAL-M NTSC-M standards ("NTSC-4.43" also possible). burst sequences internally generated, subcarrier generation being performed numerically with reference. 4-frame bursts generated 2-frame bursts NTSC. Rise fall times synchronization tips burst envelope internally controlled according relevant ITU_R SMPTE recommendations.
Master slave modes
master mode, STw80x9 supplies Hsync Odd/Even sync signals (with independently programmable polarities) drive other blocks. STw80x9 starts encoding counting clock cycles soon master mode been loaded into control register (Reg Configuration bits "Syncout_ad[1:0]" (Reg allow shift relative position sync signals clock cycles cope with YcbCr phasing. slave modes, several modes available, Odd/Even+Hsync based, Vsync+Hsync based, Odd/Even-only based, Vsync-only based Sync-in-data based.
Auto test mode
auto test mode available, which causes STw80x9 produce color pattern, appropriate standard, independently from video input.
Input demultiplexor
incoming YcbCr 4:2:2 data demultiplexed into chroma information stream, "bluedifference" "red-difference", luma information stream. Incoming data bits treated blue, luma samples according their relative position with respect sync signals. Brightness, Saturation Contrast then performed demultiplexed data. ITU-R601 recommendation defines black luma level Y=16dec maximum white luma level Y=235dec. Similarly defines quantification levels color difference components (Cr, centered around 128. Accordingly, incoming YcbCr samples saturated. this case STw80x9 provides saturation limitation feature avoid having heavily saturated signal before digital analog conversion avoid generating distorted signal STw80x9 CVBS outputs.
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STw8009/STw8019
Functional description
Video timing
DENC outputs video PAL-B,D,G,H,I, PAL-N, PAL-M NTSC-J, standards (`NTSC4.43' also possible). burst sequences internally generated, subcarrier generation being performed numerically with PIX_CLK reference. 4-frame bursts generated 2-frame bursts NTSC. Rise fall times synchronization tips burst envelope internally controlled according relevant ITU-R SMPTE recommendations.
Figure depict typical waveforms.
possible allow encoding incoming YCrCb data those lines that bear line sync pulses pre/post-equalization pulses (Figure This mode operation referred "partial blanking" default set-up. allows keep encoded waveform data present digitized form incoming YCrCb stream. Alternatively, complete fully blanked, incoming YCrCb data encoded these lines. `complete' comprises following lines: 525/60 systems (SMPTE line numbering convention): lines second half line line 625/50 systems (CCIR line numbering convention): second half line line lines 525/60 systems (SMPTE line numbering convention): lines second half line line 625/50 systems (CCIR line numbering convention): second half line line lines
`partial' consists
Full partial blanking controlled configuration `blkli configuration register1'.
Note:
line 525/60/SMPTE systems either fully blanked fully active. line 625/60/CCIR systems always fully active.
ITU-R656-compliant digital line, active portion digital line portion included between (Start Active Video) (End Active Video) words. However, this digital active line starts somewhat earlier slightly later than active line usually defined analog standards. DENC permits approaches:
Encodes full digital line (720 pixels 1440 clock cycles). this case, output waveform will reflect full YCrCb stream included between EAV. Drops some YCrCb samples extremities digital line that encoded analog line fits within `analog' ITU-R/SMPTE specifications.
Selection between these modes operation performed with `aline' configuration register cases, transitions between horizontal blanking active video shaped avoid steep edges within active video. Figure page gives timings concerning horizontal blanking interval active video interval.
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Functional description Figure Input data format (ITU-R656/D1 4:2:2)
STw8009/STw8019
128T NTSC, 137T 146T (PAL 128T SECAM 151T (145T SECAM)
1440T 1716T Digital active line
1440T 1728T Digital active line
115T Square pixel system 131T 1560T
1280T Digital active line
Square pixel system
139T 1888T 169T
1536T Digital active line clock period PAL, NTSC: 37.037
Note:
burst envelope shown here indicates location from which first subcarrier positive zero crossing sought (with respect reference). normal burst always starts with such positive zero crossing.
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STw8009/STw8019 Figure
Functional description
PAL-BDGHI, PAL-N typical waveform, interlaced mode (ITU-R625 line numbering)
Full VBI1
Partial VBI1
Partial VBI2
Full VBI2
Frame synchronization reference III, 5th, 6th, 7th, fields Burst phase nominal value +135° Burst phase nominal value -135° Burst suppression internal
Figure
NTSC-M typical waveforms, interlaced mode (SMTPE-524 line numbering
Full VBI1 Partial VBI1
Full VBI2 Partial VBI2
0.5H
0.5H VBI3
VBI4
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Functional description Figure
STw8009/STw8019
PAL-M typical waveforms, interlaced mode (ITU-R/CCIR-525 line numbering)
Full VBI1 Partial VBI1
Partial VBI2
Full VBI2
Frame synchronization reference III, 5th, 6th, 7th, fields Burst phase nominal value +135° Burst phase nominal value -135° Burst suppression internal
Figure
Horizontal blanked interval active video timings
Horizontal blanking interval Active video
Full digital line encoding (720 pixels 1440 `Analog' line encoding
(bit aline
(bit aline
(bit aline (bit aline
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STw8009/STw8019 Table NTSC timings
PAL-BDGHI 5.54 (A-type) 5.66 (B-type) 1.52 10.48 PAL-N 5.54 (A-type) 5.66 (B-type) 1.52 10.48
Functional description
NTSC-M a(1) 5.38 (even lines) 5.52 (odd lines) 1.56 1.56 9.41 cycles 3.58MHz
PAL-M 5.73 (A-type) 5.87 (B-type) 1.56 1.56 9.41 cycles 3.58MHz
cycles 4.43MHz cycles 3.58MHz
These typical values. Actual values will depend static offset programmed subcarrier generation
Sub-carrier generation
Direct Digital Frequency Synthesizer (DDFS) generates required color sub-carrier frequency using 24-bit phase accumulator. Sub-carrier frequency programmable with step.
Luminance encoding
luminance that added chrominance create composite CVBS signal trap-filtered 3.58 (NTSC) 4.43 (PAL). This supports application oriented towards low-end sets which subject cross-color. pedestal programmed needed with standards. This allows particular encode Argentinian non-Argentinian PAL-N, Japanese NTSC. programmable delay inserted luminance path offset chroma/luma delay introduced off-chip filtering. STw80x9 output signals modulated NTSC standard that sound notch filter required. notch filter which Luma path defined coefficients implemented STw80x9 default values. also programmable.
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Functional description Figure Luma filtering
STw8009/STw8019
Amplitude (dB)
Frequency (MHz)
Figure Luma filtering with 3.58 trap
Frequency (MHz)
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STw8009/STw8019 Figure Luma filtering with 4.43 trap
Functional description
Frequency (MHz)
Chrominance encoding
Chroma components computed from demultiplexed samples. Before modulating subcarrier, chroma components band-limited interpolated pixel clock rate. different filters available chroma filtering suit wide variety applications different standards filters recommended ITU-R 624-4 SMPTE170-M. available -3dB bandwidths 1.1, 1.3, MHz. Narrow bandwidths useful against cross-luminance artifacts while wide bandwidths allow keep higher chroma contents.
Figure chroma filter
Amplitude (dB)
Frequency (MHz)
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Functional description Figure chroma filter
STw8009/STw8019
Amplitude (dB)
Frequency (MHz)
Figure chroma filter
Amplitude (dB)
Frequency (MHz)
Figure chroma filter
Amplitude (dB)
Frequency (MHz)
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STw8009/STw8019
Functional description
Composite video signal generation
composite video signal created adding luminance chrominance components. saturation function included adder avoid overflow errors.
4.10
Macrovisioncopy protection
chrominance luminance composite video signals video signals altered according Macrovisioncopy protection Revision 7.01 Revision 6.1. This process controlled bus. programming document available those customers have executed license non-disclosure agreement with Macrovision Corporation. relevant information document please contact: Macrovision Corporation: 2830 Cruz Blvd. Santa Clara, CALIFORNIA 95050 www.macrovision.com
4.11
TV/VCR plug insertion detection
Plugdet ball used detect connection VCR. host read status dedicated register standby active modes.
4.12
STw80x9 outputs generate Composite video signal output video signals outputs. embedded 10-bit DACs allow STw80x9 directly drive 37.5 Ohms loads each output.
4.13
Power management
Power management includes power supplies, reset signals, clock gating dedicated pins registers. Power management used STw80x9 different operating modes.
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Functional description
STw8009/STw8019
4.13.1
Operating modes
STw80x9 following operating modes.
1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V present. values from STw80x9 registers lost. 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V present. suspend signal active. DACs their minimum power consumption mode. values from STw80x9 registers lost. pixel clock must activated power supplies present: 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V. pixel clock must activated. suspend signal inactive. STw80x9 standby mode programming Control power Management Unit registers (Reg 132) through wire serial interface. STw80x9 saves register values. other registers (Reg 109) accessible this mode. DACs their minimum power consumption mode. This mode power state that enables fast switching active mode. power supplies present: 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V. STw80x9 receives pixel clock. suspend signal inactive. STw80x9 placed active mode programming control power management unit registers (Reg 132), through wire serial interface. STw80x9 saves register values. pixel clock distributed STw80x9.
Sleep
Standby
Active
DACs supplied /3.3 individually activated deactivated. example only CVBS output both DACs output.
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STw8009/STw8019
Functional description
4.13.2
Mode transition diagram
following mode transition diagram shows main possible transitions between modes actions.
Figure Mode transition diagram
Power supply applied Registers values lost supplies applied STw8009 suspend asserted Register values lost power mode
PORn reset occurs PORn reset occurs after 1.2V, 1.8V after CLK27M have been applied have been applied (see AN2347).
Sleep
STw8009 looses registers configuration when entering Sleep mode Suspend
Suspend
Standby
need reset Registers maintained Power consumption reduced DENC clock gated DACs power Normal operation functions available DACs dynamically used demand
Active
reconfigure DENC either direction
Transitions mode
possible transitions indicated Figure Mode transition diagram10 dotted lines. internal data needs saved STw80x9 turned from mode. only restriction comply with power supply rules described here after.
Transition from mode Sleep mode then Active mode
Power must done starting from Sleep mode then from Sleep Active mode. Sleep Standby possible. host sends order STw80x9 switch from Sleep Active mode releasing Suspend ball. device then generates reset sequence DENC part.
Transition from Active mode Sleep mode
Sleep mode, DENC powered When Suspend signal changes from device goes from Active Sleep mode internal Reset signal generated Control Power Unit management DENC part. This signal pixclk duration (pixclk MHz).
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Functional description
STw8009/STw8019
Transition between Standby Active modes
Transitions between these modes applied software configuration through interface.
Supply management
power supplies must applied according following sequence: VddIO1, VddIO2 (1.8V/2.8V) then, (1.2V/1.4V) then, VccA1, VccA2, VccA3, VccA4 (2.8V/3.3V) removed according following sequence: VccA1, VccA2, VccA3, VccA4 (2.8V/3.3V) then, (1.2V/1.4V) then, VddIO1, VddIO2 (1.8V/2.8V)
4.14
JTAG interface
ease integration STw80x9 system application, JTAG interface available.
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STw8009/STw8019
Control registers
Table
Name
Control registers
Register addresses
Register addresses
Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DENC registers
configuration0 configuration1 configuration2 configuration3 configuration4 configuration5 configuration6 configuration7 configuration8 Status increment_dfs increment_dfs increment_dfs phase_dfs phase_dfs dac2mult reserved line_reg line_reg line_reg Reserved reserved reserved c_mult Brightness Contrast Saturation Chroma_coef_0 Chroma_coef_1 Chroma_coef_2 std1 blkli nintrl main_ entrap syncin_ad1 selrst_inc softreset ph_rst_ mode1 std0 flt1 enrst trap_4.43 syncin_ad0 bkdac2 jump ph_rst_ mode0 atfr sync2 flt0 bursten sync1 sync_ok sync0 coki selrst main_del_ aline cfc1 blk_all fldct2 polh setup_main rstosc_buf val_422_ck _mux hue_en cfc0 bypass_ sync_corr flsct1 polv valrst1 fldct0 ltarg2 lref3 c0(1) c1(1) c2(1) freerun valrst0 dacinv maxdyn jump ltarg1 lref2 bcs_en_main c0(0) c1(0) c2(0)
syncout_ad syncout_ad bkdac1 dec_ninc free_jump val_422_
dac2_mult5 dac2_mult4 dac2_mult3 dac2_mult2 dac2_mult1 dac2_mult0 ltarg8 ltarg0 lref1 c_mult3 flt_s ltarg7 lref8 lref0 c_mult2 plg_div1 c8(8) c2(6) ltarg6 lref7 c_mult1 plg_div0 c1(5) c2(5) ltarg5 lref6 c_mult0 c0(4) c1(4) c2(4) ltarg4 lref5 c0(3) c1(3) c2(3) ltarg3 lref4 c0(2) c1(2) c2(2)
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Control registers Table
Name
Chroma_coef_3 Chroma_coef_4 Chroma_coef_5 Chroma_coef_6 Chroma_coef_7 Chroma_coef_8 configuration9 luma_coef_0 luma_coef_1 luma_coef_2 luma_coef_3 luma_coef_4 luma_coef_5 luma_coef_6 luma_coef_7 luma_coef_8 luma_coef_9 configuration11 configuration12 configuration13 hue_control dac1_mult Chroma_delay Chroma_delay_
STw8009/STw8019
Register addresses
Type
Bit7
c4(7) c5(7) c6(7) c7(7) c8(7) main_del3 l9(9) l6(8) l7(8) l4(7) l5(7) l6(7) l7(7) l8(7) l9(7) hue_cont
Bit6
c3(6) c4(6) c5(6) c6(6) c7(6) c8(6) main_del2 l9(8) l2(6) l3(6) l4(6) l5(6) l6(6) l7(6) l8(6) l9(6) hue_cont
Bit5
c3(5) c4(5) c5(5) c6(5) c7(5) c8(5) main_del1 l8(8) l1(5) l2(5) l3(5) l4(5) l5(5) l6(5) l7(5) l8(5) l9(5) dac12_conf hue_cont
Bit4
c3(4) c4(4) c5(4) c6(4) c7(4) c8(4) main_del0 l0(4) l1(4) l2(4) l3(4) l4(4) l5(4) l6(4) l7(4) l8(4) l9(4) hue_cont
Bit3
c3(3) c4(3) c5(3) c6(3) c7(3) c8(3) l0(3) l1(3) l2(3) l3(3) l4(3) l5(3) l6(3) l7(3) l8(3) l9(3) hue_cont
Bit2
c3(2) c4(2) c5(2) c6(2) c7(2) c8(2) plg_div_y1 l0(2) l1(2) l2(2) l3(2) l4(2) l5(2) l6(2) l7(2) l8(2) l9(2) main_if_del ennotch hue_cont
Bit1
c3(1) c4(1) c5(1) c6(1) c7(1) c8(1) plg_div_y0 l0(1) l1(1) l2(1) l3(1) l4(1) l5(1) l6(1) l7(1) l8(1) l9(1) hue_cont
Bit0
c3(0) c4(0) c5(0) c6(0) c7(0) c8(0) flt_ys l0(0) l1(0) l2(0) l3(0) l4(0) l5(0) l6(0) l7(0) l8(0) l9(0) hue_cont(0) dac1_mult0 main_chr_del main_chr_ del_en
dac1_mult5 dac1_mult4 dac1_mult3 dac1_mult2 dac1_mult1 main_chr_ del3 main_chr_ del2 main_chr_ del1
Control power management unit registers
Cpmu_conf0 Cpmu_conf1 dac2ctrl dac1ctrl Plugdet I_test0 poff1 poff2 notzero-d1 notzerod2 standby cpmuswrst pedestalOnd pedestalOnd loadD
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STw8009/STw8019
Control registers
Caution:
Description
DEFAULT mode when not_reset active (LOW level) binary values quoted should understood MSB.LSB
5.2.1
DENC registers
REGISTER content default std1 configuration0 std0 sync2 Address: 0x0000 sync1 sync0 Type: polh polv freerun
Table
std1
std1, std0
std0 BDGHI (see set-up) NTSC M(1) Standard selected
Standard hardware reset NTSC; standard modification selects automatically right parameters correct subcarrier generation.
Table
sync2
sync2, sync1, sync0
sync1 sync0 Configuration ODDEV-only based SLAVE mode (frame locked) based SLAVE mode (frame locked) ODDEV+HSYNC based SLAVE mode (line locked) VSYNC-only based SLAVE mode (frame locked)(1) VSYNC+HSYNC based SLAVE mode (line locked) MASTER mode AUTOTEST mode (colour pattern)
VSYNC-only based slave mode (sync[2:0]="100"), HSYNC nevertheless needed input.
polh: synchro: active edge HSYNC selection (when input) polarity HSYNC (when output)
HSYNC negative pulse (128 Tpix_clk wide) falling edge active HSYNC positive pulse (128 Tpix_clk wide) rising edge active
polv: synchro: active edge ODDEV/VSYNC selection (when input) falling edge ODDEV flags start field1 (odd field) VSYNC active rising edge ODDEV flags start field1 (odd field) VSYNC active high
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Control registers freerun: disabled enabled
STw8009/STw8019
Note:
This taken into account ODDEV-only VSYNC-only based slave modes irrelevant other synchronization modes.
REGISTER content default blkli configuration1 flt1 flt0 Address: 0x0001 sync_ok coki Type: setup_ main
blkli: Vertical Blanking Interval selection active video lines area (`partial blanking') Only following lines inside Vertical Interval blanked
NTSC-M: PAL-M: Other PAL: NTSC-M: PAL-M: Other PAL: lines [263(half); 272] (525-SMPTE) lines [523; [260(half); 269] (525-CCIR) lines [623(half); [311; 318] (625-CCIR) lines 19], [263(half); 282] (525-SMPTE) lines [523; 16], [260(half); 279] (525-CCIR) lines [623(half); 22], [311; 335] (625-CCIR)
"full blanking" lines inside blanked
flt[1:0]: Chroma filter bandwidth selection Table
flt1
Register
flt0 bandwidth f-3dB=1.1MHz f-3dB=1.3MHz f-3dB=1.6MHz f-3dB=1.9MHz Typical application NTSC filter filter high def. NTSC filter (ATSC compliant) (ITU-R 624.4 compliant) high def. filter: BDG/I compliant.
sync_ok: availability sync signals (analog digital) case input synchronization loss with free-run active (i.e. freerun=0) synchro output signals output synchro signals available CVBS and, when applicable, HSYNC output port), ODDEV output port): same behavior free-run except that video outputs blanked active portion line. coki: color killer color color suppressed CVBS output signal (CVBS=YS) color still present output. color suppression chroma `C', register bkdac1.
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Control registers
setup_main: pedestal Blanking level black level identical lines. (e.g.: Argentinian PAL-N, Japan NTSC-M, PAL-BDGHI) Black level above blanking level lines outside (e.g. Paraguayan Uruguayan PAL-N).
cases, gain factor adjusted obtain required levels chrominance.
Note:
Depending different output configurations chosen programming from dac12_conf, pedestal automatically selected
REGISTER content default nintrl configuration2 enrst bursten Address: 0x0002 selrst Type: rstosc_ valrst1 valrst0
nintrl: non-interlaced mode select interlaced mode (625/50 525/60 system) non-interlaced mode(2x312/50 2x262/60 system) enrst: cyclic update DDFS phase cyclic subcarrier phase reset cyclic subcarrier phase reset depending valrst1 valrst0 (see below) bursten: chrominance burst control burst turned CVBS, chrominance output affected burst enabled selrst: selects reset values Direct Digital Frequency Synthesizer accumulator hardware reset values phase subcarrier oscillator (see description registers and14 values) loaded reset values selected (see contents registers rstosc_buf: software phase reset DDFS (Direct Digital Frequency Synthesizer) buffer when 0-to-1 transition occurs either hard-wired default phase value value loaded Reg. 13-14 (according `selrst') phase buffer. This value then loaded into accumulator (phase sub-carrier) when bits `ph_rst_mode' from register programmed when standard changes when soft reset occur.
Note:
`rstosc_buf' automatically back after buffer loaded.
valrst [1:0]
Note: valrst[1:0] taken into account only `enrst' set.
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Control registers Table valrst1 valrst0 selection
valrst0 selection Automatic reset oscillator every line Automatic reset oscillator every field Automatic reset oscillator every field Automatic reset oscillator every field
STw8009/STw8019
valrst1
Resetting oscillator means forcing value phase accumulator nominal value avoid accumulating errors finite number bits used internally. value which accumulator reset either hard-wired default phase value value loaded Reg. 13-14 (according `selrst') which 900, 1800, 2700 correction applied according field line which reset performed.
REGISTER content default main_ entrap configuration3 trap_4.43 Address: 0x0003 Type:
main_del_ val_422_
main_entrap: enable trap filter trap filter disabled trap filter enabled trap_4.43: trap filter centered frequency value selection trap filter centered around 3.58 trap filter centered around 4.43
Note:
`trap_4.43' taken into account only `main_entrap' set.
main_del_en: Enable chroma luma delay programming cvbs output: disabled (DENC automatically this delay) enabled (chroma luma delay programmed del(3:0) bits from register
Note:
This delay affects only cvbs output. component outputs remain unaffected. Refer register program chroma luma delay output.
val_422_ck_mux: should programmed only.
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Control registers
REGISTER content default
configuration4 syncin_ syncin_
Address: 0x0004 aline
Type: hue_en
syncout_ syncout_
syncin_ad[1:0]: Adjustment incoming sync signals. Used insure correct interpretation incoming video samples when encoder slaved incoming sync signals (inc. `F/H' flags stripped ITU-R656/D1 data). Table syncin_ad[1:0]
syncin_ad0 Internal delay undergone incoming sync nominal* pix_clk pix_clk pix_clk
syncin_ad1
syncout_ad[1:0]: Adjustment outgoing sync signals. Used ensure correct interpretation incoming video samples when encoder master supplies sync signals. Table syncout_ad[1:0]
syncout_ad0 Delay added sync signals before they output nominal* pix_clk pix_clk pix_clk
syncout_ad1
aline: video active line duration control Full digital video line encoding (720 pixels 1440 clock cycles) Active line duration follows ITU-R/SMPTE `analog' standard requirements hue_en: Enables variance phase subcarrier, programmed register_105, during active video with respect phase subcarrier during color burst. Once set, this automatically reset `0'.
Disabled Enabled
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Control registers
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REGISTER content default selrst_
configuration5 bkdac2 bkdac1
Address: 0x0005
Type: dacinv
selrst_inc: Choice Digital Frequency Synthesizer increment after soft reset when ph_rst_mode `01' Register
hard wired value (depending standard) soft (value from registers
bkdacN: blanking DACs normal operation input code forced black level output blanking level CVBS output depending dac12_conf configuration13 register. dacinv: `Inverts' codes compensate inverting output stage application inverted inputs (outputs) inverted inputs (outputs)
REGISTER content default configuration6 softreset jump dec_ninc Address: 0x0006 free_ jump cfc1 Type: cfc0 maxdyn
softreset: software reset reset software reset
Note:
`softreset' automatically reset after internal reset generation. Software reset active during PIX_CLK periods. When softreset activated, device reset with hardware reset except first nine user registers (registers configurations).Registers (increment phase oscillator), 25-30, 31-33 39-42 never reset (hard/soft).
Table
jump
jump, dec_ninc, free_jump
dec_ ninc free_ jump update mode Normal mode line skip/insert capability) ITU-R (CCIR): 313/312 263/262 non-interlaced: 312/312 262/262 Manual mode line insert ("dec_ninc"=0) skip ("dec_ninc"=1) capability. Both fields frames following writing this value modified according "lref" "ltar" bits registers 2122-23 default, "lref"=0 "ltar"=1 which leads normal mode above).
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STw8009/STw8019 Table
jump
Control registers jump, dec_ninc, free_jump
dec_ ninc free_ jump update mode Automatic line insert mode. field frame following writing this value increased. Line insertion done after line 525/60 after line 625/50. "lref" "ltar" ignored.(1) Automatic line skip mode. field frame following writing this value decreased. Line suppression done after line 525/60 after line 625/50. "lref" "ltar" ignored.(1) used.
lines skipped (inserted) 525/60 four lines 625/50 standards
Note:
"jump" automatically reset after use.
Table
cfc1
cfc[1:0]: color frequency control line
cfc0 update mode disabled (update done loading registers 10,11 and12) update increment DDFS just after serial loading update increment DDFS next active edge HSYNC update increment DDFS just before next color burst
maxdyn: dynamic magnitude allowed YCrCb inputs encoding. 10hex EBhex 10hex F0hex chrominance (Cr,Cb) 01hex FEhex
Note:
case, words replaced blanking values before being luminance Chrominance processing.
REGISTER content default configuration7 Address: 0x0007 Type: bypass_ sync_ corr
bypass_sync_corr: tst_dac bypass mode with sync correction. This test mode which data coming from port tst_dac output with without sync correction given dacs.
There sync correction applicable data coming from tst_dac. Sync correction takes place before setting dacs provided tst_ana(0) `1'. Please note that this case only MSBs used generate 10-bit sync corrected output from filter.
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Control registers
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REGISTER content default ph_rst_ mode1
configuration8 ph_rst_ mode0
Address: 0x0008 val_422_ blk_all
Type:
Table
ph_rst_mode[1:0]:sub-carrier phase reset
update mode disabled enabled phase updated with value from phase buffer register (see Reg2 rstosc_buf) beginning next video line. mean time, increment updated with hard soft values depending selreg_inc value (see Register enabled phase updated with values from Registers based next increment update from (depending loading moment Register6 cfc(1:0) bits. enabled phase reset following detection line, pix_clk after loading cfc's LSB.
ph_rst_mode ph_rst_mode
Note:
Bits `ph_rst_mode(1:0)' automatically back `00' following oscillator reset modes `01' `10'.
val_422_mux: should programmed only after each reset. blk_all: blanking video lines disabled enabled (all inputs ignored 80hex instead 10hex instead
REGISTER content atfr Address: 0x0009 fieldct2 Type: Read only fieldct1 fieldct0 jump
DEFAULT mode when not_reset active (LOW level)
hok: Hamming decoding frame sync flag embedded within ITU-R656 compliant YCrCb streams Consecutive errors single error
Note:
Signal quality detector issued from Hamming decoding EAV, from YcrCb
atfr Frame synchronization flag encoder synchronized slave mode: encoder synchronized
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Control registers
fieldct[2:0]: Digital field identification number indicates field indicates field fieldct[0] also represents odd/even information (odd='0', even='1') jump: indicates whether frame length modification been programmed from programming bit' jump' frame(s) concerned.
(*)default Refer register registers 21-22-23
Address: 0x000A 0x000C
REGISTERS Increment_dfs register_10 register_11 register_12
Type:
These registers contain 24-bit increment used DDFS `selrst_inc' equals generate subcarrier phase i.e. address that supplied sine ROM. therefore allows customize subcarrier synthesized frequency. 1.609325 procedure validate usage these registers rather than hard-wired values following: Load registers with required value `selrst_inc' (Reg Perform software reset (Reg
Note:
values loaded Reg10-12 taken into account after software reset, ONLY `selrst_inc'='1' (Reg. These registers never reset must explicitly written into contain sensible information. hardware software reset with selrst_inc='0', DDFS initialized with hardwired increment, independent Registers 10-12. These hardwired values being user register cannot read. These values are:
Value d(23:0): 21F07C hexa NTSC d(23:0): 2A098B hexa B,G,H,I,N d(23:0): 21F694 hexa d(23:0): 21E6F0 hexa Frequency synthesized f=3.5795452 f=4.43361875MHz f=3.5820558
f=3.57561149
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Control registers
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REGISTERS register_13 register_14
Phase_dfs
Address: 0x000D 0x000E
Type:
Static phase offset digital frequency synthesizer bits only)
Under certain circumstances (detailed below), these registers contain MSBs value with which phase accumulator DDFS initialized after 0-to-1 transition `rstosc_buf' after standard change, when cyclic phase readjustment been programmed (see bits valrst[1:0] remaining LSBs loaded into accumulator these cases `0's (this allows define phase reset value with 0.35o accuracy). procedure validate usage these registers rather than hard-wired values following: Load registers with required value `selrst' (Reg Perform software reset `rstosc_buf' (Reg soft phase value into tampon register) ph_rst_mode[1:0]
Note:
Registers 13-14 never reset must explicitly written into contain sensible information. `selrst'=0 (e.g. after hardware reset) phase offset used every time DDFS initialized hard-wired value. hard-wired values being register, they cannot read out. Reset values: D9C000hex BDGHI, 1FC000hex NTSC-M, 000000hex (blue lines)
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Control registers
REGISTER content default dac2_ mult5
dac2 multiplying factors dac2_ mult4 dac2_ mult3
Address: 0x0011 dac2_ mult2 dac2_ mult1
Type: dac2_ mult0
dac2_mult[5:0]: multiplying factor dac2_c digital signal before converters with 0.78% step. Table dac2_mult[5:0]: multiplying factor dac2_c digital signal
dac2_mult[5:0] Address: 75.00% 75.78% 76.56% 77.34% 100% 124.22%
REGISTERS
clig_i_reg ltarg[8:0] lref[8:0]
register register register ltarg8 ltarg0 lref1 ltarg7 lref8 lref0 ltarg6 lref7
0x0015 0x0017
ltarg5 lref6 ltarg4 lref5
Type: ltarg3 lref4 ltarg2 lref3 ltarg1 lref2
These registers used jump from reference line (end that line) target line SAME FIELD. However, lines skipped repeated with problems and, needed, this functionality should USED WITH CAUTION. lref[8:0] contains, binary format, reference line from which jump required. ltarg[8:0] contains target line binary number. Default values: lref[8:0]:= 000000000 ltarg[8:0]:= 000000001.
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Control registers
STw8009/STw8019
REGISTER content default c_mult3
C_mult&ttxs
c_mult2 c_mult1
Address: 0x0041 c_mult0
Type: bcs_en_ main
c_mult[3:0]: multiplying factor digital output (before convertors) color part CVBS signal. Table c_mult[3:0]: multiplying factor digital output
c_mult2 c_mult1 c_mult0 factor value (c_mult) 1.000000 (1.000000 Dec.) 1.000001 (1.015625 Dec.) 1.000010 (1.031250 Dec.) 1.000011 (1.046875 Dec.) 1.001111 (1.234375 Dec.)
c_mult3
bcs_en_main: Brightness, Contrast Saturation control Registers 4:4:4 video input disable enable
REGISTER content default
Brightness
Address: 0x0045
Type:
adjust luminance intensity display video image, following formula used: Yout -128 8-bit input luminance Yout result `Brightness' operation (still bits) This value saturated (16) according register6 `maxdyn', brightness (unsigned value with center 128, default 128)
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Control registers
REGISTER content default
Contrast
Address: 0x0046
Type:
Adjustment relative difference between high intensity luminance values displayed image made according following formula:
-128
8-bit input luminance, Yout result `Contrast' operation (still bits) This value saturated (16) according register6 `maxdyn', contrast (2's complement value from -128 127, default
REGISTER content default
Saturation
Address: 0x0047
Type:
adjust color intensity displayed video image, following formula used:
Cbin Cbout Crin
Crin, Cbin 8-bit input chroma, Crout, Cbout result `Saturation' operation (still bits) This value saturated (16) according `maxdyn' (Reg saturation value (unsigned value with centre 128, default 128)
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Control registers
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REGISTERS
Address:
Chroma filter coefficients Table Chroma main_coef_[8:0]
reg_ main_plg main_flt_s _div1 reg_ reg_ reg_ reg_ coef4(7) reg_ coef5(7) reg_ coef6(7) reg_ coef7(7) reg_ coef8(7) coef8(8) coef2(6) coef3(6) coef4(6) coef5(6) coef6(6) coef7(6) coef8(6) main_plg _div0 coef1(5) coef2(5) coef3(5) coef4(5) coef5(5) coef6(5) coef7(5) coef8(5)
0x0048 0x0050
Type:
chroma_main_coef_0 chroma_main_coef_1 chroma_main_coef_2 chroma_main_coef_3 chroma_main_coef_4 chroma_main_coef_5 chroma_main_coef_6 chroma_main_coef_7 chroma_main_coef_8
coef0(4) coef0(3) coef0(2) coef0(1) coef0(0) coef1(4) coef1(3) coef1(2) coef1(1) coef1(0) coef2(4) coef2(3) coef2(2) coef2(1) coef2(0) coef3(4) coef3(3) coef3(2) coef3(1) coef3(0) coef4(4) coef4(3) coef4(2) coef4(1) coef4(0) coef5(4) coef5(3) coef5(2) coef5(1) coef5(0) coef6(4) coef6(3) coef6(2) coef6(1) coef6(0) coef7(4) coef7(3) coef7(2) coef7(1) coef7(0) coef8(4) coef8(3) coef8(2) coef8(1) coef8(0)
Values from these registers used only when main_flt_s (Reg main_flt_s highest priority over rest. With main_flt_s bits from main_plg_div[1:0] need programmed chroma coefficients. Alternatively, coefficients default values loaded depending selected mode selected filter type particular mode with flt(1:0) bits from register values soft loaded when main_flt_s value loaded register should actual coefficient value offset. hardware will internally subtract this offset actual coefficient value.
main_flt-s default value:
main_plg_div value chosen according coefficients.
main_plg_div when coeffs 4096 main_plg_div when coeffs 2048 main_plg_div when coeffs 1024, (default) main_plg_div when coeffs
Offset change before loading user register:
chroma_main_coef0 Actual value chroma_main_coef1 Actual value chroma_main_coef2 Actual value chroma_main_coef3 Actual value
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Control registers
chroma_main_coef4 Actual value chroma_main_coef5 Actual value chroma_main_coef6 Actual value chroma_main_coef7 Actual value chroma_main_coef8 Actual value
Default values:
chroma_main_coef0[4:0] 10001 chroma_main_coef1[5:0] 100111 chroma_main_coef2[6:0] 1010100 chroma_main_coef3[6:0] 1000111 chroma_main_coef4[7:0] 01011111 chroma_main_coef5[7:0] 01110111 chroma_main_coef6[7:0] 01101100 chroma_main_coef7[7:0] 01111011 chroma_main_coef8[8:0] 010000000
means means means means means means means 108; means 123; means 128.
symmetrical filter following response:
filter working frequency comprised range [pix_clk, MHz] filtering done upsampled signal (half pix_clk pix_clk frequency padding zeros).
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Control registers
STw8009/STw8019
REGISTER content default
Configuration
Address: 0x0051
Type: plg_div_ plg_div_ flt_ys
main_de main_de main_de main_de
main_del[3:0]: delay chroma path with reference luma path, encoded signal coming from main outputs. delay value varies with modes, delays hardwired have different delays different modes. delays made programmable, main_del_en (Reg enable soft delay from main_del[3:0]. Table
main_ del3
main_del[3:0]
main_ del2 Others Others main_ del1 main_ del0 Delay chroma path with reference luma path encoding [One pixel corresponds 2/fpix_clk] pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma (reference delay) pixel delay chroma
main_del_en then delays used are:
main_del[3:0] 0010 when mode PAL/NTSC 4:2:2 format CVBS main_del[3:0] 0001 when mode PAL/NTSC 4:4:4. plg_div_y when coefficients plg_div_y when coefficients (default) plg_div_y when coefficients 1024 plg_div_y when coefficients 2048
flt_ys enables software loading capability luma coefficients. Values from registers used only when "flt_ys" this register "flt_ys" highest priority. With this bits from plg_div_y[1:0] must programmed luma coefficients. Alternatively, default values coefficients loaded. luma coefficients mode standard independent.
flt_ys default value "0".
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Control registers
REGISTERS
luma filter coefficients
Address:
0x0052 0x005B
Type:
Table
Luma_coef_[0:9]
reg_82 reg_83 l9(9) reg_84 l6(8) reg_85 l7(8) reg_86 l4(7) reg_87 l5(7) reg_88 l6(7) reg_89 l7(7) reg_90 l8(7) reg_91 l9(7) l9(8) l2(6) l3(6) l4(6) l5(6) l6(6) l7(6) l8(6) l9(6) l8(8) l1(5) l2(5) l3(5) l4(5) l5(5) l6(5) l7(5) l8(5) l9(5) l0(4) l1(4) l2(4) l3(4) l4(4) l5(4) l6(4) l7(4) l8(4) l9(4) l0(3) l1(3) l2(3) l3(3) l4(3) l5(3) l6(3) l7(3) l8(3) l9(3) l0(2) l1(2) l2(2) l3(2) l4(2) l5(2) l6(2) l7(2) l8(2) l9(2) l0(1) l1(1) l2(1) l3(1) l4(1) l5(1) l6(1) l7(1) l8(1) l9(1) l0(0) l1(0) l2(0) l3(0) l4(0) l5(0) l6(0) l7(0) l8(0) l9(0)
luma_coef_0 luma_coef_1 luma_coef_2 luma_coef_3 luma_coef_4 luma_coef_5 luma_coef_6 luma_coef_7 luma_coef_8 luma_coef_9
Values from these registers used only when flt_ys register coefficient values luma_coef_0 luma_coef_7 should entered complement, rest normal positive values. hardware will internally generate normal positive values. Default values:
luma_coef_0[4:0] 00001 luma_coef_1[5:0] 111111 luma_coef_2[6:0] 1110111 luma_coef_3[6:0] 0000011 luma_coef_4[7:0] 00011111 luma_coef_5[7:0] 11111011 luma_coef_6[8:0] 110101100 luma_coef_7[8:0] 000000111 luma_coef_8[8:0] 100111101 luma_coef_9[9:0] 0111111000
means means means means means +31; means means -84; means means +317; means +504;
filter symmetrical with following response:
Working frequency this filter pix_clk (27, 24.545454 29.5 MHz), filtering done upsampled signal (half pix_clk pix_clk frequency padding zeros).
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Control registers
STw8009/STw8019
REGISTER content default
Configuration
Address: 0x005D
Type: main_if_
main_if_del: delay luma comparing chroma CVBS S-VHS outputs. This delay clock cycles clock). enabled disabled
REGISTER content default
Configuration
Address: 0x005E
Type: ennotch
ennotch: Notch filtering cvbs output disabled enabled
REGISTER content default
Configuration
dac12_ conf
Address: 0x005F
Type:
dac12_conf: Please refer table below combinations observed DACs. Table dac12_conf
dac12_conf (*)0 REGISTER content default control hue_ cont hue_ cont hue_con Address: 0x0069 hue_ cont hue_ cont dac1 dac2 CVBS Type: hue_ cont hue_ cont hue_ cont
Defines phase shift subcarrier during active video with respect subcarrier phase during color burst. Once enabled Register_4(2) "hue_en", phase variation would range 22.324 degrees with increments 0.17578127.
Note:
Pulse Register_4(2) "hue_en" make sure that value programmed this register effective immediately after programming Hue_control. Once enabled, disable phase shift active subcarrier burst, write default value into Hue_control register followed pulse Register_4(2) "hue_en".
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STw8009/STw8019 hue_control [6:0]: absolute value phase adjustment, range 127. (0x01) implies 0.17578127 degrees, 0x7F imply 22.324 degrees hue_control [7]: Sign phase +ve;
"00000000" "10000000" "11111111" "01111111"
REGISTER content default
Control registers
phase shift phase shift +22.324 degrees phase -22.324 degrees phase
dac1 multiplying factor Address: 0x006A dac1_ mult5 dac1_ mult4 dac1_ mult3 Type: dac1_ mult2 dac1_ mult1 dac1_ mult0
dac1_mult(5:0): multiplying factor dac1_y digital signal before converters with 0.78% step. Table dac1_multi[5:0]
dac1_mult[5:0] REGISTER content default Chroma Delay 75.00% 75.78% 76.56% 77.34% 100% 124.22% Type: main_chr_ del1 main_chr_ del0
Address: 0x006C main_chr_ del3 main_chr_ del2
main_chr_del[3:0]: delay chroma path with reference luma path encoded component outputs. delay value varies with modes delays hardwired have different delays different modes. delays made programmable make bitmain_chr_del_en (Reg 109). That way, soft delay from main_chr_del[3:0] enabled.
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Control registers Table main_chr_del[3:0]
STw8009/STw8019
main_ main_ main_ main_ chr_ del3 chr_ del2 chr_ del1 chr_ del0 Others Others
Delay chroma path with reference luma path encoding [One pixel corresponds /fpix_clk] pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma pixel delay chroma (reference delay) pixel delay chroma
main_chr_del_en then delays used are:
main_chr_del[3:0] 0010 when mode PAL/NTSC 4:2:2 format CVBS. main_chr_del[3:0] 0001 when mode PAL/NTSC 4:4:4
REGISTER content default Chroma Delay Enable Address: 0x006D Type: main_chr _del_en
main_chr_del_en: Enable luma chroma delay 4:4:4 component outputs. disabled (DENC automatically sets this delay) enabled (chroma luma delay programmed main_chr_del[3:0] bits (Reg 108).
Note:
This delay affects only component Y/C. cvbs output remains unaffected. Refer register program chroma luma delay cvbs output signal.
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Control registers
5.2.2
Control power management unit registers
Control power management unit
REGISTER content default
Configuration0
Address: 0x0080
Type: standby
standby: this mode analog subsystem supplied 1.2V/1.4V 2.8V/3.3V, DACs power down mode, poff[1:2] bits (Reg 131). Digital analog data conversion disabled. disabled (active mode) standby Control power management unit reset
REGISTER content default
Configuration
Address: 0x0081
Type: cpmuswrst
cpmuswrst: Control power management unit reset disabled control power management unit software reset
Note:
cpmuswrst automatically reset default value after internal reset generation data transfer stopped. This reset kept available cycle.
REGISTER content default
DAC1 control
Address: 0x0082 poff1
Type: notzerod1 pedestal Ond1
poff1: DAC2 power off, then turn DAC2 power consumption mode disabled (DAC2 active) turned
Note:
Default value "1", Digital processor must write when going from sleep standby active mode.
notzerod1 null digital data inputed DAC2 independently what coming from digital part, "0000000000" forced DAC2 input. disabled, values issued from DENC transmitted DAC2. pedestalOnd1 Black level video pedestal active DAC2 disabled video pedestal active
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Control registers
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REGISTER content default
DAC2 control
Address: 0x0083 poff2
Type: notzerod2 pedestal Ond2
poff2: DAC1 power off, then turn DAC1 power consumption mode. disabled (DAC1 active) (*)1 turned
Note:
Default value "1", Digital processor must write when going from sleep standby active mode.
notzerod2 null digital data input DAC1 independently that coming from digital part, "0000000000" forced DAC1 input. (*)1 disabled, values issued from DENC transmitted DAC1. pedestalOnd2: Black level video pedestal active DAC1 disabled video pedestal active
REGISTER content default
Plugdet
Address: 0x0084
Type: LoadD
LoadD: Reports Plugdet Ball status. Unless otherwise specified voltages referenced GND.
Plugdet ball voltage less than Plugdet ball voltage higher than
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STw8009/STw8019
interface
interface
wire serial control interface (I2C compatible)
STw80x9 serial control interface compliant with standard acts only slave device. supports speeds. addition basic definition standard (SDA signals), STw80x9 serial interface additional "Add" input used select slave addresses. device supports 7-bit 10-bit addresses.
Table
STw80x9 addresses
7-bit addresses Read Write 01000000 01000010 10-bit addresses Read 00001000001 00001000011 Write 00001000000 00001000010
01000001 01000011
7-bit address mode
Write mode, several data sent without re-initializing transfer data written successive registers. (Figure 2-wire serial control interface format (I2C compatible) 7-bit addresses). Read mode: (Figure 18).
Double transaction read: operation split into transactions: first write that transmits desired address. interface memorizes address register. second transfer read that repeated read successive registers. After each read byte except last one, master issues "acknowledge". master indicates that reading last byte issuing acknowledge" instead "acknowledge". Single transaction read: opposed double transaction, instead stopping first transaction starting second one, transactions combined with repeated start condition.
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interface
STw8009/STw8019
Figure 2-wire serial control interface format (I2C compatible) 7-bit addresses
Write operation bits addresses) STw8009 slave address STw8009 register address STw8009 register data
Write
repeated times write successive registers
Double transaction read STw8009 slave address STw8009 register address
Write
STw8009 slave address
STw8009 register data
A/NA
Read Single transaction read
repeated times read successive registers
STw8009 slave address
STw8009 register address
STw8009 slave address
STw8009 register data
A/NA
Write
Read
repeated times read successive registers
Start condition
Repeated start condition
Stop condition A/NA Acknowledge Acknoledge
From master slave
From slave master
bits address mode
Write mode, several data sent without re-initializing transfer, this case, data written successive registers. (Figure 2-wire serial control interface format (I2C compatible) 10-bit addresses) Read mode: (Figure
Double transaction read: operation split into transactions: first write that transmits desired address. interface memorizes address register. second transfer read that repeated read successive registers. After each read byte except last one, master issues "acknowledge". master indicates that reading last byte issuing acknowledge" instead "acknowledge".
Note:
Only higher part address sent again before sending read indication. Single transaction read: opposed double transaction, instead stopping first transaction starting second one, transactions combined with repeated start condition.
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STw8009/STw8019
interface
Figure 2-wire serial control interface format (I2C compatible) 10-bit addresses
Write operation bits addresses) 11110 2MSBs LSBs STw8009 register address STw8009 register data
Write repeated times write successive registers STw8009 slave address Double transaction read 11110 2MSBs LSBs STw8009 register address
Write STw8009 slave address 11110 2MSBs LSBs 11110 2MSBs STw8009 register data A/NA
Write STw8009 slave address Single transaction read 11110 2MSBs LSBs Read repeated times read successive registers
STw8009 register address
11110
2MSBs
STw8009 register data
A/NA
Write STw8009 slave address Read repeated times read successive registers
Start condition
Repeated start condition
Stop condition A/NA Acknowledge Acknoledge
From master slave
From slave master
Figure 2-wire serial control interface timing
tHD_DAT tSU_DAT
tBUF tSU_STA tHD_STA tSU_STO
tHD_STA
tLOW
tHIGH
P=Stop
S=Start
Sr=Start repeated
Stop
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interface
STw8009/STw8019
YcbCr
Figure YcbCr format
YCbCr[7:0]
Table
Symbol CLK27M CLKdc
YcBCr data timing (Figure
Parameter Clock frequency Clock duty cycle Data input hold time Data input setup time Test conditions Min. Typ. Max. Unit
Figure Data timing
CCIR data CLK27M
CCIR data CLK27M setup time CCIR data CLK27M hold time
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STw8009/STw8019
Electrical characteristics
Electrical characteristics
Absolute maximum rating
Unless otherwise specified: TA=+25°C, voltages referenced GND.
Table
Symbol VddIO VccA VDCdig VDCana Pmax Tstg Vesd
Absolute maximum ratings
Parameter Digital core supply voltage digital supply voltage Analog supply voltage input voltage digital input voltage analog Maximum power dissipation Storage temperature range Human body Electrostatic discharge voltage model(1) Value -0.3 +1.65 -0.3 +3.6 -0.3 +3.8 -0.3 +2.0 -0.3 +3.8 -500 +500 Unit
Charge device model(2)
tests have been performed compliance with JESD22-A114-B S5.1-2001.HBM tests have been performed compliance with ANSI-ESDSTM5.3.1-1999
Operating conditions
Unless otherwise specified: TA=+25°C, voltages referenced GND.
Table
Symbol VddIO VccA
Operating conditions
Parameter Digital core supply voltage digital supply voltage Analog supply voltage Operating temperature Min. 1.08 1.65 Typ. Max. 1.47 Unit
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Electrical characteristics
STw8009/STw8019
Table
Symbol fSCL tBUF tHD_STA tLOW tHIGH tHD_DAT tSU_DAT tSU_STA tSU_STO
Electrical timing characteristics
Unless otherwise specified: TA=+25°C, voltages referenced GND.
wire serial control interface timing (Figure
Parameter Clock Frequency free time Start condition hold time SCLK fall time SCLK pulse width SCLK rise time SCLK pulse width high Data input hold time Data input time Start condition time Stop condition time 1300 1300 Test conditions Min. Typ. Max. Unit
Table
Symbol
Digital interface
Parameter Input voltage Input High voltage Output level Output High level Input current Input High current Test conditions digital inputs digital inputs digital outputs digital outputs digital inputs digital inputs VCCIO 0.8*VddIO 0.7*VddIO 0.1*VddIO Min. Typ. Max. 0.2*VddIO Unit
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STw8009/STw8019 Table
Symbol PSLVdd PSTVdd PSTVcca PACVdd PACVddIO PAC0Vcca PAC1Vcca PAC2Vcca
Electrical characteristics
Power consumption/R load 37.5
Parameter Sleep mode Stand mode Stand mode Vcca Active mode Active mode VddIO Active mode Vcca Active mode Vcca Active mode Vcca Test conditions 1.2V clock 1.2V Vcca 2.8V enabled VddIO 1.8V Vcca 2.8V enabled Vcca 2.8V enabled Vcca 2.8V enabled Min. Typ. Max. Unit
Table
Symbol RDAC INLDAC DNLDAC VFR1 VFR2 SFDR PSRR
Video output characteristics Rload 37.5 Rext kohm
Parameter Resolution Integral linearity Differential linearity Full range output voltage Pedestal Full range output voltage Pedestal high Spurious free dynamic range Signal noise ratio Power supply rejection ratio With white level supply Average measurements NTC7comp CCIR17 line test patterns Average measurements NTC7comp CCIR17 line test patterns -1.5 -0.8 1.14 1.24 1.21 1.31 Test conditions Min. Typ. +1.5 +0.8 1.27 1.38 Max. Unit Bits
DiffG
Differential gain
DiffPh
Differential phase
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Application information
STw8009/STw8019
Application information
Figure Typical application schematic
Video Interface
YCbCr[0:7]
C/CVBS Optional L.P. filter wire
PORn
STw8009
Protection Optional L.P. filter
Digital Processor
Suspend Rext VccA
Only S-VHS
VccA
capacitor connected each ball supply
Supply
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STw8009/STw8019
Color test pattern waveforms
Color test pattern waveforms
Figure NTSC composite
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Color test pattern waveforms Figure NTSC S-video
STw8009/STw8019
56/65
STw8009/STw8019 Figure composite
Color test pattern waveforms
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Color test pattern waveforms Figure S-video
STw8009/STw8019
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STw8009/STw8019
Package mechanical data
10.1
Package mechanical data
TFBGA balls
Table TFBGA 4x4x1.2
Dimensions (mm) Reference 3.85 0.25 3.85 4.00 3.00 4.00 3.00 0.50 0.08 0.15 0.05 4.15 0.15 0.35 4.15
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Package mechanical data Figure TFBGA balls body size
STw8009/STw8019
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STw8009/STw8019
Package mechanical data
10.2
VFBGA balls
Table VFBGA 3x3x1.0 balls Pitch ball 0.25
Dimensions (mm) Reference A(1) b(2) eee(3) fff(4)
VFBGA stands Very thin profile Fine pitch Ball Grid Array. Very thin profile: 0.80mm<A<=1.00mm/Fine pitch: e<1.00mm maximum total package height calculated following methodology
A2Typ A1Typ tolerancevalues
1.00
0.125 0.615 0.18 0.45 0.22 2.95 0.26 3.00 2.40 2.95 3.00 2.40 0.40 0.30 0.08 0.13 0.04 3.05 0.30 3.05
typical ball diameter before mounting 0.25mm VFBGA with 0.40mm ball pitch registered JEDEC publications. tolerance position that controls location balls with respect datum each ball there cylindrical tolerance zone perpendicular datum located true position with respect datum defined axis perpendicular datum each ball must within this tolerance zone. tolerance position that controls location balls within matrix with respect each other. each ball there cylindrical tolerance zone perpendicular datum located true position defined axis perpendicular datum each ball must within this tolerance zone. Each tolerance zone array contained entirely respective zone above. axis each ball must simultaneously both tolerance zones.
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Package mechanical data Figure VFBGA balls body size
STw8009/STw8019
Note Note:
Note:
terminal corner must identified surface using corner chamfer, metallized markings, other feature package body integral heatslug. distinguishing feature allowable bottom surface package identify terminal corner. Exact shape each corner optional.
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STw8009/STw8019
Ordering information
Ordering information
Table Order codes
Package TFBGA49 TFBGA49 TFBGA49 TFBGA49 VFBGA49 VFBGA49 VFBGA49 VFBGA49 Tray Tray Tape reel Tape reel Tray Tray Tape reel Tape reel Packing
Part number STW8009B27R/LF STW8019B27R/LF STW8009B27T/LF STW8019B27T/LF STW8009BS3R/LF STW8019BS3R/LF STW8009BS3T/LF STW8019BS3T/LF
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Revision history
STw8009/STw8019
Revision history
Table
Date 02-Feb-2006 08-Mar-2006
Document revision history
Revision Initial release. Correction Table dac12_conf page Added Section 4.5: Video timing. Corrected list supported formats (NTSC-J, Updated Section 7.3: Electrical timing characteristics. Added Chapter Color test pattern waveforms. Reverted into into Moved ordering information from cover page Chapter Ordering information. Document status updated final datasheet. Updated Vesd values Table Absolute maximum ratings added table footnotes about test conditions. Added DiffG DiffPh Table Video output characteristics Rload 37.5 Rext kohm. Updated definition (charge device model) Table Absolute maximum ratings. Removed reference TQFP64 cover page. Updated Figure Mode transition diagram. Reviewed text paragraph" transition from mode sleep mode" Section 4.13.2: Mode transition diagram. Updated "sleep mode" paragraph Section 4.13.1: Operating modes. Added Table Figure Section 6.2: YcbCr bus. Updated Section 4.10: Macrovisioncopy protection. Changes
9-Jun-2006
08-Mar-2007
21-Mar-2007
15-Jun-2007
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STw8009/STw8019
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Mobile video DENC analog outputs bits DAC) with: CVBS (Composite)

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