Analog Multichannel, 12-bit, MSPS analog-to-digital converter (ADC) ch

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Analog Multichannel, 12-bit, MSPS analog-to-digital converter (ADC) ch

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Precision Analog Microcontroller ARM7TDMI with 12-Bit ADuC7128/ADuC7129
Analog Multichannel, 12-bit, MSPS analog-to-digital converter (ADC) channels Fully differential single-ended modes VREF analog input range 10-bit digital-to-analog converter (DAC) 32-bit direct digital synthesis (DDS) Current-to-voltage (I/V) conversion Integrated second-order low-pass filter (LPF) input line driver On-chip voltage reference On-chip temperature sensor (±3°C) Voltage comparator Microcontroller ARM7TDMI core, 16-/32-bit RISC architecture JTAG port supports code download debug External watch crystal/clock source 41.78 with 8-way programmable divider Optional trimmed on-chip oscillator Memory Flash/EE memory, SRAM In-circuit download, JTAG-based debug Software triggered in-circuit reprogrammability On-chip peripherals UART, serial 40-pin GPIO port general-purpose timers Wake-up watchdog timers (WDT) Power supply monitor 16-bit generator Quadrature encoder Programmable logic array (PLA) Power Specified operation Active mode 5.22 MHz) 41.78 MHz) Packages temperature range 64-lead LFCSP package, -40°C 125°C 64-lead LQFP, -40°C +125°C 80-lead LQFP, -40°C +125°C Tools cost QuickStart development system Full third-party support
DACGND DACV GNDREF IOGND IOGND AGND DGND IOVDD IOVDD AVDD LVDD
ADC0
TEMP SENSOR
12-BIT 1MSPS 10-BIT IOUT
VDACOUT LD1TX LD2TX
CMP0 CMP1 CMPOUT VREF
BAND REFERENCE
ADuC7129
ARM7TDMI-BASED WITH ADDITIONAL PERIPHERALS PURPOSE kBYTES TIMERS kBYTES kBYTES 8192 BYTES WAKE-UP/ FLASH/EE FLASH/EE SRAM TIMER (32k (31k BITS) BITS) BITS) INTERRUPT CONTROLLER GPIO JTAG UART0 UART1 CONTROL JTAG P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.3 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6
06020-001
XCLKI XCLKO XCLK
OSC/PLL
QUAD ENCODER
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. rights reserved.
ADuC7128/ADuC7129 TABLE CONTENTS
Features Functional Block Diagram Revision History General Description Specifications. Timing Specifications Absolute Maximum Ratings. Caution. Configuration Function Descriptions. Typical Performance Characteristics Terminology Specifications Specifications. Overview ARM7TDMI Core. Thumb Mode (T). Long Multiply (M). EmbeddedICE Exceptions Registers Interrupt Latency. Memory Organization Flash/EE Memory. SRAM Memory Mapped Registers Complete Listing. Circuit Overview Transfer Function. Typical Operation. Converter Operation. Driving Analog Inputs Temperature Sensor Band Reference. Nonvolatile Flash/EE Memory Flash/EE Memory Overview. Flash/EE Memory. Flash/EE Memory Security Flash/EE Control Interface. Execution Time from SRAM FLASH/EE. Reset Remap Other Analog Peripherals. DAC. Power Supply Monitor Comparator Oscillator PLL-Power Control. Digital Peripherals. General Overview. Convert Start Control General-Purpose Serial Port Mux. UART Serial Interface. Serial Peripheral Interface. I2C-Compatible Interfaces. Registers Programmable Logic Array (PLA). Processor Reference Peripherals. Interrupt System Timers Timer0-Lifetime Timer. Timer1-General-Purpose Timer Timer2-Wake-Up Timer. Timer3-Watchdog Timer. Timer4-General-Purpose Timer External Memory Interfacing Timing Diagrams Hardware Design Considerations Power Supplies Grounding Board Layout Recommendations. Clock Oscillator. Power-On Reset Operation. Development Tools. In-Circuit Serial Downloader. Outline Dimensions Ordering Guide
REVISION HISTORY
4/07-Revision Initial Version
Rev. Page
ADuC7128/ADuC7129 GENERAL DESCRIPTION
ADuC7128/ADuC7129 fully integrated, MSPS, 12-bit data acquisition systems incorporating high performance, multichannel analog-to-digital converter (ADC), with line driver, 16-/32-bit MCU, Flash/EE memory single chip. consists single-ended inputs. operate single-ended differential input modes. input voltage VREF. drift band reference, temperature sensor, voltage comparator complete peripheral set. ADuC7128/ADuC7129 integrate differential line driver output. This line driver transmits sine wave whose values calculated on-chip voltage output determined DACDAT MMR. devices operate from on-chip oscillator PLL, generating internal high frequency clock 41.78 MHz. This clock routed through programmable clock divider from which core clock operating frequency generated. microcontroller core ARM7TDMI®, 16-/32-bit reduced instruction computer (RISC), offering MIPS peak performance. There nonvolatile Flash/EE provided on-chip, well SRAM. ARM7TDMI core views memory registers single linear array. On-chip factory firmware supports in-circuit serial download UART serial interface port, nonintrusive emulation also supported JTAG interface. These features incorporated into cost QuickStartdevelopment system supporting this MicroConverter® family. parts operate from specified over industrial temperature range -40°C +125°C. When operating 41.78 MHz, power dissipation line driver output, enabled, consumes additional
Rev. Page
ADuC7128/ADuC7129 SPECIFICATIONS
AVDD IOVDD VREF internal reference, fCORE 41.78 MHz. specifications TMAX TMIN, unless otherwise noted. Table
Parameter CHANNEL SPECIFICATIONS Power-Up Time Accuracy Resolution Integral Nonlinearity ±0.7 ±0.7 ±2.0 ±0.5 ±0.6 ±2.0 ±1.5 +1/-0.9 Unit Bits sine wave, fSAMPLE MSPS Test Conditions/Comments Eight acquisition clocks fADC/2
Differential Nonlinearity3 Code Distribution ENDPOINT ERRORS Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Channel-to-Channel Crosstalk Crosstalk Between Channel Channel ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Drop When Enabled Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT Input Voltage Range Input Impedance CHANNEL SPECIFICATIONS VDAC Output Voltage Swing
internal reference 85°C 125°C only internal reference -40°C +85°C external reference internal reference external reference input voltage
VREF/2 VREF
ppm/°C
85°C 125°C only -40°C +85°C During acquisition 0.47 from VREF AGND Measured 25°C Reference drop when enabled
±2.5 0.625 AVDD
(0.33 VREF VREF) 1.33
Rev. Page
VREF internal reference
Output Resistance Low-Pass Filter Point Resolution
Bits
mode selected 2-pole
ADuC7128/ADuC7129
Parameter Relative Accuracy Differential Nonlinearity, Differential Nonlinearity, Offset Error Gain Error Voltage Output Settling Time 0.1% Line Driver Output 0.35 -0.15 Unit Test Conditions/Comments
-190 +150
Total Harmonic Distortion Output Voltage Swing COMMON MODE Mode
±1.768 1.65
measured into range specified loads (see Figure LD1TX LD2TX, unless otherwise noted operating 691.2
Mode
DIFFERENTIAL INPUT IMPEDANCE Leakage Current LD1TX, LD2TX Short-Circuit Current Line Driver Power-Up Time COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis3, Response Time TEMPERATURE SENSOR Voltage Output 25°C Voltage Temperature Coefficient Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy GLITCH IMMUNITY PIN3 WATCHDOG TIMER (WDT) Timeout Period FLASH/EE MEMORY Endurance Data Retention DIGITAL INPUTS Logic Input Current (Leakage Current) Logic Input Current (Leakage Current) Input Capacitance
Each output common mode AVDD swings VREF above below this; VREF internal reference Each output common mode VREF swings VREF above below this; VREF internal reference Line driver buffer disabled Line driver buffer disabled protection diodes, allowable current
AGND
AVDD Hysteresis turned CMPHYST CMPCON register Response time modified CMPRES bits CMPCON register
-1.3 2.79 3.07 ±2.5 10,000 ±0.2 +125
mV/°C Cycles Years selectable trip points selected nominal trip point voltage
85°C digital inputs, including XCLKI XCLKO VINH VINH VINL except VINL Only
Rev. Page
ADuC7128/ADuC7129
Parameter LOGIC INPUTS3 VINL, Input Voltage VINH, Input High Voltage Quadrature Encoder Inputs S1/S2/CLR (Schmitt-Triggered Inputs) LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Voltage CRYSTAL INPUTS XCLKI XCLKO VINL, Input Voltage VINH, Input High Voltage XCLKI, Input Capacitance XCLKO, Output Capacitance CLOCK RATE (PLL) 326.4 41.77920 INTERNAL OSCILLATOR Tolerance STARTUP TIME Power-On From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Propagation Delay Element Propagation Delay POWER REQUIREMENTS Power Supply Voltage Range IOVDD, AVDD, DACVDD (Supply Voltage Chip) LVDD (Regulator Output from Chip) Power Supply Current Normal Mode Additional Line Driver Supply Current Pause Mode Sleep Mode
Unit
Test Conditions/Comments logic inputs, including XCLKI XCLKO
1.65 0.75 IOVDD
ISOURCE ISINK Logic inputs, XCLKI only Logic inputs, XCLKI only
32.768
Eight programmable core clock selections within this range (32.768 1275)/128 (32.768 1275)/1 -40°C 85°C 85°C 125°C only Core clock 41.78
From input output
5.22 clock 41.78 clock kHz, maximum load (see Figure 41.78 clock External crystal internal
channel specifications guaranteed during normal MicroConverter core operation. Apply input channels. production tested; supported design and/or characterization data production release. Measured using external AD845 input buffer stage, shown Figure Based external system components. input signal centered common-mode voltage (VCM), long this value within voltage input range specified. When using external reference input pin, internal reference must disabled setting REFCON memory mapped register Endurance qualified JEDEC Std. Method A117 measured -40°C, +25°C, +85°C. Retention lifetime equivalent junction temperature (TJ) 85°C JEDEC Std. Method A117. Retention lifetime derates with junction temperature. Test carried with maximum eight I/Os output level. Power supply current consumption measured normal, pause, sleep modes under following conditions: normal mode supply, pause mode supply, sleep mode supply. IOVDD power supply current decreases typically during Flash/EE erase cycle.
Rev. Page
ADuC7128/ADuC7129
Line Driver Load
100nF LD1TX
100nF LD2TX
27.5µH
100nF LD1TX
100nF LD2TX
8.9µH
06020-002
Figure Line Driver Load Minimum (Top) Maximum (Bottom)
Rev. Page
ADuC7128/ADuC7129
TIMING SPECIFICATIONS
Table External Memory Write Cycle
Parameter tMS_AFTER_CLKH tADDR_AFTER_CLKH tAE_H_AFTER_MS tHOLD_ADDR_AFTER_AE_L tHOLD_ADDR_BEFORE_WR_L tWR_L_AFTER_AE_L tDATA_AFTER_WR_L tWR_H_AFTER_CLKH tHOLD_DATA_AFTER_WR_H tBEN_AFTER_AE_L tRELEASE_MS_AFTER_WR_H (XMxPAR[14:12] (!XMxPAR[10]) (!XMxPAR[8]) (!XMxPAR[10] !XMxPAR[8]) (XMxPAR[7:4] (!XMxPAR[8]) (!XMxPAR[8] UCLK Unit
tMS_AFTER_CLKH
tAE_H_AFTER_MS
tWR_L_AFTER_AE_L
tRELEASE_MS_AFTER_WR_H tWR_H_AFTER_CLKH
tHOLD_DATA_AFTER_WR_H
tHOLD_ADDR_AFTER_AE_L tHOLD_ADDR_BEFORE_WR_L tADDR_AFTER_CLKH
A/D[15:0] FFFF 9ABC
tDATA_AFTER_WR_L
5678 9ABE 1234
tBEN_AFTER_AE_L
06020-065
Figure External Memory Write Cycle
Rev. Page
ADuC7128/ADuC7129
Table External Memory Read Cycle
Parameter tMS_AFTER_CLKH tADDR_AFTER_CLKH tAE_H_AFTER_MS tHOLD_ADDR_AFTER_AE_L tRD_L_AFTER_AE_L tRD_H_AFTER_CLKH tDATA_BEFORE_RD_H tDATA_AFTER_RD_H tRELEASE_WS_AFTER_RD_H 1/MD Clock (CDPOWCON[2:0] (XMxPAR[14:12] XMxPAR[10] XMxPAR[10]+ XMxPAR[9] (XMxPAR[3:0] XMxPAR[9]) Unit
ECLK
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
tMS_AFTER_CLKH
tAE_H_AFTER_MS
tRD_L_AFTER_AE_L
tRELEASE_WS_AFTER_RD_H
tRD_H_AFTER_CLKH
SAMPLE_ADDR_1
tADDR_AFTER_CLKH
SAMPLE_ADDR_0 A/D[15:0] FFFF 2348 XXXX
tDATA_BEFORE_RD_H tDATA_AFTER_RD_H
CDEF SAMPLE_DATA_L 234A 89AB SAMPLE_DATA_H
tHOLD_ADDR_AFTER_AE_L
06020-067
XA16
Figure External Memory Read Cycle
Rev. Page
ADuC7128/ADuC7129
I2C® Timing Specifications
Table Timing Fast Mode (400 kHz)
Parameter tSHD tDSU tDHD tRSU tPSU tBUF tSUP
Description SCLOCK pulse width1 SCLOCK high pulse width1 Start condition hold time Data setup time Data hold time Setup time repeated start Stop condition setup time Bus-free time between stop condition start condition Rise time both SCLOCK SDATA Fall time both SCLOCK SDATA Pulse width spike suppressed
Slave
Slave
Master 1360 1140 251,350 12.51350
Unit
tHCLK depends clock divider bits PLLCON MMR, tHCLK tUCLK/2CD.
tBUF
SDATA (I/O)
tSUP
tDSU tPSU tSHD
SCLOCK STOP START CONDITION CONDITION
tDHD
tDSU tRSU
tDHD
S(R) REPEATED START
Figure I2C-Compatible Interface Timing
Rev. Page
06020-003
tSUP
ADuC7128/ADuC7129
Timing Specifications
Table Master Mode Timing (PHASE Mode
Parameter tDAV tDSU tDHD
Description SCLOCK pulse width SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
(SPIDIV tHCLK (SPIDIV tHCLK
tHCLK tUCLK tUCLK tUCLK 12.5 12.5 12.5 12.5
Unit
tHCLK depends clock divider bits PLLCON MMR, tHCLK tUCLK/2CD. tUCLK 23.9 corresponds 41.78 internal clock from before clock divider.
SCLOCK (POLARITY SCLOCK (POLARITY
tDAV
MOSI
MISO
06020-004
tDSU tDHD
Figure Master Mode Timing (PHASE Mode
Rev. Page
ADuC7128/ADuC7129
Table Master Mode Timing (PHASE Mode
Parameter tDAV tDOSU tDSU tDHD
Description SCLOCK pulse width SCLOCK high pulse width1 Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
(SPIDIV tHCLK (SPIDIV tHCLK
tHCLK tUCLK tUCLK tUCLK 12.5 12.5 12.5 12.5
Unit
tHCLK depends clock divider bits PLLCON MMR, tHCLK tUCLK/2CD. tUCLK 23.9 corresponds 41.78 internal clock from before clock divider.
SCLOCK (POLARITY
SCLOCK (POLARITY
tDOSU
MOSI
tDAV
MISO
tDHD
Figure Master Mode Timing (PHASE Mode
Rev. Page
06020-005
tDSU
ADuC7128/ADuC7129
Table Slave Mode Timing (PHASE Mode
Parameter tDAV tDSU tDHD tSFS
Description SCLOCK edge SCLOCK pulse width SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time high after SCLOCK edge
tUCLK
(SPIDIV tHCLK (SPIDIV tHCLK
tHCLK tUCLK tUCLK tUCLK 12.5 12.5 12.5 12.5
Unit
tUCLK 23.9 corresponds 41.78 internal clock from before clock divider. tHCLK depends clock divider bits PLLCON MMR, tHCLK tUCLK/2CD.
SCLOCK (POLARITY
tSFS
SCLOCK (POLARITY
tDAV
MISO
MOSI
tDSU tDHD
06020-006
Figure Slave Mode Timing (PHASE Mode
Rev. Page
ADuC7128/ADuC7129
Table Slave Mode Timing (PHASE Mode
Parameter tDAV tDSU tDHD tDOCS tSFS
Description SCLOCK edge SCLOCK pulse width SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after edge high after SCLOCK edge
tUCLK
(SPIDIV tHCLK (SPIDIV tHCLK
tHCLK tUCLK tUCLK tUCLK 12.5 12.5 12.5 12.5
Unit
tUCLK 23.9 corresponds 41.78 internal clock from before clock divider. tHCLK depends clock divider bits PLLCON MMR, tHCLK tUCLK/2CD.
SCLOCK (POLARITY
tSFS
SCLOCK (POLARITY
tDOCS
MISO
tDAV
MOSI
06020-007
tDSU
tDHD
Figure Slave Mode Timing (PHASE Mode
Rev. Page
ADuC7128/ADuC7129 ABSOLUTE MAXIMUM RATINGS
DVDD IOVDD, AGND REFGND DACGND GNDREF. 25°C, unless otherwise noted. Table
Parameter AVDD DVDD AGND DGND IOVDD IOGND, AVDD AGND Digital Input Voltage IOGND Digital Output Voltage IOGND VREF AGND Analog Inputs AGND Analog Output AGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature Thermal Impedance 64-Lead LFCSP 64-Lead LQFP 80-Lead LQFP Peak Solder Reflow Temperature SnPb Assemblies sec) RoHS Compliant Assemblies sec) Rating -0.3 +0.3 -0.3 +0.3 -0.3 -0.3 IOVDD -0.3 IOVDD -0.3 AVDD -0.3 AVDD -0.3 AVDD -40°C +125°C -65°C +150°C 150°C 24°C/W 47°C/W 38°C/W 240°C 260°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Only absolute maximum rating applied time.
CAUTION
Rev. Page
ADuC7128/ADuC7129 CONFIGURATION FUNCTION DESCRIPTIONS
ADC4 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV AVDD AGND DACGND VREF P4.5 P4.4 P4.3/PWMTRIP P4.2 P1.0/SPM0 P1.1/SPM1
ADC5 VDACOUT ADC9 ADC10 GNDREF ADCNEG AVDD ADC12/LD1TX ADC13/LD2TX AGND P4.6/SPM10 P4.7/SPM11 P0.0/BM/CMPOUT P0.6/T1/MRST
INDICATOR
ADuC7128
VIEW (Not Scale)
P1.2/SPM2 P1.3/SPM3 P1.4/SPM4 P1.5/SPM5 P4.1/S2 P4.0/S1 IOVDD IOGND P1.6/SPM6 P1.7/SPM7 DGND PVDD XCLKI XCLKO P0.7/SPM8/ECLK/XCLK P2.0/SPM9
IOGND IOVDD LVDD DGND P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4 P0.3/ADCBUSY /TRST P3.4/PWM5 P3.5/PWM6 P0.4/IRQ0/CONVST P0.5/IRQ1/ADCBUSY
Figure ADuC7128 Configuration
Table ADuC7128 Function Descriptions
Mnemonic ADC5 VDACOUT ADC9 ADC10 GNDREF ADCNEG Type Description Single-Ended Differential Analog Input 5/Line Driver Input. Output from Buffer. Single-Ended Differential Analog Input Single-Ended Differential Analog Input Ground Voltage Reference ADC. optimal performance, analog power supply should separated from IOGND DGND. Bias Point Negative Analog Input Pseudo Differential Mode. Must connected ground signal convert. This bias point must between Analog Power. Single-Ended Differential Analog Input 12/DAC Differential Negative Output. Single-Ended Differential Analog Input 13/DAC Differential Positive Output. Analog Ground. Ground reference point analog circuitry. JTAG Test Port Input, Test Mode Select. Debug download access. JTAG Test Port Input, Test Data Debug download access. General-Purpose Input Output Port 4.6/Serial Port General-Purpose Input Output Port 4.7/Serial Port General-Purpose Input Output Port 0.0/Boot Mode. ADuC7128 enters download mode reset executes code pulled high reset through resistor/voltage comparator output. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output. JTAG Test Port Input, Test Clock. Debug download access. JTAG Test Port Output, Test Data Out. Debug download access. Ground GPIO. Typically connected DGND. Supply GPIO Input On-Chip Voltage Regulator.
AVDD ADC12/LD1TX ADC13/LD2TX AGND P4.6/SPM10 P4.7/SPM11 P0.0/BM/CMPOUT
P0.6/T1/MRST IOGND IOVDD
Rev. Page
06020-063
ADuC7128/ADuC7129
Mnemonic LVDD DGND P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4 P0.3/ADCBUSY/TRST P3.4/PWM5 P3.5/PWM6 P0.4/IRQ0/CONVST P0.5/IRQ1/ADCBUSY P2.0/SPM9 P0.7/SPM8/ECLK/XCLK XCLKO XCLKI PVDD DGND P1.7/SPM7 P1.6/SPM6 P4.0/S1 P4.1/S2 P1.5/SPM5 P1.4/SPM4 P1.3/SPM3 P1.2/SPM2 P1.1/SPM1 P1.0/SPM0 P4.2 P4.3/ PWMTRIP P4.4 P4.5 VREF DACGND DACVDD ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4
Type
Description Output On-Chip Voltage Regulator. Must connected 0.47 capacitor DGND. Ground Core Logic. General-Purpose Input Output Port 3.0/PWM1 Output. General-Purpose Input Output Port 3.1/PWM2 Output. General-Purpose Input Output Port 3.2/PWM3 Output. General-Purpose Input Output Port 3.3/PWM4 Output. General-Purpose Input Output Port 3.3/ADCBUSY Signal/JTAG Test Port Input, Test Reset. Debug download access. Reset Input (Active Low). General-Purpose Input Output Port 3.4/PWM5 Output. General-Purpose Input Output Port 3.5/PWM6 Output. General-Purpose Input Output Port 0.5/External Interrupt Request Active High/Start Conversion Input Signal ADC. General-Purpose Input Output Port 0.6/External Interrupt Request Active High/ADCBUSY Signal. General-Purpose Input Output Port 2.0/Serial Port General-Purpose Input Output Port 0.7/Serial Port 8/Output External Clock Signal/Input Internal Clock Generator Circuits. Output from Crystal Oscillator Inverter. Input Crystal Oscillator Inverter Input Internal Clock Generator Circuits. Supply. Must connected capacitor DGND. Should connected output. Ground PLL. General-Purpose Input Output Port 1.7/Serial Port General-Purpose Input Output Port 1.6/Serial Port General-Purpose Input Output Port 4.0/Quadrature Input General-Purpose Input Output Port 4.1/Quadrature Input General-Purpose Input Output Port 1.5/Serial Port General-Purpose Input Output Port 1.4/Serial Port General-Purpose Input Output Port 1.3/Serial Port General-Purpose Input Output Port 1.2/Serial Port General-Purpose Input Output Port 1.1/Serial Port General-Purpose Input Output Port 1.0/Serial Port General-Purpose Input Output Port 4.2. General-Purpose Input Output Port 4.3/PWM Safety Cutoff. General-Purpose Input Output Port 4.4. General-Purpose Input Output Port 4.5. Internal Voltage Reference. Must connected 0.47 capacitor when using internal reference. Ground DAC. Typically connected AGND. Power Supply DAC. This must supplied with This connected output. Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input 2/Comparator Positive Input. Single-Ended Differential Analog Input 3/Comparator Negative Input. Single-Ended Differential Analog Input
input, output, supply.
Rev. Page
ADuC7128/ADuC7129
P4.3/PWMTRIP/AD11 ADC3/CMP1 ADC2/CMP0
P1.0/SPM0
P1.1/SPM1
P4.5/AD13
P4.4/AD12
P4.2/AD10
DACGND
REFGND
DACV
IOGND
ADC11
AGND
AGND
ADC1
ADC0
AVDD
AVDD
VREF
ADC4 ADC5 ADC6 ADC7 ADC9 ADC10 GNDREF ADCNEG
P1.2/SPM2 P1.3/SPM3 P1.4/SPM4 P1.5/SPM5 P4.1/S2/AD9 P4.0/S1/AD8 IOVDD IOGND P1.6/SPM6 P1.7/SPM7 P2.2/RS P2.1/WS P2.7/MS3 P3.7/AD7 P3.6/AD6 DGND PVDD XCLKI XCLKO P0.7/SPM8/ECLK/XCLK
VDACOUT/ADC8
ADuC7129
VIEW (Not Scale)
AVDD ADC12/LD1TX ADC13/LD2TX AGND TDI/P0.1/BLE P2.3/AE P4.6/SPM10/AD14 P4.7/SPM11/AD15 P0.0/BM/CMPOUT/MS0 P0.6/T1/MRST
IOGND
P0.3/ADC BUSY /TRST/A16
P0.4/IRQ0/CONVST/MS1
TDO/P0.2/BHE
P2.4/MS0
P2.5/MS1
P2.6/MS2
P3.0/PWM1/AD0
P3.1/PWM2/AD1
P3.2/PWM3/AD2
P3.3/PWM4/AD3
P3.4/PWM5/AD4
P3.5/PWM6/AD5
P0.5/IRQ1/ADCBUSY
P2.0/SPM9
IOVDD
LVDD
DGND
Figure ADuC7129 Configuration
Table ADuC7129 Function Descriptions
Mnemonic ADC4 ADC5 ADC6 ADC7 VDACOUT/ADC8 ADC9 ADC10 GNDREF ADCNEG Type1 Description Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Output from Buffer/Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Ground Voltage Reference ADC. optimal performance, analog power supply should separated from IOGND DGND. Bias Point Negative Analog Input Pseudo Differential Mode. Must connected ground signal convert. This bias point must between Analog Supply. Single-Ended Differential Analog Input 12/DAC Differential Negative Output. Single-Ended Differential Analog Input 13/DAC Differential Positive Output. Analog Ground. Ground reference point analog circuitry. JTAG Test Port Input, Test Mode Select. Debug download access. JTAG Test Port Input, Test Data Debug download access/general-purpose input output Port 0.1/External Memory BLE. General-Purpose Input Output Port 2.3/AE Output.
Rev. Page
AVDD ADC12/LD1TX ADC13/LD2TX AGND TDI/P0.1/BLE P2.3/AE
06020-064
ADuC7128/ADuC7129
Mnemonic P4.6/SPM10/AD14 P4.7/SPM11/AD15 P0.0/BM/CMPOUT/MS0 Type1 Description General-Purpose Input Output Port 4.6/Serial Port 10/External Memory AD14. General-Purpose Input Output Port 4.7/Serial Port 11/External Memory AD15. General-Purpose Input Output Port /Boot Mode. ADuC7129 enters download mode reset executes code pulled high reset through resistor/voltage comparator output/external memory MS0. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/External Memory JTAG Test Port Input, Test Clock. Debug download access. JTAG Test Port Output, Test Data Out. Debug download access/general-purpose input output Port 0.2/External Memory BHE. Ground GPIO. Typically connected DGND. Supply GPIO Input On-Chip Voltage Regulator. Output On-Chip Voltage Regulator. Must connected 0.47 capacitor DGND. Ground Core Logic. General-Purpose Input Output Port 3.0/PWM1 Output/External Memory AD0. General-Purpose Input Output Port 3.1/PWM2 Output/External Memory AD1. General-Purpose Input Output Port 3.2/PWM3 Output/External Memory AD2. General-Purpose Input Output Port 3.3/PWM4 Output//External Memory AD3. General-Purpose Input Output Port 2.4/Memory Select General-Purpose Input Output Port 3.3/ADCBUSY Signal/JTAG Test Port Input, Test Reset. Debug download access/External Memory A16. General-Purpose Input Output Port 2.5/Memory Select General-Purpose Input Output Port 2.6/Memory Select Reset Input (Active Low). General-Purpose Input Output Port 3.4/PWM5 Output/External Memory AD4. General-Purpose Input Output Port 3.5/PWM6 Output/External Memory AD5. General-Purpose Input Output Port 0.5/External Interrupt Request Active High/Start Conversion Input Signal ADC/External Memory MS1. General-Purpose Input Output Port 0.6/External Interrupt Request Active High/ADCBUSY Signal. General-Purpose Input Output Port 2.0/Serial Port General-Purpose Input Output Port 0.7/Serial Port 8/Output External Clock Signal/Input Internal Clock Generator Circuits. Output from Crystal Oscillator Inverter. Input Crystal Oscillator Inverter Input Internal Clock Generator Circuits. Supply. Must connected capacitor DGND. Should connected output. Ground PLL. General-Purpose Input Output Port 3.6/External Memory AD6. General-Purpose Input Output Port 3.7/External Memory AD7. General-Purpose Input Output Port 2.7/Memory Select General-Purpose Input Output Port 2.1/Memory Write Select. General-Purpose Input Output Port 2.1/Memory Read Select. General-Purpose Input Output Port 1.7/Serial Port General-Purpose Input Output Port 1.6/Serial Port General-Purpose Input Output Port 4.0/Quadrature Input 1/External Memory AD8. General-Purpose Input Output Port 4.1/Quadrature Input 2/External Memory AD9. General-Purpose Input Output Port 1.5/Serial Port General-Purpose Input Output Port 1.4/Serial Port General-Purpose Input Output Port 1.3/Serial Port General-Purpose Input Output Port 1.2/Serial Port General-Purpose Input Output Port 1.1/Serial Port General-Purpose Input Output Port 1.0/Serial Port
Rev. Page
P0.6/T1/MRST TDO/P0.2/BHE IOGND IOVDD LVDD DGND P3.0/PWM1/AD0 P3.1/PWM2/AD1 P3.2/PWM3/AD2 P3.3/PWM4/AD3 P2.4/MS0 P0.3/ADCBUSY/TRST/A16 P2.5/MS1 P2.6/MS2 P3.4/PWM5/AD4 P3.5/PWM6/AD5 P0.4/IRQ0/CONVST/MS1 P0.5/IRQ1/ADCBUSY P2.0/SPM9 P0.7/SPM8/ECLK/XCLK XCLKO XCLKI PVDD DGND P3.6/AD6 P3.7/AD7 P2.7/MS3 P2.1/WS P2.2/RS P1.7/SPM7 P1.6/SPM6 P4.0/S1/AD8 P4.1/S2/AD9 P1.5/SPM5 P1.4/SPM4 P1.3/SPM3 P1.2/SPM2 P1.1/SPM1 P1.0/SPM0
ADuC7128/ADuC7129
Mnemonic P4.2/AD10 P4.3/PWMTRIP/AD11 P4.4/AD12 P4.5/AD13 REFGND VREF DACGND AGND DACVDD ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
Type1
Description General-Purpose Input Output Port 4.2/External Memory AD10. General-Purpose Input Output Port 4.3/PWM Safety Cutoff/External Memory AD11. General-Purpose Input Output Port 4.4/External Memory AD12. General-Purpose Input Output Port 4.5/External Memory AD13. Ground VREF. Typically connected DGND. Internal Voltage Reference. Must connected 0.47 capacitor when using internal reference. Ground DAC. Typically connected AGND. Analog Ground. Power Supply DAC. This must supplied with connected output. Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input 2/Comparator Positive Input. Single-Ended Differential Analog Input 3/Comparator Negative Input.
input, output, supply.
Rev. Page
ADuC7128/ADuC7129 TYPICAL PERFORMANCE CHARACTERISTICS
(LSB)
(LSB)
774kSPS
-0.2 -0.4 -0.6 -0.8
06020-008
774kSPS
-0.2 -0.4 -0.6 -0.8 -1.0 1000 2000 CODES 3000 4000
1000
2000 CODES
3000
4000
Figure Typical Error, kSPS
(LSB)
(LSB)
Figure Typical Error, kSPS
-0.2 -0.4 -0.6 -0.8
06020-009
1MSPS
1MSPS
-0.2 -0.4 -0.6 -0.8 -1.0 1000 2000 CODES 3000 4000
1000
2000 CODES
3000
4000
Figure Typical Error, MSPS
-0.1 -0.2 -0.3 -0.4 -0.1 -0.2
Figure Typical Error, MSPS
-0.3 -0.4 EXTERNAL REFERENCE
06020-013
(LSB)
(LSB)
(LSB)
EXTERNAL REFERENCE
-0.5 -0.6 -0.7 -0.8 -0.9
-0.5 -0.6 -0.7 -0.8 -0.9
Figure Typical Worst Case Error VREF, kSPS
06020-010
-1.0
-1.0
Figure Typical Worst Case Error VREF, kSPS
Rev. Page
(LSB)
06020-012
-1.0
06020-011
-1.0
ADuC7128/ADuC7129
9000 8000 7000 6000
FREQUENCY
(dB) (dB)
06020-019 06020-018
06020-017
5000 4000 3000
2000 1000
06020-014
1161
1162
1163
EXTERNAL REFERENCE
Figure Code Histogram Plot
1350
Figure Typical Dynamic Performance VREF
1500 1450 1400
774kSPS,
69.3dB, -80.8dB, PHSN -83.4dB
CODE
(dB)
1300 1250 1200 1150
-100 -120
1100
-140
06020-015
1050
-160
FREQUENCY (kHz)
1000
TEMPERATURE (°C)
Figure Dynamic Performance, kSPS
Figure On-Chip Temperature Sensor Voltage Output Temperature
39.8 39.7 39.6 39.5
1MSPS,
70.4dB, -77.2dB, PHSN -78.9dB
(dB)
-100 -120 -140 FREQUENCY (kHz)
06020-016
(mA)
39.4 39.3 39.2 39.1 39.0 38.9 TEMPERATURE (°C)
-160
Figure Dynamic Performance, MSPS
Figure Current Consumption Temperature
Rev. Page
ADuC7128/ADuC7129
12.05 12.00 11.95 11.90 11.85
(mA)
11.80 11.75 11.70 11.65 11.60
06020-020
(µA)
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure Current Consumption Temperature
7.85 7.80
Figure Current Consumption Temperature Sleep Mode
37.4
37.2 7.75 7.70 37.0
(mA)
(mA)
7.65 7.60 7.55 7.50
36.8
36.6
36.4 7.45
06020-021
TEMPERATURE (°C)
62.25
125.00 250.00 500.00 SAMPLING FREQUENCY (kSPS)
1000.00
Figure Current Consumption Temperature
Figure Current Consumption Speed
Rev. Page
06020-023
7.40
36.2
06020-022
11.55
ADuC7128/ADuC7129 TERMINOLOGY
SPECIFICATIONS
Integral Nonlinearity maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero scale, point below first code transition full scale, point above last code transition. Differential Nonlinearity difference between measured ideal change between adjacent codes ADC. Offset Error deviation first code transition (0000 000) (0000 001) from ideal, that LSB. Gain Error deviation last code transition from ideal voltage (full scale LSB) after offset error been adjusted out. Signal (Noise Distortion) Ratio measured ratio signal (noise distortion) output ADC. signal amplitude fundamental. Noise nonfundamental signals half sampling frequency (fS/2), excluding ratio dependent number quantization levels digitization process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02 1.76) Thus, 12-bit converter, this Total Harmonic Distortion ratio harmonics fundamental.
SPECIFICATIONS
Relative Accuracy Otherwise known endpoint linearity, relative accuracy measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting zero error full-scale error. Voltage Output Settling Time amount time takes output settle within level full-scale input change.
Rev. Page
ADuC7128/ADuC7129 OVERVIEW ARM7TDMI CORE
ARM7 core 32-bit reduced instruction computer (RISC). uses single 32-bit instruction data. length data bits, bits, bits. length instruction word bits. ARM7TDMI ARM7 core with following four additional features: support Thumb® (16-bit) instruction support debug support long multiplications includes embedded module support embedded system debugging
EXCEPTIONS
supports five types exceptions privileged processing mode each type. five types exceptions Normal interrupt IRQ. This provided service general-purpose interrupt handling internal external events. Fast interrupt FIQ. This provided service data transfer communication channel with latency. priority over IRQ. Memory abort. Attempted execution undefined instruction. Software interrupt instruction (SWI). This used make call operating system.
THUMB MODE
ARM® instruction 32-bits long. ARM7TDMI processor supports second instruction that been compressed into 16-bits, called Thumb instruction set. Faster execution from 16-bit memory greater code density usually achieved using Thumb instruction instead instruction set, which makes ARM7TDMI core particularly suitable embedded applications. However, Thumb mode limitations: Thumb code typically requires more instructions same job. result, code usually best maximizing performance time-critical code. Thumb instruction does include some instructions needed exception handling, which automatically switches core code exception handling.
Typically, programmer defines interrupt IRQ, higher priority interrupt, that faster response time, programmer define interrupt FIQ.
REGISTERS
ARM7TDMI total registers: general-purpose registers status registers. Each operating mode dedicated banked registers. When writing user-level programs, general-purpose, 32-bit registers R14), program counter (R15), current program status register (CPSR) usable. remaining registers used only system-level programming exception handling. When exception occurs, some standard registers replaced with registers specific exception mode. exception modes have replacement banked registers stack pointer (R13) link register (R14), represented Figure fast interrupt mode more registers R12) fast interrupt processing. Interrupt processing begin without need save restore these registers and, thus, saves critical time interrupt handling process. More information relative programmer's model ARM7TDMI core architecture found following ARM7TDMI technical architecture manuals available directly from Ltd.: DDI0029G, ARM7TDMI Technical Reference Manual DDI-0100, Architecture Reference Manual
ARM7TDMI user guide details core architecture, programming model, both Thumb instruction sets.
LONG MULTIPLY
ARM7TDMI instruction includes four extra instructions that perform 32-bit 32-bit multiplication with 64-bit result, 32-bit 32-bit multiplication-accumulation (MAC) with 64-bit result. This result achieved fewer cycles than required standard ARM7 core.
EMBEDDEDICE
EmbeddedICE provides integrated on-chip support core. EmbeddedICE module contains breakpoint watchpoint registers that allow code halted debugging purposes. These registers controlled through JTAG test port. When breakpoint watchpoint encountered, processor halts enters debug state. Once debug state, processor registers inspected, well Flash/EE, SRAM, memory mapped registers.
Rev. Page
ADuC7128/ADuC7129
(PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND USABLE USER MODE SYSTEM MODES ONLY
this time, ARM7TDMI executes instruction Address 0x1C (FIQ interrupt vector address). maximum total time processor cycles, which just under system using continuous 41.78 processor clock. maximum latency calculation similar, must allow fact that higher priority could delay entry into handling routine arbitrary length time. This time reduced cycles command used; some compilers have option compile without using this command. Another option part Thumb mode, where time reduced cycles. minimum latency interrupts five cycles. consists shortest time request take through synchronizer plus time enter exception mode. Note that ARM7TDMI always runs (32-bit) mode when privileged modes, that when executing interrupt service routines.
06020-024
CPSR
SPSR_FIQ MODE
SPSR_SVC MODE
SPSR_ABT
USER MODE
ABORT MODE
MODE
UNDEFINED MODE
Figure Register Organization
INTERRUPT LATENCY
worst case latency consists following: longest time request take pass through synchronizer time longest instruction complete (the longest instruction LDM) that loads registers, including time data abort entry time entry
Rev. Page
ADuC7128/ADuC7129 MEMORY ORGANIZATION
ADuC7128/ADuC7129 incorporate three separate blocks memory: SRAM on-chip Flash/EE memory. There on-chip Flash/EE memory available user, remaining reserved factoryconfigured boot page. These blocks mapped shown Figure Note that default, after reset, Flash/EE memory mirrored Address 0x00000000. possible remap SRAM Address 0x00000000 clearing REMAP MMR. This remap function described more detail Flash/EE Memory section.
0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x0009F800 FLASH/EE 0x00080000 RESERVED 0x00041FFF SRAM 0x00040000 RESERVED 0x0001FFFF
06020-025
FLASH/EE MEMORY
Flash/EE organized banks bits. first block, bits user space bits reserved factory-configured boot page. page size this Flash/EE memory bytes. second block organized similar manner. arranged bits. this available user space. Flash/EE available user code nonvolatile data memory. There distinction between data program code shares same space. real width Flash/EE memory bits, meaning that mode (32-bit instruction), accesses Flash/EE necessary each instruction fetch. Therefore, recommended that Thumb mode used when executing from Flash/EE memory optimum access speed. maximum access speed Flash/EE memory 41.78 Thumb mode 20.89 full mode (see Execution Time from SRAM FLASH/EE section).
SRAM
SRAM available user, organized bits, that words. code directly from SRAM 41.78 MHz, given that SRAM array configured 32-bit wide memory array (see Execution Time from SRAM FLASH/EE section).
REMAPPABLE MEMORY SPACE (FLASH/EE SRAM) 0x00000000
Figure Physical Memory
MEMORY MAPPED REGISTERS
memory mapped register (MMR) space mapped into upper pages memory array accessed indirect addressing through ARM7 banked registers. space provides interface between on-chip peripherals. registers except core registers reside area. shaded locations shown Figure unoccupied reserved locations should accessed user software. Table through Table full memory map. access time reading writing depends advanced microcontroller architecture (AMBA) used access peripheral. processor AMBA buses: advanced high performance (AHB) used system modules, advanced peripheral (APB) used lower performance peripherals. Access cycle, access cycles. peripherals ADuC7128/ADuC7129 except Flash/EE memory GPIOs.
MEMORY ACCESS
ARM7 core sees memory linear array byte locations where different blocks memory mapped outlined Figure ADuC7128/ADuC7129 memory organization configured little endian format: least significant byte located lowest byte address most significant byte highest byte address.
BYTE BYTE BITS BYTE BYTE 0x00000004
06020-026
0xFFFFFFFF
0x00000000
Figure Little Endian Format
Rev. Page
ADuC7128/ADuC7129
0xFFFFFFFF 0xFFFF06BC 0xFFFF0690 0xFFFF0688 0xFFFF0670 0xFFFF0544 0xFFFF0500 0xFFFF04A8 0xFFFF0480 0xFFFF0448 0xFFFF0440 0xFFFF0434 0xFFFF0400 0xFFFF0394 0xFFFF0380 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0318 0xFFFF0300 0xFFFF0240 0xFFFF0200 0xFFFF0110 0xFFFF0000 TIMER 0xFFFF0FBC 0xFFFF0F80 0xFFFF0F18 0xFFFF0F00 0xFFFF0EA8 0xFFFF0E80 0xFFFF0E28 0xFFFF0E00 0xFFFF0D70 GPIO 0xFFFF0D00 0xFFFF0C30 0xFFFF0C00 0xFFFF0B54 0xFFFF0B00 0xFFFF0A14 0xFFFF0A00 0xFFFF0948 I2C1 0xFFFF0900 0xFFFF0848 0xFFFF0800 0xFFFF076C 0xFFFF0740 0xFFFF072C UART0 0xFFFF0700 UART1 I2C0 FLASH CONTROL INTERFACE
Table System Control Base Address 0xFFFF0200
Address 0x0220 0x0230 0x0234 Name REMAP RSTSTA RSTCLR Byte Access Type Cycle
Table Timer Base Address 0xFFFF0300
Address 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 0x038C 0x0390 Name T0LD T0VAL0 T0VAL1 T0CON T0ICLR T0CAP T1LD T1VAL T1CON T1ICLR T1CAP T2LD T2VAL T2CON T2ICLR T3LD T3VAL T3CON T3ICLR T4LD T4VAL T4CON T4ICLR T4CAP Byte Access Type Cycle
BANDGAP REFERENCE
FLASH CONTROL INTERFACE
POWER SUPPLY MONITOR
OSCILLATOR CONTROL
EXTERNAL MEMORY
GENERAL PURPOSE TIMER
WATCHDOG TIMER
WAKEUP TIMER
GENERAL PURPOSE TIMER
REMAP SYSTEM CONTROL
INTERRUPT CONTROLLER
Figure Memory Mapped Registers
COMPLETE LISTING
Note that Access Type column corresponds access time reading writing MMR. depends AMBA used access peripheral. processor AMBA buses: (advanced high performance bus) used system modules (advanced peripheral bus) used lower performance peripherals. Table Base Address 0xFFFF0000
Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C Name IRQSTA IRQSIG IRQEN IRQCLR SWICFG FIQSTA FIQSIG FIQEN FIQCLR Byte Access Type Cycle
06020-027
Table Base Address 0xFFFF0400
Address 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 Name POWKEY1 POWCON POWKEY2 PLLKEY1 PLLCON PLLKEY2 Byte Access Type Cycle
Table Base Address 0xFFFF0440
Address 0x0440 0x0444 Name PSMCON CMPCON Byte Access Type Cycle
Table Reference Base Address 0xFFFF0480
Address 0x048C Name REFCON Byte Access Type Cycle
Rev. Page
ADuC7128/ADuC7129
Table Base Address 0xFFFF0500
Address 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST Byte Access Type Cycle
Table I2C0 Base Address 0xFFFF0800
Address 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0824 0x0828 0x082C 0x0830 0x0838 0x083C 0x0840 0x0844 0x0848 0x084C Name I2C0MSTA I2C0SSTA I2C0SRX I2C0STX I2C0MRX I2C0MTX I2C0CNT I2C0ADR I2C0BYT I2C0ALT I2C0CFG I2C0DIV I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0SSC I2C0FIF Byte Access Type Cycle
Table Base Address 0xFFFF0670
Address 0x0670 0x0690 0x0694 0x0698 0x06A4 0x06B4 0x06B8 0x06BC Name DACCON DDSCON DDSFRQ DDSPHS DACKEY0 DACDAT DACEN DACKEY1 Byte Access Type Cycle
Table UART0 Base Address 0xFFFF0700
Address 0x0700 Name COM0TX COM0RX COM0DIV0 COM0IEN0 COM0DIV1 COM0IID0
COM0CON0 COM0CON1 COM0STA0 COM0STA1
0x0704 0x0708 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0X072C
COM0SCR COM0IEN1 COM0IID1 COM0ADR COM0DIV2
Byte
Access Type
Cycle
Table I2C1 Base Address 0xFFFF0900
Address 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0924 0x0928 0x092C 0x0930 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C Name I2C1MSTA I2C1SSTA I2C1SRX I2C1STX I2C1MRX I2C1MTX I2C1CNT I2C1ADR I2C1BYT I2C1ALT I2C1CFG I2C1DIV I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1SSC I2C1FIF Byte Access Type Cycle
Table UART1 Base Address 0xFFFF0740
Address 0x0740 Name COM1TX COM1RX COM1DIV0 COM1IEN0 COM1DIV1 COM1IID0
COM1CON0 COM1CON1 COM1STA0 COM1STA1
0x0744 0x0748 0x074C 0x0750 0x0754 0x0758 0x075C 0x0760 0x0764 0x0768 0X076C
COM1SCR COM1IEN1 COM1IID1 COM1ADR COM1DIV2
Byte
Access Type
Cycle
Table Base Address 0xFFFF0A00
Address 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 Name SPISTA SPIRX SPITX SPIDIV SPICON Byte Access Type Cycle
Rev. Page
ADuC7128/ADuC7129
Table Base Address 0xFFFF0B00
Address 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLAOUT Byte Access Type Cycle
Table GPIO Base Address 0xFFFF0D00
Address 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D10 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D50 0x0D54 0x0D58 0x0D5C 0x0D60 0x0D64 0x0D68 0x0D6C Name GP0CON GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP3DAT GP3SET GP3CLR GP3PAR GP4DAT GP4SET GP4CLR GP4PAR Byte Access Type Cycle
Table External Memory Base Address 0xFFFF0C00
Address 0x0C00 0x0C10 0x0C14 0x0C18 0x0C1C 0x0C20 0x0C24 0x0C28 0x0C2C Name XMCFG XM0CON XM1CON XM2CON XM3CON XM0PAR XM1PAR XM2PAR XM3PAR Byte Access Type Cycle
Table Flash/EE Block Base Address 0xFFFF0E00
Address 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 Name FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID Byte Access Type Cycle
Table Flash/EE Block Base Address 0xFFFF0E80
Address 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E98 0x0E9C 0x0EA0 Name FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID Byte Access Type Cycle
Rev. Page
ADuC7128/ADuC7129
Table Base Address 0xFFFF0F00
Address 0x0F00 0x0F04 0x0F08 0x0F0C 0x0F14 0x0F18 Name QENCON QENSTA QENDAT QENVAL QENCLR QENSET Byte Access Type Cycle
Table Base Address 0xFFFF0F80
Address 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8 Name
PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR
Byte
Access Type
Cycle
Rev. Page
ADuC7128/ADuC7129 CIRCUIT OVERVIEW
analog-to-digital converter (ADC) incorporates fast, multichannel, 12-bit ADC. operate from supplies capable providing throughput MSPS when clock source 41.78 MHz. This block provides user with multichannel multiplexer, differential track-andhold, on-chip reference, ADC. consists 12-bit successive approximation converter based around capacitor DACs. Depending input signal configuration, operate following three modes: Fully differential mode, small balanced signals Single-ended mode, single-ended signals Pseudo differential mode, single-ended signals, taking advantage common mode rejection offered pseudo differential input
TRANSFER FUNCTION
Pseudo Differential Mode Single-Ended Mode
pseudo differential single-ended mode, input range VREF. output coding straight binary pseudo differential single-ended modes with FS/4096 V/4096 0.61 when VREF ideal code transitions occur midway between successive integer values (that LSB, LSBs, LSBs, LSBs). ideal input/output transfer characteristic shown Figure
1111 1111 1111 1111 1111 1110 1111 1111 1101
converter accepts analog input range VREF when operating single-ended mode pseudo differential mode. fully differential mode, input signal must balanced around common-mode voltage VCM, range AVDD with maximum amplitude VREF (see Figure 32).
AVDD 2VREF 2VREF
OUTPUT CODE
1111 1111 1100 1LSB 4096
0000 0000 0011 0000 0000 0010 0000 0000 0001 1LSB VOLTAGE INPUT 1LSB
06020-029
0000 0000 0000
06020-028
2VREF
Figure Transfer Function Pseudo Differential Mode Single-Ended Mode
Fully Differential Mode
amplitude differential signal difference between signals applied VIN+ VIN- pins (that VIN+ VIN-). maximum amplitude differential signal therefore, -VREF +VREF VREF). This regardless common mode (CM). common mode average signals (VIN+ VIN-)/2, therefore, voltage upon which inputs centered. This results span each input being VREF/2. This voltage externally, range varies with VREF (see Driving Analog Inputs section). output coding twos complement fully differential mode with VREF/4096 V/4096 1.22 when VREF output result bits, this shifted right. This allows result ADCDAT declared signed integer when writing code. designed code transitions occur midway between successive integer values (that LSB, LSBs, LSBs, LSBs). ideal input/output transfer characteristic shown Figure
Figure Examples Balanced Signals Fully Differential Mode
high precision, drift, factory-calibrated reference provided on-chip. external reference also connected described Band Reference section. Single continuous conversion modes initiated software. external CONVST pin, output generated from on-chip PLA, Timer0, Timer1 overflow also used generate repetitive trigger conversions. signal been deasserted time conversion complete, second conversion begins automatically. voltage output from on-chip band reference proportional absolute temperature also routed through front-end multiplexer, effectively additional channel input. This facilitates internal temperature sensor channel, measuring temperature accuracy ±3°C.
Rev. Page
ADuC7128/ADuC7129
SIGN 1111 1111 1110 1111 1111 1100 1111 1111 1010 1LSB
Current Consumption
VREF 4096
OUTPUT CODE
0000 0000 0001 0000 0000 0000 1111 1111 1110
standby mode, that powered converting, typically consumes internal reference adds During conversion, extra current multiplied sampling frequency kHz).
Timing
Figure gives details timing. Users control clock speed number acquisition clock ADCCON MMR. default, acquisition time eight clocks clock divider two. number extra clocks (such trial write) giving sampling rate kSPS. conversion temperature sensor, acquisition time automatically clocks clock divider When using multiple channels, including temperature sensor, timing settings revert back userdefined settings after reading temperature sensor channel.
TRIAL WRITE
0000 0000 0100 0000 0000 0010
06020-030
0000 0000 0000 -VREF 1LSB 0LSB +VREF 1LSB VOLTAGE INPUT (VIN+ VIN-)
Figure Transfer Function Differential Mode
TYPICAL OPERATION
Once configured control channel selection registers, converts analog input provides 11-bit result data register. four bits sign bits, 12-bit result placed from shown Figure fully differential mode, result bits. Again, should noted that fully differential mode, result represented twos complement format shifted right, pseudo differential single-ended mode, result represented straight binary format.
06020-031
CLOCK
CONVSTART
ADCBUSY
ADCDAT
DATA
SIGN BITS
12-BIT RESULT
Figure Result Format
INTERRUPT
Figure Timing
MMRs Interface
controlled configured number MMRs (see Table that described detail following pages. Table MMRs
Name ADCCON ADCCP ADCCN ADCSTA Description Control Register. Allows programmer enable peripheral, select mode operation (either single-ended, pseudo differential, fully differential mode), select conversion type (see Table 33). Positive Channel Selection Register. Negative Channel Selection Register. Status Register. Indicates when conversion result ready. ADCSTA register contains only bit, ADCREADY (Bit representing status ADC. This conversion generating interrupt. cleared automatically reading ADCDAT MMR. When performing conversion, status read externally ADCBusy pin. This high during conversion. When conversion finished, ADCBusy goes back low. This information available P0.5 (see General-Purpose section) enabled GP0CON register. Data Result Register. Holds 12-bit result, shown Table Reset Register. Resets registers their default values.
ADCDAT ADCRST
Rev. Page
06020-032
ADCSTA
ADCSTA
ADuC7128/ADuC7129
Table ADCCON Designations
12:10 Value Description Clock Speed (fADC FCORE, Conversion Clocks Acquisition Time). fADC/1. This divider provided obtain MSPS with external clock <41.78 MHz. fADC/2 (default value). fADC/4. fADC/8. fADC/16. fADC/32. Acquisition Time (Number Clocks). clocks. clocks. clocks (default value). clocks. Enable Conversion. user enable conversion mode. Cleared user disable conversion mode. Reserved. This should user. Power Control. user place normal mode. must powered least before converts correctly. Cleared user place power-down mode. Conversion Mode. Single-ended Mode. Differential Mode. Pseudo Differential Mode. Reserved. Conversion Type. Enable CONVST conversion input. Enable Timer1 conversion input. Enable Timer0 conversion input. Single Software Conversion. after conversion. ADCCON should cleared after starting single software conversion avoid further conversions triggered CONVST pin. Continuous Software Conversion. Conversion. Conversion. Reserved.
Other
Rev. Page
ADuC7128/ADuC7129
Table ADCCP1 Designations
Value Description Reserved Positive Channel Selection Bits ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12/LD2TX2 ADC13/LD1TX2 Reserved Reserved Temperature Sensor AGND Reference AVDD/2 Reserved
Table ADCCN1 Designations
Value Description Reserved Negative Channel Selection Bits ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12/LD2TX ADC13/LD1TX Reserved Reserved Temperature Sensor Reserved
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others
channel availability depends part model.
Table ADCSTA Designations
Value Description Indicates that conversion complete. automatically once conversion completes. Automatically cleared reading ADCDAT MMR.
channel availability depends part model. Because ADC12 ADC13 shared with line driver pins, high level crosstalk seen these pins when used mode.
Table ADCDAT Designations
27:16 Value Description Holds result (see Figure 35).
Table ADCRST Designations
Value Description user reset registers their default values.
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ADuC7128/ADuC7129
CONVERTER OPERATION
incorporates successive approximation (SAR) architecture involving charge-sampled input stage. This architecture described three different modes operation: differential mode, pseudo differential mode, single-ended mode.
Pseudo Differential Mode
pseudo differential mode, Channel- linked VIN- ADuC7128/ADuC7129, switches between (Channel-) (VREF). VIN- must connected ground voltage. input signal VIN+ then vary from VIN- VREF VIN-. Note that VIN- must chosen that VREF VIN- does exceed AVDD.
CAPACITIVE AIN0 AIN13 CHANNEL+ CAPACITIVE
06020-035 06020-036
Differential Mode
ADuC7128/ADuC7129 contain successive approximation based capacitive DACs. Figure Figure show simplified schematics acquisition conversion phase, respectively. comprises control logic, SAR, capacitive DACs. Figure (the acquisition phase), closed Position comparator held balanced condition, sampling capacitor arrays acquire differential signal input.
CAPACITIVE AIN0 AIN13 CHANNEL+ CHANNEL- CAPACITIVE
06020-033
COMPARATOR
CONTROL LOGIC
VIN-
VREF CHANNEL-
Figure Pseudo Differential Mode
COMPARATOR
Single-Ended Mode
single-ended mode, always connected internally ground. VIN- floating. input signal range VIN+ VREF.
CAPACITIVE AIN0 AIN13 CHANNEL+ CHANNEL- COMPARATOR
CONTROL LOGIC
VREF
Figure Acquisition Phase
When starts conversion (see Figure 38), opens move Position causing comparator become unbalanced. Both inputs disconnected once conversion begins. control logic charge redistribution DACs used subtract fixed amounts charge from sampling capacitor arrays bring comparator back into balanced condition. When comparator rebalanced, conversion complete. control logic generates output code. output impedances sources driving VIN+ VIN- must matched; otherwise, inputs have different settling times, resulting errors.
CAPACITIVE AIN0 AIN13 CHANNEL+ CHANNEL- CAPACITIVE
06020-034
CONTROL LOGIC
CAPACITIVE
Figure Single-Ended Mode
Analog Input Structure
Figure shows equivalent circuit analog input structure ADC. four diodes provide protection analog inputs. Care must taken ensure that analog input signals never exceed supply rails more than Voltage excess would cause these diodes become forward biased start conducting into substrate. These diodes conduct without causing irreversible damage part. capacitors Figure typically primarily attributed capacitance. resistors lumped components made resistance switches. value these resistors typically about capacitors sampling capacitors have capacitance typical.
COMPARATOR
CONTROL LOGIC
VREF
Figure Conversion Phase
Rev. Page
ADuC7128/ADuC7129
AVDD
Table Ranges
AVDD
AVDD
VREF 2.048 1.25 2.048 1.25
1.25 1.024 0.75 1.25 1.024 0.75
2.05 2.276 2.55 1.75 1.976 2.25
Signal Peak-to-Peak 2.048 1.25 2.048 1.25
06020-037
TEMPERATURE SENSOR
ADuC7128/ADuC7129 provide voltage output from on-chip band reference proportional absolute temperature. voltage output also routed through front multiplexer (effectively additional channel input), facilitating internal temperature sensor channel, measuring temperature accuracy ±3°C. following code example configure with temperature sensor:
main(void) float short ADCCON 0x20; delay(2000);
ADC0
06020-038
Figure Equivalent Analog Input Circuit Conversion Phase: Switches Open, Track Phase: Switches Closed
applications, removing high frequency components from analog input signal recommended through low-pass filter relevant analog input pins. applications where harmonic distortion signal-to-noise ratio critical, analog input should driven from impedance source. Large source impedances significantly affect performance necessitate input buffer amplifier. choice function particular application. Figure Figure give example front end.
ADuC7128
0.01µF
power-on
ADCCP 0x10; Select Temperature Sensor input REFCON 0x01;// connect internal 2.5V reference Vref ADCCON 0xE4;// continuous conversion while(1) while (!ADCSTA){};
Figure Buffering Single-Ended/Pseudo Differential Input
ADuC7128
ADC0 VREF
06020-039
ADC1
(ADCDAT 16); calculate temperature formula: 0x525 ((Temperature 0x525 Sensor Voltage) 1.3) 1.3; floor(a); printf("Temperature: oC\n",b); return
Figure Buffering Differential Inputs
When amplifier used drive analog input, source impedance should limited values lower than maximum source impedance depends amount total harmonic distortion (THD) that tolerated. increases source impedance increases performance degrades.
DRIVING ANALOG INPUTS
Internal external reference used ADC. differential mode operation, there restrictions common-mode input signal (VCM) that dependent reference value supply voltage used ensure that signal remains within supply rails. Table gives some calculated minimum maximum values.
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ADuC7128/ADuC7129
BAND REFERENCE
ADuC7128/ADuC7129 provide on-chip band reference that used DAC. This internal reference also appears VREF pin. When using internal reference, capacitor 0.47 must connected from external VREF AGND ensure stability fast response during conversions. This reference also connected external (VREF) used reference other circuits system. Table REFCON Designations
Description Reserved. Internal Reference Output Enable. user connect internal reference VREF pin. reference used external components needs buffered. Cleared user disconnect reference from VREF pin. Note: on-chip functional only with internal reference output enable set. does work with external reference.
external buffer required because drive capability VREF output. programmable option also allows external reference input VREF pin. Note that possible disable internal reference. Therefore, external reference source must capable overdriving internal reference source. band reference interface consists 8-bit REFCON MMR, described Table
Rev. Page
ADuC7128/ADuC7129 NONVOLATILE FLASH/EE MEMORY
FLASH/EE MEMORY OVERVIEW
ADuC7128/ADuC7129 incorporate Flash/EE memory technology on-chip provide user with nonvolatile, incircuit reprogrammable memory space. Like EEPROM, Flash memory programmed in-system byte level, although must first erased. erase performed page blocks. result, Flash memory often, more correctly, referred Flash/EE memory. Overall, Flash/EE memory represents step closer ideal memory device that includes nonvolatility, in-circuit programmability, high density, cost. Incorporated ADuC7128/ADuC7129, Flash/EE memory technology allows user update program code space in-circuit, without need replace one-time programmable (OTP) devices remote operating nodes. indicated Table Specifications section, Flash/EE memory endurance qualification carried accordance with JEDEC Retention Lifetime Specification A117 over industrial temperature range -40° +125°C. results allow specification minimum endurance figure over supply temperature 10,000 cycles. Retention quantifies ability Flash/EE memory retain programmed data over time. Again, parts qualified accordance with formal JEDEC Retention Lifetime Specification (A117) specific junction temperature 85°C). part this qualification procedure, Flash/EE memory cycled specified endurance limit, described previously, before data retention characterized. This means that Flash/EE memory guaranteed retain data fully specified retention lifetime every time Flash/EE memory reprogrammed. Note, too, that retention lifetime, based activation energy derates with shown Figure
FLASH/EE MEMORY
ADuC7128/ADuC7129 contain arrays Flash/EE memory. first block, lower available user upper this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download. embedded firmware also contain power-on configuration routine that downloads factory calibrated coefficients various calibrated peripherals, such band references. This embedded firmware hidden from user code. possible user read, write, erase this page. second block, Flash/EE memory available user. Flash/EE memory programmed in-circuit, using serial download mode JTAG mode provided.
RETENTION (Years)
04955-085
JUNCTION TEMPERATURE (°C)
Flash/EE Memory Reliability
Flash/EE memory arrays parts fully qualified Flash/EE memory characteristics: Flash/EE memory cycling endurance Flash/EE memory data retention. Endurance quantifies ability Flash/EE memory cycled through many program, read, erase cycles. single endurance cycle composed four independent, sequential events, defined Initial page erase sequence Read/verify, sequence single Flash/EE location Byte program sequence memory Second read/verify sequence endurance cycle
Figure Flash/EE Memory Data Retention
Serial Downloading (In-Circuit Programming)
ADuC7128/ADuC7129 facilitate code download standard UART serial port. ADuC7128/ADuC7129 enter serial download mode after reset power cycle pulled through external resistor. Once serial download mode, user download code full Flash/EE memory while device in-circuit target application hardware. serial download executable provided part development system serial downloads UART. additional information, application note available www.analog.com/microconverter describing protocol serial downloads UART.
reliability qualification, every half word (16-bit wide) location three pages (top, middle, bottom) Flash/EE memory cycled 10,000 times from 0x0000 0xFFFF.
JTAG Access
JTAG protocol uses on-chip JTAG interface facilitate code download debug.
Rev. Page
ADuC7128/ADuC7129
FLASH/EE MEMORY SECURITY
Flash/EE memory available user read write protected. FEE0PRO/FEE0HID protects from being read through JTAG also parallel programming mode. other bits this register protect writing Flash/EE memory; each protects four pages, that Write protection activated access types. FEE1PRO FEE1HID similarly protect second block. bits this used protect four pages time. sequence write shown following example; this protects writing Page Page Flash/EE memory:
FEE0PRO=0xFFFFFFFD; FEE0MOD=0x48; FEE0ADR=0x1234; FEE0DAT=0x5678; FEE0CON= 0x0C; //Protect pages //Write enable //16 value //16 value Write command
same sequence should followed protect part permanently with FEExADR 0xDEAD FEExDAT 0xDEAD.
Three Levels Protection
Protection removed writing directly into FEExHID MMR. This protection does remain after reset. Protection writing into FEExPRO MMR. takes effect only after save protection command (0x0C) reset. FEExPRO protected avoid direct access. saved once must entered again modify FEExPRO. mass erase sets back 0xFFFF also erases user code. Flash/EE memory permanently protected using FEEPRO particular value 0xDEADDEAD key. Entering again modify FEExPRO register allowed.
FLASH/EE CONTROL INTERFACE
FEE0DAT Register
Name FEE0DAT Address 0xFFFF0E0C Default Value 0xXXXX Access
FEE0DAT 16-bit data register.
FEE0ADR Register
Name FEE0ADR Address 0xFFFF0E10 Default Value 0x0000 Access
FEE0ADR 16-bit address register.
FEE0SGN Register
Name FEE0SGN Address 0xFFFF0E18 Default Value 0xFFFFFF Access
Sequence Write
Write FEExPRO corresponding page protected. Enable protection setting FEExMOD (Bit must equal Write 32-bit FEExADR, FEExDAT. write command FEExCON; wait read successful monitoring FEExSTA. Reset part.
FEE0SGN 24-bit code signature.
FEE0PRO Register
Name FEE0PRO Address 0xFFFF0E1C Default Value 0x00000000 Access
FEE0PRO provides protection following subsequent reset MMR. requires software (see Table 44).
FEE0HID Register
Name FEE0HID Address 0xFFFF0E20 Default Value 0xFFFFFFFF Access
remove modify protection, same sequence used with modified value FEExPRO. chosen value 0xDEAD, then memory protection cannot removed. Only mass erase unprotects part, also erases user code.
FEE0HID provides immediate protection MMR. does require software keys (see Table 44).
Command Sequence Executing Mass Erase
FEE0DAT 0x3CFF; FEE0ADR 0xFFC3; FEE0MOD FEE0MOD|0x8; //Erase enable FEE0CON 0x06; //Mass erase command
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ADuC7128/ADuC7129
FEE1DAT Register
Name FEE1DAT Address 0xFFFF0E8C Default Value 0xXXXX Access
FEE0STA Register
Name FEE0STA Address 0xFFFF0E00 Default Value 0x0000 Access
FEE1DAT 16-bit data register.
FEE1ADR Register
Name FEE1ADR Address 0xFFFF0E90 Default Value 0x0000 Access
FEE1STA Register
Name FEE1STA Address 0xFFFF0E80 Default Value 0x0000 Access
FEE1ADR 16-bit address register.
FEE0MOD Register
Access Name FEE0MOD Address 0xFFFF0E04 Default Value 0x80 Access
FEE1SGN Register
Name FEE1SGN Address 0xFFFF0E98 Default Value 0xFFFFFF
FEE1SGN 24-bit code signature.
FEE1MOD Register
Name FEE1MOD Address 0xFFFF0E84 Default Value 0x80 Access
FEE1PRO Register
Name FEE1PRO Address 0xFFFF0E9C Default Value 0x00000000 Access
FEE0CON Register
Name FEE0CON Address 0xFFFF0E08 Default Value 0x0000 Access
FEE1PRO provides protection following subsequent reset MMR. requires software (see Table 45).
FEE1HID Register
Name FEE1HID Address 0xFFFF0EA0 Default Value 0xFFFFFFFF Access
FEE1CON Register
Name FEE1CON Address 0xFFFF0E88 Default Value 0x0000 Access
FEE1HID provides immediate protection MMR. does require software keys (see Table 45).
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ADuC7128/ADuC7129
Table FEExSTA Designations
15:6 Description Reserved. Reserved. Reserved. Flash/EE Interrupt Status Bit. automatically when interrupt occurs, that when command complete Flash/EE interrupt enable FEExMOD register set. Cleared when reading FEExSTA register. Flash/EE Controller Busy. automatically when controller busy. Cleared automatically when controller busy. Command Fail. automatically when command completes unsuccessfully. Cleared automatically when reading FEExSTA register. Command Complete. MicroConverter when command complete. Cleared automatically when reading FEExSTA register.
Table FEExMOD Designations
Description Reserved. Flash/EE Interrupt Enable. user enable Flash/EE interrupt. interrupt occurs when command complete. Cleared user disable Flash/EE interrupt Erase/Write Command Protection. user enable erase write commands. Cleared protect Flash/EE memory against erase/write command. Reserved. Should always user. Flash/EE Wait States. Both Flash/EE blocks must have same wait state value change take effect.
Table Command Codes FEExCON
Code 0x00 0x011 0x021 0x031 0x041 0x051 0x061 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
Command Null Single read Single write Erase/Write Single verify Single erase Mass erase Reserved Reserved Reserved Reserved Signature Protect Reserved Reserved Ping
Description Idle State. Load FEExDAT with 16-bit data indexed FEExADR. Write FEExDAT address pointed FEExADR. This operation takes Erase page indexed FEExADR write FEExDAT location pointed FEExADR. This operation takes Compare contents location pointed FEExADR data FEExDAT. result comparison returned FEExSTA Erase page indexed FEExADR. Erase user space. kernel protected Block This operation takes 2.48 sec. prevent accidental execution, command sequence required execute this instruction. Reserved. Reserved. Reserved. Reserved. Gives signature Flash/EE 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles. This command only once. value FEExPRO saved removed only with mass erase (0x06) with key. Reserved. Reserved. Operation, Interrupt Generated.
FEExCON register always reads 0x07 immediately after execution these commands.
Rev. Page
ADuC7128/ADuC7129
Table FEE0PRO FEE0HID Designations
Description Read Protection. Cleared user protect Block user allow reading Block Write Protection Page Page 120, Page Page 116, Page Page Cleared user protect pages writing. user allow writing pages.
30:0
Table FEE1PRO FEE1HID Designations
Description Read Protection. Cleared user protect Block user allow reading Block Write Protection Page Page 120. Cleared user protect pages writing. user allow writing pages. Write Protection Page Page Page Page Cleared user protect pages writing. user allow writing pages.
31:0
EXECUTION TIME FROM SRAM FLASH/EE
This section describes SRAM Flash/EE access times during execution applications where execution time critical.
Execution from SRAM
Fetching instructions from SRAM takes clock cycle because access time SRAM clock cycle minimum. However, instruction involves reading writing data memory, extra cycle must added data SRAM three cycles data Flash/EE), cycle execute instruction cycles 32-bit data from Flash/EE. control flow instruction, such branch instruction, takes cycle fetch, also takes cycles fill pipeline with instructions.
Timing identical both modes when executing instructions that involve using Flash/EE data memory. instruction executed control flow instruction, extra cycle needed decode address program counter then four cycles needed fill pipeline. data processing instruction involving only core registers doesn't require extra clock cycles, involves data Flash/EE, extra clock cycle needed decode address data cycles 32-bit data from Flash/EE. extra cycle must also added before fetching another instruction. Data transfer instructions more complex summarized Table Table Execution Cycles ARM/Thumb Mode
Instructions LDM/PUSH STRH STRM/POP Fetch Cycles Dead Time Data Access Dead Time
Execution from Flash/EE
Because Flash/EE width bits access time 16-bit words execution from Flash/EE cannot done cycle done from SRAM when addition, some dead times needed before accessing data value bits. mode, where instructions bits, cycles needed fetch instruction when Thumb mode, where instructions bits, cycle needed fetch instruction.
With number bytes data load store multiple load/store instruction. SWAP instruction combines instruction with only fetch, giving total eight cycles plus
Rev. Page
ADuC7128/ADuC7129
RESET REMAP
exception vectors situated bottom memory array, from Address 0x00000000 Address 0x00000020, shown Figure
0xFFFFFFFF
Remap Operation
When reset occurs ADuC7128/ADuC7129, execution starts automatically factory-programmed internal configuration code. This kernel hidden cannot accessed user code. ADuC7128/ADuC7129 normal mode (the high), they execute power-on configuration routine kernel then jump reset vector Address 0x00000000 execute user's reset exception routine. Because Flash/EE mirrored bottom memory array reset, reset interrupt routine must always written Flash/EE. remap done from Flash/EE setting REMAP register. Precautions must taken execute this command from Flash/EE, above Address 0x00080020, from bottom array because this replaced SRAM. This operation reversible: Flash/EE remapped Address 0x00000000 clearing REMAP MMR. Precaution must again taken execute remap function from outside mirrored area. kind reset remaps Flash/EE memory bottom array.
KERNEL INTERRUPT SERVICE ROUTINES
0x0008FFFF FLASH/EE 0x00080000
0x00041FFF INTERRUPT SERVICE ROUTINES 0x00040000
SRAM
MIRROR SPACE EXCEPTION VECTOR ADDRESSES 0x00000020 0x00000000 0x00000000
06020-040
Figure Remap Exception Execution
Reset Operation
There four kinds reset: external reset, power-on reset, watchdog expiration, software force. RSTSTA register indicates source last reset RSTCLR clears RSTSTA register. These registers used during reset exception service routine identify source reset. RSTSTA null, reset external. Note that when clearing RSTSTA, bits that currently must cleared. Otherwise, reset event occurs.
default after reset, Flash/EE mirrored bottom memory array. remap function allows programmer mirror SRAM bottom memory array, facilitating execution exception routines from SRAM instead from Flash/EE. This means exceptions executed twice fast, with exception being executed mode bits), SRAM being bits wide instead 16-bit wide Flash/EE memory. Table REMAP Designations
Name Remap
Description Remap Bit. user remap SRAM Address 0x00000000. Cleared automatically after reset remap Flash/EE memory Address 0x00000000.
Table RSTSTA Designations
Description Reserved. Software Reset. user force software reset. Cleared setting corresponding RSTCLR. Watchdog Timeout. automatically when watchdog timeout occurs. Cleared setting corresponding RSTCLR. Power-On Reset. automatically when power-on reset occurs. Cleared setting corresponding RSTCLR.
Rev. Page
ADuC7128/ADuC7129 OTHER ANALOG PERIPHERALS
ADuC7128/ADuC7129 feature 10-bit current that used generate user-defined waveforms sine waves generated DDS. consists 10-bit IDAC followed current-to-voltage conversion. current output IDAC passed through resistor capacitor network where both filtered converted voltage. This voltage then buffered passed line driver. Table DACCON Designations
Value
function, internal voltage reference must enabled driven onto external capacitor, REFCON 0x01. Once enabled, users drop internal reference value. This bias currents drawn from reference used circuitry. recommended that using DAC, left powered avoid seeing variations results.
10:9
Description Reserved. These bits should written user. Reserved. This should written user. Reserved. This should written user. Reserved. This should written user. Output Enable. This operates modes. Line Driver mode, this should set. user enable line driver output. Cleared user disable line driver output. this mode line driver output high impedance. Single-Ended Differential Output Control. user operate differential mode, output differential voltage between LD1TX LD2TX. voltage output range VREF/2 VREF/2. Cleared user reference LD1TX output AGND. voltage output range AVDD/2 VREF/2. Reserved. This should user. Operation Mode Control. This selects mode operation DAC. Power-Down. Reserved. Reserved. Mode. Selected DACEN. Update Rate Control. This effect when mode. user update negative edge Timer1. This allows user core CLK, CLK, baud CLK, user divide these down 256, 32,768. user waveform generation writing data register from updating regular intervals Timer1. Cleared user update negative edge HCLK.
Rev. Page
ADuC7128/ADuC7129
DACEN Register
Name DACEN Address 0xFFFF06B8 Default Value 0x00 Access
DACDAT controls output DAC. data written this register ±9-bit signed value. This means that 0x0000 represents midscale, 0x0200 represents zero scale, 0x01FF represents full scale. DACEN DACDAT require access. write these MMRs, sequences shown Table Table DACEN DACDAT Write Sequences
DACEN DACKEY0 0x07 DACEN user value DACKEY1 0xB9 DACDAT DACKEY0 0x07 DACDAT user value DACKEY1 0xB9
Table DACEN Designations
Description Reserved. user enable mode. user enable mode.
DACDAT Register
Name DACDAT Address 0xFFFF06B4 Default Value 0x0000 Access
used generate digital sine wave signal ADuC7128/ADuC7129. enabled into free running mode user. Both phase frequency controlled.
Table DACDAT Designations
15:10 Description Reserved. 10-bit data DAC.
Table DDSCON Designations
Description Reserved. Output Enable. user enable output. This effect only selected DACCON. Cleared user disable output. Reserved. Binary Divide Control. Scale Ratio 0000 0.000 0001 0.125 0010 0.250 0011 0.375 0100 0.500 0101 0.625 0110 0.750 0111 0.875 1xxx 1.000
Rev. Page
ADuC7128/ADuC7129
DDSFRQ Register
Name DDSFRQ Address 0xFFFF0694 Default Value 0x00000000 Access
Table DDSFRQ Designations
31:0 Description Frequency select word (FSW)
This monitor function allows user save working registers avoid possible data loss supply brown-out conditions. also ensures that normal code execution does resume until safe supply level been established. does operate correctly when using JTAG debug. should disabled JTAG debug mode.
frequency controlled DDSFRQ MMR. This contains 32-bit word (FSW) that controls frequency according following formula:
COMPARATOR
ADuC7128/ADuC7129 integrate uncommitted voltage comparator. positive input multiplexed with ADC2, negative input options: ADC3 internal reference. output comparator configured generate system interrupt, routed directly programmable logic array, start conversion, external pin, CMPOUT.
ADC2/CMP0 ADC3/CMP1
06020-042
Frequency
20.8896
Default Value 0x00000000 Access
DDSPHS Register
Name DDSPHS Address 0xFFFF0698
Table DDSPHS Designations
31:12 11:0 Description Reserved Phase
START CONVERSION
phase offset controlled DDSPHS MMR. This contains 12-bit value that controls phase output according following formula:
P0.0/CMPOUT
Figure Comparator
Phase Offset
Phase
Hysteresis
Figure shows input offset voltage hysteresis terms defined. Input offset voltage (VOS) difference between center hysteresis range ground level. This either positive negative. hysteresis voltage (VH) width hysteresis range.
COMPOUT
POWER SUPPLY MONITOR
power supply monitor ADuC7128/ADuC7129 indicates when IOVDD supply drops below supply trip points. monitor function controlled PSMCON register (see Table 56). enabled IRQEN FIQEN register, monitor interrupts core using PSMI PSMCON MMR. This cleared immediately once goes high. Note that interrupt generated exited before goes high (IOVDD above trip point), further interrupts generated until returns high. user should ensure that code execution remains within until returns high. Table PSMCON Designations
Name
COMP0
Figure Comparator Hysteresis Transfer Function
PSMEN
PSMI
Description Comparator Bit. This read-only that directly reflects state comparator. Read indicates IOVDD supply above selected trip point power-down mode. Read indicates IOVDD supply below selected trip point. This should before leaving interrupt service routine. Trip Point Selection Bit. 2.79 3.07 Power Supply Monitor Enable Bit. user enable power supply monitor circuit. Cleared user disable power supply monitor circuit. Power Supply Monitor Interrupt Bit. This high MicroConverter low, indicating supply. PSMI used interrupt processor. Once returns high, PSMI cleared writing this location. write effect. There timeout delay. PSMI cleared immediately once goes high.
Rev. Page
06020-041
ADuC7128/ADuC7129
Comparator Interface
comparator interface consists 16-bit MMR, CMPCON, described Table Table CMPCON Designations
15:11 Value Name CMPEN Description Reserved. Comparator Enable Bit. user enable comparator. Cleared user disable comparator. Note: comparator interrupt generated enable comparator. This should cleared user software. Comparator Negative Input Select Bits. AVDD/2. ADC3 input. VREF 0.6. Reserved. Comparator Output Configuration Bits. connections disabled. connections disabled. connections enabled. connections enabled. Comparator Output Logic State Bit. When low, comparator output high when positive input (CMP0) above negative input (CMP1). When high, comparator output high when positive input below negative input. Response Time. response time typical large signals (2.5 differential). response time typical small signals (0.65 differential). Reserved. Reserved. response time typical signal type. Comparator Hysteresis Bit. user have hysteresis about Cleared user have hysteresis. Comparator Output Rising Edge Interrupt. automatically when rising edge occurs monitored voltage (CMP0). Cleared user writing this bit. Comparator Output Falling Edge Interrupt. automatically when falling edge occurs monitored voltage (CMP0). Cleared user.
CMPIN
CMPOC
CMPOL
CMPRES
CMPHYST
CMPORI
CMPOFI
Rev. Page
ADuC7128/ADuC7129
OSCILLATOR PLL-POWER CONTROL
ADuC7128/ADuC7129 integrate 32.768 oscillator, clock divider, PLL. locks onto multiple (1275) internal oscillator provide stable 41.78 clock system. core operate this frequency, binary submultiples allow power saving. default core clock clock divided MHz. core clock frequency output ECLK described Figure Note that when ECLK used output core clock, output signal buffered suitable clock source external device without external buffer. power-down mode available ADuC7128/ADuC7129. operating mode, clocking mode, programmable clock divider controlled MMRs, PLLCON (see Table POWCON (see Table 62). PLLCON controls operating mode clock system, POWCON controls core clock frequency power-down mode.
WATCHDOG TIMER INT. 32kHz1 OSCILLATOR CRYSTAL OSCILLATOR XCLKO XCLKI
Example Source Code
T2LD TCON 0x480; while ((T2VAL t2val_old) (T2VAL //ensures timer value loaded IRQEN 0x10; //enable interrupt PLLKEY1 0xAA; PLLCON 0x01; PLLKEY2 0x55; POWKEY1 0x01; POWCON 0x27; Core into mode POWKEY2 0xF4;
noisy environments, noise couple external crystal pins, lose lock momentarily. interrupt provided interrupt controller. core clock immediately halted, this interrupt serviced only when lock restored. case crystal loss, watchdog timer should used. During initialization, test RSTSTA determine reset came from watchdog timer.
WAKEUP TIMER POWER OCLK 32.768kHz 40.78MHz MDCLK UCLK ANALOG PERIPHERALS P0.7/XCLK
External Clock Selection
switch external clock P0.7, configure P0.7 Mode external clock MHz, providing tolerance
Example Source Code
T2LD TCON 0x480; while ((T2VAL t2val_old) (T2VAL //ensures timer value loaded
06020-043
CORE
/2CD HCLK
132.768kHz
P0.7/ECLK
IRQEN 0x10; //enable interrupt PLLKEY1 0xAA; PLLCON 0x03; //Select external clock PLLKEY2 0x55; POWKEY1 0x01; POWCON 0x27; Core into mode POWKEY2 0xF4;
Figure Clocking System
External Crystal Selection
switch external crystal, following procedure: Enable Timer2 interrupt configure timeout period >120 Follow write sequence PLLCON register, setting MDCLK bits clearing OSEL bit. Force part into mode following correct write sequence POWCON register. When part interrupted from mode Timer2 interrupt source, clock source switched external clock.
Power Control System
choice operating modes available ADuC7128/ ADuC7129. Table describes what part ADuC7128/ ADuC7129 powered different modes indicates power-up time. Table gives some typical values total current consumption (analog digital supply currents) different modes, depending clock divider bits. turned off. Note that these values also include current consumption regulator other parts test board which these values were measured.
Rev. Page
ADuC7128/ADuC7129
Table Operating Modes
Mode Active Pause Sleep Stop PC[2:0] Core Peripherals XTAL/T2/T3 XIRQ Start-Up/Power-On Time 3.06 3.06 1.58 6.45 3.85
Table Typical Current Consumption 25°C
Mode Active Pause Sleep Stop 33.1 22.7 21.2 13.3 13.8
MMRs Keys
prevent accidental programming, certain sequence must followed when writing PLLCON POWCON registers (see Table 60).
Table PLLCON Designations
Value Name OSEL Description Reserved. Input Selection. user internal oscillator. default. Cleared user external crystal. Reserved. Clocking Modes. Reserved. PLL. Default configuration. Reserved. External clock P0.7 pin.
PLLKEYx Register
Name PLLKEY1 PLLKEY2 Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access Default Value 0x21 Access MDCLK
PLLCON Register
Name PLLCON Address 0xFFFF0414
POWKEYx Register
Name POWKEY1 POWKEY2 Address 0xFFFF0404 0xFFFF040C Default Value 0x0000 0x0000 Access
Table POWCON Designations
Value Name Description Reserved. Operating Modes. Active mode. Pause mode. Nap. Sleep mode. IRQ0 IRQ3 Timer2 wake ADuC7128/ADuC7129. Stop mode. Reserved. Reserved. Clock Divider Bits. 41.779200 MHz. 20.889600 MHz. 10.444800 MHz. 5.222400 MHz. 2.611200 MHz. 1.305600 MHz. 654.800 kHz. 326.400 kHz.
POWCON Register
Name POWCON Address 0xFFFF0408 Default Value 0x0003 Access
Table PLLCON POWCON Write Sequence
PLLCON PLLKEY1 0xAA PLLCON 0x01 PLLKEY2 0x55 POWCON POWKEY1 0x01 POWCON user value POWKEY2 0xF4 Others
Rev. Page
RSVD
ADuC7128/ADuC7129 DIGITAL PERIPHERALS
GENERAL OVERVIEW
ADuC7128/ADuC7129 integrate channel interface. outputs configured drive H-bridge used standard outputs. power outputs default H-bridge mode. This ensures that motor turned default. standard mode, outputs arranged three pairs pins. Users have control over period each pair outputs over duty cycle each individual output. Table MMRs
Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Description Control Compare Register Outputs Compare Register Outputs Compare Register Outputs Frequency Control Outputs Compare Register Outputs Compare Register Outputs Compare Register Outputs Frequency Control Outputs Compare Register Outputs Compare Register Outputs Compare Register Outputs Frequency Control Outputs Convert Start Control Interrupt Clear
HIGH SIDE (PWM1)
SIDE (PWM2)
PWM1COM3 PWM1COM2 PWM1COM1 PWM1LEN
06020-044
Figure Timing
clock selectable PWMCON1 with following values: UCLK/2, 128, 256. length period defined PWMxLEN. waveforms count value 16-bit timer compare registers contents shown with PWM1 PWM2 waveforms above. low-side waveform, PWM2, goes high when timer count reaches PWM1LEN, goes when timer count reaches value held PWM1COM3 when high-side waveform PWM1 goes low. high-side waveform, PWM1, goes high when timer count reaches value held PWM1COM1, goes when timer count reaches value held PWM1COM2.
modes, PWMxCOMx MMRs controls point which outputs change state. example first pair outputs (PWM1 PWM2) shown Figure Table PWMCON1 Designations
Name SYNC Description Enables Synchronization. user that counters reset next clock edge after detection high-to-low transition SYNC pin. Cleared user ignore transitions SYNC pin. user invert PWM6. Cleared user PWM6 normal mode. user invert PWM4. Cleared user PWM4 normal mode. user invert PWM2. Cleared user PWM2 normal mode. user enable trip interrupt. When PWMTRIP input low, PWMEN cleared interrupt generated. Cleared user disable PWMTRIP interrupt. HOFF HMODE user enable outputs. Cleared user disable outputs. HOFF HMODE Table H-Bridge mode, this effect. Clock Prescaler Bits. Sets UCLK divider.
Rev. Page
PWM6INV PWM4NV PWM2INV PWMTRIP
PWMCP2 PWMCP1
ADuC7128/ADuC7129
Name PWMCP0 Description 128. 256. user invert outputs. Cleared user outputs normal. High Side Off. user force PWM1 PWM3 outputs high. This also forces PWM2 PWM4 low. Cleared user outputs normal. Load Compare Registers. user load internal compare registers with values PWMxCOMx next transition timer from 0x00 0x01. Cleared user values previously stored internal compare registers. Direction Control. user enable PWM1 PWM2 output signals while PWM3 PWM4 held low. Cleared user enable PWM3 PWM4 output signals while PWM1 PWM2 held low. Enables H-bridge mode. user enable H-Bridge mode PWMCON1. Cleared user operate PWMs standard mode. user enable outputs. Cleared user disable outputs.
POINV HOFF
LCOMP
HMODE
PWMEN
H-bridge mode, HMODE Table determine outputs. Table Output Selection
PWMCOM1 HOFF POINV
PWM1
Outputs PWM2 PWMR3
PWM4
trip interrupt cleared writing value PWMICLR MMR. Note that when using trip interrupt, interrupt should cleared before exiting ISR. This prevents generation multiple interrupts.
CONVERT START CONTROL
configured generate convert start signal after active side signal goes high. There programmable delay between when low-side signal goes high convert start signal generated. This controlled PWMCON2 MMR. delay selected higher than width pulse, interrupt remains low.
high side, side.
power-up, PWMCON1 defaults 0x12 (HOFF HMODE GPIO pins associated with configured mode default (see Table 66). Table Compare Register
Name PWM1COM1 PWM1COM2 PWM1COM3 PWM2COM1 PWM2COM2 PWM2COM3 PWM3COM1 PWM3COM2 PWM3COM3 Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Access
Rev. Page
ADuC7128/ADuC7129
Table PWMCON2 Designations
Value Name CSEN Description user enable generate convert start signal. Cleared user disable convert start signal. Reserved. This should user. Convert Start Delay. Delays convert start signal number clock pulses.
Quadrature Encoder
quadrature encoder used determine both speed direction rotating shaft. most common form, there digital outputs, shaft rotates, both toggle; however, they phase. leading output determines direction rotation. time between each transition indicates speed rotation.
RSVD CSD3 CSD2 CSD1 CSD0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses. clock pulses.
CLOCKWISE
06020-046
COUNTER CLOCKWISE
Figure Quadrate Encoder Input Values
quadrature encoder takes incremental input shown Figure increments decrements counter depending direction speed rotating shaft. ADuC7128/ADuC7129, internal counter clocked rising edge input, input indicates direction rotation/count. counter increments when high decrements when low. addition, software prior knowledge direction rotation, input ignored (S2) other clock (S1). additional flexibility, inputs internally inverted prior use. quadrature encoder operates asynchronously from system clock.
When calculating time from convert start delay start conversion, user needs take account internal delays. example below shows case delay four clocks. additional clock required pass convert start signal logic. Once logic receives convert start signal conversion begins next clock edge (see Figure 50).
UCLOCK
Input Filtering
Filtering applied input setting FILTEN QENCON. normally acts clock counter; however, filter used ignore positive edges unless there been high pulse between positive edges (see Figure 52).
06020-045
SIDE
COUNT SIGNAL CONVST SIGNAL PASSED LOGIC
Figure Conversion
HIGH PULSE
PULSE
Figure Input Filtering
Rev. Page
06020-047
ADuC7128/ADuC7129
Table QENCON Designations
15:11 Name RSVD FILTEN RSVD S2INV Description Reserved. user enable filtering pin. Cleared user disable filtering pin. Reserved. This should user. user invert input. Cleared user input normal. DIRCON set, then S2INV controls direction counter. this case, user operate counter increment mode. Cleared user operate counter decrement mode. user invert input. Cleared user input normal. Direction Control. user enable input counter clock. direction counter controlled S2INV bit. Cleared user operate normal mode. user generate when low-to-high transition detected Cleared user disable interrupt. This should user. Underflow Enable. user generate interrupt QENVAL underflows. Cleared user disable interrupt. Overflow Enable. user generate interrupt QENVAL overflows. Cleared user disable interrupt. This should user. Quadrature Encoder Enable. user enable quadrature encoder. Cleared user disable quadrature encoder.
S1INV DIRCON
S1IRQEN RSVD UIRQEN
OIREQEN
RSVD ENQEN
Table QENSTA Designations
Name RSVD S1EDGE Description Reserved. Rising Edge. This automatically rising edge Cleared reading QENSTA. Reserved. Underflow Flag. This automatically underflow occurs. Cleared reading QENSTA. This automatically overflow occurred. Cleared reading QENSTA. Direction Counter. hardware indicate that counter incrementing. hardware indicate that counter decrementing.
RSVD UNDER
OVER
QENDAT Register
Name QENDAT Address 0xFFFF0F08 Default Value 0Xffff Access
QENVAL Register
Name QENVAL Address 0xFFFF0F0C Default Value 0x0000 Access
QENDAT register holds maximum value allowed QENVAL register. QENVAL register increments past value this register, overflow condition occurs. When overflow occurs, QENVAL register reset 0x0000. When QENVAL register decrements past zero during underflow, loaded with value QENDAT.
QENVAL register contains current value quadrature encoder counter.
Rev. Page
ADuC7128/ADuC7129
QENCLR Register
Name QENCLR Address 0xFFFF0F14 Default Value 0x00000000 Access
GENERAL-PURPOSE
ADuC7128/ADuC7129 provide general-purpose, bidirectional (GPIO) pins. pins tolerant, meaning that GPIOs support input voltage general, many GPIO pins have multiple functions (see Table 70). default, GPIO pins configured GPIO mode. GPIO pins have internal pull-up resistor about their drive capability Note that maximum GPIO drive same time. following GPIOs have programmable pull-up: P0.0, P0.4, P0.5, P0.6, P0.7, eight GPIOs GPIOs grouped five ports: Port Port Each port controlled four five MMRs, with representing port number.
Writing value QENCLR register clears QENVAL register 0x0000. bits this register undefined.
QENSET Register
Name QENSET Address 0xFFFF0F18 Default Value 0x00000000 Access
Writing value QENSET register loads QENVAL register with value QENDAT. bits this register undefined. Note that interrupt conditions OR'ed together form interrupt interrupt controller. interrupt service routine should check QENSTA register find cause interrupt. inputs appear QENS1 QENS2 inputs GPIO list. motor speed measured using capture facility Timer0 Timer1. overflow either timer checked using checking IRQSIG.
GPxCON Register
Name GP0CON GP1CON GP2CON GP3CON GP4CON Address 0xFFFF0D00 0xFFFF0D04 0xFFFF0D08 0xFFFF0D0C 0xFFFF0D10 Default Value 0x00000000 0x00000000 0x00000000 0x11111111 0x00000000 Access
counter with quadrature encoder gray encoded ensure reliable data transfer across clock boundaries. When underflow overflow occur, count value does jump other scale; instead, direction count changes. When this happens, value QENDAT subtracted from value derived from gray count. When value QENDAT changes, value read back from QENVAL changes. However, gray encoded value does change. This only occurs after underflow overflow. value QENDAT changes, there must write QENSET QENCLR ensure valid number read back from QENVAL.
Note that kernel changes P0.6 from default configuration reset (MRST) GPIO mode. MRST used external circuitry, external pull-up resistor should used ensure that level P0.6 does drop when kernel switches mode. Otherwise, P0.6 goes reset period. example, MRST required power-down, reconfigured GP0CON MMR. input level GPIO read time GPxDAT MMR, even when configured mode other than GPIO. input always active. When ADuC7128/ADuC7129 enter power-saving mode, GPIO pins retain their state. GPxCON Port control register, selects function each Port described Table
Rev. Page
ADuC7128/ADuC7129
Table GPIO Function Designations
Port P0.0 P0.11 P0.21 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.11 P2.21 P2.31 P2.41 P2.51 P2.61 P2.71 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.61 P3.71 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7
Table GPxCON Designations
PLAI[7] ADCBUSY PLAO[1] PLAO[2] PLAO[3] PLAO[4] PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6] PLAO[0] PLAO[5] PLAO[6] PLAO[7]
GPIO GPIO GPIO GPIO GPIO/IRQ0 GPIO/IRQ1 GPIO/T1 GPIO GPIO/T1 GPIO GPIO GPIO GPIO/IRQ2 GPIO/IRQ3 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Configuration TRST CONVST ADCBUSY PLM_COMP MRST ECLK/XCLK2 SIN0 SIN0 SCL0 SOUT0 SDA0 RTS0 SCL1 CTS0 SDA1 DCD0 MISO DSR0 MOSI DTR0 SYNC SOUT RTS1 CTS1 DCD1 DSR1 DTR1 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM1 PWM3 QENS1 QENS2 RSVD AD10 AD11 Trip (Shutdown) PLMIN AD12 PLMOUT AD13 SIN1 AD14 SOUT1 AD15
31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10
Description Reserved Select function Px.7 Reserved Select function Px.6 Reserved Select function Px.5 Reserved Select function Px.4 Reserved Select function Px.3 Reserved Select function Px.2 Reserved Select function Px.1 Reserved Select function Px.0
GPxPAR Register
Name GP0PAR GP1PAR GP3PAR GP4PAR Address 0xFFFF0D2C 0xFFFF0D3C 0xFFFF0D5C 0xFFFF0D6C Default Value 0x20000000 0x00000000 0x00222222 0x00000000 Access
PLAI[8] PLAI[9] PLAI[10] PLAI[11] PLAI[12] PLAI[13] PLAI[14] PLAI[15] PLAO[8] PLAO[9] PLAO[10] PLAO[11] PLAO[12] PLAO[13] PLAO[14] PLAO[15]
GPxPAR programs parameters Port Port Port Port Note that GPxDAT must always written after changing GPxPAR MMR. Table GPxPAR Designations
31:29 27:25 23:21 19:17 15:13 11:9 Description Reserved Pull-up disable Px.7 Reserved Pull-up disable Px.6 Reserved Pull-up disable Px.5 Reserved Pull-up disable Px.4 Reserved Pull-up disable Px.3 Reserved Pull-up disable Px.2 Reserved Pull-up disable Px.1 Reserved Pull-up disable Px.0
Available only 80-lead ADuC7129. When configured Mode PO.7 ECLK default, core clock output. configure clock ouput, MDCLK bits PLLCON must
Rev. Page
ADuC7128/ADuC7129
GPxDAT Register
Name GP0DAT GP1DAT GP2DAT GP3DAT GP4DAT Address 0xFFFF0D20 0xFFFF0D30 0xFFFF0D40 0xFFFF0D50 0xFFFF0D60 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access
SERIAL PORT
serial port multiplexes serial port peripherals (two I2Cs, SPI, UARTs) programmable logic array (PLA) GPIO pins. Each must configured specific function described Table Table Configuration
SPM0 SPM1 SPM2 SPM3 SPM4 SPM5 SPM6 SPM7 SPM8 SPM9 SPM10 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access SPM11 SPM12 SPM13 SPM14 SPM15 SPM16 SPM17
GPxDAT Port configuration data register. configures direction GPIO pins Port sets output value pins configured output, receives stores input value pins configured input. Table GPxDAT Designations
31:24 Description Direction Data. user configure GPIO pins outputs. Cleared user configure GPIO pins inputs. Port Data Output. Reflect state Port pins reset (read only). Port Data Input (Read Only). Address 0xFFFF0D24 0xFFFF0D34 0xFFFF0D44 0xFFFF0D54 0xFFFF0D64
GPIO (00) P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.7 P2.0
UART (01) SIN0 SOUT0 RTS0 CTS0 DCD0 DSR0 DTR0 ECLK PWMSYNC RTS1 CTS1 DCD1 DSR1 DTR1 SIN1 SOUT1
UART/I2C/SPI (10) I2C0SCL I2C0SDA I2C1SCL I2C1SDA SPICLK SPIMISO SPIMOSI SPICSL SIN0 SOUT0 AD14 AD15
(11) PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6] PLAO[0] PLAO[4] PLAO[5] PLAO[7]
23:16 15:8 Name GP0SET GP1SET GP2SET GP3SET GP4SET
GPxSET Register
P2.21 P2.31 P2.41 P2.51 P2.61 P2.71 P4.6 P4.7
PLAO[14] PLAO[15]
GPxSET data Port register. Table GPxSET Designations
31:24 23:16 Description Reserved. Data Port Bit. user Port also sets corresponding GPxDAT MMR. Cleared user; does affect data out. Reserved. Address 0xFFFF0D28 0xFFFF0D38 0xFFFF0D48 0xFFFF0D58 0xFFFF0D68 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access
Available only 80-lead ADuC7129.
Table details mode each SPMUX GPIO pins. This configuration performed GP0CON, GP1CON GP2CON MMRs. default these pins configured GPIOs.
15:0 Name GP0CLR GP1CLR GP2CLR GP3CLR GP4CLR
UART SERIAL INTERFACE
ADuC7128/ADuC7129 contain identical UART blocks. Although only UART0 described here, UART1 functions exactly same way. UART peripheral full-duplex universal asynchronous receiver/transmitter, fully compatible with 16450 serial port standard. UART performs serial-to-parallel conversion data characters received from peripheral device modem, parallel-to-serial conversion data characters received from CPU. UART includes fractional divider baud rate generation network-addressable mode. UART function made available pins ADuC7128/ ADuC7129 (see Table 77).
GPxCLR Register
GPxCLR data clear Port register. Table GPxCLR Designations
31:24 23:16 Description Reserved. Data Port Clear Bit. user clear Port also clears corresponding GPxDAT MMR. Cleared user; does affect data out. Reserved.
15:0
Rev. Page
ADuC7128/ADuC7129
Table UART Signal Descriptions
SPM0 (Mode SPM1 (Mode SPM2 (Mode SPM3 (Mode SPM4 (Mode SPM5 (Mode SPM6 (Mode SPM7 (Mode SPM8 (Mode SPM9 (Mode Signal SIN0 SOUT0 RTS0 CTS0 DCD0 DSR0 DTR0 SIN0 SOUT0 Description Serial Receive Data. Serial Transmit Data. Request Send. Clear Send. Ring Indicator. Data Carrier Detect. Data Ready. Data Terminal Ready. Serial Receive Data. Serial Transmit Data.
Calculation baud rate using fractional divider follows:
Baud Rate
41.78 2048
41.78 2048 Baud Rate
example, generation 19,200 bauds with bits Table gives 0x08.
41.78 2048 19200
serial communication adopts asynchronous protocol that supports various word-length, stop-bits, parity generation options selectable configuration register.
1.06 2048
Baud Rate Generation
There ways generating UART baud rate: normal UART baud rate generation using fractional divider.
where: 0.06 2048
Normal UART Baud Rate Generation
baud rate divided version core clock, using value COM0DIV0 COM0DIV1 MMRs (16-bit value, DL).
Baud Rate
41.78 2048
Baud Rate
41.78
Table gives some common baud rate values.
Table Baud Rate Using Normal Baud Rate Generator
Baud Rate 9600 19,200 115,200 9600 19,200 115,200 0x88 0x44 0x0B 0x11 0x08 0x01 Actual Baud Rate 9600 19,200 118,691 9600 20,400 163,200 Error 6.25% 41.67%
where: Baud Rate 19,200 bps. Error compared 6.25% with normal baud rate generator.
UART Register Definitions
UART interface consists registers.
Table UART MMRs
Register Description
Using Fractional Divider
fractional divider combined with normal baud rate generator allows generating wider range more accurate baud rates.
CORE CLOCK FBEN
COMxTX COMxRX COMxDIV0 COMxTX, COMxRX, COMxDIV0
N/2048)
Figure Baud Rate Generation Options
06020-048
/16DL
UART
COMxDIV1 COMxCON0 COMxSTA0 COMxIEN0 COMxIID0 COMxCON1 COMxSTA1 COMxDIV2 COMxSCR
8-Bit Transmit Register. 8-Bit Receive Register. Divisor Latch (Low Byte). Share Same Address Location. COMxTX COMxRX accessed when COMxCON0 register cleared. COMxDIV0 accessed when COMxCON0 set. Divisor Latch (High Byte). Line Control Register. Line Status Register. Interrupt Enable Register. Interrupt Identification Register. Modem Control Register. Modem Status Register. 16-Bit Fractional Baud Divide Register. 8-Bit Scratch Register Used Temporary Storage. Also used network addressable UART mode.
Rev. Page
ADuC7128/ADuC7129
Table COMxCON0 Designations
Value Name DLAB Description Divisor Latch Access. user enable access COMxDIV0 COMxDIV1 registers. Cleared user disable access COMxDIV0 COMxDIV1 enable access COMxRX COMxTX. Break. user force SOUT Cleared operate normal mode. Stick Parity. user force parity defined values. Even Parity Select Bit. even parity. Cleared parity. Parity Enable Bit. user transmit check parity bit. Cleared user parity transmission checking. Stop Bit. user transmit stop bits word length bits stop bits word length bits, bits, bits. receiver checks first stop only, regardless number stop bits selected. Cleared user generate stop transmitted data. Word Length Select. bits. bits. bits. bits.
STOP
Table COMxSTA0 Designations
Name RSVD TEMT Description Reserved. COMxTX Empty Status Bit. automatically COMxTX empty. Cleared automatically when writing COMxTX. COMxTX COMxRX Empty. automatically COMxTX COMxRX empty. Cleared automatically when registers receives data. Break Error. when held more than maximum word length. Cleared automatically. Framing Error. when stop invalid. Cleared automatically. Parity Error. when parity error occurs. Cleared automatically. Overrun Error. automatically data overwritten before read. Cleared automatically. Data Ready. automatically when COMxRX full. Cleared reading COMxRX.
THRE
Rev. Page
ADuC7128/ADuC7129
Table COMxIEN0 Designations
Name RSVD EDSSI Description Reserved. Modem Status Interrupt Enable Bit. user enable generation interrupt COMxSTA1[3:0] set. Cleared user. Status Interrupt Enable Bit. user enable generation interrupt COMxSTA0[3:1] set. Cleared user. Enable Transmit Buffer Empty Interrupt. user enable interrupt when buffer empty during transmission. Cleared user. Enable Receive Buffer Full Interrupt. user enable interrupt when buffer full during reception. Cleared user.
ELSI
ETBEI
ERBFI
Table COMxIID0 Designations
Status Bits NINT Priority Definition Interrupt. Receive Line Status Interrupt. Receive Buffer Full Interrupt. Transmit Buffer Empty Interrupt. Modem Status Interrupt. Clearing Operation Read COMxSTA0. Read COMxRX. Write data COMxTX read COMxIID0. Read COMxSTA1.
Table COMxCON1 Designations
Name RSVD LOOPBACK Description Reserved. Loop Back. user enable loop-back mode. loop-back mode, SOUT forced high. addition, modem signals directly connected status inputs (RTS CTS, DSR, OUT1 OUT2 DCD). Reserved. Reserved. Request Send. user force output Cleared user force output Data Terminal Ready. user force output Cleared user force output
Rev. Page
ADuC7128/ADuC7129
Table COMxSTA1 Designations
Name DDCD Description Data Carrier Detect. Ring Indicator. Data Ready. Clear Send. Delta Data Carrier Detect. automatically changed state since COMxSTA1 last read. Cleared automatically reading COMxSTA1. Trailing Edge Ring Indicator. changed from since COMxSTA1 last read. Cleared automatically reading COMxSTA1. Delta Data Ready. automatically changed state since COMxSTA1 last read. Cleared automatically reading COMxSTA1. Delta Clear Send. automatically changed state since COMxSTA1 last read. Cleared automati

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