CODEC Fully Integrated Encoder Decoder Operating Modes: encoder m

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CODEC Fully Integrated Encoder Decoder Operating Modes: encoder m

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STA027
CODEC
Fully Integrated Encoder Decoder Operating Modes: encoder mode (PCM In/Serial Output) input: 44.1, 48kHz Channel Mode: Mono, Dual, Stereo Subbands: Allocation Methods: Loudness/SNR Decoder Mode Serial Input Output: 44.1, 48kHz Digital Volume Bass Treble Control Serial Bitstream Input/output Interface 2Mbit/s Easy Programmable Input Interface Serial Output Interface (I2S other Formats) Internal Clock Output Clock Generation Control Power 2.4V CMOS Technology with 3.3V Tolerant Capable
TQFP64
Wireless Audio Dongle Wireless Speakers Generic Compressed Audio LinkS Wireless Headphone/Headsets
Description
STA027 fully integrated codec targeting wireless audio transmission such rear channels wireless speakers, dongle, wireless speakers. device fully controllable through standard bus.
Compression Engine
Subband Coding engine used when high quality audio required wireless applications (such Bluetooth). audio coding system specially designed Bluetooth applications obtain high quality audio medium rates, having computational complexity. uses subbands, adaptive allocation algorithm, simple adaptive block quantizers.
Applications
bluetooth Applications Wirless Speaker Options
Order codes
Part number STA027 Package TQFP64 Packing Tube
September 2005
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www.st.com
STA027
Contents
Typical application circuit block diagram
Block diagram Typical bluetooth wireless audio application
Pins description connection diagram
description
Electrical Specification
Absolute maximum ratings Electrical characteristics
Host register
Register
Register description
Version registers description
5.1.1 5.1.2 5.1.3 VERSION IDENT SOFT_VERSION
PLL_AUDIO_CONFIGURATION registers description
5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176
5.2.10 PLL_AUDIO_MDIV_176
PLL_SYSTEM_CONFIGURATION registers description
5.3.1 5.3.2 5.3.3 PLL_SYSTEM_PEL_50 PLL_SYSTEM_PEH_50 PLL_SYSTEM_NDIV_50
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5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 PLL_SYSTEM_XDIV_50 PLL_SYSTEM_MDIV_50 PLL_SYSTEM_PEL_42_5 PLL_SYSTEM_PEH_42_5 PLL_SYSTEM_NDIV_42_5 PLL_SYSTEM_XDIV_42_5
5.3.10 PLL_SYSTEM_MDIV_42_5
I2Sout_CONFIGURATION registers description
5.4.1 5.4.2 5.4.3 5.4.4 OUTPUT_CONF PCM_DIV PCM_CONF PCM_CROSS
GPSO_CONFIGURATION registers description
5.5.1 5.5.2 OUTPUT_CONF GPSO_CONF
I2Sin_CONFIGURATION registers description
5.6.1 5.6.2 5.6.3 5.6.4 INPUT_CONF I_AUDIO_CONFIG_1: I_AUDIO_CONFIG_2 I_AUDIO_CONFIG_3
SDI_CONFIGURATION registers description
5.7.1 5.7.2 5.7.3 POL_REQ INPUT_CONF I_AUDIO_CONFIG_1
COMMAND registers description
5.8.1 5.8.2 5.8.3 5.8.4 5.8.5 5.8.6 5.8.7 5.8.8 SOFT_RESET CK_CMD DEC_SEL CRC_IGNORE MUTE SKIP PAUSE
STATUS registers description
5.9.1 5.9.2 STATUS_MODE STATUS_CHANS_NB
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5.9.3 5.9.4 5.9.5 STATUS_SF STATUS_FE HEADER
5.10
MIX_CONFIGURATION registers description
5.10.1 MIX_MODE: 5.10.2 MIX_DLA: 5.10.3 MIX_DLB: 5.10.4 MIX_DRA: 5.10.5 MIX_DRB:
5.11
TONE_CONFIGURATION registers description
5.11.1 TONE_ON: 5.11.2 TONE_FCUTH 5.11.3 TONE_FCUTL 5.11.4 TONE_GAINH 5.11.5 TONE_GAINL 5.11.6 TONE_GAIN_ATTEN
TABLES
Notations
CELL DESCRIPTION
Tristate Output Buffer, capable 4mA, with Slew Rate Control Schmitt Trigger Bidir Buffer, capable, 4mA, with Slew Rate Control Schmitt Trigger Inpud Buffer, capable Inpud Buffer, capable with Pull-Up Schmitt Trigger Bidir Buffer, with Pull-up, 4mA, with slew rate control capable Input Buffer, capable, with pull down
Package Informations Revision history
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Typical application circuit block diagram
Typical application circuit block diagram
Block diagram
Figure Block diagram
BSO_LRCK BSI_BCK BSI_DATA DREQ BCKI LRCKI MMDSP CORE CODEC BSO_DATA BSO_BCK GPSO_CK GPSO GPSO_SDO GPSO_REQ
INPUT BUFFER
BCKO OUTPUT BUFFER LRCKO
RQST
AUDIO
BANK
SYSTEM
OSCK
D05AU1615
Typical bluetooth wireless audio application
Figure Transmitter block diagram
ENCODER
MODULE
STA027
D05AU1616
Figure
Receiver block diagram
DECODER
MODULE
STA027
D05AU1617
Note:
Bluetooth chipset please refer following device: SLTLC2416, STLC2150, STLC2500. solutions please refer following devices: STW5094, STW5095, TDA7535.
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Pins description connection diagram
STA027
Table
Pins description connection diagram
description
description
Name Type Description Source/Dest
interface interface DREQ BSI_LRCK BSI_BCK BSI_DATA Bitstream data request Bitstream interface left/right Clock Bitstream interface clock Bitstream interface serial data From From From BSO_LRCK BSO_BCK BSO_DATA Interface left/right Clock interface serial data interface clock From From From
interface LRCKI BCKI left/right Clock clock serial data From From From
interface GPSO interface GPSO_SDO GPSO_CK GPSO_REQ GPSO serial data GPSO clock GPSO request signal From OSCK LRCKO BCKO oversampling clock Interface left/right Clock clock serial data DAC/ADC
GPIO interface IODATA0 IODATA1 IODATA2 IODATA3 IODATA4 IODATA5 GPIODATA0 GPIODATA1 GPIODATA2 GPIODATA3 GPIODATA4 GPIODATA5
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Table
Pins description connection diagram
description
Name IODATA6 IODATA7 IODATA8 IODATA9 IODATA10 IODATA11 IODATA12 IODATA13 IODATA14 IODATA15 Type GPIODATA6 GPIODATA7 GPIODATA8 GPIODATA9 GPIODATA10 GPIODATA11 GPIODATA12 GPIODATA13 GPIODATA14 GPIODATA15 Description Source/Dest
HANDSHAKE SIGNALS LINK clock signal data signal From RQST data signal Strobe signal From
MISCELLANEOUS -RESET -TESTEN CLKOUT FILT1 FILT0 Reset Reserved test purpose Oscillator input Oscillator output Buffered output clock external filter external filter
POWER SUPPLY VDD_1 VSS_1 VDD_2 VSS_2 VCC_1 VSS_3 VDD_3 VSS_4 Digital supply (2.5V Power Supply) Ground Digital supply (2.5V Power Supply) Ground Digital supply (3.3V Power Supply) Ground Digital supply (2.5V Power Supply) Ground
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Pins description connection diagram
STA027
Table
description
Name VDD_4 VSS_5 PLL_VCC PLL_GND VCC_2 VSS_6 VSS_7 VDD_5 VSS_8 VCC_3 VSS_9 VDD_6 Type Description Digital supply (2.5V Power Supply) Ground Digital supply (2.5V Power Supply) Ground Digital supply (3.3V Power Supply) Ground Ground Digital supply (2.5V Power Supply) Ground Digital supply (3.3V Power Supply) Ground Digital supply (2.5V Power Supply) Source/Dest
Figure
GPSO_REQ GPSO_SDO IODATA15 IODATA14 IODATA13 GPSO_CK
VCC_3
VDD_6
VDD_5
VSS_8
VSS_9
BSO_LRCK BSO_BCK BSO_DATA DREQ VDD_1 VSS_1 BSI_LRCK BSI_BCK BSI_DATA VDD_2 VSS_2 LRCK1 BCKI RESET TESTEN
VCC_1 VSS_3 CLKOUT IODATA0 IODATA1 IODATA2 VDD_3 VSS_4 IODATA3 IODATA4 LRCKO BCKO OSCK
VSS_7
RQST
IODATA12 IODATA11 IODATA10 IODATA9 IODATA8 VSS_6 VCC_2 PLL_GND FILT0 PLL_VCC FILT1 VSS_5 VDD_4 IODATA7 IODATA6 IODATA5
D00AU1227
Table
Symbol j-amb
Thermal Data
Parameter Thermal resistance Junction Ambient Value Unit °C/W
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Electrical Specification
Electrical Specification
Absolute maximum ratings
Table
Symbol PLL-VCC VIH/VIL Tstg
Absolute Maximum Ratings
Parameter Digital Power Supply 2.5V (nominal) Digital Power Supply 3.3V (nominal) Analog Supply Voltage 2.5V (nominal) Voltage input pins (3.3V pads) Storage Temperature Operative ambient temp Operating Junction Temperature Value -0.5 -0.5 -0.5 -0.5 +0.5 +150 +85(*) Unit
Electrical characteristics
(Tamb 25°C; unless otherwise specified) Table
Symbol Power Supply Voltage Power Supply Voltage
Operating Conditions
Parameter Value 0.25 0.25 Unit
PLL_VCC Power Supply Voltage
Table
Symbol Vesd
General Interface Electrical Characteristics
Parameter Level Input CurrentWithout pullup device Test Condition Min. 2000 Typ. Max. Unit Note
High Level Input CurrentWithout pullVi device Electrostatic Protection Leakage
Note: leakage currents generally very small, 1nA. value given here maximum that occur after electrostatic stress pin. Human Body Model.
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Electrical Specification
STA027
Table
Symbol
electrical characteristics
Parameter Level Input Voltage High Level Input Voltage Level Output Voltage High Level Output Voltage 0.85*VCC 0.8*VCC 0.4V Test Condition Min. Typ. Max. 0.2*VCC Unit Note
Note: Takes into account 200mV voltage drop both supply lines. source/sink current under worst case conditions reflected name cell according drive capability. Table
Symbol Parameter Pull-up current Equivalent Pull-up Resistance Test Condition numbers Min. Typ. Max. -125 Unit Note
Note: Min. condition: 2.7V, 125°C process Max. condition: 3.6V, -20°C Max. Table
Symbol
Power Dissipation
Parameter Power Dissipation@ 2.4V Test Condition Sampling_freq Sampling_freq Sampling_freq Min. Typ. Max. Unit Note
Note:
power measurements refer encoder mode.
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Host register
Host register
following table gives description STA027 register list. STA027 device includes registers. this document, only user-oriented registers described. undocumented registers reserved unused. These registers must never accessed Read Write mode). Read-Only registers must never written split data flux different time periods (see following diagram) meanwhile host registers read written
During Whole Time time during process). During External Config (period between RUN=2 RUN=1). During Boot (period between RUN=0 RUN=2). After BOot (period after RUN=1). After External Config (period after RUN=2). Every Decoded Frame (each time frame been decoded). Every Decoded Block (each time block been decoded).
Figure
SOFT_RESET CK_CMD block1 frame1 block2 frame1 block1 frame2
RUN==0
RUN==2
RUN==1
time
D01AU1260
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Host register
STA027
Table
Register
register function
0x00 VERSION IDENT SOFT_VERSION PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 PLL_SYSTEM_PEL_50 PLL_SYSTEM_PEH_50 PLL_SYSTEM_NDIV_50 PLL_SYSTEM_XDIV_50 PLL_SYSTEM_MDIV_50 PLL_SYSTEM_PEL_42_5 PLL_SYSTEM_PEH_42_5 PLL_SYSTEM_NDIV_42_5 PLL_SYSTEM_XDIV_42_5 PLL_SYSTEM_MDIV_42_5 OUTPUT_CONF PCM_DIV PCM_CONF PCM_CROSS OUTPUT_CONF GPSO_CONF INPUT_CONF I_AUDIO_CONFIG_1 I_AUDIO_CONFIG_2 I_AUDIO_CONFIG_3 Name Type When Register function
VERSION
0x01 0xD3 0xDC 0xDD 0xDE 0xDF 0xE0
PLL_AUDIO_CONFIGURATION 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA PLL_SYSTEM_CONFIGURATION 0xEB 0xEC 0xED 0xEE 0xEF 0x66 I2Sout_CONFIGURATION 0x67 0x68 0x69 0x66 GPSO_CONFIGURATION 0x6A 0x5A I2Sin_CONFIGURATION 0x5B 0x5C 0x5D
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Table register function
0x59 SDI_CONFIGURATION 0x5A 0x5B 0x10 0x3A 0x55 0x56 COMMAND 0x52 0x53 0x57 0x58 0xCC 0xCD 0xCE 0x6F 0xD4 STATUS 0xD5 0xD6 0xD7 0xD8 0xD9 0x7b 0x7c MIX_CONFIGURATION 0x7d 0x7e 0x7f 0x75 0x76 0x77 TONE_CONFIGURATION 0x78 0x79 0x7A TONE_GAINH TONE_GAINL TONE_GAIN_ATTEN HEADER_2 HEADER_3 HEADER_4 HEADER_5 HEADER_6 MIX_MODE MIX_DLA MIX_DLB MIX_DRA MIX_DRB TONE_ON TONE_FCUTH TONE_FCUTL CRC_IGNORE MUTE SKIP PAUSE STATUS_MODE STATUS_CHAN_NB STATUS_SF STATUS_FE HEADER_1 POL_REQ INPUT_CONF I_AUDIO_CONFIG_1 SOFT_RESET CK_CMD DEC_SEL Name
Host register
Register function
Type
When
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Register description
STA027
5.1.1
Register description
Version registers description
VERSION
Address 0x00 Type Software Reset 0x10 Hardware Reset 0x10
Description VERSION register Read-only used identify application board.
5.1.2
IDENT
Address 0x01 Type Software Reset 0xAC Hardware Reset 0xAC
Description IDENT read-only register used identify application board. IDENT always value 0xAC.
5.1.3
SOFT_VERSION
Address 0xD3 (211) Type Software Reset Description SOFT_VERSION register Read-only used identify software running
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Register description
5.2.1
PLL_AUDIO_CONFIGURATION registers description
PLL_AUDIO_PEL_192
Address 0xDC (220) Type Software Reset
Description This register must contain value that enables audio generate frequency ofact*192 PCMCK.See table ofact oversampling factor needed (ofac==246 ofac==384). Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
5.2.2
PLL_AUDIO_PEH_192
Address 0xDD (221) Type Software Reset
Description This register must contain value that enables audio generate frequency ofact*192 PCMCK.See table Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
5.2.3
PLL_AUDIO_NDIV_192
Address 0xDE (222) Type Software Reset
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Register description
STA027
Description This register must contain NDIV value that enables audio generate frequency ofact*192 PCMCK.See table Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
5.2.4
PLL_AUDIO_XDIV_192
Address 0xDF (223) Type Software Reset
Description This register must contain XDIV value that enables audio generate frequency ofact*192 PCMCK.See table Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
5.2.5
PLL_AUDIO_MDIV_192
Address 0xE0 (224) Type Software Reset
Description This register must contain MDIV value that enables audio generate frequency ofact*192 PCMCK.See table Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
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Register description
5.2.6
PLL_AUDIO_PEL_176
Address 0xE1 (225) Type Software Reset
Description This register must contain value that enables audio generate frequency ofact*176 PCMCK.See table Default value soft reset assume fact external crystal provide CRYCK running 14.31818
5.2.7
PLL_AUDIO_PEH_176
Address 0xE2 (226) Type Software Reset
Description This register must contain value that enables audio generate frequency ofact*176 PCMCK.See table Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
5.2.8
PLL_AUDIO_NDIV_176
Address 0xE3 (227) Type Software Reset
Description This register must contain NDIV value that enables audio generate frequency ofact*176 PCMCK.See table
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Register description
STA027
Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
5.2.9
PLL_AUDIO_XDIV_176
Address 0xE4 (228) Type Software Reset
Description This register must contain XDIV value that enables audio generate frequency ofact*176 PCMCK.See table Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
5.2.10 PLL_AUDIO_MDIV_176
Address 0xE5 (229) Type Software Reset
Description This register must contain MDIV value that enables audio generate frequency ofact*176 PCMCK.See table Default value soft reset assume ofact external crystal provide CRYCK running 14.31818
5.3.1
PLL_SYSTEM_CONFIGURATION registers description
PLL_SYSTEM_PEL_50
Address 0xE6 (230)
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Type Software Reset
Register description
Description This register must contain value that enables system generate frequency SYSCK. table Default value soft reset assume external crystal provide CRYCK running 14.31818
5.3.2
PLL_SYSTEM_PEH_50
Address 0xE7 (231) Type Software Reset
Description This register must contain value that enables system generate frequency SYSCK. table Default value soft reset assume external crystal provide CRYCK running 14.31818
5.3.3
PLL_SYSTEM_NDIV_50
Address 0xE8 (232) Type Software Reset
Description This register must contain NDIV value that enables system generate frequency SYSCK. table Default value soft reset assume external crystal provide CRYCK running 14.31818
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Register description
STA027
5.3.4
PLL_SYSTEM_XDIV_50
Address 0xE9 (233) Type Software Reset Description This register must contain XDIV value that enables system generate frequency SYSCK. table Default value soft reset assume external crystal provide CRYCK running 14.31818
5.3.5
PLL_SYSTEM_MDIV_50
Address 0xEA (234) Type Software Reset
Description This register must contain MDIV value that enables system generate frequency SYSCK. table Default value soft reset assume external crystal provide CRYCK running 14.31818
5.3.6
PLL_SYSTEM_PEL_42_5
Address 0xE6 (230) Type Software Reset
Description This register must contain value that enables system generate frequency 42.5 SYSCK.See table Default value soft reset assume external crystal provide CRYCK running 14.31818
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Register description
5.3.7
PLL_SYSTEM_PEH_42_5
Address 0xE7 (231) Type Software Reset
Description This register must contain value that enables system generate frequency 42.5 SYSCK.See table Default value soft reset assume external crystal provide CRYCK running 14.31818
5.3.8
PLL_SYSTEM_NDIV_42_5
Address 0xE8 (232) Type Software Reset
Description This register must contain NDIV value that enables system generate frequency 42.5 SYSCK.See table Default value soft reset assume external crystal provide CRYCK running 14.31818
5.3.9
PLL_SYSTEM_XDIV_42_5
Address 0xE9 (233) Type Software Reset
Description This register must contain XDIV value that enables system generate frequency 42.5 SYSCK.See table Default value soft reset assume external crystal provide CRYCK running 14.31818
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Register description
STA027
5.3.10 PLL_SYSTEM_MDIV_42_5
Address 0xEA (234) Type Software Reset
Description This register must contain MDIV value that enables system generate frequency 42.5 SYSCK.See table Default value soft reset assume external crystal provide CRYCK running 14.31818
5.4.1
I2Sout_CONFIGURATION registers description
OUTPUT_CONF
Address 0x66 (102) Type Software Reset
Description enable configurability PCM-BLOCK Output thanks following registers, else disable this configurability take embedded default configuration PCM-BLOCK registers. Note that this embedded default configuration retrieved user thanks following setting PCM_DIV PCM_CONF PCM_CROSS
5.4.2
PCM_DIV
Address 0x67 (103) Type
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Software Reset
Register description
Description OUTPUT_CONF configure divider generate clock I2Sout interface, called BCK0, from PCMCK. according following relation BCKO PCMCK (PCM_DIV+1)
5.4.3
PCM_CONF
Address 0x68 (104) Type Software Reset
Description OUTPUT_CONF configure I2Sout interface according following table Table
Comment bits mode slots transmitted). bits mode slots transmitted). bits mode slots transmitted). bits mode slots transmitted). Polarity BCKO data sent falling edge stable rising). (data sent rising edge stable falling). format selected other format selected Polarity LRCKO low->right, high->left). low->left, high->right compliant format data last BCKO cycles LRCKO (right aligned data). data first BCKO cycles LRCKO (left aligned data). transmission first. transmission first.
fields
CO[1:0]
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Register description
STA027
5.4.4
PCM_CROSS
Address 0x69 (105) Type Software Reset
Description OUTPUT_CONF CR[1:0] used configure output crossbar according following table Table
Comment Left channel mapped left output. Right channel mapped right output. Left channel duplicated both output channels. Right channel duplicated both output channels. Right left channels toggled.
5.5.1
GPSO_CONFIGURATION registers description
OUTPUT_CONF
Address 0x66 (102) Type Software Reset
Description Table
fields Comment Configuration gpso take embedded default configuration. configure gpso from register GPSO_CONF.
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Table
fields Comment
Register description
block generate clocks (PCMCK, LRCK BCK): use. Configuration block: take embedded default configuration. configure block from PCM_DIV PCM_CONF registers.
Note:
that embedded default configuration GPSO retrieved user thanks following setting GPSO_CONF b00000011; that embedded default configuration block described previous chapter.
Note:
5.5.2
GPSO_CONF
Address 0x6A (106) Type Software Reset
Description OUTPUT_CONF this register configure GPSO interface Table
Comment Polarity GPSO_CK data provided rising edge stable falling edge data provided falling edge stable rising edge Polarity GPSO_REQ data valid when GPSO_REQ high data valid when GPSO_REQ Reserved
fields
CF[7:2]
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Register description
STA027
5.6.1
I2Sin_CONFIGURATION registers description
INPUT_CONF
Address 0x5A (90) Type Software Reset
Description enable configurability I2Sin Input thanks following registers, else disable this configurability take embedded default configuration I2Sin registers. Note that this embedded default configuration retrieved user thanks following setting I_AUDIO_CONFIG_1 b00000110; I_AUDIO_CONFIG_2 b11100000; I_AUDIO_CONFIG_3 b00000001;
5.6.2
I_AUDIO_CONFIG_1:
Address 0x5B (91) Type Software Reset
Description INPUT_CONF this register configure I2Sin interface. Table
fields Comment Relative synchro synchro with first data synchro before first data Data reception configuration first first Polarity clock data provided falling edge stable rising edge. data provided rising edge stable falling edge
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Table
fields Polarity clock LRCK negative positive Comment
Register description
CF[7:5]
Start value LRCK combined with CF3, this enable user determine left/right couple according following table. Reserved
Table
Left/Right couples (data1/data2), (data3/data4),. (data0/data1), (data2/data3),. (data0/data1), (data2/data3),. (data1/data2), (data3/data4),.
5.6.3
I_AUDIO_CONFIG_2
Address 0x5C (92) Type Software Reset
Description I_AUDIO_CONFIG_3 register description.
5.6.4
I_AUDIO_CONFIG_3
Address 0x5D (93) Type Software Reset
Description INPUT_CONF this register used configure phase LRCK I2Sin.
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Register description
STA027
Table
fields Comment Position data within LRCK phase (LSB), value must to[31 SL[9:5] position first data within LRCK phase]. LR[4:0] (MSB), value must position first data within LRCK phase.
Note:
LR[9:5] LR[15:10]
that range value this position [0:31].
Length-1 data. value Reserved
5.7.1
SDI_CONFIGURATION registers description
POL_REQ
Address 0x59 (89) Type Software Reset
Description This register manage polarity data signal DREQ input interface. data requested when data requested when
5.7.2
INPUT_CONF
Address 0x5A (90) Type Software Reset
Description enable configurability input interfaces burst mode thanks following register, else disable this configurability take embedded default configuration. Note that this embedded default configuration retrieved user thanks following setting
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I_AUDIO_CONFIG1 b00000000;// polarity choice
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Register description
5.7.3
I_AUDIO_CONFIG_1
Address 0x5B (91) Type Software Reset
Description INPUT_CONF this register used configure clock Table
Comment Polarity clock BS_BCK data provided falling edge stable rising edge. data provided rising edge stable falling edge.
5.8.1
COMMAND registers description
SOFT_RESET
Address 0x10 (16) Type Software Reset
Description When user write this register, soft reset occurs. core command register interrupt register cleared. decoder goes into idle mode.
5.8.2
CK_CMD
Address 0x3A (58) Type Software Reset Hardware Reset
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Register description
STA027
Description After soft reset, user must write CK_CMD core clock chip. This will begin boot chip, idle state.
5.8.3
DEC_SEL
Address 0x55 (85) Type Software Reset
Description This register select encoder/decoder data flux according mode written following table Table
Bit(7:0) Mode SINE (test mode chip alive) decoder ADC/GPSO encoder SDI/GPSO encoder ADC/SDO encoder
Note:
available modes depends patch code used
5.8.4
Address 0x56 (86) Type Software Reset
Description When software reset occurs, register reset (value (see When boot routines finished, write inside register value this start external configuration period (start When external device wants external configuration period, must write value inside register RUN: this command that starts decoding process (see
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Register description
5.8.5
CRC_IGNORE
Address 0x52 (82) Type Software Reset
Description decoders having abilities (see each decoder configuration), enable check CRC, disable check CRC.
5.8.6
MUTE
Address 0x53 (83) Type Software Reset
Description decoders having MUTE abilities (see each decoder configuration), disable mute decoder, enable mute decoder. Note that during MUTE input stream keeps entering.
5.8.7
SKIP
Address 0x57 (87) Type Software Reset
Description data flux using USSB Input, SKIP n>2, decoder skip (n-1) frames. Note that maximum value n==0 n==1, frames skipped.
5.8.8
PAUSE
Address 0x58 (88)
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Register description
STA027
Type Software Reset
Description decoders having PAUSE abilities (see each decoder configuration), disable pause decoder, enable pause decoder. Note that during PAUSE input stream stopped.
5.9.1
STATUS registers description
STATUS_MODE
Address 0xCC (204) Type Software Reset Description This register give type currently decoded bitstream.
5.9.2
STATUS_CHANS_NB
Address 0xCD (205) Type Software Reset
Description This register gives number channel currently decoded.
5.9.3
STATUS_SF
Address 0xCE (206) Type Software Reset
Description
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Register description
This register gives index sampling frequency stream currently decoded. Note that sampling frequency indexes given table
5.9.4
STATUS_FE
Address 0x6F (111) Type Software Reset
Description This register give status synchronization process according following table. Table
Value Syncrho started Syncword found Syncword search Syncword hard find Level
5.9.5
HEADER
Address 0xD4 (212) 0xD9 (217) Type Software Reset
Description This register give byte header frame currently decoded
5.10
MIX_CONFIGURATION registers description
5.10.1 MIX_MODE:
Address 0x7B (123) Type Software Reset
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Register description
STA027
Description This register selectes mode mix/volume control Table
Value diseable mix/volume control volume control mono stereo (up-mix) stereo mono (down-mix) Mode
5.10.2 MIX_DLA:
Address 0x7C (124) Type Software Reset
Description This register specifies direct left attenuation dB).
5.10.3 MIX_DLB:
Address 0x7D (125) Type Software Reset
Description This register specifies left attenuation rigth channel.
5.10.4 MIX_DRA:
Address 0x7E (126) Type Software Reset
Description This register specifies direct right attenuation dB).
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Register description
5.10.5 MIX_DRB:
Address 0x7F (127) Type Software Reset
Description This register specifies rigth attenuation left channel.
5.11
TONE_CONFIGURATION registers description
5.11.1 TONE_ON:
Address 0x75 (117) Type Software Reset
Description This register enables/diseables (1/0) tone control.
5.11.2 TONE_FCUTH
Address 0x76 (118) Type Software Reset
Description This register specifies high frequency: fcut(in Hz)=(TONE_FCUTH+1)*50.
5.11.3 TONE_FCUTL
Address 0x77 (119) Type Software Reset
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Register description
STA027
Description This register specifies frequency: fcut(in (TONE_FCUTL+1)*10
5.11.4 TONE_GAINH
Address 0x78 (120) Type Software Reset
Description This register specifies gain high frequencies: gain(in Db)=(TONE_GAINH-12)*1.5
5.11.5 TONE_GAINL
Address 0x79 (121) Type Software Reset
Description This register specifies gain high frequencies: gain Db)=(TONE_GAINL-12)*1.5. Value register from
5.11.6 TONE_GAIN_ATTEN
Address 0x7A (122) Type Software Reset
Description This register specifies attenuation global spectrum: gain dB)=TONE_GAIN_ATTEN*1.5. Value register from
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TABLES
TABLES
Table values configure audio ofact==256.
This table give values configure audio according CRYCK that generate PCMCK 256*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK CRYCK 14.31818 CRYCK 14.7456
Table
values configure audio ofact==384
This table give values configure audio according CRYCK that generate PCMCK 384*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK CRYCK 14.31818 CRYCK 14.7456
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TABLES
STA027
Table values configure audio ofact==512.
This table give values configure audio according CRYCK that generate PCMCK 512*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK CRYCK 14.31818 CRYCK 14.7456
Table
values configure system SYSCK.
This table give values configure system according CRYCK that generate SYSCK 50MHz. SYSCK 42.5MHz.
Register PLL_SYSTEM_PEL_50 PLL_SYSTEM_PEH_50 PLL_SYSTEM_NDIV_50 PLL_SYSTEM_XDIV_50 PLL_SYSTEM_MDIV_50 PLL_SYSTEM_PEL_42_5 PLL_SYSTEM_PEH_42_5 PLL_SYSTEM_NDIV_42_5 PLL_SYSTEM_XDIV_42_5 PLL_SYSTEM_MDIV_42_5 CRYCK CRYCK 14.31818 CRYCK 14.7456
Table
index Sampling Frequency
Index Frequency 44.1 88.2
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Table index Sampling Frequency
Index Frequency 22.05 11.025 176.4 illegal frequency
TABLES
Notations
After BOot (see After External Config (see BCK: ClocK BSA: BitStream input interface Audio mode. BSB: BitStream input interface Burst mode. BitStream input interface. BYPASSA decoder BYPASS Audio stream. input interface ClocK. CRYCK: CRYstal ClocK provided chip external crystal. During BOot (see During External Config (see During Whole Time (see Every Decoded Block (see Every Decoded Frame (see LRCK: Left Right ClocK interface. ofact: oversampling factor PCMCK (PCMCK ofact SF). PCMCK: ClocK (can generated audio PLL). Sampling Frequency. SYSCK: SYStem ClocK (clock core, generated system PLL). don't care.
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CELL DESCRIPTION
STA027
CELL DESCRIPTION
Tristate Output Buffer, capable 4mA, with Slew Rate Control
numbers:
D98AU904
INPUT
LOAD 100pF
Schmitt Trigger Bidir Buffer, capable, 4mA, with Slew Rate Control
numbers:
INPUT
CAPACITANCE
OUTPUT
LOAD 100pF
D98AU905
Schmitt Trigger Inpud Buffer, capable
numbers:17,
INPUT
CAPACITANCE
D98AU905
Inpud Buffer, capable with Pull-Up
numbers:15,
INPUT
CAPACITANCE
D98AU907
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Schmitt Trigger Bidir Buffer, with Pull-up, 4mA, with slew rate control capable
numbers:
INPUT
CAPACITANCE
OUTPUT
LOAD 100pF
D00AU1150
Input Buffer, capable, with pull down
numbers:
INPUT
CAPACITANCE
D00AU1222
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Package Informations
STA027
Figure
Package Informations
TQFP64 (10x10x1.4mm) Mechanical Data Package Dimensions
DIM. MIN. 0.45 11.80 9.80 0.05 1.35 0.17 0.09 11.80 9.80 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 12.20 10.20 0.464 0.386 12.20 10.20 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.002 0.053 0.055 MIN. TYP. MAX. 0.063 0.006 0.057 inch
OUTLINE MECHANICAL DATA
0.0066 0.0086 0.0106 0.0035 0.464 0.386 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0177 0.0236 0.0295 0.0393 0.480 0.401 0.480 0.401
(min.), 3.5° (min.), 7°(max.) 0.080 0.0031
TQFP64 1.4mm)
0.08mm Seating Plane
TQFP64
0051434
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Revision history
Revision history
Date 1-sept-2005 Revision Initial release. Changes
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STA027
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2005 STMicroelectronics rights reserved STMicroelectronics group companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States America www.st.com
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CD00066274

CODEC Fully Integrated Encoder Decoder Operating Modes: encoder m

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