high-performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-b
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Blackfin® Embedded Processor
high-performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register instruction model ease programming compiler-friendly support Advanced debug, trace, performance monitoring core with on-chip voltage regulation (ADSP-BF523, ADSP-BF525, ADSP-BF527 only) tolerant with specific tolerant balls 289-ball 208-ball CSP_BGA packages
ADSP-BF522/523/524/525/526/527
One-Time-Programmable (OTP) Memory Memory management unit providing memory protection
PERIPHERALS
high speed on-the-go (OTG) with Integrated IEEE 802.3-compliant 10/100 Ethernet Parallel peripheral interface (PPI), supporting ITU-R video data formats Host port (HOSTDP) dual-channel, full-duplex synchronous serial ports (SPORTs), supporting eight stereo channels peripheral DMAs, mastered Ethernet memory-to-memory DMAs with external request lines Event handler with interrupt inputs Serial peripheral interface (SPI) compatible port UARTs with IrDA® support Two-wire interface (TWI) controller Eight 32-bit timers/counters with support 32-bit up/down counter with rotary support Real-time clock (RTC) watchdog timer 32-bit core timer general-purpose I/Os (GPIOs), with programmable drivers hysteresis NAND flash controller (NFC) Debug/JTAG interface On-chip capable frequency multiplication
MEMORY
132K bytes on-chip memory: bytes instruction SRAM bytes instruction SRAM/cache bytes data SRAM bytes data SRAM/cache bytes scratchpad SRAM External memory controller with glueless support SDRAM asynchronous 8-bit 16-bit memories Flexible booting options from external flash, memory from host devices including SPI, TWI, UART Code Security with LockboxSecure Technology
WATCHDOG TIMER VOLTAGE REGULATOR JTAG TEST EMULATION PERIPHERAL ACCESS SPORT0
INSTRUCTION MEMORY DATA MEMORY EXTERNAL ACCESS EXTERNAL PORT FLASH, SDRAM CONTROL
SPORT1 INTERRUPT CONTROLLER UART1 UART0 CONTROLLER EXTERNAL TIMER7-1 TIMER0 BOOT EMAC HOST PORT PORT PORT PORT
CORE
Blackfin Blackfin logo registered trademarks Analog Devices, Inc.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2007 Analog Devices, Inc. rights reserved.
ADSP-BF522/523/524/525/526/527
TABLE CONTENTS
General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Controllers Host Port Real-Time Clock Watchdog Timer Timers Up/Down Counter Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports High Speed Controller Interface 10/100 Ethernet Ports Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Dynamic Power Management Voltage Regulation Clock Signals Booting Modes Instruction Description Development Tools Designing Emulator-Compatible Processor Board (Target) Package Information Related Documents Signal Descriptions Specifications
Operating Conditions ADSP-BF523/ADSP-BF525/ADSPBF527 Operating Conditions ADSP-BF522/ADSP-BF524/ADSPBF526 Electrical Characteristics Absolute Maximum Ratings Sensitivity Timing Specifications Clock Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port-Master Timing Serial Peripheral Interface (SPI) Port-Slave Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing HOSTDP Timing- Host Read Cycle HOSTDP Timing- Host Write Cycle Timing JTAG Test Emulation Port Timing 10/100 Ethernet Controller Timing Output Drive Currents Power Dissipation Test Conditions Environmental Conditions 289-Ball CSP_BGA Ball assignment 208-Ball CSP_BGA Ball assignment Outline Dimensions Ordering Guide
REVISION HISTORY
12/07-Revision PrD: Numerous small changes throughout document. 4/07-Revision PrC: Added 208-Ball Mini-BGA Pinout 1/07-Revision PrB: Changed signal names Descriptions Rewrote Booting Modes Changed operating instruction rate multiple locations from MHz. 7/06-Revision PrA: Initial Version
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Preliminary Technical Data GENERAL DESCRIPTION
ADSP-BF522/523/524/525/526/527 processors members Blackfin family products, incorporating Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine dual-MAC state-of-the-art signal processing engine, advantages clean, orthogonal RISClike microprocessor instruction set, single-instruction, multiple-data (SIMD) multimedia capabilities into single instruction-set architecture. ADSP-BF522/523/524/525/526/527 processors completely code compatible with other Blackfin processors. processors offer performance MHz. ADSP-BF522/ADSP-BF524/ ADSP-BF526 processors offer performance reduced static power consumption. Differences with respect peripheral combinations shown Table Table Processor Comparison
ADSP-BF522 ADSP-BF524 ADSP-BF526 ADSP-BF523 ADSP-BF525 ADSP-BF527
ADSP-BF522/523/524/525/526/527
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management performance. They produced with power voltage design methodology feature on-chip dynamic power management, which ability vary both voltage frequency operation significantly lower overall power consumption. This capability result substantial reduction power consumption, compared with just varying frequency operation. This allows longer battery life portable appliances.
SYSTEM INTEGRATION
ADSP-BF522/523/524/525/526/527 processors highly integrated system-on-a-chip solutions next generation embedded network connected applications. combining industry-standard interfaces with high performance signal processing core, cost-effective applications developed quickly, without need costly external components. system peripherals include IEEE-compliant 802.3 10/100 Ethernet MAC, high speed controller, controller, NAND flash controller, UART ports, port, serial ports (SPORTs), nine general purpose 32-bit timers (eight with capability), real-time clock, watchdog timer, Host (HOSTDP) interface, parallel peripheral interface (PPI).
Feature Host Ethernet SPORTs UARTs Timers Watchdog Timers Parallel Peripheral Interface GPIOs Instruction SRAM Instruction SRAM/Cache Data SRAM Data SRAM/Cache Scratchpad Boot Maximum Speed Grade Maximum System Clock Speed Package Options Memory (bytes)
289-Ball CSP_BGA 208-Ball CSP_BGA
PROCESSOR PERIPHERALS
ADSP-BF522/523/524/525/526/527 processors contain rich peripherals connected core several high bandwidth buses, providing flexibility system configuration well excellent overall system performance (see block diagram Page ADSP-BF522/523/524/525/526/527 processors contain dedicated network communication modules high speed serial parallel ports, interrupt controller flexible management interrupts from on-chip peripherals external sources, power management control functions tailor performance power characteristics processor system many application scenarios. peripherals, except general-purpose I/O, TWI, real-time clock, timers, supported flexible structure. There also separate memory channels dedicated data transfers between processor's various memory spaces, including external SDRAM asynchronous memory. Multiple on-chip buses running provide enough bandwidth keep processor core running along with activity on-chip external peripherals. ADSP-BF522/523/524/525/526/527 processors include on-chip voltage regulator support processor's dynamic power management capability. voltage regulator provides range core voltage levels when supplied from single 2.25 input. voltage regulator bypassed user's discretion.
integrating rich industry-leading system peripherals memory, Blackfin processors platform choice next-generation applications that require RISC-like programmability, multimedia support, leading-edge signal processing integrated package.
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BLACKFIN PROCESSOR CORE
shown Figure Page Blackfin processor core contains 16-bit multipliers, 40-bit accumulators, 40-bit ALUs, four video ALUs, 40-bit shifter. computation units process 16-, 32-bit data from register file.
ADDRESS ARITHMETIC UNIT
compute register file contains eight 32-bit registers. When performing compute operations 16-bit operand data, register file operates independent 16-bit registers. operands compute operations come from multiported register file instruction constant fields.
MEMORY
DAG1 DAG0
PREG
ASTAT
SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER DECODE ALIGN
LOOP BUFFER
CONTROL UNIT
DATA ARITHMETIC UNIT
Figure Blackfin Processor Core
Each perform 16-bit 16-bit multiply each cycle, accumulating results into 40-bit accumulators. Signed unsigned formats, rounding, saturation supported. ALUs perform traditional arithmetic logical operations 16-bit 32-bit data. addition, many special instructions included accelerate various signal processing tasks. These include operations such field extract population count, modulo multiply, divide primitives, saturation rounding, sign/exponent detection. video instructions include byte alignment packing operations, 16-bit 8-bit adds with clipping, 8-bit average operations, 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided compare/select vector search instructions.
certain instructions, 16-bit operations performed simultaneously register pairs 16-bit high half 16-bit half compute register). second used, quad 16-bit operations possible. 40-bit shifter perform shifts rotates used support normalization, field extract, field deposit instructions. program sequencer controls flow instruction execution, including instruction alignment decoding. program flow control, sequencer supports relative indirect conditional jumps (with static branch prediction), subroutine calls. Hardware provided support zero-overhead looping. architecture fully interlocked, meaning that programmer need manage pipeline when executing instructions with data dependencies. address arithmetic unit provides addresses simultaneous dual fetches from memory. contains multiported register file consisting four sets 32-bit index, modify,
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length, base registers (for circular buffering), eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. addition, multiple memory blocks provided, offering configurable SRAM cache. memory management unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access. architecture provides three modes operation: user mode, supervisor mode, emulation mode. User mode restricted access certain system resources, thus providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin processor instruction been optimized that 16-bit opcodes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin processor assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with C/C++ compiler, resulting fast efficient software implementations.
ADSP-BF522/523/524/525/526/527
0xFFFF FFFF CORE REGISTERS BYTES) 0xFFE0 0000 SYSTEM REGISTERS BYTES) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTES) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM CACHE (16K BYTES) 0xFFA1 0000 0xFFA0 C000 INSTRUCTION BANK SRAM (16K BYTES) 0xFFA0 8000 INSTRUCTION BANK SRAM (32K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM CACHE (16K BYTES) 0xFF90 4000 DATA BANK SRAM (16K BYTES) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK SRAM CACHE (16K BYTES) 0xFF80 4000 DATA BANK SRAM (16K BYTES) 0xFF80 0000 RESERVED 0xEF00 8000 BOOT (32K BYTES) RESERVED 0x2040 0000 ASYNC MEMORY BANK BYTES) 0x2030 0000 ASYNC MEMORY BANK BYTES) 0x2020 0000 ASYNC MEMORY BANK BYTES) 0x2010 0000 ASYNC MEMORY BANK BYTES) 0x2000 0000 RESERVED 0x08 0000 SDRAM MEMORY (16M BYTES 512M BYTES) 0x0000 0000
EXTERNAL MEMORY INTERNAL MEMORY
RESERVED
0xEF00 0000
Figure Internal/External Memory
Internal (On-Chip) Memory
processor three blocks on-chip memory providing high-bandwidth access core. first block instruction memory, consisting bytes SRAM, which bytes configured four-way set-associative cache. This memory accessed full processor speed. second on-chip memory block data memory, consisting banks bytes each. Each memory bank configurable, offering both cache SRAM functionality. This memory block accessed full processor speed. third memory block byte scratchpad SRAM which runs same speed memories, only accessible data SRAM cannot configured cache memory.
MEMORY ARCHITECTURE
Blackfin processor views memory single unified byte address space, using 32-bit addresses. resources, including internal memory, external memory, control registers, occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, low-latency on-chip memory cache SRAM, larger, lower-cost performance off-chip memory systems. Figure on-chip memory system highest-performance memory available Blackfin processor. off-chip memory system, accessed through external interface unit (EBIU), provides expansion with SDRAM, flash memory, SRAM, optionally accessing 516M bytes physical memory. memory controller provides high-bandwidth datamovement capability. perform block transfers code data between internal memory external memory spaces.
External (Off-Chip) Memory
External memory accessed EBIU. This 16-bit interface provides glueless connection bank synchronous DRAM (SDRAM) well four banks asynchronous memory devices including flash, EPROM, ROM, SRAM, memory mapped devices.
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PC133-compliant SDRAM controller programmed interface 512M bytes SDRAM. separate open each SDRAM internal bank SDRAM controller supports internal SDRAM banks, improving overall performance. asynchronous memory controller programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies byte segment regardless size devices used, that these banks only contiguous each fully populated with byte memory.
address, etc. Hence generic parts shipped which then programmed protected developer within this non-volatile memory.
Memory Space
processor does define separate space. resources mapped through flat 32-bit address space. Onchip devices have their control registers mapped into memory-mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, which contains control MMRs core functions, other which contains registers needed setup control on-chip peripherals outside core. MMRs accessible only supervisor mode appear reserved space on-chip peripherals.
NAND Flash Controller (NFC)
ADSP-BF522/523/524/525/526/527 processors provide NAND flash controller (NFC). NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, lower reliability over device lifetimes. Because this, NAND flash often used read-only code storage. this case, code stored NAND flash then transferred faster memory (such SDRAM SRAM) before execution. Another common NAND flash storage multimedia files other large data segments. this case, software file system used manage reading writing NAND flash device. file system selects memory segments storage with goal avoiding blocks equally distributing memory accesses across address locations. Hardware features include: Support page program, page read, block erase NAND flash devices, with accesses aligned page boundaries. Error checking correction (ECC) hardware that facilitates error detection correction. single 8-bit external interface commands, addresses data. Support (single level cell) NAND flash devices unlimited size, with page sizes bytes. Larger page sizes supported software. Capability releasing external interface pins during long accesses. Support internal requests 16-bits 32-bits. engine transfer data between internal memory NAND flash device.
Booting
processor contains small on-chip boot kernel, which configures appropriate peripheral booting. processor configured boot from boot memory space, processor starts executing from on-chip boot ROM. more information, Booting Modes Page
Event Handling
event controller processor handles asynchronous synchronous events processor. processor provides event handling that supports both nesting prioritization. Nesting allows multiple event service routines active simultaneously. Prioritization ensures that servicing higher-priority event takes precedence over servicing lower-priority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset This event resets processor. Nonmaskable Interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shutdown system. Exceptions Events that occur synchronously program flow other words, exception taken before instruction allowed complete). Conditions such data alignment violations undefined instructions cause exceptions. Interrupts Events that occur asynchronously program flow. They caused input signals, timers, other peripherals, well explicit software instruction. Each event type associated register hold return address associated return-from-event instruction. When event triggered, state processor saved supervisor stack. processor event controller consists stages, core event controller (CEC) system interrupt controller (SIC). core event controller works with system interrupt
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One-Time Programmable Memory
processor bits one-time programmable non-volatile memory that programmed developer only time. includes array logic support read access programming. Additionally, pages write protected. enables developers store both public private data on-chip. addition storing public private data applications requiring security, also allows developers store completely user-definable data such customer product
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controller prioritize control system events. Conceptually, interrupts from peripherals enter into SIC, then routed directly into general-purpose interrupts CEC.
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Table Core Event Controller (CEC)
Priority Highest) Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt Entry IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Core Event Controller (CEC)
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest-priority interrupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals processor. Table describes inputs CEC, identifies their names event vector table (EVT), lists their priorities.
System Interrupt Controller (SIC)
system interrupt controller provides mapping routing events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although processor provides default mapping, user alter mappings priorities interrupt events writing appropriate values into interrupt assignment registers (SIC_IARx). Table describes inputs into default mappings into CEC. Table System Interrupt Controller (SIC)
Peripheral Interrupt Event Wakeup Interrupt Error (generic) DMAR0 Block Interrupt DMAR1 Block Interrupt DMAR0 Overflow Error DMAR1 Overflow Error Error Status SPORT0 Status SPORT1 Status Reserved Reserved UART0 Status UART1 Status Channel (PPI/NFC) Channel (SPORT0 Channel (SPORT0 Channel (SPORT1 Channel (SPORT1 Channel (SPI) DMA8 Channel (UART0 DMA9 Channel (UART0 General Purpose Interrupt Reset) IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10
Peripheral Interrupt
Default Core Interrupt Registers IAR0 IMASK0 ISR0 IAR0 IMASK0 ISR0 IAR0 IMASK0 ISR0 IAR0 IMASK0 ISR0 IAR0 IMASK0 ISR0 IAR0 IMASK0 ISR0 IAR0 IMASK0 ISR0 IAR0 IMASK0 ISR0 IAR1 IMASK0 ISR0 IAR1 IMASK0 ISR0 IAR1 IMASK0 ISR0 IAR1 IMASK0 ISR0 IAR1 IMASK0 ISR0 IAR1 IMASK0 ISR0 IAR1 IMASK0 ISR0 IAR1 IMASK0 ISR0 IAR2 IMASK0 ISR0 IAR2 IMASK0 ISR0 IAR2 IMASK0 ISR0 IAR2 IMASK0 ISR0 IAR2 IMASK0 ISR0 IAR2 IMASK0 ISR0 IAR2 IMASK0 ISR0 IAR2 IMASK0 ISR0
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Table System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event DMA10 Channel (UART1 DMA11 Channel (UART1 Memory Interrupt Counter DMA1 Channel (MAC RX/HOSTDP) Port Interrupt DMA2 Channel (MAC TX/NFC) Port Interrupt Timer Timer Timer Timer Timer Timer Timer Timer Port Interrupt Port Interrupt MDMA Stream MDMA Stream Software Watchdog Timer Port Interrupt Port Interrupt Status Status HOSTDP Status Host Read Done USB_EINT Interrupt USB_INT0 Interrupt USB_INT1 Interrupt USB_INT2 Interrupt USB_DMAINT Interrupt General Purpose Interrupt Reset) IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG13 IVG13 IVG13 IVG13 IVG13 IVG7 IVG7 IVG7 IVG7 IVG10 IVG10 IVG10 IVG10 IVG10 Peripheral Interrupt
Default Core Interrupt Registers IAR3 IMASK0 ISR0 IAR3 IMASK0 ISR0 IAR3 IMASK0 ISR0 IAR3 IMASK0 ISR0 IAR3 IMASK0 ISR0 IAR3 IMASK0 ISR0 IAR3 IMASK0 ISR0 IAR3 IMASK0 ISR0 IAR4 IMASK1 ISR1 IAR4 IMASK1 ISR1 IAR4 IMASK1 ISR1 IAR4 IMASK1 ISR1 IAR4 IMASK1 ISR1 IAR4 IMASK1 ISR1 IAR4 IMASK1 ISR1 IAR4 IMASK1 ISR1 IAR5 IMASK1 ISR1 IAR5 IMASK1 ISR1 IAR5 IMASK1 ISR1 IAR5 IMASK1 ISR1 IAR5 IMASK1 ISR1 IAR5 IMASK1 ISR1 IAR5 IMASK1 ISR1 IAR5 IMASK1 ISR1 IAR6 IMASK1 ISR1 IAR6 IMASK1 ISR1 IAR6 IMASK1 ISR1 IAR6 IMASK1 ISR1 IAR6 IMASK1 ISR1 IAR6 IMASK1 ISR1 IAR6 IMASK1 ISR1 IAR6 IMASK1 ISR1
Event Control
processor provides very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each register bits wide. interrupt latch register (ILAT) Indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller, written only when corresponding IMASK cleared. interrupt mask register (IMASK) Controls masking unmasking individual events. When IMASK register, that event unmasked processed when asserted. cleared
IMASK register masks event, preventing processor from servicing event even though event latched ILAT register. This register read written while supervisor mode. (Note that general-purpose interrupts globally enabled disabled with instructions, respectively.) interrupt pending register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode.
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allows further control event processing providing three pairs 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table Page interrupt mask registers (SIC_IMASKx) Control masking unmasking each peripheral interrupt event. When these registers, that peripheral event unmasked processed system when asserted. cleared register masks peripheral event, preventing processor from servicing event. interrupt status registers (SIC_ISRx) multiple peripherals mapped single event, these registers allow software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt, cleared indicates peripheral asserting event. interrupt wakeup enable registers (SIC_IWRx) enabling corresponding these registers, peripheral configured wake processor, should core idled when event generated. more information Dynamic Power Management Page Because multiple interrupt sources single generalpurpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt event already detected this interrupt input. IPEND register contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires core clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point recognizes queues next rising edge event corresponding event input. minimum latency from rising edge transition generalpurpose interrupt IPEND output asserted three core clock cycles; however, latency much higher, depending activity within state processor.
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capability supports arbitrary column sizes elements elements, arbitrary column step sizes ±32K elements. Furthermore, column step size less than step size, allowing implementation interleaved data streams. This feature especially useful video applications where data deinterleaved fly. Examples types supported processor controller include: single, linear buffer that stops upon completion circular, auto-refreshing buffer that interrupts each full fractionally full buffer using linked list descriptors using array descriptors, specifying only base address within common page addition dedicated peripheral channels, there memory channels provided transfers between various memories processor system. This enables transfers blocks data between memories-including external SDRAM, ROM, SRAM, flash memory-with minimal processor intervention. Memory transfers controlled very flexible descriptor-based methodology standard register-based autobuffer mechanism. processor also external controller capability dual external request pins when used conjunction with external interface unit (EBIU). This functionality used when high speed interface required external FIFOs high bandwidth communications peripherals such 2.0. allows control number data transfers memory DMA. number transfers edge programmable. This feature programmed allow memory have increased priority external relative core.
HOST PORT
host port interface allows external host master transfer data device. host device masters transactions Blackfin slave. host port enabled through interface. Once enabled, controlled external host, which then program send/receive data valid internal external memory location. host port interface controller following features. Allows external master configure read/write data transfers read port status. Uses asynchronous memory protocol external interface. 8-/16-bit external data interface host device. Half duplex operation Little-/big-endian data transfer. Acknowledge mode allows flow control host transactions. Interrupt mode guarantees burst FIFO depth host transactions.
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CONTROLLERS
processor multiple, independent channels that support automated data transfers with minimal overhead processor core. transfers occur between processor's internal memories DMA-capable peripherals. Additionally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including SDRAM controller asynchronous memory controller. DMA-capable peripherals include Ethernet MAC, NFC, HOSTDP, USB, SPORTs, port, UARTs, PPI. Each individual DMA-capable peripheral least dedicated channel. processor controller supports both one-dimensional (1-D) two-dimensional (2-D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks.
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REAL-TIME CLOCK
real-time clock (RTC) provides robust digital watch features, including current time, stopwatch, alarm. clocked 32.768 crystal external Blackfin processor. peripheral dedicated power supply pins that remain powered clocked even when rest processor low-power state. provides several programmable interrupt options, including interrupt second, minute, hour, clock ticks, interrupt programmable stopwatch countdown, interrupt programmed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: 60-second counter, 60-minute counter, 24-hour counter, 32,768-day counter. When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms: first alarm time day. second alarm time that day. stopwatch function counts down from programmed value, with one-second resolution. When stopwatch enabled counter underflows, interrupt generated. Like other peripherals, wake processor from sleep mode upon generation wakeup event. Additionally, wakeup event wake processor from deep sleep mode, wake on-chip internal voltage regulator from hibernate operating mode. Connect pins RTXI RTXO with external components shown Figure
RTXI RTXO
expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. configured generate hardware reset, watchdog timer resets both core processor peripherals. After reset, software determine watchdog source hardware reset interrogating status watchdog timer control register. timer clocked system clock (SCLK), maximum frequency fSCLK.
TIMERS
There nine general-purpose programmable timer units processors. Eight timers have external that configured either pulse width modulator (PWM) timer output, input clock timer, mechanism measuring pulse widths periods external events. These timers synchronized external clock input several other associated pins, external clock input PPI_CLK input pin, internal SCLK. timer units used conjunction with UARTs measure width pulses data stream provide software auto-baud detect function respective serial channels. timers generate interrupts processor core providing periodic events synchronization, either system clock count external signals. addition eight general-purpose programmable timers, ninth timer also provided. This extra timer clocked internal processor clock typically used system tick clock generation operating system periodic interrupts.
UP/DOWN COUNTER THUMBWHEEL INTERFACE
32-bit up/down counter provided that sense 2-bit quadrature binary codes typically emitted industrial drives manual thumb wheels. counter also operate general-purpose up/down count modes. Then, count direction either controlled level-sensitive input edge detectors. third input provide flexible zero marker support alternatively used input push-button signal thumb wheels. three pins have programmable debouncing circuit. internal signal forwarded timer unit enables timer measure intervals between count events. Boundary registers enable auto-zero operation simple system warning interrupts when programmable count values exceeded.
SUGGESTED COMPONENTS: IPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 LOAD (SURFACE-MOUNT PACKAGE) NOTE: SPECIFIC CRYSTAL SPECI FIED CONTACT CRYSTAL MANUFACTURER DETAILS. SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE
Figure External Components
WATCHDOG TIMER
processor includes 32-bit timer that used implement software watchdog function. software watchdog improve system availability forcing processor known state through generation hardware reset, nonmaskable interrupt (NMI), general-purpose interrupt, timer
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SERIAL PORTS
processors incorporate dual-channel synchronous serial ports (SPORT0 SPORT1) serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation Each SPORT sets independent transmit receive pins, enabling eight channels stereo audio. Buffered (8-deep) transmit receive ports Each port data register transferring data words from other processor components shift registers shifting data data registers. Clocking Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131,070) (fSCLK/2) Word length Each SPORT supports serial data words from bits length, transferred most-significant-bit first least-significant-bit first. Framing Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulse widths early late frame sync. Companding hardware Each SPORT perform A-law -law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead Each SPORT automatically receive transmit multiple buffers memory data. processor link chain sequences transfers between SPORT memory. Interrupts Each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer, buffers, through DMA. Multichannel capability Each SPORT supports channels 1024-channel window compatible with H.100, H.110, MVIP-90, HMVIP standards.
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port provides full-duplex, synchronous serial interface, which supports both master/slave modes multimaster environments. port's baud rate clock phase/polarities programmable, integrated channel, configurable support transmit receive data streams. SPI's channel only service unidirectional accesses given time. port's clock rate calculated SCLK Clock Rate SPI_BAUD Where 16-bit SPI_BAUD register contains value 65,535. During transfers, port simultaneously transmits receives serially shifting data serial data lines. serial clock line synchronizes shifting sampling data serial data lines.
UART PORTS
processors provide full-duplex universal asynchronous receiver/transmitter (UART) ports, which fully compatible with PC-standard UARTs. Each UART port provides simplified UART interface other peripherals hosts, supporting full-duplex, DMA-supported, asynchronous transfers serial data. UART port includes support five eight data bits, stop bits, none, even, parity. Each UART port supports modes operation: (programmed I/O) processor sends receives data writing reading mapped UART registers. data double-buffered both transmit receive. (direct memory access) controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. UART dedicated channels, transmit receive. These channels have lower default priority than most channels because their relatively service rates. Each UART port's baud rate, serial data format, error code generation status, interrupts programmable: Supporting rates ranging from (fSCLK/1,048,576) (fSCLK/16) bits second. Supporting data formats from seven bits frame. Both transmit receive operations configured generate maskable interrupts processor. UART port's clock rate calculated SCLK UART Clock Rate UART_Divisor Where 16-bit UART_Divisor comes from UART_DLH (most significant bits) UART_DLL (least significant bits) registers.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
processors have SPI-compatible port that enables processor communicate with multiple SPI-compatible devices. interface uses three pins transferring data: data pins (Master Output-Slave Input, MOSI, Master InputSlave Output, MISO) clock (serial clock, SCK). chip select input (SPISS) lets other devices select processor, seven chip select output pins (SPISEL7-1) processor select other devices. select pins reconfigured general-purpose pins. Using these pins,
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conjunction with general-purpose timer functions, autobaud detection supported. capabilities UARTs further extended with support infrared data association (IrDA®) serial infrared physical layer link specification (SIR) protocol.
Data framing encapsulation: generation detection preamble, length padding, FCS. Media access management half-duplex operation): collision contention handling, including control retransmission collision frames back-off timing. Flow control full-duplex operation): generation detection PAUSE frames. Station management: generation MDC/MDIO frames read-write access registers. SCLK operating range down (active sleep operating modes). Internal loopback from Some advanced features are: Buffered crystal output external support single crystal system. Automatic checksum computation header payload fields frames. Independent 32-bit descriptor-driven channels. Frame status delivery memory DMA, including frame completion semaphores, efficient buffer queue management software. support separate descriptors header payload eliminate buffer copy operations. Convenient frame alignment modes support even 32-bit alignment encapsulated packet data memory after 14-byte header. Programmable Ethernet event interrupt supports combination selected frame status conditions. interrupt condition. Wakeup frame detected. selected management counter(s) halffull. descriptor error. management statistics counters with selectable clear-on-read behavior programmable interrupts half maximum value. Programmable address filters, including 64-bin address hash table multicast and/or unicast frames, programmable filter modes broadcast, multicast, unicast, control, damaged frames. Advanced power management supporting unattended transfer frames status to/from external memory during low-power sleep mode. System wakeup from sleep operating mode upon magic packet four user-definable wakeup frame filters. Support 802.3Q tagged VLAN frames.
HIGH SPEED
processors provide high speed controller support direct connection host system 480M bits second data rate. interface provides flexible programmable environment with seven data points control endpoint. Each endpoint support data types packet sizes including control, bulk, interrupt, isochronous. feature supported which allows devices host. When processor operating device, capable bus-powered operations. accomplish this, device must capable operations when core clock system clock running same frequency full speed input MHz). This ensures that processor lowest current until request more current from host. port eight dedicated channels five interrupt completion channels minimize processor polling overhead enable asynchronous requests attention only when transfer management required.
CONTROLLER INTERFACE
processors include wire interface (TWI) module providing simple exchange method control data between multiple devices. compatible with widely used I2C® standard. module offers capabilities simultaneous master slave operation, support both 7-bit addressing multimedia data arbitration. interface utilizes pins transferring clock (SCL) data (SDA) supports protocol speeds 400k bits/sec. interface pins compatible with logic levels. Additionally, module fully compatible with serial camera control (SCCB) functionality easier control various CMOS camera sensor devices.
10/100 ETHERNET
ADSP-BF526/ADSP-BF527 processors offer capability directly connect network embedded Fast Ethernet Media Access Controller (MAC) that supports both 10-BaseT (10M bits/sec) 100-BaseT (100M bits/sec) operation. 10/100 Ethernet peripheral processor fully compliant IEEE 802.3-2002 standard provides programmable features designed minimize supervision, use, message processing rest processor system. Some standard features are: Support RMII protocols external PHYs. Full duplex half duplex modes.
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Programmable clock rate preamble suppression. RMII operation, seven unused pins configured GPIO pins other purposes.
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PARALLEL PERIPHERAL INTERFACE (PPI)
processor provides parallel peripheral interface (PPI) that connect directly parallel converters, ITUR-601/656 video encoders decoders, other general-purpose peripherals. consists dedicated input clock pin, frame synchronization pins, data pins. ITU-R-656 modes, receives parses data stream 8-bit 10-bit data elements. On-chip decode embedded preamble control synchronization information supported. Three distinct ITU-R-656 modes supported: Active video only mode does read data between Active Video (EAV) Start Active Video (SAV) preamble symbols, data present during vertical blanking intervals. this mode, control byte sequences stored memory; they filtered PPI. Vertical blanking only mode only transfers vertical blanking interval (VBI) data, well horizontal blanking information control byte sequences lines. Entire field mode entire incoming bitstream read through PPI. This includes active video, control preamble sequences, ancillary data that embedded horizontal vertical blanking intervals. Though explicitly supported, ITU-R-656 output functionality achieved setting entire frame structure (including active video, blanking, control information) memory streaming data frame sync-less mode. processor's features facilitate this transfer allowing static frame buffer (blanking control codes) placed memory once, simply updating active video information per-frame basis. general-purpose modes intended suit wide variety data capture transmission applications. modes divided into four main categories, each allowing bits data transfer PPI_CLK cycle: Data receive with internally generated frame syncs Data receive with externally generated frame syncs Data transmit with internally generated frame syncs Data transmit with externally generated frame syncs These modes support ADC/DAC connections, well video communication with hardware signalling. Many modes support more than level frame synchronization. desired, programmable delay inserted between assertion frame sync reception/transmission data.
PORTS
Because rich peripherals, processor groups many peripheral signals four ports-Port Port Port Port Most associated pins shared multiple signals. ports function multiplexer controls. Slew rate drive strength output drivers well hysteresis inputs programmable.
General-Purpose (GPIO)
processor bidirectional, general-purpose (GPIO) pins allocated across three separate GPIO modules-PORTFIO, PORTGIO, PORTHIO, associated with Port Port Port respectively. Port does provide GPIO functionality. Each GPIO-capable shares functionality with other processor peripherals multiplexing scheme; however, GPIO functionality default state device upon power-up. Neither GPIO output input drivers active default. Each general-purpose port individually controlled manipulation port control, status, interrupt registers: GPIO direction control register Specifies direction each individual GPIO input output. GPIO control status registers processor employs "write modify" mechanism that allows combination individual GPIO pins modified single instruction, without affecting level other GPIO pins. Four control registers provided. register written order values, register written order clear values, register written order toggle values, register written order specify value. Reading GPIO status register allows software interrogate sense pins. GPIO interrupt mask registers GPIO interrupt mask registers allow each individual GPIO function interrupt processor. Similar GPIO control registers that used clear individual values, GPIO interrupt mask register sets bits enable interrupt function, other GPIO interrupt mask register clears bits disable interrupt function. GPIO pins defined inputs configured generate hardware interrupts, while output pins triggered software interrupts. GPIO interrupt sensitivity registers GPIO interrupt sensitivity registers specify whether individual pins level- edge-sensitive specify-if edge-sensitive- whether just rising edge both rising falling edges signal significant. register selects type sensitivity, register selects which edges significant edge-sensitivity.
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CODE SECURITY WITH LOCKBOX SECURE TECHNOLOGY
security system consisting blend hardware software provides customers with flexible rich code security features with Lockbox secure technology. features include: memory Unique chip Code authentication Secure mode operation security scheme based upon concept authentication digital signatures using standards-based algorithms provides secure processing environment which execute code protect assets.
Table Power Settings (Continued)
Mode/State Bypassed Sleep Enabled Deep Sleep Disabled Hibernate Disabled Core Clock (CCLK) Disabled Disabled Disabled System Clock (SCLK) Enabled Disabled Disabled Core Power
Sleep Operating Mode-High Dynamic Power Savings
sleep mode reduces dynamic power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typically external event activity wakes processor. When sleep mode, asserting wakeup causes processor sense value BYPASS control register (PLL_CTL). BYPASS disabled, processor transitions full mode. BYPASS enabled, processor transitions active mode. System access memory supported sleep mode.
DYNAMIC POWER MANAGEMENT
processor provides four operating modes, each with different performance/power profile. addition, dynamic power management provides control functions dynamically alter processor core supply voltage, further reducing power dissipation. When configured volt core supply voltage, processor enters hibernate state. Control clocking each processor peripherals also reduces power consumption. Table summary power settings each mode.
Deep Sleep Operating Mode-Maximum Dynamic Power Savings
deep sleep mode maximizes dynamic power savings disabling clocks processor core (CCLK) synchronous peripherals (SCLK). Asynchronous peripherals, such RTC, still running cannot access internal resources external memory. This powered-down mode only exited assertion reset interrupt (RESET) asynchronous interrupt generated RTC. When deep sleep mode, asynchronous interrupt causes processor transition Active mode. Assertion RESET while deep sleep mode causes processor transition full mode.
Full-On Operating Mode-Maximum Performance
full-on mode, enabled bypassed, providing capability maximum operational frequency. This power-up default execution state which maximum performance achieved. processor core enabled peripherals full speed.
Active Operating Mode-Moderate Dynamic Power Savings
active mode, enabled bypassed. Because bypassed, processor's core clock (CCLK) system clock (SCLK) input clock (CLKIN) frequency. this mode, CLKIN CCLK multiplier ratio changed, although changes realized until full-on mode entered. access available appropriately configured memories. active mode, possible disable through control register (PLL_CTL). disabled, must re-enabled before transitioning full-on sleep modes. Table Power Settings
Core Clock Mode/State Bypassed (CCLK) Full Enabled Enabled Active Enabled/ Enabled Disabled System Clock (SCLK) Enabled Enabled Core Power
Hibernate State-Maximum Static Power Savings
hibernate state maximizes static power savings disabling voltage clocks processor core (CCLK) synchronous peripherals (SCLK). internal voltage regulator processor shut writing b#00 FREQ bits VR_CTL register. This disables both CCLK SCLK. Furthermore, sets internal power supply voltage (VDDINT) provide lowest static power dissipation. critical information stored internally (memory contents, register contents, etc.) must written non-volatile storage device prior removing power processor state preserved. Since VDDEXT still supplied this mode, external pins three-state, unless otherwise specified. This allows other devices that connected processor still have power applied without drawing unwanted current. Ethernet modules wake internal supply regulator. PG15 does connect PHYINT signal external device, pulled other device wake processor regulator also
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woken real-time clock wakeup event asserting RESET pin. hibernate wakeup events initiate hardware reset sequence. Individual sources enabled VR_CTL register. EXT_WAKE signal provided indicate occurrence wakeup events. With exception VR_CTL registers, internal registers memories lose their content hibernate state. State variables held external SRAM SDRAM. SCKELOW VR_CTL register controls whether SDRAM operates self-refresh mode, which allows retain content while processor hibernate through subsequent reset sequence.
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fCCLKRED reduced core clock frequency VDDINTNOM nominal internal supply voltage VDDINTRED reduced internal supply voltage TNOM duration running fCCLKNOM TRED duration running fCCLKRED
VOLTAGE REGULATION
processor provides on-chip voltage regulator that generate processor core voltage levels from external supply. Figure shows typical external components required complete power management system. regulator controls internal logic voltage levels programmable with voltage regulator control register (VR_CTL) increments reduce standby power consumption, internal voltage regulator programmed remove power processor core while keeping power supplied. While hibernate state, VDDEXT still applied, eliminating need external buffers. voltage regulator activated from this power down state either through wakeup, wakeup, ethernet wakeup, asserting RESET other peripheral wakeup events, each which then initiates boot sequence. regulator also disabled bypassed user's discretion. voltage regulator modes VRSEL pin-the normal pulse width control external external supply mode which signal power down during hibernate external regulator. VRSEL VDDEXT external regulator VRSEL internal regulator. external mode VROUT becomes EXT_WAKE. internal regulator used, another EXT_WAKE control other power sources system during hibernate operating mode. Both signals high-true power-up connected directly low-true shut down input many common regulators. (Soft Start/Power Good indication) feature ADSP-BF522/523/524/525/526/527 processors. mode this changes from according state VRSEL pin. When using internal regulator SS/PG Soft Start when using external
Power Savings
shown Table processor supports different power domains, which maximizes flexibility while maintaining compliance with industry standards conventions. isolating internal logic processor into power domain, separate from other I/O, processor take advantage dynamic power management without affecting other devices. There sequencing requirements various power domains. Table Power Domains
Power Domain internal logic, except RTC, Memory, USB, internal logic crystal Memory logic logic logic other Range VDDINT VDDRTC VDDMEM VDDUSB VDDOTP VDDEXT
dynamic power management feature processor allows both processor's input voltage (VDDINT) clock frequency (fCCLK) dynamically controlled. power dissipated processor largely function clock frequency square operating voltage. example, reducing clock frequency results reduction dynamic power dissipation, while reducing voltage reduces dynamic power dissipation more than 40%. Further, these power savings additive, that clock frequency supply voltage both reduced, power savings dramatic, shown following equations. Power Savings Factor CCLKRED DDINTRED CCLKNOM DDINTNOM Power Savings Power Savings Factor 100% where variables equations are: fCCLKNOM nominal core clock frequency
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regulator Power Good. complete description Soft Start Power Good functionality refer ADSP-BF52x Blackfin Processor Hardware Reference.
DECOUPLING CAPACITORS
CLKOUT
specified crystal manufacturer. user should verify customized values based careful investigations multiple devices over temperature range.
BLACKFIN
2.25V 3.6V INPUT VOLTAGE RANGE
VDDEXT (LOW-INDUCTANCE)
CIRCUITRY
100F
VDDEXT
CLKBUF
100nF 100F FDS9431A
VDDINT
CLKIN XTAL OVERTONE OPERATION ONLY:
100F ZHCS1000
SS/PG
VROUT SHORT LOWINDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH FDS9431A. VRSEL
NOTE: VALUES MARKED WITH MUST CUSTOMIZED DEPENDING CRYSTAL LAYOUT. PLEASE ANALYZE CAREFULLY.
Figure External Crystal Connections Figure Voltage Regulator Circuit
CLOCK SIGNALS
processor clocked external crystal, sine wave input, buffered, shaped clock derived from external clock oscillator. external clock used, should compatible signal must halted, changed, operated below specified frequency during normal operation. This signal connected processor's CLKIN pin. When external clock used, XTAL must left unconnected. Alternatively, because processor includes on-chip oscillator circuit, external crystal used. fundamental frequency operation, circuit shown Figure parallel-resonant, fundamental frequency, microprocessor-grade crystal connected across CLKIN XTAL pins. onchip resistance between CLKIN XTAL range. Further parallel resistors typically recommended. capacitors series resistor shown Figure fine tune phase amplitude sine frequency. capacitor resistor values shown Figure typical values only. capacitor values dependent upon crystal manufacturers' load capacitance recommendations physical layout. resistor value depends drive level
third-overtone crystal used frequencies above MHz. circuit then modified ensure crystal operation only third overtone, adding tuned inductor circuit shown Figure design procedure third-overtone operation discussed detail application note (EE-168) Using Third Overtone Crystals with ADSP-218x Analog Devices website (www.analog.com)-use site search "EE-168." CLKBUF output pin, which buffered version input clock. This particularly useful Ethernet applications limit number required clock sources system. this type application, single crystal applied directly processor. output CLKBUF then connected external Ethernet RMII device. CLKBUF output active default disabled using VR_CTL register power savings. Blackfin core runs different clock rate than on-chip peripherals. shown Figure core clock (CCLK) system peripheral clock (SCLK) derived from input clock (CLKIN) signal. on-chip capable multiplying CLKIN signal programmable multiplication factor (bounded specified minimum maximum frequencies). default multiplier modified software instruction sequence. On-the-fly frequency changes effected simply writing PLL_DIV register. maximum allowed CCLK SCLK rates depend applied voltages VDDINT VDDEXT, always permitted frequency specified part's speed grade. CLKOUT reflects SCLK frequency off-chip world. belongs SDRAM
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interface, functions reference signal other timing specifications well. While active default, disabled using EBIU_SDGCTL EBIU_AMGCTL registers.
"FINE" ADJUSTMENT REQUIRES SEQUENCING "COARSE" ADJUSTMENT ON-THE-FLY
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maximum CCLK frequency only depends part's speed grade (see Page 70), also depends applied VDDINT voltage. Table details. maximal system clock rate (SCLK) depends chip package applied VDDEXT voltage (see Table Page 30).
BOOTING MODES
processor several mechanisms (listed Table automatically loading internal external memory after reset. boot mode defined four BMODE input pins dedicated this purpose. There categories boot modes. master boot modes processor actively loads data from parallel serial memories. slave boot modes processor receives data from external host devices. boot modes listed Table provide number mechanisms automatically loading processor's internal external memories after reset. default, boot modes slowest meaningful configuration settings. Default settings altered initialization code feature boot time proper programming pre-boot time. BMODE pins reset configuration register, sampled during poweron resets software-initiated resets, implement modes shown Table Table Booting Modes
BMODE3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Idle boot Boot from 16-bit external flash memory Boot from 16-bit asynchronous FIFO Boot from serial memory (EEPROM flash) Boot from host device Boot from serial memory (EEPROM/flash) Boot from host Boot from UART0 Host Boot from UART1 Host Reserved Boot from SDRAM Boot from memory Reserved Reserved Boot from 16-Bit Host Boot from 8-Bit Host
CLKIN
CCLK
SCLK
SCLK CCLK SCLK
Figure Frequency Modification Methods
on-chip peripherals clocked system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output (VCO) system clock. SCLK divider values through Table illustrates typical system clock ratios. Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value changed dynamically without lock latencies writing appropriate values divisor register (PLL_DIV). Table Example System Clock Ratios
Example Frequency Ratios (MHz) SCLK
Signal Name SSEL3-0 0001 0110 1010
Divider Ratio VCO/SCLK 10:1
core clock (CCLK) frequency also dynamically changed means CSEL1-0 bits PLL_DIV register. Supported CCLK divider ratios shown Table This programmable core clock capability useful fast core frequency modifications. Table Core Clock Ratios
Example Frequency Ratios Divider Ratio (MHz) VCO/CCLK CCLK
Signal Name CSEL1-0
Idle/no boot mode (BMODE 0x0) this mode, processor goes into idle. idle boot mode helps recover from illegal operating modes, such when user misconfigured memory. Boot from 8-bit 16-bit external flash memory (BMODE 0x1) this mode, boot kernel loads first block header from address 0x2000 0000 and-depending instructions containing header-the boot kernel performs 8-bit 16-bit boot starts program execution address provided header. default,
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configuration settings slowest device possible (3-cycle hold time, 15-cycle access times, 4-cycle setup). ARDY enabled default, enabled programming. Similarly, interface behavior timings customized programming. This includes activation burst-mode page-mode operation. this mode, signals belonging asynchronous interface enabled port muxing level. Boot from 16-bit asynchronous FIFO (BMODE 0x2) this mode, boot kernel starts booting from address 0x2030 0000. Every 16-bit word that boot kernel read from FIFO must requested placing pulse DMAR1 pin. Boot from serial memory, EEPROM flash (BMODE 0x3) 8-bit, 16-bit, 24-bit 32-bit addressable devices supported. processor uses GPIO select single EEPROM/flash device, submits read command successive address bytes (0x00) until valid 16-, 24-, 32-bit addressable device detected. Pull-up resistors required SSEL MISO pins. default, value 0x85 written SPI_BAUD register. Boot from host device (BMODE 0x4) processor operates slave mode configured receive bytes file from host (master) agent. host, HWAIT signal must interrogated host before every transmitted byte. pull-up resistor required SPISS input. pull-down serial clock improve signal quality booting robustness. Boot from serial memory, EEPROM/flash (BMODE 0x5) processor operates master mode selects slave connected with unique 0xA0. processor submits successive read commands memory device starting internal address 0x0000 begins clocking data into processor. memory device should comply with Philips I2C® Specification version should able auto-increment internal address counter such that contents memory device read sequentially. default, PRESCALE value TWI_CLKDIV value 0x0811 used. Unless altered settings, memory that takes address bytes assumed. development tools ensure that data booted memories that cannot accessed Blackfin core written intermediate storage location then copied final destination memory DMA. Boot from host (BMODE 0x6) host selects slave with unique 0x5F. processor replies with acknowledgement host then downloads boot stream. host agent should comply with Philips Specification version 2.1. multiplexer used select processor time when booting multiple processors from single TWI.
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Boot from UART0 host Port (BMODE 0x7) Using autobaud handshake sequence, boot-stream formatted program downloaded host. host selects rate within UART clocking capabilities. When performing autobaud, UART expects (0x40) character (eight bits data, start bit, stop bit, parity bit) determine rate. UART then replies with acknowledgement composed bytes (0xBF-the value UART0_DLL 0x00-the value UART0_DLH). host then download boot stream. hold host Blackfin processor signals host with boot host wait (HWAIT) signal. Therefore, host must monitor HWAIT before every transmitted byte. Boot from UART1 host Port (BMODE 0x8). Same BMODE except that other UART port used. Boot from SDRAM (BMODE 0xA) This warm boot scenario, where boot kernel starts booting from address 0x0000 0010. SDRAM expected contain valid boot stream SDRAM controller must configured settings. Boot from memory (BMODE 0xB) This provides stand-alone booting method. boot stream loaded from on-chip memory. default boot stream expected start from page 0x40 occupy public memory page 0xDF. This 2560 bytes. Since start page programmable maximum size boot stream extended 3072 bytes. Boot from 16-Bit Host (BMODE 0xE) this mode, host port configured 16-bit Acknowledge mode, little endian. Unlike other modes, here host responsible interpreting boot stream. writes data block data block into Host port. Before configuring settings each block, host either poll ALLOW_CONFIG HOST_STATUS wait interrupted HWAIT signal. When using HWAIT, host must still check ALLOW_CONFIG least once before beginning configure Host Port. After completing configuration host required poll READY HOST_STATUS before beginning transfer data. When host sends HIRQ control command, boot kernel issues CALL instruction 0xFFA0 0000 address. host's responsibility ensure valid code been placed this address. routine 0xFFA0 0000 simple initialization routine configure internal resources, such SDRAM controller, then returns using instruction. routine also final application which will never return boot kernel. Boot from 8-Bit Host (BMODE 0xF) this mode, Host port configured 8-bit interrupt mode, little endian. Unlike other modes, here host responsible interpreting boot stream. writes data block data block into Host port. Before configuring settings each block, host either poll ALLOW_CONFIG HOST_STATUS
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wait interrupted HWAIT signal. When using HWAIT, host must still check ALLOW_CONFIG least once before beginning configure Host Port. host will receive interrupt from HOST_ACK signal every time allowed send next FIFO depth (Sixteen 32-bit words) information. When host sends HIRQ control command, boot kernel issues CALL instruction address 0xFFA0 0000. host's responsibility ensure valid code been place this address. routine 0xFFA0 0000 simple initialization routine configure internal resources, such SDRAM controller, then returns using instruction. routine also final application which will never return boot kernel. each boot modes, 16-byte header first read from external memory device. header specifies number bytes transferred memory destination address. Multiple memory blocks loaded boot sequence. Once blocks loaded, program execution commences from address stored EVT1 register. Prior booting, pre-boot routine interrogates memory. Individual boot modes customized even disabled based programming. External hardware, especially booting hosts watch HWAIT signal determine when pre-boot finished boot kernel starts boot process. programming memory, user instruct preboot routine also customize: Voltage Regulator; SDRAM Controller; Asynchronous Interface. boot kernel differentiates between regular hardware reset wakeup-from-hibernate event speed booting later case. Bits system reset configuration (SYSCR) register used bypass pre-boot routine and/or boot kernel case software reset. They also used simulate wakeup-from-hibernate boot software reset case. boot process further customized "initialization code." This piece code that loaded executed prior regular application boot. Typically, this used configure SDRAM controller speed booting managing PLL, clock frequencies, wait states, serial rates. boot also features C-callable function entries that called user application time. This enables second-stage boot boot management schemes implemented with ease.
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(O/S kernel, device drivers, debuggers, ISRs) modes operation, allowing multiple levels access core processor resources. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/MCU features optimized both 8-bit 16-bit operations. multi-issue load/store modified-Harvard architecture, which supports 16-bit four 8-bit load/store pointer updates cycle. registers, I/O, memory mapped into unified byte memory space, providing simplified programming model. Microcontroller features, such arbitrary bit-field manipulation, insertion, extraction; integer operations 16-, 32-bit data-types; separate user supervisor stack pointers. Code density enhancements, which include intermixing 16-bit 32-bit instructions mode switching, code segregation). Frequently used instructions encoded bits.
DEVELOPMENT TOOLS
processor supported with complete CROSSCORE® software hardware development tools, including Analog Devices emulators VisualDSP++® development environment. same emulator hardware that supports other Blackfin processors also fully emulates ADSP-BF522/523/524/525/526/527 processors.
EZ-KIT Lite® Evaluation Board
evaluation processors, ADSP-BF527 EZ-KIT Lite board available from Analog Devices. Order part number ADZS-BF527EZLITE. board comes with on-chip emulation capabilities equipped enable software development. Multiple daughter cards available. ADSP-BF526 EZ-KIT Lite board under development.
DESIGNING EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)
Analog Devices family emulators tools that every system developer needs order test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG processor. emulator uses access internal features processor, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. processor must halted send data commands, once operation been completed emulator, processor system running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator.
INSTRUCTION DESCRIPTION
Blackfin processor family assembly language instruction employs algebraic syntax designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow programmer many processor core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor
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details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, (EE-68) Analog Devices JTAG Emulation Technical Reference Analog Devices website (www.analog.com)- site search "EE-68." This document updated regularly keep pace with improvements emulator support.
PACKAGE INFORMATION
information presented Figure Table provides details about package branding ADSPBF522/523/524/525/526/527 processors. complete listing product availability, Ordering Guide Page
ADSP-BF525 tppZccc vvvvvv.x yyww country_of_origin
Figure Product Information Package
Table Package Brand Information
Brand ADSP-BF522 ADSP-BF523 ADSP-BF524 ADSP-BF525 ADSP-BF526 ADSP-BF527 vvvvvv.x yyww Field Description Product Name
Temperature Range Package Type Lead Free Option Ordering Guide Assembly Code Silicon Revision Date Code
RELATED DOCUMENTS
following publications that describe ADSPBF522/523/524/525/526/527 processors (and related processors) ordered from Analog Devices sales office accessed electronically website: Getting Started With Blackfin Processors ADSP-BF52x Blackfin Processor Hardware Reference ADSP-BF53x/BF56x Blackfin Processor Programming Reference Blackfin Processor Anomaly List Blackfin Processor Anomaly List
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Preliminary Technical Data SIGNAL DESCRIPTIONS
ADSP-BF522/523/524/525/526/527 processor signal definitions listed Table order maintain maximum function reduce package size ball count, some balls have dual, multiplexed functions. cases where ball function reconfigurable, default state shown plain text, while alternate function shown italics. pins three-stated during immediately after reset, except memory interface, asynchronous memory control, synchronous memory control pins, which driven high. Table Signal Descriptions
Signal Name EBIU ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 AMS3-0 ARDY SRAS SCAS SCKE CLKOUT SA10 OTG2 USB_DP USB_DM USB_XTALIN USB_XTALOUT USB_ID USB_VREF USB_RSET Data Data Type Function
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unused pins have their input buffers disabled with exception pins that need pull-ups pull-downs noted table footnotes. (serial data) (serial clock) balls open drain therefore require pullup resistor. Consult version specification proper resistor value.
Driver Type1
Address Data Byte Enables/Data Mask Bank Select Hardware Ready Control Output Enable Read Enable Write Enable SDRAM Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM Clock Enable SDRAM Clock Output SDRAM Signal SDRAM Bank Select
Crystal Input (This ball should always pulled when used.) Crystal Output mode resistance set. Preliminary designs should connect USB_RSET unpopulated resistor pad. other terminal unpopulated resistor should connect GND.
voltage reference. Connect capacitor between USB_VREF GND.
USB_VBUS
VBUS
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Table Signal Descriptions (Continued)
Signal Name Port GPIO Multiplexed Peripherals PF0/PPI D0/DR0PRI /ND_D0A PF1/PPI D1/RFS0/ND_D1A PF2/PPI D2/RSCLK0/ND_D2A PF3/PPI D3/DT0PRI/ND_D3A PF4/PPI D4/TFS0/ND_D4A/TACLK0 PF5/PPI D5/TSCLK0/ND_D5A/TACLK1 PF6/PPI D6/DT0SEC/ND_D6A/TACI0 PF7/PPI D7/DR0SEC/ND_D7A/TACI1 PF8/PPI D8/DR1PRI PF9/PPI D9/RSCLK1/SPISEL6 PF10/PPI D10/RFS1/SPISEL7 PF11/PPI D11/TFS1/CZM PF12/PPI D12/DT1PRI/SPISEL2/CDG PF13/PPI D13/TSCLK1/SPISEL3/CUD PF14/PPI D14/DT1SEC/UART1TX PF15/PPI D15/DR1SEC/UART1RX/TACI3 Port GPIO Multiplexed Peripherals PG0/HWAIT Type Function
Driver Type1
GPIO/PPI Data 0/SPORT0 Primary Receive Data /NAND Alternate Data GPIO/PPI Data 1/SPORT0 Receive Frame Sync /NAND Alternate Data GPIO/PPI Data 2/SPORT0 Receive Serial Clock /NAND Alternate Data 2/Alternate Capture Input GPIO/PPI Data 3/SPORT0 Transmit Primary Data /NAND Alternate Data GPIO/PPI Data 4/SPORT0 Transmit Frame Sync /NAND Alternate Data 4/Alternate Timer Clock GPIO/PPI Data 5/SPORT0 Transmit Serial Clock /NAND Alternate Data 5/Alternate Timer Clock GPIO/PPI Data 6/SPORT0 Transmit Secondary Data /NAND Alternate Data 6/Alternate Capture Input GPIO/PPI Data 7/SPORT0 Receive Secondary Data /NAND Alternate Data 7/Alternate Capture Input GPIO/PPI Data 8/SPORT1 Primary Receive Data GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter Down Gate
GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Direction GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit GPIO/PPI Data 15/SPORT1 Receive Secondary Data /UART1 Receive /Alternate Capture Input
GPIO/Boot Host Wait (Boot host wait GPIO signal toggled boot kernel. mandatory external pull-up/pull-down resistor defines signal polarity.) GPIO/SPI Slave Select Input/SPI Slave Select GPIO/SPI Clock GPIO/SPI Master Slave Out/Sport Alternate Receive Data Secondary GPIO/SPI Master Slave In/Sport Alternate Transmit Data Secondary GPIO/Timer1/PPI Frame Sync2 GPIO/SPORT0 Alternate Primary Transmit Data Timer2 Frame Sync3 GPIO/Timer3/Sport Alternate Receive Data Primary/UART0 Transmit GPIO/Timer 4/Sport Alternate Receive Clock/Frame Sync /UART0 Receive/Alternate Capture Input GPIO/Timer5/Sport Alternate Receive Clock /Alternate Capture Input GPIO/Timer /Sport Alternate Transmit /Alternate Capture Input GPIO/Timer7/Host Write Enable
PG1/SPISS/SPISEL1 PG2/SCK PG3/MISO/DR0SECA PG4/MOSI/DT0SECA PG5/TMR1/PPIFS2 PG6/DT0PRIA/TMR2/PPIFS3 PG7/TMR3/DR0PRIA/UART0TX PG8/TMR4/RFS0A/UART0RX/TACI4 PG9/TMR5/RSCLK0A/TACI5 PG10/TMR6/TSCLK0A/TACI6 PG11/TMR7/HOST_WR
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Table Signal Descriptions (Continued)
Signal Name PG12/DMAR1/UART1TXA/HOST_ACK PG14/TSCLK0A1/MDC/HOST_RD Type Function
ADSP-BF522/523/524/525/526/527
Driver Type1
GPIO/DMA Request 1/Alternate UART1 Transmit/Host Acknowledge GPIO/DMA Request 0/Alternate UART1 Receive/Host Address/Alternate Capture Input GPIO/SPORT0 Alternate Transmit/Ethernet Management Channel Clock /Host Read Enable
PG153/TFS0A/MII PHYINT/RMII MDINT/HOST_CE Port GPIO Multiplexed Peripherals PH1/ND_D1/ERxER/HOST_D1 PH2/ND_D2/MDIO/HOST_D2 PH3/ND_D3/ETxEN/HOST_D3 PH5/ND_D5/ETxD0/HOST_D5 PH6/ND_D6/ERxD0/HOST_D6 PH7/ND_D7/ETxD1/HOST_D7 PH10/ND_CE/ERxD2/HOST_D10/ PH11/ND_WE/ETxD3/HOST_D11/ PH12/ND_RE/ERxD3/HOST_D12/ PH13/ND_BUSY/ERxCLK/HOST_D13/ PH14/ND_CLE/ERxDV/HOST_D14/
GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII Interrupt/RMII Management Channel Data Interrupt/Host Chip Enable GPIO/NAND D0/Ethernet RMII Carrier Sense/Host GPIO/NAND D1/Ethernet RMII Receive Error/Host GPIO/NAND D2/Ethernet Management Channel Serial Data/Host GPIO/NAND D3/Ethernet Transmit Enable/Host GPIO/NAND D4/Ethernet RMII Reference Clock/Host GPIO/NAND D5/Ethernet RMII Transmit D0/Host GPIO/NAND D6/Ethernet Receive D0/Host GPIO/NAND D7/Ethernet Transmit D1/Host
GPIO/Alternate Capture Input 2/Ethernet RMII Receive D1/Host /SPI Slave Select GPIO/SPI Slave Select 5/Ethernet Transmit D2/Host /Alternate Timer Clock GPIO/NAND Chip Enable/Ethernet Receive D2/Host GPIO/NAND Write Enable/Ethernet Transmit D3/Host GPIO/NAND Read Enable/Ethernet Data Receive D3/Host GPIO/NAND Busy/Ethernet Receive Clock/Host GPIO/NAND Command Latch Enable/Ethernet RMII Receive Data Valid/Host GPIO/NAND Address Latch Enable/Ethernet Collision/Host Data
PH15/ND_ALE/COL/HOST_D15/ Port Multiplexed Peripherals PJ0: PPIFS1/TMR0 PJ1: PPICLK/TMRCLK PJ2: PJ3: Real Time Clock RTXI RTXO
Frame Sync1/Timer0 Clock/Timer Clock
Serial Clock Serial Data Crystal Input (This ball should always pulled when used.) Crystal Output
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ADSP-BF522/523/524/525/526/527
Table Signal Descriptions (Continued)
Signal Name JTAG Port TRST Clock CLKIN XTAL CLKBUF Mode Controls RESET BMODE3-0 Voltage Regulator VROUT VRSEL SS/PG EXT_WAKE Power Supplies VDDEXT VDDINT VDDRTC VDDUSB VDDMEM VDDOTP VPPOTP
Driver Type1
Type Function JTAG Clock JTAG Serial Data JTAG Serial Data JTAG Mode Select JTAG Reset (This ball should pulled JTAG port used.) Emulation Output Clock/Crystal Input Crystal Output Buffered XTAL Output Reset Nonmaskable Interrupt (This ball should always pulled HIGH when used.) Boot Mode Strap External Drive External/Internal Voltage Regulator Select Soft Start/Power Good Wake Indication Power Supply Internal Power Supply (regulated from 2.25 Real Time Clock Power Supply Power Supply Power Supply Power Supply Programming Voltage Ground Supplies
Output Drive Currents Page more information about each driver type. When using peripheral terminating these balls ADSP-BF522/ADSP-BF523, following guide should used: USB_DP GND, USB_DM GND, USB_XTALIN GND, USB_XTALOUT Connect), USB_ID GND, USB_VREF USB_RSET USB_VBUS GND, VDDUSB VDDEXT When driven low, PG15 ball used wake processor from hibernate state, either normal GPIO mode Ethernet mode PHYINT#. ball used wake enable feature with PHYWE VR_CTL register, pull-up ball with resistor.
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Preliminary Technical Data SPECIFICATIONS
Specifications subject change without notice.
ADSP-BF522/523/524/525/526/527
OPERATING CONDITIONS
Parameter VDDINT Internal Supply Voltage1 VDDEXT External Supply Voltage3 VDDRTC5 Real Time Clock Power Supply Voltage VDDMEM6 Supply Voltage2 VDDOTP Supply Voltage2 VPPOTP Programming Voltage2 VDDUSB Supply Voltage2 High Level Input Voltage7, VIHCLKIN High Level Input Voltage9 VIH5V High Level Input Voltage10 Level Input Voltage7, Level Input Voltage10 VIL5V Junction Temperature Junction Temperature
Conditions
VDDEXT maximum VDDEXT maximum VDDEXT maximum VDDEXT minimum VDDEXT minimum 289-Ball CSP_BGA TAMBIENT +70°C 208-Ball CSP_BGA TAMBIENT +70°C
1.75 2.25 1.75 2.25 2.25 VBUS11 -0.3 -0.3
Nominal
1.26 1.84, 1.8, 2.75 2.75 +0.6 +0.8 +105 +105
Unit
voltage regulator generate VDDINT levels with tbd% +tbd% tolerance. Must remain powered (even associated function used). VDDEXT supply voltage regulator GPIO. voltage regulator being used, VROUT ball should tied supplies. does apply voltage regulator. used, power with VDDEXT. Balls that VDDMEM DATA15-0, ADDR19-1, ABE1-0, ARE, AWE, AOE, AMS3-0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls tolerant voltages higher than VDDMEM. Bidirectional balls (PF15-0, PG15-0, PH15-0) input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, BMODE3-0) ADSP-BF522/523/524/525/526/527 tolerant (always accept maximum VIH). Voltage compliance outputs, VOH) limited VDDEXT supply voltage. Parameter value applies input bidirectional balls except CLKIN, SDA, SCL. Parameter value applies CLKIN ball only. Balls tolerant (always accept maximum VIH). Voltage compliance outputs (VOH) limited VDDEXT supply voltage. pulled VBUS. Parameter value applies input bidirectional balls except SCL.
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ADSP-BF522/523/524/525/526/527
OPERATING CONDITIONS
Parameter VDDINT Internal Supply Voltage1 VDDEXT2 External Supply Voltage3 VDDRTC5 Real Time Clock Power Supply Voltage VDDMEM6 Supply Voltage2 VDDOTP Supply Voltage2 VPPOTP Programming Voltage Reads2 Writes7 VDDUSB Supply Voltage2 High Level Input Voltage8, VIHCLKIN High Level Input Voltage10 VIH5V High Level Input Voltage11 Level Input Voltage7, VIL5V Level Input Voltage10 Junction Temperature Junction Temperature
Conditions
1.75 2.25 1.75 2.25
Nominal Unit 1.84, 1.8, 2.75 2.75 +0.6 +0.8 +105 +105
VDDEXT maximum VDDEXT maximum VDDEXT maximum VDDEXT minimum VDDEXT minimum 289-Ball CSP_BGA TAMBIENT +70°C 208-Ball CSP_BGA TAMBIENT +70°C
2.25 VBUS12 -0.3 -0.3
voltage regulator generate VDDINT levels with tbd% +tbd% tolerance. Must remain powered (even associated function used). VDDEXT supply voltage regulator GPIO. voltage regulator being used, VROUT ball should tied supplies. does apply voltage regulator. used, power with VDDEXT. Balls that VDDMEM DATA15-0, ADDR19-1, ABE1-0, ARE, AWE, AOE, AMS3-0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls tolerant voltages higher than VDDMEM. VDDOTP voltage writes must only applied when programming memory. There finite amount cumulative time that this voltage applied (dependent voltage junction temperature) over lifetime part. Please Table Page details. Bidirectional balls (PF15-0, PG15-0, PH15-0) input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, BMODE3-0) ADSPBF522/523/524/525/526/527 tolerant (always accept maximum VIH). Voltage compliance outputs (VOH) limited VDDEXT supply voltage. Parameter value applies input bidirectional balls except CLKIN, SDA, SCL. Parameter value applies CLKIN ball only. Balls tolerant (always accept maximum VIH). Voltage compliance outputs, VOH) limited VDDEXT supply voltage. pulled VBUS. Parameter value applies input bidirectional balls except SCL.
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ELECTRICAL CHARACTERISTICS
Parameter High Level Output Voltage (All Outputs I/Os Except Port Port Port High Level Output Voltage (Port Port Port -Low Drive Strength High Level Output Voltage (Port Port Port -High Drive Strength
ADSP-BF522/523/524/525/526/527
Test Conditions VDDEXT 10%, VDDEXT 10%, VDDEXT 10%, VDDEXT 10%, VDDEXT 10%, VDDEXT 10%, VDDEXT 10%, VDDEXT 10%,
Typical
Unit
High Level Output Current VDDEXT (Maximum Combined Port F7-0) High Level Output Current (Maximum Total Port Port Port Balls) Level Output Voltage (All Outputs I/Os Except Port Port Port Level Output Voltage (Port F7-0) Level Output Voltage (Port F15-8, Port Port VDDEXT
VDDEXT 10%, VDDEXT 10%, VDDEXT 10%, VDDEXT 10%,
IIHP IOZH IOZH5V IOZL IDDHIBERNATE IDDRTC8
Level Output Current (Maximum Combined Port F7-0) High Level Input Current1 Level Input Current
VDDEXT =3.6 VDDEXT =3.6 VDDEXT VDDEXT VDDEXT =3.0 VDDEXT MHz, TAMBIENT 25°C,
High Level Input Current JTAG Three-State Leakage Current3 Three-State Leakage Current Three-State Leakage Current Input Capacitance
Power Dissipation Hibernate Mode nominal Power Dissipation Hibernate Mode nominal
Applies input balls. Applies JTAG input balls (TCK, TDI, TMS, TRST). Applies three-statable balls. Applies bidirectional balls SDA. Applies signal balls. Guaranteed, tested. Measured VDDEXT 3.65 with voltage regulator (VDDINT Measured VDDRTC 25°C.
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ADSP-BF522/523/524/525/526/527
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed table cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Parameter Internal Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage
Table Maximum Duty Cycle Input Transient Voltage1
Maximum Duty Cycle
Rating +tbd -0.3 +3.8 -0.5 +3.6 -0.5 +5.5 -0.5 +5.25 -0.5 VDDEXT +0.5 -65°C +150°C +110°C
Applies signal balls with exception CLKIN, XTAL, VROUT.
Input Voltage1, Input Voltage1, Output Voltage Swing Load Capacitance Storage Temperature Range Junction Temperature Underbias
Applies 100% transient duty cycle. other duty cycles Table Applies only when VDDEXT within specifications. When VDDEXT outside specifications, range VDDEXT Volts. Applies balls SDA. Applies balls USB_DP, USB_DM, USB_VBUS. proper SDRAM controller operation, maximum load capacitance ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, SMS.
When programming memory ADSP-BF522/ADSPBF524/ADSP-BF526 processor VPPOTP ball must write value specified Operating Conditions ADSPBF522/ADSP-BF524/ADSP-BF526 Page There finite amount cumulative time that write voltage applied (dependent voltage junction temperature) VPPOTP over lifetime part. Therefore, maximum memory programming time ADSP-BF522/ADSPBF524/ADSP-BF526 shown Table ADSPBF523/ADSP-BF525/ADSP-BF527 processor does have similar restriction. Table Maximum Memory Programming Time
Temperature VPPOTP Voltage 25°C 2400 1000 85°C 110°C 125°C
SENSITIVITY
(electrostatic discharge) sensitive device. Charged devices circuit boards discharge without detection. Although this product features patented proprietary circuitry, damage occur devices subjected high energy ESD. Therefore, proper precautions should taken avoid performance degradation loss functionality.
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TIMING SPECIFICATIONS
Table describes timing requirements ADSP-BF522/523/524/525/526/527 processor clocks. Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock system clock. Table describes phase-locked loop operating conditions.
ADSP-BF522/523/524/525/526/527
Table Core Clock (CCLK) Speed Grade1,
Parameter fCCLK fCCLK fCCLK
Minimum Core Clock Frequency (VDDINT =1.2 nominal) Core Clock Frequency (VDDINT =1.15 nominal) Core Clock Frequency (VDDINT nominal)
Maximum
Unit
speed grade given part printed chip's package shown Figure Page also seen Ordering Guide Page stands maximum allowed CCLK frequency VDDINT maximum allowed frequency supply voltage. Values VDDINT this table have range
Table Core Clock (CCLK) Speed Grade1,
Parameter fCCLK fCCLK
Minimum Core Clock Frequency (VDDINT =1.15 nominal) Core Clock Frequency (VDDINT nominal)
Maximum
Unit
speed grade given part printed chip's package shown Figure Page also seen Ordering Guide Page stands maximum allowed CCLK frequency VDDINT maximum allowed frequency supply voltage. Values VDDINT this table have range
Table Core Clock (CCLK) Speed Grade1,
Parameter fCCLK fCCLK fCCLK fCCLK fCCLK
Minimum Core Clock Frequency (VDDINT =tbd nominal) Core Clock Frequency (VDDINT =tbd nominal) Core Clock Frequency (VDDINT nominal) Core Clock Frequency (VDDINT nominal) Core Clock Frequency (VDDINT nominal)
Maximum
Unit
speed grade given part printed chip's package shown Figure Page also seen Ordering Guide Page stands maximum allowed CCLK frequency VDDINT maximum allowed frequency supply voltage. Values VDDINT this table have range
Table Core Clock (CCLK) Speed Grade1,
Parameter fCCLK fCCLK fCCLK fCCLK fCCLK
Minimum Core Clock Frequency (VDDINT =tbd nominal) Core Clock Frequency (VDDINT =tbd nominal) Core Clock Frequency (VDDINT nominal) Core Clock Frequency (VDDINT nominal) Core Clock Frequency (VDDINT nominal)
Maximum
Unit
speed grade given part printed chip's package shown Figure Page also seen Ordering Guide Page stands maximum allowed CCLK frequency VDDINT maximum allowed frequency supply voltage. Values VDDINT this table have range
Table Phase-Locked Loop Operating Conditions
Parameter fVCO
Voltage Controlled Oscillator (VCO) Frequency
Minimum
Maximum Unit Speed Grade1
speed grade given part printed chip's package shown Figure Page also seen Ordering Guide Page stands maximum allowed CCLK frequency VDDINT maximum allowed frequency supply voltage.
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ADSP-BF522/523/524/525/526/527
Table Maximum SCLK Conditions
Parameter1, fSCLK CLKOUT/SCLK Frequency (VDDINT fSCLK CLKOUT/SCLK Frequency (VDDINT
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Unit
tSCLK 1/fSCLK) must greater than equal tCCLK. fSCLK subject additional restrictions SDRAM interface operation. Table Page
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Clock Reset Timing
Table Figure describe clock reset operations. Absolute Maximum Ratings Page combinations CLKIN clock multipliers must select core/peripheral clocks excess MHz/133 MHz. Table Clock Reset Timing
Parameter Timing Requirements tCKIN CLKIN Period1 tCKINL CLKIN Pulse2 CLKIN High Pulse2 tCKINH tBUFDLAY CLKIN CLKBUF Delay tWRST RESET Asserted Pulse Width Low3
ADSP-BF522/523/524/525/526/527
Minimum 25.0 10.0 10.0 tCKIN
Maximum 100.0
Unit
Combinations CLKIN frequency clock multiplier must exceed allowed fVCO, fCCLK, fSCLK settings discussed Table through Table Since default multiplying CLKIN frequency ADSP-BF522/523/524/525/526/527 full CLKIN period range. Applies bypass mode non-bypass mode. Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than 2000 CLKIN cycles, while RESET asserted, assuming stable power supplies CLKIN (not including start-up time external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH tBUFDLAY tBUFDLAY
CLKBUF
tWRST
RESET
Figure Clock Reset Timing
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Asynchronous Memory Read Cycle Timing
Table Asynchronous Memory Read Cycle Timing
Parameter Timing Requirements tSDAT DATA15-0 Setup Before CLKOUT tHDAT DATA15-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics Output Delay After CLKOUT1 Output Hold After CLKOUT
Minimum
Maximum
Unit
Output balls include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
SETUP CYCLES
PROGRAMMED READ ACCESS CYCLES
ACCESS EXTENDED CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ABE, ADDRESS
tSARDY
ARDY
tHARDY
tHARDY
tSARDY
tSDAT tHDAT
DATA15-0
READ
Figure Asynchronous Memory Read Cycle Timing
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Asynchronous Memory Write Cycle Timing
Table Asynchronous Memory Write Cycle Timing
Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA15-0 Disable After CLKOUT tENDAT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT1 Output Hold After CLKOUT
ADSP-BF522/523/524/525/526/527
Minimum
Maximum
Unit
Output balls include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
SETUP CYCLES
PROGRAMMED WRITE ACCESS CYCLES
ACCESS EXTENDED CYCLE
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ABE, ADDRESS
SARDY
ARDY
HARDY
tSARDY ENDAT
DATA15-0 WRITE DATA
DDAT
Figure Asynchronous Memory Write Cycle Timing
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ADSP-BF522/523/524/525/526/527
SDRAM Interface Timing
Table SDRAM Interface Timing (VDDINT VDDINT
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit 12.5
Parameter Timing Requirements tSSDAT Data Setup Before CLKOUT tHSDAT Data Hold After CLKOUT Switching Characteristics tSCLK CLKOUT Period1 tSCLKH CLKOUT Width High tSCLKL CLKOUT Width tDCAD Command, Address, Data Delay After CLKOUT2 tHCAD Command, Address, Data Hold After CLKOUT2 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT
tSCLK value inverse fSCLK specification discussed Table Package type reduced supply voltages affect best-case values listed here. Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
CLKOUT
tSCLKH
tSSDAT tHSDAT
DATA (IN)
tSCLKL
tDCAD tENSDAT
DATA (OUT)
tDSDAT tHCAD
tDCAD
COMMAND, ADDRESS (OUT)
tHCAD
NOTE: COMMAND SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure SDRAM Interface Timing
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External Request Timing
Table Figure describe External Request operations. Table External Request Timing
ADSP-BF522/523/524/525/526/527
Parameter Timing Parameters DMARx Asserted CLKOUT High Setup CLKOUT High DMARx Deasserted Hold Time tDMARACT DMARx Active Pulse Width tDMARINACT DMARx Inactive Pulse Width
Minimum tSCLK 1.75 tSCLK
Maximum
Unit
CLKOUT
DMAR0/1 (Active Low)
tDMARINACT
tDMARACT
DMAR0/1 (Active High)
tDMARACT
tDMARINACT
Figure External Request Timing
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Parallel Peripheral Interface Timing
Table Figure Page Figure Page Figure Page describe parallel peripheral interface operations. Table Parallel Peripheral Interface Timing
Parameter Timing Requirements tPCLKW PPI_CLK Width1 tPCLK PPI_CLK Period1 Timing Requirements Input Frame Capture Modes tSFSPE External Frame Sync Setup Before PPI_CLK (Nonsampling Edge Sampling Edge tHFSPE External Frame Sync Hold After PPI_CLK tSDRPE Receive Data Setup Before PPI_CLK tHDRPE Receive Data Hold After PPI_CLK Switching Characteristics Output Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK tDDTPE Transmit Data Delay After PPI_CLK tHDTPE Transmit Data Hold After PPI_CLK
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit 15.0 16.0
PPI_CLK frequency cannot exceed fSCLK/2
DATA0 SAMPLED PPI_CLK POLC PPI_CLK POLC
FRAME SYNC SAMPLED DATA0
DATA1 SAMPLED
tSFSPE POLS PPI_FS1 POLS
HFSPE
POLS PPI_FS2 POLS
SDRPE
HDRPE
PPI_DATA
Figure Mode with External Frame Sync Timing
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ADSP-BF522/523/524/525/526/527
FRAME SYNC SAMPLED PPI_CLK POLC PPI_CLK POLC tHFSPE tSFSPE POLS PPI_FS1 POLS
DATA0 DRIVEN
POLS PPI_FS2 POLS
HDTPE
PPI_DATA
DATA0
Figure Mode with External Frame Sync Timing
FRAME SYNC DRIVEN POLC PPI_CLK
DATA0 SAMPLED
PPI_CLK POLC tDFSPE tHOFSPE POLS PPI_FS1 POLS
POLS PPI_FS2 POLS tSDRPE tHDRPE
PPI_DATA
Figure Mode with Internal Frame Sync Timing
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FRAME SYNC DRIVEN
DATA0 DRIVEN
PPI_CLK POLC PPI_CLK POLC tHOFSPE POLS PPI_FS1 POLS
DFSPE
POLS PPI_FS2 POLS
DDTPE
HDTPE
PPI_DATA
DATA0
Figure Mode with Internal Frame Sync Timing
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Serial Ports
Table through Table Page Figure Page through Figure Page describe serial port operations. Table Serial Ports-External Clock
ADSP-BF522/523/524/525/526/527
Parameter Timing Requirements tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1 tSDRE Receive Data Setup Before RSCLKx1 tHDRE Receive Data Hold After RSCLKx1 tSCLKEW TSCLKx/RSCLKx Width tSCLKE TSCLKx/RSCLKx Period Switching Characteristics tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1 tDDTE Transmit Data Delay After TSCLKx1 tHDTE Transmit Data Hold After TSCLKx1
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit 15.0 10.0 10.0 12.0 12.0
Referenced sample edge. Referenced drive edge.
Table Serial Ports-Internal Clock
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit -1.5 -1.5 15.0 -1.0 -1.0 -1.8 -4.0 11.3 -1.5 11.3 -1.5 18.0
Parameter Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1 tSDRI Receive Data Setup Before RSCLKx1 tHDRI Receive Data Hold After RSCLKx1 tSCLKEW TSCLKx/RSCLKx Width tSCLKE TSCLKx/RSCLKx Period Switching Characteristics tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1 tDDTI Transmit Data Delay After TSCLKx1 tHDTI Transmit Data Hold After TSCLKx1 tSCLKIW TSCLKx/RSCLKx Width
Referenced sample edge. Referenced drive edge.
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Table Serial Ports-Enable Three-State
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit 10.0 -2.0 -2.0 10.0
Parameter Switching Characteristics tDTENE Data Enable Delay from External TSCLKx1 tDDTT Data Disable Delay from External TSCLKx1
tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1
Referenced drive edge.
Table External Late Frame Sync
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit 10.0 10.0
Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFSx External RFSx with tDTENLFSE Data Enable from Late
TFSx enable TFSx valid follow tDDTENFS tDDTLFSE. external RFSx/TFSx setup RSCLKx/TSCLKx tSCLKE/2 then tDDTTE/I tDTENE/I apply, otherwise tDDTLFSE tDTENLFS apply.
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DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
ADSP-BF522/523/524/525/526/527
DATA RECEIVE-EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
RSCLKx RSCLKx
tSCLKEW
tDFSI tHOFSI
RFSx
tDFSE tSFSI tHFSI
RFSx
tHOFSE
tSFSE
tHFSE
tSDRI
tHDRI
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE. DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT-EXTERNAL CLOCK DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKIW
TSCLKx TSCLKx
tSCLKEW
tDFSI tHOFSI
TFSx
tDFSE tSFSI tHFSI
TFSx
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
tDDTE tHDTE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE.
Figure Serial Ports
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ADSP-BF522/523/524/525/526/527
EXTERNAL RFSx WITH DRIVE RSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
RFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
LATE EXTERNAL TFSx DRIVE TSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
TFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
Figure External Late Frame Sync
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Serial Peripheral Interface (SPI) Port-Master Timing
Table Figure describe port master operations.
ADSP-BF522/523/524/525/526/527
Table Serial Peripheral Interface (SPI) Port-Master Timing
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 -1.0 11.6 -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 -1.0
Parameter Timing Requirements tSSPIDM Data Input Valid Edge (Data Input Setup) tHSPIDM Sampling Edge Data Input Invalid Switching Characteristics tSDSCIM SPISELx First Edge tSPICHM Serial Clock High Period tSPICLM Serial Clock Period tSPICLK Serial Clock Period tHDSM Last Edge SPISELx High tSPITDM Sequential Transfer Delay tDDSPIDM Edge Data Valid (Data Delay) tHDSPIDM Edge Data Invalid (Data Hold)
SPISELx (OUTPUT)
tSDSCIM
(CPOL (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
(CPOL (OUTPUT)
tSPICHM
tDDSPIDM
MOSI (OUTPUT) CPHA=1 MISO (INPUT)
tHDSPIDM
tSSPIDM
VALID
tHSPIDM
tSSPIDM
VALID
tHSPIDM
tDDSPIDM
MOSI (OUTPUT) CPHA=0 MISO (INPUT)
tHDSPIDM
tSSPIDM
VALID
tHSPIDM
VALID
Figure Serial Peripheral Interface (SPI) Port-Master Timing
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ADSP-BF522/523/524/525/526/527
Serial Peripheral Interface (SPI) Port-Slave Timing
Table Figure describe port slave operations. Table Serial Peripheral Interface (SPI) Port-Slave Timing
Parameter Timing Requirements tSPICHS Serial Clock High Period tSPICLS Serial Clock Period tSPICLK Serial Clock Period tHDS Last Edge SPISS Asserted tSPITDS Sequential Transfer Delay tSDSCI SPISS Assertion First Edge tSSPID Data Input Valid Edge (Data Input Setup) tHSPID Sampling Edge Data Input Invalid Switching Characteristics tDSOE SPISS Assertion Data Active tDSDHI SPISS Deassertion Data High Impedance tDDSPID Edge Data Valid (Data Delay) tHDSPID Edge Data Invalid (Data Hold)
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5
SPISS (INPUT)
tSPICHS
(CPOL (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
(CPOL (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPID tHDSPID tDDSPID tDSDHI
MISO (OUTPUT) CPHA=1 MOSI (INPUT)
tSSPID
VALID
tHSPID
tSSPID
tHSPID
VALID
tDSOE
MISO (OUTPUT) CPHA=0 MOSI (INPUT)
tDDSPID
tDSDHI
tHSPID tSSPID
VALID VALID
Figure Serial Peripheral Interface (SPI) Port-Slave Timing
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General-Purpose Port Timing
Table Figure describe general-purpose port operations. Table General-Purpose Port Timing
ADSP-BF522/523/524/525/526/527
Parameter Timing Requirement tWFI General-Purpose Port Ball Input Pulse Width Switching Characteristics tGPOD General-Purpose Port Ball Output Delay from CLKOUT
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit tSCLK tSCLK 9.66
CLKOUT
tGPOD
GPIO OUTPUT
tWFI
GPIO INPUT
Figure General-Purpose Port Timing
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ADSP-BF522/523/524/525/526/527
Timer Cycle Timing
Table Figure describe timer expired operations. input signal asynchronous "width capture mode" "external clock mode" absolute maximum input frequency (fSCLK/2) MHz. Table Timer Cycle Timing
Parameter Timing Characteristics Timer Pulse Width Input (Measured SCLK Cycles)1 Timer Pulse Width Input High (Measured SCLK Cycles)1 tTIS Timer Input Setup Time Before CLKOUT Low2 tTIH Timer Input Hold Time After CLKOUT Low2 Switching Characteristics tHTO Timer Pulse Width Output (Measured SCLK Cycles) tTOD Timer Output Update Delay After CLKOUT High
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Unit tSCLK tSCLK tSCLK tSCLK tSCLK (232-1)tSCLK tSCLK (232-1)tSCLK
minimum pulse widths apply TMRx signals width capture external clock modes. They also apply PF15 PPI_CLK signals output mode. Either valid setup hold time valid pulse width sufficient. There need resynchronize programmable flag inputs.
CLKOUT
tTOD
TIMER OUTPUT
tHTO tTIS
TIMER INPUT
tTIH
tWH,
Figure Timer Cycle Timing
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Timer Clock Timing
Table Figure describe timer clock timing. Table Timer Clock Timing
Parameter Switching Characteristic tTODP Timer Output Update Delay After PPICLK High
ADSP-BF522/523/524/525/526/527
Minimum
Maximum 12.64
Unit
CLOCK
tTODP
TIMER OUTPUT
Figure Timer Clock Timing
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ADSP-BF522/523/524/525/526/527
HOSTDP Timing- Host Read Cycle
Table describe HOSTDP Host Read Cycle timing requirements. Table Host Read Cycle Timing Requirements
Parameter Timing Requirements tSADRDL HOST_ADDR Host_CE Setup before Host_RD assertion tsclk tHADRDH HOST_ADDR Host_CE Hold after Host_RD assertion tRDWL Host_RD pulse width tDRDYRDL tRDYPRD tDRDHRDY (ACK mode) tsclk (INT mode) tRDWH Host_RD pulse width high tsclk tDRDHRDY Host_RD de-assertion delay after Host_ACK de-assertion Switching Characteristics tSDATRDY Data valid after Host_ACK assertion tsclk tDRDYRDL Host_ACK assertion delay after Host_RD tsclk tRDYPRD Host_ACK pulse-width Read access Data Delay tHDARWH Data disable after Host_RD
ADSP-BF523 ADSP-BF522 ADSP-BF525 ADSP-BF524 ADSP-BF527 ADSP-BF526 Minimum Maximum Minimum Maximum Units tsclk tDRDYRDL tRDYPRD tDRDHRDY (ACK mode) tsclk (INT mode) tsclk 6.16 tsclk Data Delay tsclk
HOST_ADDR HOST_CE
tSADRDL tRDWL
HOST_RD
tHADRDH
tRDWH
tDRDYRDL
tRDYPRD
tDRDHRDY tHDARWH
HOST_ACK
tSDATRDY
HOST_D15-0
Figure HOSTDP A/C- Host Read Cycle
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HOSTDP Timing- Host Write Cycle
Table describes HOSTDP Host Write Cycle timing requirements. Table Host Write Cycle Timing Requirements
ADSP-BF522/523/524/525/526/527
ADSP-BF523 ADSP-BF525 ADSP-BF527 Parameter Timing Requirements tSADWRH HOST_ADDR/Host_CE Setup before Host_WR tHADWRH HOST_ADDR/Host_CE Hold after Host_WR tWRWL Host_WR pulse width Minimum (1.5 tsclk)+ 10.8 tDRDYWRL tRDYPRD tDWRHRDY (ACK mode) tsclk (INT mode) tsclk Maximum Minimum
ADSP-BF522 ADSP-BF524 ADSP-BF526 Maximum Units
tWRWH Host_WR pulse width high tDWRHRDY Host_WR de-assertion delay after Host_ACK de-assertion tHDATWH Data Hold after Host_WR de-assertion tSDATWH Data Setup before Host_WR de-assertion Switching Characteristics tDRDYWRL Host_ACK delay after Host_WR/Host_CE tRDYPWR Host_ACK pulse-width Write access
(1.5 tsclk)+ 10.8 tDRDYWRL tRDYPRD tDWRHRDY (ACK mode) tsclk (INT mode) tsclk tsclk tsclk
HOST_ADDR HOST_CE
tSADWRH tWRWL
HOST_WR
tHADWRH
tWRWH
tDRDYWRL tRDYPWR
HOST_ACK
tDWRHRDY
tHDATWH tSDATWH
HOST_D15-0
Figure HOSTDP A/C- Host Write Cycle
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ADSP-BF522/523/524/525/526/527
Timing
Table Timing Parameters1
Parameter tFACC Memory Read Access Time tRPGM Memory Charge Pump Release Time tCPS Memory Charge Pump Setup Time tCPH Memory Charge Pump Hold Time tPGM Memory Program Time
ADSP-BF523 ADSP-BF525 ADSP-BF527 Minimum Maximum
ADSP-BF522 ADSP-BF524 ADSP-BF526 Minimum Maximum
Units
These parameters programmed into OTP_TIMING register. ADSP-BF52x Blackfin Processor Hardware Reference application note "EE-TBD: Programming Blackfin Processors" details.
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JTAG Test Emulation Port Timing
Table Figure describe JTAG port operations. Table JTAG Port Timing
Parameter Timing Parameters tTCK Period tSTAP TDI, Setup Before High TDI, Hold After High tHTAP tSSYS System Inputs Setup Before High1 tHSYS System Inputs Hold After High1 tTRSTW TRST Pulse Width2 (measured cycles) Switching Characteristics tDTDO Delay from System Outputs Delay After Low3 tDSYS
ADSP-BF522/523/524/525/526/527
Minimum
Maximum
Unit
System Inputs DATA15-0, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15-0, PG15-0, PH15-0, MDIO, TCK, TD1, TMS, TRST, RESET, NMI, BMODE2-0. Maximum System Outputs DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15-0, PG15-0, PH15-0, MDC, MDIO, TD0, EMU.
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure JTAG Port Timing
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ADSP-BF522/523/524/525/526/527
10/100 Ethernet Controller Timing
Table through Table Figure through Figure describe 10/100 Ethernet Controller operations. Table 10/100 Ethernet Controller Timing: Receive Signal
Parameter1 tERXCLKF tERXCLKW tERXCLKIS tERXCLKIH
ERxCLK Frequency (fSCLK SCLK Frequency) ERxCLK Width (tERxCLK ERxCLK Period) Input Valid ERxCLK Rising Edge (Data Setup) ERxCLK Rising Edge Input Invalid (Data Hold)
Minimum None tERxCLK
Maximum fSCLK tERxCLK
Unit
inputs synchronous ERxCLK ERxD3-0, ERxDV, ERxER.
Table 10/100 Ethernet Controller Timing: Transmit Signal
Parameter1 tETF tETXCLKW tETXCLKOV tETXCLKOH
ETxCLK Frequency (fSCLK SCLK Frequency) ETxCLK Width (tETxCLK ETxCLK Period) ETxCLK Rising Edge Output Valid (Data Valid) ETxCLK Rising Edge Output Invalid (Data Hold)
Minimum None tETxCLK
Maximum fSCLK tETxCLK
Unit
outputs synchronous ETxCLK ETxD3-0.
Table 10/100 Ethernet Controller Timing: RMII Receive Signal
Parameter1 tEREFCLKF tEREFCLKW tEREFCLKIS tEREFCLKIH
REF_CLK Frequency (fSCLK SCLK Frequency) EREF_CLK Width (tEREFCL
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